From patchwork Wed May 17 14:46:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 99983 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp267170qge; Wed, 17 May 2017 07:47:20 -0700 (PDT) X-Received: by 10.99.95.88 with SMTP id t85mr4365042pgb.50.1495032440418; Wed, 17 May 2017 07:47:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495032440; cv=none; d=google.com; s=arc-20160816; b=OsJ3Y5NJESKHnfixAXJNZpNFCFC5MdfYh7iyBUeze6NJCzL8MXvO9JiezyO+5yM9gK BONlHyYwtaIPolApEvvF9gSmeR+7Sn1NNH2mGzgWFN5Xr4L21hMcv6vxsHmfFqvD7HWl kPZaU3kSbIlYu/pxVfK6OZZxx5PfSP4PdTI4mX9UgTQlPVZVAAU1fOboaymLLI42pAHg BrCdCq1wK3pOY/WohufkkGxnF+drQN3pwVc7oDDuASxiTvRsT3jgsaw04eethYcATDso wjGpOALPJ0tDLjo95CSWzv5cqVTxEtnzkKgNYprHGystKgGSM4QxxH9c+MLsgIogYKIx 6WZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=7zWEZPpu93+n0wx93U3ummvk7Kyrf9cVDLndhDPIAQE=; b=d/1hIcr+fOrf7lgXmW2W8k9X5ArTHBC+bh1cUMeV13N3ZhRMvtEEaBA2HEXkbBxsQw 6yWTivmVsidIoTIidik9fRbXQe1rHn69kRb+ikENh2XeY1mv9Mr36daLVKgqEPelBztr YKB7BEm5GKyPJXIuPeb9WH9FaimANrvSuSVjH3z6uZLrEQ3UB32O9hLd5Gyurj16/Qdn 8TeBes3qCHKK08kSvtZCOWHd6QjnfCkNLjU1I7cUX+5YiXHjl/8hRYaymrXIvBg3k3hM zkBzUvS+NN1RKkyb45bmOo9V7vpLNbgJs0biO5ykkgbeEqWXcniwOG+cWTYXM+VIBy+Y yNAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id v9sm4845037pfa.43.2017.05.17.07.46.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 07:46:53 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Guodong Xu , Zhong Kaihua , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 1/2] clk: Hi3660: change to register clock with CLK_OF_DECLARE Date: Wed, 17 May 2017 22:46:31 +0800 Message-Id: <1495032392-19102-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495032392-19102-1-git-send-email-leo.yan@linaro.org> References: <1495032392-19102-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The timer will register into system at very early phase at kernel boot; if timer needs to use clock, the clock should be get ready in function of_clk_init() so later the timer driver probe can retrieve clock successfully. This is finished in below flow on arm64: start_kernel() `-> time_init() `-> of_clk_init(NULL) => register timer's clock `-> clocksource_probe() => register timer On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered as platform driver rather than CLK_OF_DECLARE method. As result, sp804 timer probe returns failure due if cannot bind clock properly. To fix the failure, this patch is to change crgctrl clock registration from platform driver to CLK_OF_DECLARE method so the clocks can be registered ahead with function of_clk_init() and then timer driver can use it. In the clock driver clk-hi3660.c, it's pointless to mix clock registration with platform driver mode and CLK_OF_DECLARE mode; this patch changes all clocks registration to CLK_OF_DECLARE mode to make code neat. Signed-off-by: Leo Yan --- drivers/clk/hisilicon/clk-hi3660.c | 48 ++++---------------------------------- 1 file changed, 5 insertions(+), 43 deletions(-) -- 1.9.1 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index fd5ce7f..fc11719 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -465,6 +465,7 @@ static void hi3660_clk_iomcu_init(struct device_node *np) ARRAY_SIZE(hi3660_iomcu_gate_sep_clks), clk_data); } +CLK_OF_DECLARE(hi3660_clk_iomcu, "hisilicon,hi3660-iomcu", hi3660_clk_iomcu_init); static void hi3660_clk_pmuctrl_init(struct device_node *np) { @@ -478,6 +479,7 @@ static void hi3660_clk_pmuctrl_init(struct device_node *np) hisi_clk_register_gate(hi3660_pmu_gate_clks, ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data); } +CLK_OF_DECLARE(hi3660_clk_pmuctrl, "hisilicon,hi3660-pmuctrl", hi3660_clk_pmuctrl_init); static void hi3660_clk_pctrl_init(struct device_node *np) { @@ -490,6 +492,7 @@ static void hi3660_clk_pctrl_init(struct device_node *np) hisi_clk_register_gate(hi3660_pctrl_gate_clks, ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data); } +CLK_OF_DECLARE(hi3660_clk_pctrl, "hisilicon,hi3660-pctrl", hi3660_clk_pctrl_init); static void hi3660_clk_sctrl_init(struct device_node *np) { @@ -513,6 +516,7 @@ static void hi3660_clk_sctrl_init(struct device_node *np) ARRAY_SIZE(hi3660_sctrl_divider_clks), clk_data); } +CLK_OF_DECLARE(hi3660_clk_sctrl, "hisilicon,hi3660-sctrl", hi3660_clk_sctrl_init); static void hi3660_clk_crgctrl_init(struct device_node *np) { @@ -547,46 +551,4 @@ static void hi3660_clk_crgctrl_init(struct device_node *np) ARRAY_SIZE(hi3660_crgctrl_divider_clks), clk_data); } - -static const struct of_device_id hi3660_clk_match_table[] = { - { .compatible = "hisilicon,hi3660-crgctrl", - .data = hi3660_clk_crgctrl_init }, - { .compatible = "hisilicon,hi3660-pctrl", - .data = hi3660_clk_pctrl_init }, - { .compatible = "hisilicon,hi3660-pmuctrl", - .data = hi3660_clk_pmuctrl_init }, - { .compatible = "hisilicon,hi3660-sctrl", - .data = hi3660_clk_sctrl_init }, - { .compatible = "hisilicon,hi3660-iomcu", - .data = hi3660_clk_iomcu_init }, - { } -}; - -static int hi3660_clk_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = pdev->dev.of_node; - void (*init_func)(struct device_node *np); - - init_func = of_device_get_match_data(dev); - if (!init_func) - return -ENODEV; - - init_func(np); - - return 0; -} - -static struct platform_driver hi3660_clk_driver = { - .probe = hi3660_clk_probe, - .driver = { - .name = "hi3660-clk", - .of_match_table = hi3660_clk_match_table, - }, -}; - -static int __init hi3660_clk_init(void) -{ - return platform_driver_register(&hi3660_clk_driver); -} -core_initcall(hi3660_clk_init); +CLK_OF_DECLARE(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl", hi3660_clk_crgctrl_init); From patchwork Wed May 17 14:46:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 99984 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp267182qge; Wed, 17 May 2017 07:47:21 -0700 (PDT) X-Received: by 10.99.137.198 with SMTP id v189mr4175369pgd.205.1495032441791; Wed, 17 May 2017 07:47:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495032441; cv=none; d=google.com; s=arc-20160816; b=hNTXUo/N4NTIfhSgO0XnZI9vMr1eO/0uLpaLbbxDL2jHPKHAnkAs5XwiB0lLsHlAfc fDYWd7VoaFXPm4lGxkzjrG8av9SZu9VFJ8rOWz/UfTD06c9CiU4VOaGCoKvI00hK4xPQ S02W/3n5tj4fjk5nqhN1+7EosUCkni2aK/rEdu286EBRQ50DXTcliCPfuv29WUPv39ax Tl/yRtVDPlDRfFhL/VOaIRZf5zfESvJJf6cwEa9QA4I1/H3qlrrn3eTjgL/wRs5O6QBr KX9nRN+tp8D6v28AN4qfItEZewG+EKJzlJENMiw9FG4lED4StK1PeVenjZTweZ6Vu8fJ VMDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wJAzihJNdQtMyT+iTeJQtD3nlj+AP+QoQkcKNRMR0+g=; b=ZeSoqsr6s09QW66FowNRygNyueZBeDTEKj59gxMFXp8q+tUVZZkEjVHxTJQG5H6Xk1 12LTYzFycxYFi+qCYakaORTDl7Ye9amtcc1HkVcXAiBwkEz0notyO/8Yz9SyaoXTOR7+ t7sjz6iVYGYBzd42jll4TW9jcAtNrWGKIq6sUhD4nIp4cA6hilnxlqjvM9QQFWD0589R F8C6u42XXLqj0vmGDLb6bWFnp/hplopTjmN83LHX9E8Gq9eOHdMLgqnUSIa1539sYULE rZW9SPb8iBPNNY3vGfkptxeO0twp6+WHo/4gtw4fEBbi9MYpkB/9ts7gjkRw8cdkaC9G 9YNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[106.186.117.108]) by smtp.gmail.com with ESMTPSA id v9sm4845037pfa.43.2017.05.17.07.46.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 07:47:01 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Guodong Xu , Zhong Kaihua , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 2/2] arm64: dts: add sp804 timer node for Hi3660 Date: Wed, 17 May 2017 22:46:32 +0800 Message-Id: <1495032392-19102-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495032392-19102-1-git-send-email-leo.yan@linaro.org> References: <1495032392-19102-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 138fcba..f75c792 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -173,6 +173,17 @@ #clock-cells = <1>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + ufs: ufs@ff3b0000 { compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; reg = <0x0 0xff3b0000 0x0 0x1000>, /* 0: HCI standard */