From patchwork Thu Jul 22 20:33:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scally X-Patchwork-Id: 484171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6DD3C4338F for ; Thu, 22 Jul 2021 20:34:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C173C60EB5 for ; Thu, 22 Jul 2021 20:34:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230465AbhGVTxz (ORCPT ); Thu, 22 Jul 2021 15:53:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230429AbhGVTxy (ORCPT ); Thu, 22 Jul 2021 15:53:54 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 135B9C061757; Thu, 22 Jul 2021 13:34:28 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id l4so76112wrs.4; Thu, 22 Jul 2021 13:34:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vzW8GMtaQ4KcRpdIHbGNsw4JG8M1qRceMOo6dYenjfc=; b=oCHwo2CcmBrFYiWf9q1Uit4Tvthunuo8sQPnOPNSfTW1nf2jwcU6ztjs5VwPOkuRqa Z+ePwWK1Qwpo3ErzxW9IctM/2K7CxDlplnA6wU92AByhujI+y6nLk6mdGhFOx+opPq4D Blsm/PN/c6MM1P0+JiCMz7JgCD4x7wmdrRvy6ldI+ddbwndkc4d5UVFvVnNTv89tn58E 3SGvRpzuGCy9pHmpTn+t/I6KSWoicmYprniVZ/4tfD8xsmo/djdnZ/uKtTdXG0R8mO5a JSn/pDFBNTRRpqDTETXtHxSkFFIPDb6GlKQy5pEnqGzSyQPh1GPCjb9vCEi8PU0fVIby OODw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vzW8GMtaQ4KcRpdIHbGNsw4JG8M1qRceMOo6dYenjfc=; b=dpIL1WgI0/nYQBBruPadmre33CoU2NPMhbRqfGWUsq9aHXn9bT5aR5EQJO5B9r0jDO 4SoL56tpdTKIedMp+6fBpkqAtEEpUFjCtSuuPAkvjfV948FAcWekfJyqH7DfURVPebX/ M7l51I1SZShS0QPY5H99CjGGG3JTUI7JRIVlNs818KqiBZXDPUqgZZEu3UWcO1N/uW0v DoVxB9q7lBBHX+bpf7kBm0yc+KXejqaVGaFavZY1MKzJRKzZdjtokVVgK8jOU8VTLoLY SMA05b94VtJpWtvaYi4vEdUbXSQX/dtG4NEp3LPIocSTZWBtqI2Vrz1oX6xkRjWuHSgx BEKg== X-Gm-Message-State: AOAM533Cr6PNgHbg0JvIR0aR9z7wy/pRWrAh4IV/Az/xjAtoe2UrrlYZ /420tHO2HAPVBha16kBOpJbnJyVXBL4= X-Google-Smtp-Source: ABdhPJx2zSqDwrfDSNQRKtL1DeWx08i0724Uqu1FwG5Z85/i5PjwlRGxfP0IKnMByzKpT9VcIpLFdg== X-Received: by 2002:a5d:4522:: with SMTP id j2mr1685636wra.43.1626986066693; Thu, 22 Jul 2021 13:34:26 -0700 (PDT) Received: from valhalla.home ([2.29.20.106]) by smtp.gmail.com with ESMTPSA id b16sm31036455wrw.46.2021.07.22.13.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jul 2021 13:34:26 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 01/13] media: i2c: Add ACPI support to ov8865 Date: Thu, 22 Jul 2021 21:33:55 +0100 Message-Id: <20210722203407.3588046-2-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The ov8865 sensor is sometimes found on x86 platforms enumerated via ACPI. Add an ACPI match table to the driver so that it's probed on those platforms. Signed-off-by: Daniel Scally --- drivers/media/i2c/ov8865.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index ce50f3ea87b8..fe60cda3dea7 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -5,6 +5,7 @@ * Author: Paul Kocialkowski */ +#include #include #include #include @@ -2946,6 +2947,12 @@ static const struct dev_pm_ops ov8865_pm_ops = { SET_RUNTIME_PM_OPS(ov8865_suspend, ov8865_resume, NULL) }; +static const struct acpi_device_id ov8865_acpi_match[] = { + {"INT347A"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov8865_acpi_match); + static const struct of_device_id ov8865_of_match[] = { { .compatible = "ovti,ov8865" }, { } @@ -2956,6 +2963,7 @@ static struct i2c_driver ov8865_driver = { .driver = { .name = "ov8865", .of_match_table = ov8865_of_match, + .acpi_match_table = ov8865_acpi_match, .pm = &ov8865_pm_ops, }, .probe_new = ov8865_probe, From patchwork Thu Jul 22 20:33:57 2021 Content-Type: text/plain; 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Thu, 22 Jul 2021 13:34:28 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 03/13] media: i2c: Defer probe if not endpoint found Date: Thu, 22 Jul 2021 21:33:57 +0100 Message-Id: <20210722203407.3588046-4-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The ov8865 driver is one of those that can be connected to a CIO2 device by the cio2-bridge code. This means that the absence of an endpoint for this device is not necessarily fatal, as one might be built by the cio2-bridge when it probes. Return -EPROBE_DEFER if no endpoint is found rather than a fatal error. Signed-off-by: Daniel Scally --- drivers/media/i2c/ov8865.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index 2ef146e7e7ef..66182142c28b 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -2796,10 +2796,8 @@ static int ov8865_probe(struct i2c_client *client) /* Graph Endpoint */ handle = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); - if (!handle) { - dev_err(dev, "unable to find endpoint node\n"); - return -EINVAL; - } + if (!handle) + return -EPROBE_DEFER; sensor->endpoint.bus_type = V4L2_MBUS_CSI2_DPHY; From patchwork Thu Jul 22 20:33:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scally X-Patchwork-Id: 484169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BA5AC4338F for ; Thu, 22 Jul 2021 20:34:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E68AB60EBA for ; Thu, 22 Jul 2021 20:34:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231245AbhGVTyK (ORCPT ); Thu, 22 Jul 2021 15:54:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230526AbhGVTx6 (ORCPT ); Thu, 22 Jul 2021 15:53:58 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B636C061757; Thu, 22 Jul 2021 13:34:31 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id g12so4070317wme.2; Thu, 22 Jul 2021 13:34:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HNd/zrFSnbVVK7tkVRqXgL3ZTic0XmSJrzcwHUq0XkQ=; b=a3gJDB86ofKDN3ZwkGguIggb5pxkABuCH2vqJf/+hRte8qePyV6hKOMYhPkT/iwMk+ XQ1GIDqu4a3++cCx3FhIe/3UsBJmhkGXAFoN6DdTKJdzYFToyvcQ5T8Fu3ELVExgL8wU APqGXsxGGkAfnl0TdMRHMyHoPxxslXkh511rZ0+aVKz/SMUSsCOYVMoVGvmzva0/gzJR 2U1MAwvn9zyjA7boMx4piCmOjA0IhQl9suqwpHa97Es2ahLOmb+e0pv/diAHhztMG01a 2t+SMSgrAUPACRnKlMQvuyJbQd4CKrBzLaAlKz3iwC2F1dGiqazpE2VMwB09BD0QfMK1 D9eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HNd/zrFSnbVVK7tkVRqXgL3ZTic0XmSJrzcwHUq0XkQ=; b=AAzsSecS5/q3GY+n58Um9uHe4FxfXIYYlyesfp5HaBA+xqZDPdKG30Spdiq69dWWzQ xaDgt2dYg2iciHLDs7pz5EGpeT+xhtMgIaqMNTaaJ3SvFnm34Cwvpe5Q43izytt1O3sn H1kJWb+LtrSdLfqR8uHdGEDPyhBaqwKStn3tFoQZek00oLz/VdG6y+sRUqktXaEcfuLE kkrwC49NGvf4yHhV1cL5fuEW+5BVKv+tp4o11+vqLZao2PL0ywwCkWUGnSfB1fFcEo8N RLZLVr8c895V9jc7UF8qfYcqIfCEH4TL23DTlQ5LVGPmbCi03LjRbnH6gYMyHd9rZWRN Totw== X-Gm-Message-State: AOAM5327WVCbddQ8lLMJn3S0Bqb97OZF+i5M3V6ek+DCtJ3IV1/SPOyA IUEg3HHJAxXL+8WL8kiAXbY= X-Google-Smtp-Source: ABdhPJz+t4qUAGg3biFXCrklIBGjL8wMqIqI+QhxXLEIlZFzzY0u9ajyv4sU75PWjsCh29BsJuvAQw== X-Received: by 2002:a7b:cd9a:: with SMTP id y26mr10751114wmj.76.1626986070049; Thu, 22 Jul 2021 13:34:30 -0700 (PDT) Received: from valhalla.home ([2.29.20.106]) by smtp.gmail.com with ESMTPSA id b16sm31036455wrw.46.2021.07.22.13.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jul 2021 13:34:29 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 04/13] media: i2c: Support 19.2MHz input clock in ov8865 Date: Thu, 22 Jul 2021 21:33:58 +0100 Message-Id: <20210722203407.3588046-5-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The ov8865 driver as written expects a 24MHz input clock, but the sensor is sometimes found on x86 platforms with a 19.2MHz input clock supplied. Add a set of PLL configurations to the driver to support that rate too. As ACPI doesn't auto-configure the clock rate, check for a clock-frequency during probe and set that rate if one is found. Signed-off-by: Daniel Scally --- drivers/media/i2c/ov8865.c | 158 +++++++++++++++++++++++++++---------- 1 file changed, 115 insertions(+), 43 deletions(-) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index 66182142c28b..8739eea762c5 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -21,10 +21,6 @@ #include #include -/* Clock rate */ - -#define OV8865_EXTCLK_RATE 24000000 - /* Register definitions */ /* System */ @@ -665,6 +661,9 @@ struct ov8865_sensor { struct regulator *avdd; struct regulator *dvdd; struct regulator *dovdd; + + unsigned long extclk_rate; + unsigned int extclk_rate_idx; struct clk *extclk; struct v4l2_fwnode_endpoint endpoint; @@ -680,49 +679,83 @@ struct ov8865_sensor { /* Static definitions */ /* - * EXTCLK = 24 MHz * PHY_SCLK = 720 MHz * MIPI_PCLK = 90 MHz */ -static const struct ov8865_pll1_config ov8865_pll1_config_native = { - .pll_pre_div_half = 1, - .pll_pre_div = 0, - .pll_mul = 30, - .m_div = 1, - .mipi_div = 3, - .pclk_div = 1, - .sys_pre_div = 1, - .sys_div = 2, + +static const struct ov8865_pll1_config ov8865_pll1_configs_native[] = { + { /* 19.2 MHz input clock */ + .pll_pre_div_half = 1, + .pll_pre_div = 2, + .pll_mul = 75, + .m_div = 1, + .mipi_div = 3, + .pclk_div = 1, + .sys_pre_div = 1, + .sys_div = 2, + }, + { /* 24MHz input clock */ + .pll_pre_div_half = 1, + .pll_pre_div = 0, + .pll_mul = 30, + .m_div = 1, + .mipi_div = 3, + .pclk_div = 1, + .sys_pre_div = 1, + .sys_div = 2, + }, }; /* - * EXTCLK = 24 MHz * DAC_CLK = 360 MHz * SCLK = 144 MHz */ -static const struct ov8865_pll2_config ov8865_pll2_config_native = { - .pll_pre_div_half = 1, - .pll_pre_div = 0, - .pll_mul = 30, - .dac_div = 2, - .sys_pre_div = 5, - .sys_div = 0, +static const struct ov8865_pll2_config ov8865_pll2_configs_native[] = { + /* 19.2MHz input clock */ + { + .pll_pre_div_half = 1, + .pll_pre_div = 5, + .pll_mul = 75, + .dac_div = 1, + .sys_pre_div = 1, + .sys_div = 3, + }, + /* 24MHz input clock */ + { + .pll_pre_div_half = 1, + .pll_pre_div = 0, + .pll_mul = 30, + .dac_div = 2, + .sys_pre_div = 5, + .sys_div = 0, + } }; /* - * EXTCLK = 24 MHz * DAC_CLK = 360 MHz * SCLK = 72 MHz */ -static const struct ov8865_pll2_config ov8865_pll2_config_binning = { +static const struct ov8865_pll2_config ov8865_pll2_configs_binning[] = { + /* 19.2MHz input clock */ + { + .pll_pre_div_half = 1, + .pll_pre_div = 2, + .pll_mul = 75, + .dac_div = 2, + .sys_pre_div = 10, + .sys_div = 0, + }, + /* 24MHz input clock */ + { .pll_pre_div_half = 1, .pll_pre_div = 0, .pll_mul = 30, .dac_div = 2, .sys_pre_div = 10, .sys_div = 0, + } }; static const struct ov8865_sclk_config ov8865_sclk_config_native = { @@ -934,8 +967,8 @@ static const struct ov8865_mode ov8865_modes[] = { .frame_interval = { 1, 30 }, /* PLL */ - .pll1_config = &ov8865_pll1_config_native, - .pll2_config = &ov8865_pll2_config_native, + .pll1_config = ov8865_pll1_configs_native, + .pll2_config = ov8865_pll2_configs_native, .sclk_config = &ov8865_sclk_config_native, /* Registers */ @@ -990,8 +1023,8 @@ static const struct ov8865_mode ov8865_modes[] = { .frame_interval = { 1, 30 }, /* PLL */ - .pll1_config = &ov8865_pll1_config_native, - .pll2_config = &ov8865_pll2_config_native, + .pll1_config = ov8865_pll1_configs_native, + .pll2_config = ov8865_pll2_configs_native, .sclk_config = &ov8865_sclk_config_native, /* Registers */ @@ -1050,8 +1083,8 @@ static const struct ov8865_mode ov8865_modes[] = { .frame_interval = { 1, 30 }, /* PLL */ - .pll1_config = &ov8865_pll1_config_native, - .pll2_config = &ov8865_pll2_config_binning, + .pll1_config = ov8865_pll1_configs_native, + .pll2_config = ov8865_pll2_configs_binning, .sclk_config = &ov8865_sclk_config_native, /* Registers */ @@ -1116,8 +1149,8 @@ static const struct ov8865_mode ov8865_modes[] = { .frame_interval = { 1, 90 }, /* PLL */ - .pll1_config = &ov8865_pll1_config_native, - .pll2_config = &ov8865_pll2_config_binning, + .pll1_config = ov8865_pll1_configs_native, + .pll2_config = ov8865_pll2_configs_binning, .sclk_config = &ov8865_sclk_config_native, /* Registers */ @@ -1266,6 +1299,13 @@ static const struct ov8865_register_value ov8865_init_sequence[] = { { 0x4503, 0x10 }, }; +/* Clock rate */ + +static const unsigned long supported_extclk_rates[] = { + 19200000, + 24000000, +}; + static const s64 ov8865_link_freq_menu[] = { 360000000, }; @@ -1513,12 +1553,11 @@ static int ov8865_isp_configure(struct ov8865_sensor *sensor) static unsigned long ov8865_mode_pll1_rate(struct ov8865_sensor *sensor, const struct ov8865_mode *mode) { - const struct ov8865_pll1_config *config = mode->pll1_config; - unsigned long extclk_rate; + const struct ov8865_pll1_config *config; unsigned long pll1_rate; - extclk_rate = clk_get_rate(sensor->extclk); - pll1_rate = extclk_rate * config->pll_mul / config->pll_pre_div_half; + config = &mode->pll1_config[sensor->extclk_rate_idx]; + pll1_rate = sensor->extclk_rate * config->pll_mul / config->pll_pre_div_half; switch (config->pll_pre_div) { case 0: @@ -1552,10 +1591,12 @@ static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor, const struct ov8865_mode *mode, u32 mbus_code) { - const struct ov8865_pll1_config *config = mode->pll1_config; + const struct ov8865_pll1_config *config; u8 value; int ret; + config = &mode->pll1_config[sensor->extclk_rate_idx]; + switch (mbus_code) { case MEDIA_BUS_FMT_SBGGR10_1X10: value = OV8865_MIPI_BIT_SEL(10); @@ -1622,9 +1663,11 @@ static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor, static int ov8865_mode_pll2_configure(struct ov8865_sensor *sensor, const struct ov8865_mode *mode) { - const struct ov8865_pll2_config *config = mode->pll2_config; + const struct ov8865_pll2_config *config; int ret; + config = &mode->pll2_config[sensor->extclk_rate_idx]; + ret = ov8865_write(sensor, OV8865_PLL_CTRL12_REG, OV8865_PLL_CTRL12_PRE_DIV_HALF(config->pll_pre_div_half) | OV8865_PLL_CTRL12_DAC_DIV(config->dac_div)); @@ -2053,9 +2096,11 @@ static int ov8865_mode_configure(struct ov8865_sensor *sensor, static unsigned long ov8865_mode_mipi_clk_rate(struct ov8865_sensor *sensor, const struct ov8865_mode *mode) { - const struct ov8865_pll1_config *config = mode->pll1_config; + const struct ov8865_pll1_config *config; unsigned long pll1_rate; + config = &mode->pll1_config[sensor->extclk_rate_idx]; + pll1_rate = ov8865_mode_pll1_rate(sensor, mode); return pll1_rate / config->m_div / 2; @@ -2783,7 +2828,8 @@ static int ov8865_probe(struct i2c_client *client) struct ov8865_sensor *sensor; struct v4l2_subdev *subdev; struct media_pad *pad; - unsigned long rate; + unsigned int rate; + unsigned int i; int ret; sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); @@ -2858,13 +2904,39 @@ static int ov8865_probe(struct i2c_client *client) goto error_endpoint; } - rate = clk_get_rate(sensor->extclk); - if (rate != OV8865_EXTCLK_RATE) { - dev_err(dev, "clock rate %lu Hz is unsupported\n", rate); + /* + * We could have either a 24MHz or 19.2MHz clock rate. Check for a + * clock-frequency property and if found, set that rate. This should + * cover ACPI case. If the system uses devicetree then the configured + * rate should already be set, so we'll have to check it. + */ + + ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", + &rate); + if (!ret) { + ret = clk_set_rate(sensor->extclk, rate); + if (ret) { + dev_err(dev, "failed to set clock rate\n"); + return ret; + } + } + + sensor->extclk_rate = clk_get_rate(sensor->extclk); + + for (i = 0; i < ARRAY_SIZE(supported_extclk_rates); i++) { + if (sensor->extclk_rate == supported_extclk_rates[i]) + break; + } + + if (i == ARRAY_SIZE(supported_extclk_rates)) { + dev_err(dev, "clock rate %lu Hz is unsupported\n", + sensor->extclk_rate); ret = -EINVAL; goto error_endpoint; } + sensor->extclk_rate_idx = i; + /* Subdev, entity and pad */ subdev = &sensor->subdev; From patchwork Thu Jul 22 20:34:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scally X-Patchwork-Id: 484165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F126C4338F for ; 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Thu, 22 Jul 2021 13:34:32 -0700 (PDT) Received: from valhalla.home ([2.29.20.106]) by smtp.gmail.com with ESMTPSA id b16sm31036455wrw.46.2021.07.22.13.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jul 2021 13:34:31 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 06/13] media: i2c: Switch control to V4L2_CID_ANALOGUE_GAIN Date: Thu, 22 Jul 2021 21:34:00 +0100 Message-Id: <20210722203407.3588046-7-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The V4L2_CID_GAIN control for this driver configures registers that the datasheet specifies as analogue gain. Switch the control's ID to V4L2_CID_ANALOGUE_GAIN. Signed-off-by: Daniel Scally Reviewed-by: Paul Kocialkowski --- drivers/media/i2c/ov8865.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index c012f5cb11ab..09558a3342dd 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -2137,7 +2137,7 @@ static int ov8865_exposure_configure(struct ov8865_sensor *sensor, u32 exposure) /* Gain */ -static int ov8865_gain_configure(struct ov8865_sensor *sensor, u32 gain) +static int ov8865_analog_gain_configure(struct ov8865_sensor *sensor, u32 gain) { int ret; @@ -2447,8 +2447,8 @@ static int ov8865_s_ctrl(struct v4l2_ctrl *ctrl) if (ret) return ret; break; - case V4L2_CID_GAIN: - ret = ov8865_gain_configure(sensor, ctrl->val); + case V4L2_CID_ANALOGUE_GAIN: + ret = ov8865_analog_gain_configure(sensor, ctrl->val); if (ret) return ret; break; @@ -2493,7 +2493,7 @@ static int ov8865_ctrls_init(struct ov8865_sensor *sensor) /* Gain */ - v4l2_ctrl_new_std(handler, ops, V4L2_CID_GAIN, 128, 8191, 128, 128); + v4l2_ctrl_new_std(handler, ops, V4L2_CID_ANALOGUE_GAIN, 128, 8191, 128, 128); /* White Balance */ From patchwork Thu Jul 22 20:34:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scally X-Patchwork-Id: 484168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0711C4338F for ; Thu, 22 Jul 2021 20:34:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B421D60EB6 for ; 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Thu, 22 Jul 2021 13:34:33 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 08/13] media: i2c: Add hblank control to ov8865 Date: Thu, 22 Jul 2021 21:34:02 +0100 Message-Id: <20210722203407.3588046-9-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a V4L2_CID_HBLANK control to the ov8865 driver. This is read only with timing control intended to be done via vblanking alone. Signed-off-by: Daniel Scally --- One of the modes defined in this driver actually has HTS as a _lower_ value than output_size_x, which means the usual hblank = (hts - output_size_y) formula doesn't make sense. That seems really strange to me, but the Windows driver does it too so my understanding must be lacking there...I handled that by flooring hblank at 0, but there may be a much better way of doing this. drivers/media/i2c/ov8865.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index daead1fc9314..e1d3c0d50fdc 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -660,6 +660,7 @@ struct ov8865_state { struct ov8865_ctrls { struct v4l2_ctrl *link_freq; struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *hblank; struct v4l2_ctrl *vblank; struct v4l2_ctrl_handler handler; @@ -2500,6 +2501,7 @@ static int ov8865_ctrls_init(struct ov8865_sensor *sensor) const struct v4l2_ctrl_ops *ops = &ov8865_ctrl_ops; const struct ov8865_mode *mode = sensor->state.mode; unsigned int vblank_max, vblank_def; + unsigned int hblank; int ret; v4l2_ctrl_handler_init(handler, 32); @@ -2536,6 +2538,13 @@ static int ov8865_ctrls_init(struct ov8865_sensor *sensor) 0, 0, ov8865_test_pattern_menu); /* Blanking */ + hblank = mode->hts < mode->output_size_x ? 0 : mode->hts - mode->output_size_x; + ctrls->hblank = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HBLANK, hblank, + hblank, 1, hblank); + + if (ctrls->hblank) + ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + vblank_max = OV8865_TIMING_MAX_VTS - mode->output_size_y; vblank_def = mode->vts - mode->output_size_y; ctrls->vblank = v4l2_ctrl_new_std(handler, ops, V4L2_CID_VBLANK, @@ -2682,6 +2691,7 @@ static int ov8865_set_fmt(struct v4l2_subdev *subdev, struct v4l2_mbus_framefmt *mbus_format = &format->format; const struct ov8865_mode *mode; u32 mbus_code = 0; + unsigned int hblank; unsigned int index; int ret = 0; @@ -2726,6 +2736,10 @@ static int ov8865_set_fmt(struct v4l2_subdev *subdev, OV8865_TIMING_MAX_VTS - mode->output_size_y, 1, mode->vts - mode->output_size_y); + hblank = mode->hts < mode->output_size_x ? 0 : mode->hts - mode->output_size_x; + __v4l2_ctrl_modify_range(sensor->ctrls.hblank, hblank, hblank, 1, + hblank); + complete: mutex_unlock(&sensor->mutex); From patchwork Thu Jul 22 20:34:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scally X-Patchwork-Id: 484167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FBA7C4338F for ; Thu, 22 Jul 2021 20:34:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B15A60EB5 for ; Thu, 22 Jul 2021 20:34:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231133AbhGVTyQ (ORCPT ); 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Thu, 22 Jul 2021 13:34:34 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 09/13] media: i2c: cap exposure at height + vblank in ov8865 Date: Thu, 22 Jul 2021 21:34:03 +0100 Message-Id: <20210722203407.3588046-10-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Exposure limits depend on the total height; when vblank is altered (and thus the total height is altered), change the exposure limits to reflect the new cap. Signed-off-by: Daniel Scally --- drivers/media/i2c/ov8865.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index e1d3c0d50fdc..941b0f94f249 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -662,6 +662,7 @@ struct ov8865_ctrls { struct v4l2_ctrl *pixel_rate; struct v4l2_ctrl *hblank; struct v4l2_ctrl *vblank; + struct v4l2_ctrl *exposure; struct v4l2_ctrl_handler handler; }; @@ -2455,6 +2456,18 @@ static int ov8865_s_ctrl(struct v4l2_ctrl *ctrl) unsigned int index; int ret; + /* If VBLANK is altered we need to update exposure to compensate */ + if (ctrl->id == V4L2_CID_VBLANK) { + int exposure_max; + + exposure_max = sensor->state.mode->output_size_y + ctrl->val; + __v4l2_ctrl_modify_range(sensor->ctrls.exposure, + sensor->ctrls.exposure->minimum, + exposure_max, + sensor->ctrls.exposure->step, + min(sensor->ctrls.exposure->val, exposure_max)); + } + /* Wait for the sensor to be on before setting controls. */ if (pm_runtime_suspended(sensor->dev)) return 0; @@ -2511,8 +2524,8 @@ static int ov8865_ctrls_init(struct ov8865_sensor *sensor) /* Exposure */ - v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, 16, 1048575, 16, - 512); + ctrls->exposure = v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, 16, + 1048575, 16, 512); /* Gain */ @@ -2693,6 +2706,7 @@ static int ov8865_set_fmt(struct v4l2_subdev *subdev, u32 mbus_code = 0; unsigned int hblank; unsigned int index; + int exposure_max; int ret = 0; mutex_lock(&sensor->mutex); @@ -2740,6 +2754,12 @@ static int ov8865_set_fmt(struct v4l2_subdev *subdev, __v4l2_ctrl_modify_range(sensor->ctrls.hblank, hblank, hblank, 1, hblank); + exposure_max = mode->vts; + __v4l2_ctrl_modify_range(sensor->ctrls.exposure, + sensor->ctrls.exposure->minimum, exposure_max, + sensor->ctrls.exposure->step, + min(sensor->ctrls.exposure->val, exposure_max)); + complete: mutex_unlock(&sensor->mutex); From patchwork Thu Jul 22 20:34:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scally X-Patchwork-Id: 484166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AC19C432BE for ; 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Thu, 22 Jul 2021 13:34:38 -0700 (PDT) Received: from valhalla.home ([2.29.20.106]) by smtp.gmail.com with ESMTPSA id b16sm31036455wrw.46.2021.07.22.13.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jul 2021 13:34:37 -0700 (PDT) From: Daniel Scally To: Daniel Scally , Mauro Carvalho Chehab , Sakari Ailus , Paul Kocialkowski , Ezequiel Garcia , Hans Verkuil , Yang Li , linux-media@vger.kernel.org (open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)), linux-kernel@vger.kernel.org (open list) Cc: Yong Zhi , Bingbu Cao , Tianshu Qiu , Colin Ian King , laurent.pinchart@ideasonboard.com, kieran.bingham@ideasonboard.com Subject: [PATCH 12/13] media: i2c: Remove unused macros from ov8865 Date: Thu, 22 Jul 2021 21:34:06 +0100 Message-Id: <20210722203407.3588046-13-djrscally@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210722203407.3588046-1-djrscally@gmail.com> References: <20210722203407.3588046-1-djrscally@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org There are a number of macros defined in this driver that aren't actually used within it. There's a lot of macros defined in total, so removing the unused ones helps make it a bit less busy. Signed-off-by: Daniel Scally --- I wavered about including this, because it might be helpful for someone adding support for other features in the future to have these already defined, but in the end I thought it slightly better to be less busy. drivers/media/i2c/ov8865.c | 137 +------------------------------------ 1 file changed, 1 insertion(+), 136 deletions(-) diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index dca4db3039bb..9b38f2e16906 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -46,8 +46,6 @@ #define OV8865_PLL_CTRL6_REG 0x306 #define OV8865_PLL_CTRL6_SYS_DIV(v) (((v) - 1) & BIT(0)) -#define OV8865_PLL_CTRL8_REG 0x308 -#define OV8865_PLL_CTRL9_REG 0x309 #define OV8865_PLL_CTRLA_REG 0x30a #define OV8865_PLL_CTRLA_PRE_DIV_HALF(v) (((v) - 1) & BIT(0)) #define OV8865_PLL_CTRLB_REG 0x30b @@ -60,41 +58,21 @@ #define OV8865_PLL_CTRLE_SYS_DIV(v) ((v) & GENMASK(2, 0)) #define OV8865_PLL_CTRLF_REG 0x30f #define OV8865_PLL_CTRLF_SYS_PRE_DIV(v) (((v) - 1) & GENMASK(3, 0)) -#define OV8865_PLL_CTRL10_REG 0x310 -#define OV8865_PLL_CTRL11_REG 0x311 #define OV8865_PLL_CTRL12_REG 0x312 #define OV8865_PLL_CTRL12_PRE_DIV_HALF(v) ((((v) - 1) << 4) & BIT(4)) #define OV8865_PLL_CTRL12_DAC_DIV(v) (((v) - 1) & GENMASK(3, 0)) -#define OV8865_PLL_CTRL1B_REG 0x31b -#define OV8865_PLL_CTRL1C_REG 0x31c - #define OV8865_PLL_CTRL1E_REG 0x31e #define OV8865_PLL_CTRL1E_PLL1_NO_LAT BIT(3) -#define OV8865_PAD_OEN0_REG 0x3000 - -#define OV8865_PAD_OEN2_REG 0x3002 - -#define OV8865_CLK_RST5_REG 0x3005 - #define OV8865_CHIP_ID_HH_REG 0x300a #define OV8865_CHIP_ID_HH_VALUE 0x00 #define OV8865_CHIP_ID_H_REG 0x300b #define OV8865_CHIP_ID_H_VALUE 0x88 #define OV8865_CHIP_ID_L_REG 0x300c #define OV8865_CHIP_ID_L_VALUE 0x65 -#define OV8865_PAD_OUT2_REG 0x300d - -#define OV8865_PAD_SEL2_REG 0x3010 -#define OV8865_PAD_PK_REG 0x3011 -#define OV8865_PAD_PK_DRIVE_STRENGTH_1X (0 << 5) -#define OV8865_PAD_PK_DRIVE_STRENGTH_2X (1 << 5) -#define OV8865_PAD_PK_DRIVE_STRENGTH_3X (2 << 5) -#define OV8865_PAD_PK_DRIVE_STRENGTH_4X (3 << 5) #define OV8865_PUMP_CLK_DIV_REG 0x3015 -#define OV8865_PUMP_CLK_DIV_PUMP_N(v) (((v) << 4) & GENMASK(6, 4)) #define OV8865_PUMP_CLK_DIV_PUMP_P(v) ((v) & GENMASK(2, 0)) #define OV8865_MIPI_SC_CTRL0_REG 0x3018 @@ -102,21 +80,12 @@ GENMASK(7, 5)) #define OV8865_MIPI_SC_CTRL0_MIPI_EN BIT(4) #define OV8865_MIPI_SC_CTRL0_UNKNOWN BIT(1) -#define OV8865_MIPI_SC_CTRL0_LANES_PD_MIPI BIT(0) -#define OV8865_MIPI_SC_CTRL1_REG 0x3019 -#define OV8865_CLK_RST0_REG 0x301a -#define OV8865_CLK_RST1_REG 0x301b -#define OV8865_CLK_RST2_REG 0x301c -#define OV8865_CLK_RST3_REG 0x301d -#define OV8865_CLK_RST4_REG 0x301e #define OV8865_PCLK_SEL_REG 0x3020 #define OV8865_PCLK_SEL_PCLK_DIV_MASK BIT(3) #define OV8865_PCLK_SEL_PCLK_DIV(v) ((((v) - 1) << 3) & BIT(3)) -#define OV8865_MISC_CTRL_REG 0x3021 #define OV8865_MIPI_SC_CTRL2_REG 0x3022 -#define OV8865_MIPI_SC_CTRL2_CLK_LANES_PD_MIPI BIT(1) #define OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC BIT(0) #define OV8865_MIPI_BIT_SEL_REG 0x3031 @@ -125,7 +94,6 @@ #define OV8865_CLK_SEL0_PLL1_SYS_SEL(v) (((v) << 7) & BIT(7)) #define OV8865_CLK_SEL1_REG 0x3033 #define OV8865_CLK_SEL1_MIPI_EOF BIT(5) -#define OV8865_CLK_SEL1_UNKNOWN BIT(2) #define OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK BIT(1) #define OV8865_CLK_SEL1_PLL_SCLK_SEL(v) (((v) << 1) & BIT(1)) @@ -142,7 +110,6 @@ #define OV8865_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8) #define OV8865_EXPOSURE_CTRL_L_REG 0x3502 #define OV8865_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0)) -#define OV8865_EXPOSURE_GAIN_MANUAL_REG 0x3503 #define OV8865_GAIN_CTRL_H_REG 0x3508 #define OV8865_GAIN_CTRL_H(v) (((v) & GENMASK(12, 8)) >> 8) @@ -197,18 +164,6 @@ #define OV8865_INC_X_ODD(v) ((v) & GENMASK(4, 0)) #define OV8865_INC_X_EVEN_REG 0x3815 #define OV8865_INC_X_EVEN(v) ((v) & GENMASK(4, 0)) -#define OV8865_VSYNC_START_H_REG 0x3816 -#define OV8865_VSYNC_START_H(v) (((v) & GENMASK(15, 8)) >> 8) -#define OV8865_VSYNC_START_L_REG 0x3817 -#define OV8865_VSYNC_START_L(v) ((v) & GENMASK(7, 0)) -#define OV8865_VSYNC_END_H_REG 0x3818 -#define OV8865_VSYNC_END_H(v) (((v) & GENMASK(15, 8)) >> 8) -#define OV8865_VSYNC_END_L_REG 0x3819 -#define OV8865_VSYNC_END_L(v) ((v) & GENMASK(7, 0)) -#define OV8865_HSYNC_FIRST_H_REG 0x381a -#define OV8865_HSYNC_FIRST_H(v) (((v) & GENMASK(15, 8)) >> 8) -#define OV8865_HSYNC_FIRST_L_REG 0x381b -#define OV8865_HSYNC_FIRST_L(v) ((v) & GENMASK(7, 0)) #define OV8865_FORMAT1_REG 0x3820 #define OV8865_FORMAT1_FLIP_VERT_ISP_EN BIT(2) @@ -240,10 +195,6 @@ #define OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG BIT(2) #define OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG BIT(1) #define OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG BIT(0) -#define OV8865_AUTO_SIZE_X_OFFSET_H_REG 0x3842 -#define OV8865_AUTO_SIZE_X_OFFSET_L_REG 0x3843 -#define OV8865_AUTO_SIZE_Y_OFFSET_H_REG 0x3844 -#define OV8865_AUTO_SIZE_Y_OFFSET_L_REG 0x3845 #define OV8865_AUTO_SIZE_BOUNDARIES_REG 0x3846 #define OV8865_AUTO_SIZE_BOUNDARIES_Y(v) (((v) << 4) & GENMASK(7, 4)) #define OV8865_AUTO_SIZE_BOUNDARIES_X(v) ((v) & GENMASK(3, 0)) @@ -259,30 +210,10 @@ #define OV8865_BLC_CTRL0_TRIG_FORMAT_EN BIT(6) #define OV8865_BLC_CTRL0_TRIG_GAIN_EN BIT(5) #define OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN BIT(4) -#define OV8865_BLC_CTRL0_TRIG_MANUAL_EN BIT(3) -#define OV8865_BLC_CTRL0_FREEZE_EN BIT(2) -#define OV8865_BLC_CTRL0_ALWAYS_EN BIT(1) #define OV8865_BLC_CTRL0_FILTER_EN BIT(0) #define OV8865_BLC_CTRL1_REG 0x4001 -#define OV8865_BLC_CTRL1_DITHER_EN BIT(7) -#define OV8865_BLC_CTRL1_ZERO_LINE_DIFF_EN BIT(6) -#define OV8865_BLC_CTRL1_COL_SHIFT_256 (0 << 4) #define OV8865_BLC_CTRL1_COL_SHIFT_128 (1 << 4) -#define OV8865_BLC_CTRL1_COL_SHIFT_64 (2 << 4) -#define OV8865_BLC_CTRL1_COL_SHIFT_32 (3 << 4) #define OV8865_BLC_CTRL1_OFFSET_LIMIT_EN BIT(2) -#define OV8865_BLC_CTRL1_COLUMN_CANCEL_EN BIT(1) -#define OV8865_BLC_CTRL2_REG 0x4002 -#define OV8865_BLC_CTRL3_REG 0x4003 -#define OV8865_BLC_CTRL4_REG 0x4004 -#define OV8865_BLC_CTRL5_REG 0x4005 -#define OV8865_BLC_CTRL6_REG 0x4006 -#define OV8865_BLC_CTRL7_REG 0x4007 -#define OV8865_BLC_CTRL8_REG 0x4008 -#define OV8865_BLC_CTRL9_REG 0x4009 -#define OV8865_BLC_CTRLA_REG 0x400a -#define OV8865_BLC_CTRLB_REG 0x400b -#define OV8865_BLC_CTRLC_REG 0x400c #define OV8865_BLC_CTRLD_REG 0x400d #define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v) ((v) & GENMASK(7, 0)) @@ -337,66 +268,8 @@ /* MIPI */ -#define OV8865_MIPI_CTRL0_REG 0x4800 -#define OV8865_MIPI_CTRL1_REG 0x4801 -#define OV8865_MIPI_CTRL2_REG 0x4802 -#define OV8865_MIPI_CTRL3_REG 0x4803 -#define OV8865_MIPI_CTRL4_REG 0x4804 -#define OV8865_MIPI_CTRL5_REG 0x4805 -#define OV8865_MIPI_CTRL6_REG 0x4806 -#define OV8865_MIPI_CTRL7_REG 0x4807 -#define OV8865_MIPI_CTRL8_REG 0x4808 - -#define OV8865_MIPI_FCNT_MAX_H_REG 0x4810 -#define OV8865_MIPI_FCNT_MAX_L_REG 0x4811 - -#define OV8865_MIPI_CTRL13_REG 0x4813 -#define OV8865_MIPI_CTRL14_REG 0x4814 -#define OV8865_MIPI_CTRL15_REG 0x4815 -#define OV8865_MIPI_EMBEDDED_DT_REG 0x4816 - -#define OV8865_MIPI_HS_ZERO_MIN_H_REG 0x4818 -#define OV8865_MIPI_HS_ZERO_MIN_L_REG 0x4819 -#define OV8865_MIPI_HS_TRAIL_MIN_H_REG 0x481a -#define OV8865_MIPI_HS_TRAIL_MIN_L_REG 0x481b -#define OV8865_MIPI_CLK_ZERO_MIN_H_REG 0x481c -#define OV8865_MIPI_CLK_ZERO_MIN_L_REG 0x481d -#define OV8865_MIPI_CLK_PREPARE_MAX_REG 0x481e -#define OV8865_MIPI_CLK_PREPARE_MIN_REG 0x481f -#define OV8865_MIPI_CLK_POST_MIN_H_REG 0x4820 -#define OV8865_MIPI_CLK_POST_MIN_L_REG 0x4821 -#define OV8865_MIPI_CLK_TRAIL_MIN_H_REG 0x4822 -#define OV8865_MIPI_CLK_TRAIL_MIN_L_REG 0x4823 -#define OV8865_MIPI_LPX_P_MIN_H_REG 0x4824 -#define OV8865_MIPI_LPX_P_MIN_L_REG 0x4825 -#define OV8865_MIPI_HS_PREPARE_MIN_REG 0x4826 -#define OV8865_MIPI_HS_PREPARE_MAX_REG 0x4827 -#define OV8865_MIPI_HS_EXIT_MIN_H_REG 0x4828 -#define OV8865_MIPI_HS_EXIT_MIN_L_REG 0x4829 -#define OV8865_MIPI_UI_HS_ZERO_MIN_REG 0x482a -#define OV8865_MIPI_UI_HS_TRAIL_MIN_REG 0x482b -#define OV8865_MIPI_UI_CLK_ZERO_MIN_REG 0x482c -#define OV8865_MIPI_UI_CLK_PREPARE_REG 0x482d -#define OV8865_MIPI_UI_CLK_POST_MIN_REG 0x482e -#define OV8865_MIPI_UI_CLK_TRAIL_MIN_REG 0x482f -#define OV8865_MIPI_UI_LPX_P_MIN_REG 0x4830 -#define OV8865_MIPI_UI_HS_PREPARE_REG 0x4831 -#define OV8865_MIPI_UI_HS_EXIT_MIN_REG 0x4832 -#define OV8865_MIPI_PKT_START_SIZE_REG 0x4833 - #define OV8865_MIPI_PCLK_PERIOD_REG 0x4837 -#define OV8865_MIPI_LP_GPIO0_REG 0x4838 -#define OV8865_MIPI_LP_GPIO1_REG 0x4839 - -#define OV8865_MIPI_CTRL3C_REG 0x483c -#define OV8865_MIPI_LP_GPIO4_REG 0x483d - -#define OV8865_MIPI_CTRL4A_REG 0x484a -#define OV8865_MIPI_CTRL4B_REG 0x484b -#define OV8865_MIPI_CTRL4C_REG 0x484c -#define OV8865_MIPI_LANE_TEST_PATTERN_REG 0x484d -#define OV8865_MIPI_FRAME_END_DELAY_REG 0x484e -#define OV8865_MIPI_CLOCK_TEST_PATTERN_REG 0x484f + #define OV8865_MIPI_LANE_SEL01_REG 0x4850 #define OV8865_MIPI_LANE_SEL01_LANE0(v) (((v) << 0) & GENMASK(2, 0)) #define OV8865_MIPI_LANE_SEL01_LANE1(v) (((v) << 4) & GENMASK(6, 4)) @@ -407,7 +280,6 @@ /* ISP */ #define OV8865_ISP_CTRL0_REG 0x5000 -#define OV8865_ISP_CTRL0_LENC_EN BIT(7) #define OV8865_ISP_CTRL0_WHITE_BALANCE_EN BIT(4) #define OV8865_ISP_CTRL0_DPC_BLACK_EN BIT(2) #define OV8865_ISP_CTRL0_DPC_WHITE_EN BIT(1) @@ -416,17 +288,11 @@ #define OV8865_ISP_CTRL2_REG 0x5002 #define OV8865_ISP_CTRL2_DEBUG BIT(3) #define OV8865_ISP_CTRL2_VARIOPIXEL_EN BIT(2) -#define OV8865_ISP_CTRL2_VSYNC_LATCH_EN BIT(0) -#define OV8865_ISP_CTRL3_REG 0x5003 #define OV8865_ISP_GAIN_RED_H_REG 0x5018 #define OV8865_ISP_GAIN_RED_H(v) (((v) & GENMASK(13, 6)) >> 6) #define OV8865_ISP_GAIN_RED_L_REG 0x5019 #define OV8865_ISP_GAIN_RED_L(v) ((v) & GENMASK(5, 0)) -#define OV8865_ISP_GAIN_GREEN_H_REG 0x501a -#define OV8865_ISP_GAIN_GREEN_H(v) (((v) & GENMASK(13, 6)) >> 6) -#define OV8865_ISP_GAIN_GREEN_L_REG 0x501b -#define OV8865_ISP_GAIN_GREEN_L(v) ((v) & GENMASK(5, 0)) #define OV8865_ISP_GAIN_BLUE_H_REG 0x501c #define OV8865_ISP_GAIN_BLUE_H(v) (((v) & GENMASK(13, 6)) >> 6) #define OV8865_ISP_GAIN_BLUE_L_REG 0x501d @@ -434,7 +300,6 @@ /* VarioPixel */ -#define OV8865_VAP_CTRL0_REG 0x5900 #define OV8865_VAP_CTRL1_REG 0x5901 #define OV8865_VAP_CTRL1_HSUB_COEF(v) ((((v) - 1) << 2) & \ GENMASK(3, 2))