From patchwork Sun Jul 25 04:00:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 485922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4233CC4338F for ; Sun, 25 Jul 2021 04:02:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27D3960F44 for ; Sun, 25 Jul 2021 04:02:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230204AbhGYDWB (ORCPT ); Sat, 24 Jul 2021 23:22:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229948AbhGYDV5 (ORCPT ); Sat, 24 Jul 2021 23:21:57 -0400 Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3D37C061760 for ; Sat, 24 Jul 2021 21:02:26 -0700 (PDT) Received: by mail-oi1-x22b.google.com with SMTP id x15so6837493oic.9 for ; Sat, 24 Jul 2021 21:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fdmG3WG+Fl0BSnXJiqQEACHTkoffgPGp8XBicBQYpOo=; b=bUyKH/yL3uKMbRoFBycdV+AfDTE8ss1Qs1/Iw/icuLQwu0o4EOMDP7GIRMNwKcr9kW TI689VHRtv20TGBCCfe8QuPkiTDNYfaDpm4xbygf5xNYpF4L01c/QeVtBXhDpqxFeuiz dgvdUIOW6fmhDCjZSPqduzmtRWmExefdakj4p3o0RbSUhQu+mGrk+nggXMFUOeb481cQ JFPJdoh+CivVAFlrOF70psrME2PALWFTsqKG9GxYCzIGecNlisqhJvwRv7bTnnxyPael w+GNjKNDJbfaDWklYcEOAZw5MxZSL1sGyQy8sZgkCeqLL2mU8A1UkbZJWmCzwHMyjVUP 3a7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fdmG3WG+Fl0BSnXJiqQEACHTkoffgPGp8XBicBQYpOo=; b=do1prbco+p+GBYyNUvXYHHG0cyjyyB6/xnUI4wZE8xhXaXgolLHRMocJdPgdkTL3Zi bJpMl1N7AKIzwAgbfuKzXLJASIrHVZODuEThXRfFVGF9AkLXISO3FZfkLHxxWbr8OGMU Ef6lGQFtSssQh5PaUPOLIoQAgOCBlmP+Zt1dO/ZBW/vjupvxb1kGzLYwyy+dVqup+3Lx w7CZ8QG8fZz3o6ucmb+B4wUdIjjym7tAuy0w7chGRU/V+H0BLHeMRjYsUri+RTDio7l+ 709/CL7XaNeD4+ynhuYEmHQzCASnntMzQFYDADWtCtmqRGF8aDAYBDdQY0xi3xIwWBeA l4CA== X-Gm-Message-State: AOAM530aixadOKjUL2cxVwCyL1MgjbfHEpTX3X5v+aBiAwFvet/mM5CM w4fEkSqfB/aRTSZ5i3gvpXd7BA== X-Google-Smtp-Source: ABdhPJxiSm3YKhhzQd0mf+xM5ydNpnne/06tpn6+NFdCOwlVcrOLgOqNnXz8RgxQYmcA67KpD7pjOQ== X-Received: by 2002:aca:4355:: with SMTP id q82mr13228367oia.165.1627185746154; Sat, 24 Jul 2021 21:02:26 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id q20sm872910otv.50.2021.07.24.21.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 21:02:25 -0700 (PDT) From: Bjorn Andersson To: Bjorn Helgaas , Rob Herring , Stanimir Varbanov , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wil?= =?utf-8?q?czy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] PCI: qcom: Introduce enable/disable resource ops Date: Sat, 24 Jul 2021 21:00:36 -0700 Message-Id: <20210725040038.3966348-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210725040038.3966348-1-bjorn.andersson@linaro.org> References: <20210725040038.3966348-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The current model of doing resource enablement and controller initialization in a single "init" function invoked after dw_pcie_host_init() is invoked might result in clocks not being enabled at the time the "msi" interrupt fires. One such case happens reliably on the SC8180x (8cx) Snapdragon laptops, where it's seems like the bootloader touches PCIe and leaves things in a state that the "msi" interrupt will fire before we have a change to enable the clocks, resulting in an access of unclocked hardware. Introduce a two new callbacks, allowing the individual resource handling functions to be split between enable/init and deinit/disable. Helper functions for enable, disable and deinit are introduced to handle the fact that these functions may now be left without implementation. init is given a wrapper for symmetry. Signed-off-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8a7a300163e5..8a64a126de2b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -181,9 +181,11 @@ struct qcom_pcie; struct qcom_pcie_ops { int (*get_resources)(struct qcom_pcie *pcie); + int (*enable_resources)(struct qcom_pcie *pcie); int (*init)(struct qcom_pcie *pcie); int (*post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); + void (*disable_resources)(struct qcom_pcie *pcie); void (*post_deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); @@ -1345,6 +1347,31 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_enable_resources(struct qcom_pcie *pcie) +{ + if (pcie->ops->enable_resources) + return pcie->ops->enable_resources(pcie); + + return 0; +} + +static int qcom_pcie_init(struct qcom_pcie *pcie) +{ + return pcie->ops->init(pcie); +} + +static void qcom_pcie_deinit(struct qcom_pcie *pcie) +{ + if (pcie->ops->deinit) + pcie->ops->deinit(pcie); +} + +static void qcom_pcie_disable_resources(struct qcom_pcie *pcie) +{ + if (pcie->ops->disable_resources) + pcie->ops->disable_resources(pcie); +} + static int qcom_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1353,7 +1380,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_assert(pcie); - ret = pcie->ops->init(pcie); + ret = qcom_pcie_init(pcie); if (ret) return ret; @@ -1384,7 +1411,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) err_disable_phy: phy_power_off(pcie->phy); err_deinit: - pcie->ops->deinit(pcie); + qcom_pcie_deinit(pcie); return ret; } @@ -1520,10 +1547,14 @@ static int qcom_pcie_probe(struct platform_device *pdev) pp->ops = &qcom_pcie_dw_ops; + ret = qcom_pcie_enable_resources(pcie); + if (ret) + goto err_pm_runtime_put; + ret = phy_init(pcie->phy); if (ret) { pm_runtime_disable(&pdev->dev); - goto err_pm_runtime_put; + goto err_disable_resources; } platform_set_drvdata(pdev, pcie); @@ -1532,11 +1563,14 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (ret) { dev_err(dev, "cannot initialize host\n"); pm_runtime_disable(&pdev->dev); - goto err_pm_runtime_put; + goto err_disable_resources; } return 0; +err_disable_resources: + qcom_pcie_disable_resources(pcie); + err_pm_runtime_put: pm_runtime_put(dev); pm_runtime_disable(dev); From patchwork Sun Jul 25 04:00:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 485652 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2693890jao; Sat, 24 Jul 2021 21:02:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5GDNHqznzQLF6VuV7UlJNHe9WzmmopdyExJjYVRuf56xI9U0d1GYFK8k0XIt+/Pettrmi X-Received: by 2002:a05:6e02:1d0f:: with SMTP id i15mr7888115ila.199.1627185769711; Sat, 24 Jul 2021 21:02:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627185769; cv=none; d=google.com; s=arc-20160816; b=IJY8oF3P/jAk8zrqxe06Pa+HOpKlv1mjITcY6Bjm9givZOozDbKlNkm59cfTaAsMk6 jC8tUKx2kMRhaqc62Aof4tatzjf4Vut76MOReFw5ln1a63h2TuvheDRvIUVrazZc2Mnl tbdVn56RzhzigEE25LvjWYke8efpi3rOWVQXMRly5k0cyQ0lZrJ1jfbb8jkEXt/W7hHy 11fJKpeErPaDCMNamqRcZO0hJt5pFI6H/6p9LtjU/8gHP9WJTXJXI1BEzp7H6WNOleq3 O/hGCBa4xovQITkHXIVFQlZa4Q80RdXSVRW6VpJRZ/Cv+TxmMX4ITKIBnOPoo0Cl8vrm fI6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fJd/jugeN2YjgUvOBixRk7jqpX0of5iUQEXFzXCzPhs=; b=IUsmMG4qYjxPCuTExaYakR4C3IDTgP96v16DnJE6EqNaEj9Sl/QGxceVptkipC4iFm IEHseji6fqwY8H20tt2mxEkvNQrAMW3D52jrsCzhvpnlvwSh5ts9KPnKP9qtUHNQChTD cxpOJiXd9AgN3f+GZt51eXX9qhGSGNFN7Zn4Ip+Dq4Lj4Az6ZGHY44xIoUFGEEn2P6oQ aYQyPOnJzjT7o5tpul8HEvCgNX75l/7NonIOOtMlQ23RmsxoZt71m/Vt6A/2mM5xQkYp F2gHspUf72o9tOW9/0iKnae/JBQ1DNVNEnYPO13qLf6yhgvrTkWvpFtM+GzkbC1hG15B C1dA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="B4QCSkS/"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id q20sm872910otv.50.2021.07.24.21.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 21:02:26 -0700 (PDT) From: Bjorn Andersson To: Bjorn Helgaas , Rob Herring , Stanimir Varbanov , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wil?= =?utf-8?q?czy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] PCI: qcom: Split init and enable for 1.9.0 and 2.7.0 Date: Sat, 24 Jul 2021 21:00:37 -0700 Message-Id: <20210725040038.3966348-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210725040038.3966348-1-bjorn.andersson@linaro.org> References: <20210725040038.3966348-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On the sc8180x platform the "msi" interrupt often fires before init has a chance to enable the clocks that are necessary for the interrupt handler to access the hardware. Split out the resource enablement and disablement into the newly introduce enable/disable resource operations, to ensure that the necessary resources are enabled when needed. Signed-off-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 31 +++++++++++++++++--------- 1 file changed, 20 insertions(+), 11 deletions(-) -- 2.29.2 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8a64a126de2b..8adcbb718832 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1173,12 +1173,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) return PTR_ERR_OR_ZERO(res->pipe_clk); } -static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) +static int qcom_pcie_enable_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - u32 val; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1211,6 +1210,20 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + return 0; + +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; +} + +static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) +{ + u32 val; + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1238,15 +1251,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) } return 0; -err_disable_clocks: - clk_bulk_disable_unprepare(res->num_clks, res->clks); -err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; } -static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) +static void qcom_pcie_disable_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; @@ -1465,8 +1472,9 @@ static const struct qcom_pcie_ops ops_2_3_3 = { /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ static const struct qcom_pcie_ops ops_2_7_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, + .enable_resources = qcom_pcie_enable_2_7_0, .init = qcom_pcie_init_2_7_0, - .deinit = qcom_pcie_deinit_2_7_0, + .disable_resources = qcom_pcie_disable_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, @@ -1475,8 +1483,9 @@ static const struct qcom_pcie_ops ops_2_7_0 = { /* Qcom IP rev.: 1.9.0 */ static const struct qcom_pcie_ops ops_1_9_0 = { .get_resources = qcom_pcie_get_resources_2_7_0, + .enable_resources = qcom_pcie_enable_2_7_0, .init = qcom_pcie_init_2_7_0, - .deinit = qcom_pcie_deinit_2_7_0, + .disable_resources = qcom_pcie_disable_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, From patchwork Sun Jul 25 04:00:38 2021 Content-Type: text/plain; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id q20sm872910otv.50.2021.07.24.21.02.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jul 2021 21:02:27 -0700 (PDT) From: Bjorn Andersson To: Bjorn Helgaas , Rob Herring , Stanimir Varbanov , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wil?= =?utf-8?q?czy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] PCI: qcom: Add sc8180x compatible Date: Sat, 24 Jul 2021 21:00:38 -0700 Message-Id: <20210725040038.3966348-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210725040038.3966348-1-bjorn.andersson@linaro.org> References: <20210725040038.3966348-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SC8180x platform comes with 4 PCIe controllers, typically used for things such as NVME storage or connecting a SDX55 5G modem. Add a compatible for this, that just reuses the 1.9.0 ops. Signed-off-by: Bjorn Andersson Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++-- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3f646875f8c2..a0ae024c2d0c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -12,6 +12,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018 @@ -156,7 +157,7 @@ - "pipe" PIPE clock - clock-names: - Usage: required for sm8250 + Usage: required for sc8180x and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -245,7 +246,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 and sm8250 + Usage: required for sc8180x, sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8adcbb718832..3906e975d6db 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1597,6 +1597,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sc8180x", .data = &ops_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } };