From patchwork Mon Jul 26 02:11:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 486017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F3D4C432BE for ; Mon, 26 Jul 2021 02:11:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63BF260720 for ; Mon, 26 Jul 2021 02:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbhGZBbM (ORCPT ); Sun, 25 Jul 2021 21:31:12 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:15154 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230321AbhGZBay (ORCPT ); Sun, 25 Jul 2021 21:30:54 -0400 X-UUID: 95281973f9bc4f169cd0e472b0398342-20210726 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=c7qAG0km9s8UfLDAudvX69W67QH1Jy3xeC2kKUw1eTc=; b=Jd/MdvI2ea3uwVS0gj/mpGGBTA9buL448Cl57sMzjf3AcryDQCMGzJSUMkKVUxu+ECZ37rAx5Q3LU23yHwcpSuPHt/OUQie3Q0qX14UzOznx9Y4fmTF9GdBtSqrIdvmzSy365GHDWfYuSVba+uv0SIorIqrRH8Ufv45qJyl8+S8=; X-UUID: 95281973f9bc4f169cd0e472b0398342-20210726 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1952311626; Mon, 26 Jul 2021 10:11:16 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 10:11:08 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 10:11:06 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , Jitao Shi Subject: [PATCH v3 1/2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift Date: Mon, 26 Jul 2021 10:11:03 +0800 Message-ID: <20210726021104.80007-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: 348E4CA1722C3B1854CD867266DFB52ACF3EE66B7C134B691B943433C2BE82902000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The bridge chip ANX7625 requires the packets on lanes aligned at the end, or ANX7625 will shift the screen. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.25.1 diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index ae403c67cbd9..4735e0092ffe 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk; u32 data_rate; + /* force dsi line end without dsi_null data */ + bool force_dsi_end_without_null; unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); } + if (dsi->force_dsi_end_without_null) { + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev) dsi->bridge.of_node = dev->of_node; dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + if (dsi->next_bridge) + dsi->force_dsi_end_without_null = of_property_read_bool(dsi->next_bridge->of_node, + "force_dsi_end_without_null"); + drm_bridge_add(&dsi->bridge); ret = component_add(&pdev->dev, &mtk_dsi_component_ops); From patchwork Mon Jul 26 02:11:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 487036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85BE1C4338F for ; Mon, 26 Jul 2021 02:11:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 557B760BD3 for ; Mon, 26 Jul 2021 02:11:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231205AbhGZBax (ORCPT ); Sun, 25 Jul 2021 21:30:53 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:47205 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230272AbhGZBaw (ORCPT ); Sun, 25 Jul 2021 21:30:52 -0400 X-UUID: bb83b93e7d30446a957bb5905b6ff50e-20210726 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yslLm1vymujKFarhO3A6h6EAP8QMCCeSyOC9SgSoByQ=; b=HXEze7R926+axNQTFL/y9nSa870dUfBaUPsWrAFsSi8cRLwRgWT1nW+ANizDFX3toJ3lkfHvj1tohEgcw6lIHW6sraxyYcrfkImJtZUGb+ZgPevtp2RSGE98IMJyQFb0d3o0yj8foaG1m31qTlQhOeoHG9lIVWvvqxH1ayBbuEo=; X-UUID: bb83b93e7d30446a957bb5905b6ff50e-20210726 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 892610681; Mon, 26 Jul 2021 10:11:14 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 10:11:09 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 10:11:08 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , Jitao Shi Subject: [PATCH v3 2/2] dt-bindings: mediatek: add force_dsi_end_without_null for dsi Date: Mon, 26 Jul 2021 10:11:04 +0800 Message-ID: <20210726021104.80007-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210726021104.80007-1-jitao.shi@mediatek.com> References: <20210726021104.80007-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 57D432427D8170D0E97DD4E151E61F3C5A53BC80ABE18CDC438CC901559AF70F2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some bridge chip will shift screen when the dsi data does't ent at the same time in line. Signed-off-by: Jitao Shi --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8238a86686be..1c2f53f3ac3d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -19,6 +19,10 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached DSI panel or DSI-to-eDP encoder chip. +Optional properties: +- force_dsi_end_without_null: Some bridge chip(ex. ANX7625) requires the + packets on lanes aligned at the end. + MIPI TX Configuration Module ============================