From patchwork Tue Jul 27 20:19:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 486753 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp550694jas; Tue, 27 Jul 2021 13:20:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyudmEXyE9jS3BNmU/2zpya3+RsvyW4WGBQv/CMj+fNYvS39eLDGA0uNMUG1RpAHzyPb+h X-Received: by 2002:a05:6402:17d3:: with SMTP id s19mr29609901edy.49.1627417222493; Tue, 27 Jul 2021 13:20:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627417222; cv=none; d=google.com; s=arc-20160816; b=DBAaF0cGnR4YHBuU/aJJba5xyXn2LRyCxfGRuzNclJenvaWoIU+qEExC5DetQZmFNg h7mplj2CYWggztOnzHMZVfv7Bq+MhciKx6me0iS0fOJqaQpv759e798+r/jT1ZQh19cn P0xsKw01O+0GZA+/UcztSAV7BBPAxmrfiZFJ6bOreLa7xAgyIS2IlJ91sxciNJy6ggJr eiXPu3pTN22ScBRHvmNVrVlmmcSMjNnfsCq+3RSBdsj3yCVNhS7BH58pk56eJuvB0818 J9+uNdpGL5Mkhid8m1JRyeLC9uFL4GaDGmcuZY3sZhCfn/XnZ0sI1ubts4wydiZcitY7 WnxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D63/+TxRKfSO58fkCSffqgWBORWJvZPVM0amiHKwxec=; b=UdHDg068Yc/dB3R/OnBq6oC9tUo/NVEXuxACWSqmkWHLSQVT3Q8x7YP8Vz7hrLaBtu GOLNq2gtrnsVyHIXYM70QGfjRZCDCzlGXy+qQSO+WBT19ky434OXJHaf0Bs6KwSzK652 jQWNKwd1ec7UnWvxLllYdITJ35LusGjqltlt86nI4eRn5cFO41XK+bLxwhLiKIj4gANm 8fVg1dJvvByhkZUy3c19bUawqIzn6KUy0mecToQrwC1+KM2EprXccEfVcHMjj8PEAmBU s+hg0vi9MdhgRVvL5ExGbFZJzu52NacgmrtSAG2WIEmparKcU5PvbNy08aASpKWhrS3O izRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uc6aI1bT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qk43si2817945ejc.325.2021.07.27.13.20.22; Tue, 27 Jul 2021 13:20:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uc6aI1bT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232027AbhG0UUV (ORCPT + 7 others); Tue, 27 Jul 2021 16:20:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231351AbhG0UUU (ORCPT ); Tue, 27 Jul 2021 16:20:20 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6843C061760 for ; Tue, 27 Jul 2021 13:20:19 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id z2so23959977lft.1 for ; Tue, 27 Jul 2021 13:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D63/+TxRKfSO58fkCSffqgWBORWJvZPVM0amiHKwxec=; b=uc6aI1bT4oYPAXdYes42FS0Izp1zNLRkiWaGnSYlwTVIVOsTJSUmch0aAT5BmcYlcE ytrOkbt2DiOy0FKyOcCFU+QB/iJe6Azcx27O4p4DElOfL9rh8oagFB3QRQyOwv6/ykRA VBUr9jguO2RzUwDjQ60ngQSZABJqc1xPbbyPCkpfHBGiVdJRGYuR4ks1ey5VdH2H3HwP 4QDg8KYTIo/TvTnZDpGJDH+qyfCfrr4BDU8eu4keUJfMmRB3rDIGP6R0PasbOvffXzkU thDS7DIzY3kpx5HSg4cXVYslvWprRGRgaKWoEqZ5HXMlg2o1bt8UcQe4MwD0esSupeAp NF+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D63/+TxRKfSO58fkCSffqgWBORWJvZPVM0amiHKwxec=; b=rQVMyqXBxtxlOnWl7hp+v0uOL+L+zqlDKzFUqnqT2xhvjDveXIfrBOBUjV33qu1n5n 2MlpRK0cwzfM9Lq4QRHTokWJlFCXTCFTSyBg0f5OGITbeEikUW9GNYMsTrfuXeAzkp4D xcl23JV6i/zC1n+frFGDmVZDWEu8h7ZUtmxm1cgSmgFQg15lgvl4Z5mA3fxvxTNTyHT8 PY93m0A9S60zRt14e7l3A1ZBs+0pRkqVvclDx/pVxEN5KP8S76B2OBINmV2eeS2bd12G xDB/VWWTaCRbN3dnPT64m7l3kzjAQ/s2ZqS+F7u5FpBrUGErHbYTagOABucwRp+HQAt/ mbpA== X-Gm-Message-State: AOAM530gon06Vqutec1YrurCU2KZpsPRGYdivE8kwn6G/PamZD4atXEo qEb9oMB+l3q5i1FsbIEw6SDoEQ== X-Received: by 2002:a19:f716:: with SMTP id z22mr17747060lfe.13.1627417218148; Tue, 27 Jul 2021 13:20:18 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id i11sm376502lfe.215.2021.07.27.13.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 13:20:17 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v6 1/8] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Tue, 27 Jul 2021 23:19:57 +0300 Message-Id: <20210727202004.712665-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> References: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 6667261dc665..6b3380cf1a10 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -56,6 +56,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -70,6 +75,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -90,5 +96,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... 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For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..db4ada6acf27 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -61,6 +66,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -69,5 +75,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... 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[23.128.96.18]) by mx.google.com with ESMTP id qk43si2817945ejc.325.2021.07.27.13.20.25; Tue, 27 Jul 2021 13:20:26 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iIOKxl3O; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232296AbhG0UUX (ORCPT + 7 others); Tue, 27 Jul 2021 16:20:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232158AbhG0UUW (ORCPT ); Tue, 27 Jul 2021 16:20:22 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88A5FC061765 for ; Tue, 27 Jul 2021 13:20:21 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id e5so262048ljp.6 for ; Tue, 27 Jul 2021 13:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RNA9XwU+vnP7eUqrnZr8orLB3tT6dOo5v7UANVhsVwo=; b=iIOKxl3O8bDqaRuau8xjvmrsrZPwkWY9M/kWvlnmA/XY86NB183ykS8rVfIyMXxwMA R2y9DIJAXBBE4ztkGrjIXOYsBrbwce8IbmTiaSSQV2fpwFWLtzWMfYWtT2SO3usm94i9 BUK35lzp3bKCmDtu6S2FYAmBjGkZMtnfUqwaJE3po7PUXrGmjaM4YSQmfPrYKADmnBj3 uAGeJDpHS113sInDlmG2oJbikK1rEu5RG1WDea81//IhNpbQ5lgAd+wDLO8BVqJDcluT 3piOE3hb0tBFhalwguIZ8tli2eBJUnSbTWFsN7Qr/t2J9Nhgo429xfy82RksYVDrAnOS VgcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RNA9XwU+vnP7eUqrnZr8orLB3tT6dOo5v7UANVhsVwo=; b=URXZswWRZXFMcH9f3iieAj2BcZhPd3Gg0ff2OE5UKNUZ8Vf8oDvKuN2PaE8/5Ph6/I 8sdr8oPniqAMyjd3JdNtCZqXad/TxY8jZjTmkEvc+6zcNQhqc37XjLK2ubl2uuoPs6P7 ZniZ5b6Hl8LUQDGdqyRftJDky53iMnCRiN02em8g8VIAhhg7MHLtDXa8QjgQzZ77f5PG r1cjBhZRCGH0Q43Q/YIP9gE3MsWhHWsFzgP95j08RCEQ3aFKgZEwFF3uupMwIKQew/V+ ZXCHA+HBGQIaYT/QSAAm2Yfqwxu+RBqHD5XN9Sb0+LGoqMv1gh7YEa+1aqTZT0YHvGHG qwDg== X-Gm-Message-State: AOAM5304d+thTedOxkD2cSc4nC+BqQJuGdPxVBlBOkar00Ae+vC0L/KR tVme8NyqQszPYG9JUib8Zx5AdA== X-Received: by 2002:a05:651c:1069:: with SMTP id y9mr17500977ljm.18.1627417219794; Tue, 27 Jul 2021 13:20:19 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id i11sm376502lfe.215.2021.07.27.13.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 13:20:19 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v6 3/8] clk: qcom: dispcc-sm8250: use runtime PM for the clock controller Date: Tue, 27 Jul 2021 23:19:59 +0300 Message-Id: <20210727202004.712665-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> References: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 601c7c0ba483..108dd1249b6a 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -1226,13 +1227,31 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); +static void disp_cc_sm8250_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + static int disp_cc_sm8250_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8250_pm_runtime_disable, &pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } /* note: trion == lucid, except for the prepare() op */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); @@ -1257,7 +1276,11 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) /* DISP_CC_XO_CLK always-on */ regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); + ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver disp_cc_sm8250_driver = { From patchwork Tue Jul 27 20:20:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 486755 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp550748jas; Tue, 27 Jul 2021 13:20:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJypZMpS3M9AN0dTs7h3ul/6wK2l1tGaZhWM+PJWQr9FPJG8iVNUacB88fLNVtGyINkox0+u X-Received: by 2002:a05:6402:203a:: with SMTP id ay26mr24696629edb.280.1627417226949; Tue, 27 Jul 2021 13:20:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627417226; cv=none; d=google.com; s=arc-20160816; b=nNVMbsSS7aFVdzyp+I1eLrF+XIgfel1b+xTEYRXKzaWAnEEycZk7wpjLSwdIkIXDqw oK/5jEDVP2rnVhGvanuYQMSIz+SK0ew+vIiDFmQOluEarU4OLQ/aAPcS5SvYt7NUKZIX LdrsycQaFNN/9qLpdptc1c/yu9BQIEdlPuIdNsi5nz3h3ctqQz6rf6agei4tKkJ3a+kX rW1bZZQWxUwRlr1iAYCPLoIOhRuD+B9+1lZ8YBVggtxaKnn23fOWBC4jD55gLoxAEC91 bTNh7JYEhD0h/xnBqa73LSZTXCxKxqRHV277sMhi5HKwsCAHEV4m76LzWZAwbvniSuZe euMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DuXeupaKBu8fmjC2iX4mmn3Nc4vXMRr6696lO841Bo4=; b=GzseUbpb12hp8ZvtHlHBO67Z9iXu9ymzSoVQRpK0jyeXG0G39oDUZaLF7e4FxLCknV hvpqzk94S8qAH6ZtYeeagbyKFJT0wziH4NJB3PPQy4hE7BvoDymjLOCo+cwZZInUXoRL SjRaZhgE7FhIHPX9S18MkPmNfE1hPUaAGy1KWdMkD8eGmKZvV57zUBDmNBsxLxblIAXn yGUgWl1XpvwwCjeCD9OXcQeJz4gw6THCdpo/COrDqe00IeXDLjnGXoVwuJQlHnkSWVZX 2Q+ZHpoJ9Kz2tZ/xomAUQBr5Ay/Z2i1a/3JOGdWnm4A3DKAWekhlOS/EYfaQ8f6az4QV NUHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S2GuFMTI; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/videocc-sm8250.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 7b435a1c2c4b..8617454e4a77 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -364,13 +365,31 @@ static const struct of_device_id video_cc_sm8250_match_table[] = { }; MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table); +static void video_cc_sm8250_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + static int video_cc_sm8250_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + pm_runtime_enable(&pdev->dev); + + ret = devm_add_action_or_reset(&pdev->dev, video_cc_sm8250_pm_runtime_disable, &pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); @@ -379,7 +398,11 @@ static int video_cc_sm8250_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); + ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver video_cc_sm8250_driver = { From patchwork Tue Jul 27 20:20:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 488129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51AD4C19F31 for ; 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Tue, 27 Jul 2021 13:20:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id i11sm376502lfe.215.2021.07.27.13.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 13:20:20 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v6 5/8] clk: qcom: gdsc: enable optional power domain support Date: Tue, 27 Jul 2021 23:20:01 +0300 Message-Id: <20210727202004.712665-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> References: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Make gdsc code also use pm_runtime calls to ensure that registers are accessible during the gdsc_enable/gdsc_disable operations. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gdsc.c | 59 ++++++++++++++++++++++++++++++++++++++--- drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 51ed640e527b..a0781d7284cc 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,22 @@ enum gdsc_status { GDSC_ON }; +static int gdsc_pm_runtime_get(struct gdsc *sc) +{ + if (!sc->dev) + return 0; + + return pm_runtime_resume_and_get(sc->dev); +} + +static int gdsc_pm_runtime_put(struct gdsc *sc) +{ + if (!sc->dev) + return 0; + + return pm_runtime_put_sync(sc->dev); +} + /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) { @@ -232,9 +249,8 @@ static void gdsc_retain_ff_on(struct gdsc *sc) regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); } -static int gdsc_enable(struct generic_pm_domain *domain) +static int _gdsc_enable(struct gdsc *sc) { - struct gdsc *sc = domain_to_gdsc(domain); int ret; if (sc->pwrsts == PWRSTS_ON) @@ -290,11 +306,26 @@ static int gdsc_enable(struct generic_pm_domain *domain) return 0; } -static int gdsc_disable(struct generic_pm_domain *domain) +static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); int ret; + ret = gdsc_pm_runtime_get(sc); + if (ret) + return ret; + + ret = _gdsc_enable(sc); + + gdsc_pm_runtime_put(sc); + + return ret; +} + +static int _gdsc_disable(struct gdsc *sc) +{ + int ret; + if (sc->pwrsts == PWRSTS_ON) return gdsc_assert_reset(sc); @@ -329,6 +360,22 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } +static int gdsc_disable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + ret = gdsc_pm_runtime_get(sc); + if (ret) + return ret; + + ret = _gdsc_disable(sc); + + gdsc_pm_runtime_put(sc); + + return ret; +} + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -425,6 +472,8 @@ int gdsc_register(struct gdsc_desc *desc, for (i = 0; i < num; i++) { if (!scs[i]) continue; + if (pm_runtime_enabled(dev)) + scs[i]->dev = dev; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; ret = gdsc_init(scs[i]); @@ -439,6 +488,8 @@ int gdsc_register(struct gdsc_desc *desc, continue; if (scs[i]->parent) pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } return of_genpd_add_provider_onecell(dev->of_node, data); @@ -457,6 +508,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } of_genpd_del_provider(dev->of_node); } diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 5bb396b344d1..702d47a87af6 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -25,6 +25,7 @@ struct reset_controller_dev; * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller + * @dev: the device holding the GDSC, used for pm_runtime calls */ struct gdsc { struct generic_pm_domain pd; @@ -58,6 +59,7 @@ struct gdsc { const char *supply; struct regulator *rsupply; + struct device *dev; }; struct gdsc_desc { From patchwork Tue Jul 27 20:20:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 486897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9995BC4320A for ; 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Tue, 27 Jul 2021 13:20:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id i11sm376502lfe.215.2021.07.27.13.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 13:20:21 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v6 6/8] arm64: dts: qcom: sm8250: remove mmcx regulator Date: Tue, 27 Jul 2021 23:20:02 +0300 Message-Id: <20210727202004.712665-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> References: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Switch dispcc and videocc into using MMCX domain directly. Drop the now unused mmcx regulator. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4798368b02ef..bce5e9a9dd84 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -273,13 +273,6 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - mmcx_reg: mmcx-reg { - compatible = "regulator-fixed-domain"; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - regulator-name = "MMCX"; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2451,7 +2444,7 @@ videocc: clock-controller@abf0000 { clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; @@ -2720,7 +2713,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Tue Jul 27 20:20:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 486759 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp551036jas; Tue, 27 Jul 2021 13:20:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8+kO0RmENSScA0J2AihmDu0xeJ9wSPUaRHnPA2W1c0YCZ+dF8WC4gZjUQ+ZlQfKkm6Ft5 X-Received: by 2002:aa7:cd5c:: with SMTP id v28mr8636718edw.305.1627417245714; Tue, 27 Jul 2021 13:20:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627417245; cv=none; d=google.com; s=arc-20160816; b=ZIv9+DQWZHZKtuPF+HjQshI8XfkP1P4ie2W/DQ5sihuOmAOgVyWc2EM/COX/E70TMv F85vhvxyWk84iRonIuFc7Olh8eCQRaGP9XaTGFw3b1ONacb99r8sqbAUfWCq3jJR3NDs Bf/ltaEM3hk/6JJx+hqbAAVM8xex27+erZ1KPAQsK2Dg/C6wgiaPd0RNwLSQNxWs1tad 3treeim0iWvoOCmxBdn1SozeELGvx88926Bo47UizVWijaRHHEZNHvhFRn0SPdvLicA/ pLj3pYlouqtzS2Ipbwph94L0boi+bk34P/xZEQm6iyYcbVP7FAHdtiDkoR5Z1mfY7tkk xCKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nvC4be67S2hWmOAqpL0RQZJnOtBBOz8i5k3BFovEr8E=; b=kpPRfJiAUFG8UlXYuy/S7695Skjqr0JpW0cID9Hs73ohGsep/ayeKHVjRb5cnnw8v5 eIJeKLyCAQst6hjvqXpvm4TsulPZ3PwSJgPwy4+tiD6KlqyTpi545HfGnkQElrcJ0qXw jepxF8ehsiubM9Nq7I0knS+mWELGPoFHPC5A51eBAJL4dxB4FjaBzQTGGgmesqxCnyiR AH9vgIKKJAS/baOBv9mn+pRPu7ydaPWpSMowuqycWWQWNezo5pAUHIp5v+TNEIQi0oCl k0qi26qzlFW4oWJsyJhKqLyAzzdf1Hje7oZkMpzsSqZ/ARSKB50BqTvO7OkQysXi6fao zCzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TZiGViw0; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id nb2si3977203ejc.741.2021.07.27.13.20.45; Tue, 27 Jul 2021 13:20:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TZiGViw0; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232142AbhG0UUf (ORCPT + 7 others); Tue, 27 Jul 2021 16:20:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232338AbhG0UU0 (ORCPT ); Tue, 27 Jul 2021 16:20:26 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68F61C061796 for ; Tue, 27 Jul 2021 13:20:24 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id u3so23868540lff.9 for ; Tue, 27 Jul 2021 13:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nvC4be67S2hWmOAqpL0RQZJnOtBBOz8i5k3BFovEr8E=; b=TZiGViw063SCv+BkE5QIu7B1fC35B25RgVA+O01OE/gLyIdjZEobY2lBgSrEh+dGe3 g74N04pUX+Sep56PeAJMGHp4ADoFjj5iXf7MOPa/N5HOFz73rEH4gh3TU1st24wMqYRP AxBPDgCnNrVg8tphtxXpYpO1KTJxWICh3yColj1TMimGY/ws4hs+xkW4X03QouW6R1v8 GoeftC2RyoMipFZ6Aoqjqp0Zw7Y9PbFgOD0qWlGJotsGPlTK4F+YeS0Stv8p23nMdwLf 3+YS9ySMU45JfNjfyxk0/+DrNlE8LvJXretcix6rVkUSQd7LiPNPKW5dPNwvTAVRrWPN 5p4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nvC4be67S2hWmOAqpL0RQZJnOtBBOz8i5k3BFovEr8E=; b=Cnvk0oidWYqqCE/H/C6RYmZpD2eC2dk6qa0VaFIE8Gu9A3nfWKUth+1t4WG27gROTf Wd5ul7LbFz/WIhNdWSk0nKeJOUcGnGHY2c7iAPvf768aBx+IPpww+1mYY/3hm74Sgsik eRq8LLf4XbRxBmuAbY94eftBOa15ZNGdKE6ytyUBUwNWXU0FQA3FqNquPtx8xdrvOwZo 9zUQJx7443a4og6GoCx+AvMZHCrXEAW2RNxnjL7dao67E+ItTEACTIKclfqU0c8v7Der s3B8gPza5dA1yq0oGleeDlaigrwW4X57BV89xY2EFTCJHNHTPEtzwTWdIVDZTcAU1VLg ExAA== X-Gm-Message-State: AOAM5339pCPyqozJJFgCIt7biePeklte6l1fGfgkPct/o5/SuNmInxVo m5WR/Tb6l9MTU67VwTle972mQA== X-Received: by 2002:ac2:5d4a:: with SMTP id w10mr11295514lfd.529.1627417222819; Tue, 27 Jul 2021 13:20:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id i11sm376502lfe.215.2021.07.27.13.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 13:20:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v6 7/8] clk: qcom: dispcc-sm8250: stop using mmcx regulator Date: Tue, 27 Jul 2021 23:20:03 +0300 Message-Id: <20210727202004.712665-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> References: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdsc. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/dispcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) -- 2.30.2 diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 108dd1249b6a..cf0bb12eb6e1 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1129,7 +1129,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Tue Jul 27 20:20:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 486760 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp551061jas; Tue, 27 Jul 2021 13:20:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7dMhpj99690qtCQsceSLXYQPPw5OI2R/mkTAis71wumdO5tUCDLWlpb1Ba70t9ofQ1MNc X-Received: by 2002:aa7:cd5c:: with SMTP id v28mr8636813edw.305.1627417247523; Tue, 27 Jul 2021 13:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627417247; cv=none; d=google.com; s=arc-20160816; b=ptywM08xmS8vUICJrw4fnOibvKndkv7UMjNL1H2OQ6gNtWuCDfCa67wBf0HY8+zhZK mVU5Ji1OPK+DBdM5au+ijgxUz9Gm8JParnT2Fkx7hMBASivrnFGxeSkkaK3J3+Yydxv4 ag5H1BpexHyXUakd6NbvSPjKve3+EzM1SPx3dmq8H1eV3ixh+82cslYoPmq8QaXml8ai IRBvCFzzD3gIQ1Ib7jjDoLuR0w9hWw4qARJQfc8df1YEjbixsugzgWIpWPoHK0b1t16b WUgY70t9DX6uIBv7iaCBdAAsO9T+Gyk9A3QvscprJbkSRDMQO/38CzqoyyERxPhG9gsV 3OqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xwHyfFobMRMZKUio9uUatRxtV0PWAj3xDN5CdY+KXtw=; b=kmfqV/pyGUHROnqZ/xqrcTbk289+Uj7TrmaEuQJpPe6WnqkRDqllxkuwYK2mvlCJ39 sIHQ2iB2oJLTWGVeXXRR8awtTzqX+DEa5RzSo0+L6l8SWCOisZq1lzkRE4ltOGOizcig sK5DkTp+eOxrH78IXQ0jVXu7P0mwfJO6zd2mp3VxV0S2osYZUNCTkFMj8fVaVr91wkja 3SoKcO/JyJ1uOmv2R8NvRaAbcKZQEA1sdq2XATonyHjF7fKfZ0hnpxvK6SQ1uTrh+9t0 kUFK8+bpx1X0lwbgu2kQdSxtJ/r6qRVl8I9+beRJmP352Ih5QEqk/4OkKuM0IpltAlkK QjSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pd0N30nr; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id nb2si3977203ejc.741.2021.07.27.13.20.47; Tue, 27 Jul 2021 13:20:47 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pd0N30nr; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232597AbhG0UUq (ORCPT + 7 others); Tue, 27 Jul 2021 16:20:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232480AbhG0UUb (ORCPT ); Tue, 27 Jul 2021 16:20:31 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E44D5C0617A5 for ; Tue, 27 Jul 2021 13:20:25 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id m13so23851813lfg.13 for ; Tue, 27 Jul 2021 13:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xwHyfFobMRMZKUio9uUatRxtV0PWAj3xDN5CdY+KXtw=; b=pd0N30nr0KqMooVCHpWMLPM0lsT+3Zo1tpP7D4POtBf4e6piGSVRF/hMLEXNgAO64U Td4HPhY9c/idLVNAjwWLC3SV6ZNpzRE1mTwumX6MC1exIDQDNkVyKBmxdVvbs6C5BJtP utGHC7m6LnyDj6L97DFFZDOGOydarBu1PnvOr3VCOYQsOedejk3cGJnZzj/P7vwFop6w 6csPBbZG4ABdc3PvZJgNb5EkghoyK6bqGW1wY3ftM2QNaX7KeOG9ZRn8o3R86jzzRZBs HyzBaw3J0IvtI7blLf0nTAJaOseMbQCpTheV2fQ5jXyy9qK+wN4Jo0OfhD2NdfWb36+P 80bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xwHyfFobMRMZKUio9uUatRxtV0PWAj3xDN5CdY+KXtw=; b=MQ2q8A5qyOI5svTdF4y/DJHMS/gJaPQZI0GMugtZEjDwYb/216R7PSzu8T0gqEdYGl b/evueYGYLDh5aIZ3OdiPnANaT7RbUg0VhipuxnppBmSjvDWzynAOONHeqWi417c7TzC u6TbXGKGU+Ux/vmnwarlwylDSyhZEyGS8fNhgpvu6RWpFbJcdxRtLOhFfO5yCNjoFiHh hAZ137Y7k2NXX98P43AQzZw2cLqB5VzfTo4Lk5HKLifkwuGJUcYKYtPqoPsyrKerNgsz J61qlwowYS5GtZvMJnRpQ5NNgbMTiaDvcP2gsE/G15UKyxJ8hD6plHgyETlAVEItZ+Oe 5cLw== X-Gm-Message-State: AOAM530cTPxj2zArhHpPagyw2qQo4tlmDMUEKWIWreI//UBAnP9RF6Oz 7zVC6R30Hg9ymqr5SKc37fEZTQ== X-Received: by 2002:a05:6512:3767:: with SMTP id z7mr6831909lft.128.1627417223534; Tue, 27 Jul 2021 13:20:23 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id i11sm376502lfe.215.2021.07.27.13.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 13:20:23 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v6 8/8] clk: qcom: videocc-sm8250: stop using mmcx regulator Date: Tue, 27 Jul 2021 23:20:04 +0300 Message-Id: <20210727202004.712665-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> References: <20210727202004.712665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdscs. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8250.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 8617454e4a77..f28f2cb051d7 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -277,7 +277,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -287,7 +286,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -297,7 +295,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -307,7 +304,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = {