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[209.51.188.17]) by mx.google.com with ESMTPS id w22si820511vsf.380.2021.07.30.08.16.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Jul 2021 08:16:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PhR2e5Gt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m9UFt-0004s5-Op for patch@linaro.org; Fri, 30 Jul 2021 11:16:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m9UFg-0004le-0b for qemu-devel@nongnu.org; Fri, 30 Jul 2021 11:16:44 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:39926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m9UFc-0008SL-FC for qemu-devel@nongnu.org; Fri, 30 Jul 2021 11:16:43 -0400 Received: by mail-wr1-x42c.google.com with SMTP id b11so6412221wrx.6 for ; Fri, 30 Jul 2021 08:16:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qdsJPOGId78mowOWjxsBg3oGgGP3Tn6FPHFa9MGGUUk=; b=PhR2e5GtlUv/4uB7WBnrgj3CZF4WMProYoU/08hwbftn1aYSB/DJT9ltmJaHlRFZJ/ wZrzYmyKokBvWPJxwPsIx/j2BGtwNnFvJ0nEXulj8yh8iTpjik5BXkcKsDAPvo2M3MKe eiIJ5Ivn7Ar029I6d6g8dpBoc3G1SrOM6HdM0MfSq5jzmlWZH8o3L+X60bFyO1JVh0F5 vZiRPtKD19M+3m6pJNs5T8Mv3a4/81foyeZ7D23yEtnvGT9sc9YDoepnqdXDjXM4Xv+r Bsy2pWch56zW9CLYPh5n/v3h7/zheG09L8pr7a0aCCsBJbF0ZbGsOqdQQRPMUXlHI6gl oJKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qdsJPOGId78mowOWjxsBg3oGgGP3Tn6FPHFa9MGGUUk=; b=hcqhk7aF1nhrnzgX+bSe+4it8aLpXHdt8KRdAf1o1T3f+npyc8Dkl+zs89NrwlUbvr 5qUGoJuUvfoBU/R+AYKgNvipiXcSrCPAowbzKzQZxKNVEvbut2bqXAuw4h3ReAQ21EI+ DX4sxeBUaQd/1PH6VfiCPbaRUKgHMB2TZEQdQ+AYb7Z9a16t55ydSLRA0gJdIpadwNSo KOzemAIvKp2AO2nBbhk0QeyYD87eB5Pm/T0BQ/B2hnzwIhmirh+VN7FUrkId5i7hOWbY DRHmVzAdWidrZl6T8OhfydfImzDSnsAcEK4f4zWlX8G7mv5V72pQeIwS41u+wM3I5wIq QOiQ== X-Gm-Message-State: AOAM5313lhJGM21fvc2tx4srDy6l5PohieiU8e60YBG9BbrtzGIYSgR7 Y2NM8w64dLvwbM0pZ/MTEhKbww== X-Received: by 2002:a5d:490b:: with SMTP id x11mr3599223wrq.322.1627658199180; Fri, 30 Jul 2021 08:16:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id h12sm2020292wrm.62.2021.07.30.08.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 08:16:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: Re-indent sdiv and udiv helpers Date: Fri, 30 Jul 2021 16:16:35 +0100 Message-Id: <20210730151636.17254-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210730151636.17254-1-peter.maydell@linaro.org> References: <20210730151636.17254-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to make a code change to the sdiv and udiv helper functions, so first fix their indentation and coding style. Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 155d8bf2399..8e9c2a2cf8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9355,17 +9355,20 @@ uint32_t HELPER(uxtb16)(uint32_t x) int32_t HELPER(sdiv)(int32_t num, int32_t den) { - if (den == 0) - return 0; - if (num == INT_MIN && den == -1) - return INT_MIN; + if (den == 0) { + return 0; + } + if (num == INT_MIN && den == -1) { + return INT_MIN; + } return num / den; } uint32_t HELPER(udiv)(uint32_t num, uint32_t den) { - if (den == 0) - return 0; + if (den == 0) { + return 0; + } return num / den; } From patchwork Fri Jul 30 15:16:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 489335 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp3246735jas; Fri, 30 Jul 2021 08:18:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzQBcz+iMQtlShNGBV4MkLJj3+1KcPoMqjmGCVD4eLFcCE66j7LnauRBdDwOIpSWjpiUJLX X-Received: by 2002:a25:b7c5:: with SMTP id u5mr3941339ybj.491.1627658304551; Fri, 30 Jul 2021 08:18:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627658304; cv=none; d=google.com; s=arc-20160816; b=aifX7CqKBDL39FwIBQlRb1afHzsDAQhhOmatiGAgfT+99CjgHDCKMWs0PaeJ7bigbA BQT3KaxT4OpjgxHrlpRqFBVtQ/pRpJQoJr7oi4nXBwHbJD33J007fRtn08tFKMSn2HXe r537xECnU1ct2O3bWALw4u/yCtRudVL+Y4QMWqJ45PvUD58IVew8MsDPOjybhZm5xxfn h7+XprL2LPDnpCiebVlEMnpxrs05yBuDvjEXQdVqNoNvjUz1pHw/GvC5qIpjNgorEsqm zrTWAVwwCUfRLuBZ8gIpp1C7eXQhmuoy0fSn+4nllW9NxV2RD8RGskxom+0wmdvMxQbG d6dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y4T9Q0phKt1q1Ay7Q+sG5xGKY/jcAnzqEkcBv03G2Xk=; b=ZG9gRMBYfbY+Wor9JKF0t1c+gyqAjhHkmgAUTqLFWsx0UQzfDDHeB/FP2CylDdkt63 cDR/KzcGDSCB+q+jkZ2dMYYiR4sAVBGVwIFcRVqG9dbUpGiBxZCmX+3F06NYTH8zaQWt q4qqoZIVTtRmlVF/C3N36Ra1owtdf3jzXJAOpcC+XMUkVrnJhXxsbevha0MyB0HnkS6g xWgBUXhMyeNhOc5ZVgGxFhNdBVZaq321SmllFoAjofjdDSFUJdlx6UZqc2ixz0OdwOLb P++1fTCqWaKCBJ9PYt1e/NMW7F+1vCMzC/hPJjouevTnVdZFvEI8X4HraBRRynNh2Yjq g1Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="c0Dg/rwB"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h12sm2020292wrm.62.2021.07.30.08.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 08:16:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/arm: Implement M-profile trapping on division by zero Date: Fri, 30 Jul 2021 16:16:36 +0100 Message-Id: <20210730151636.17254-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210730151636.17254-1-peter.maydell@linaro.org> References: <20210730151636.17254-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unlike A-profile, for M-profile the UDIV and SDIV insns can be configured to raise an exception on division by zero, using the CCR DIV_0_TRP bit. Implement support for setting this bit by making the helper functions raise the appropriate exception. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.h | 4 ++-- target/arm/helper.c | 19 +++++++++++++++++-- target/arm/m_helper.c | 4 ++++ target/arm/translate.c | 4 ++-- 5 files changed, 26 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f0a5f84d50..5cf8996ae3c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -54,6 +54,7 @@ #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ +#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 248569b0cd8..aee8f0019b4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -6,8 +6,8 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32) DEF_HELPER_3(sub_saturate, i32, env, i32, i32) DEF_HELPER_3(add_usaturate, i32, env, i32, i32) DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32) -DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32) +DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) #define PAS_OP(pfx) \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e9c2a2cf8c..56c520cf8e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9345,6 +9345,18 @@ uint32_t HELPER(sxtb16)(uint32_t x) return res; } +static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) +{ + /* + * Take a division-by-zero exception if necessary; otherwise return + * to get the usual non-trapping division behaviour (result of 0) + */ + if (arm_feature(env, ARM_FEATURE_M) + && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { + raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); + } +} + uint32_t HELPER(uxtb16)(uint32_t x) { uint32_t res; @@ -9353,9 +9365,10 @@ uint32_t HELPER(uxtb16)(uint32_t x) return res; } -int32_t HELPER(sdiv)(int32_t num, int32_t den) +int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) { if (den == 0) { + handle_possible_div0_trap(env, GETPC()); return 0; } if (num == INT_MIN && den == -1) { @@ -9364,9 +9377,10 @@ int32_t HELPER(sdiv)(int32_t num, int32_t den) return num / den; } -uint32_t HELPER(udiv)(uint32_t num, uint32_t den) +uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) { if (den == 0) { + handle_possible_div0_trap(env, GETPC()); return 0; } return num / den; @@ -9567,6 +9581,7 @@ void arm_log_exception(int idx) [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", [EXCP_LSERR] = "v8M LSERR UsageFault", [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", + [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 20761c94877..47903b3dc35 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2252,6 +2252,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; break; + case EXCP_DIVBYZERO: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_DIVBYZERO_MASK; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); diff --git a/target/arm/translate.c b/target/arm/translate.c index 80c282669f0..28eabeb2323 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7992,9 +7992,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u) t1 = load_reg(s, a->rn); t2 = load_reg(s, a->rm); if (u) { - gen_helper_udiv(t1, t1, t2); + gen_helper_udiv(t1, cpu_env, t1, t2); } else { - gen_helper_sdiv(t1, t1, t2); + gen_helper_sdiv(t1, cpu_env, t1, t2); } tcg_temp_free_i32(t2); store_reg(s, a->rd, t1);