From patchwork Mon Aug 2 06:21:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A64CFC4338F for ; Mon, 2 Aug 2021 06:30:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83A5F61042 for ; Mon, 2 Aug 2021 06:30:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229734AbhHBGbD (ORCPT ); Mon, 2 Aug 2021 02:31:03 -0400 Received: from smtpbg604.qq.com ([59.36.128.82]:51875 "EHLO smtpbg604.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229792AbhHBGbC (ORCPT ); Mon, 2 Aug 2021 02:31:02 -0400 X-Greylist: delayed 496 seconds by postgrey-1.27 at vger.kernel.org; Mon, 02 Aug 2021 02:31:01 EDT X-QQ-mid: bizesmtp41t1627885344tq5561ka Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:18 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: +I1LNsReFTRaBe0n8cyJfpYfsGxVjZPD3N/FdcxwlrxZwKc7m/2gsZPIGovsH XjkzYmg6tgcfos6kuz/rLPqQu/zHumGHTOeq+BU/G4OboZbFCvcMQNqoyqZ8Bb7wInD/etJ iw7pmwaY/snfXSfqOVtrhOrBeoWQ2XC8bMAEhsQ8/OpL5eO3ZROyKgtIqIoIayYtdwr8+65 ghx3SMe3z/FTTrunvHG4xUlLGaOiMylfJjtftyBBskVahc2Ver3TEDEyeU8hnjPB3T0P+03 8tzJCi79USCGw1pjOn7JPWMhc60dgiPhdh6O7zcEwdvjxXQUcXCbzbea980DiYc1oSFHlgg n/oPRQehSASnB8yK94= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 01/17] rtc: sun6i: Fix time overflow handling Date: Mon, 2 Aug 2021 14:21:56 +0800 Message-Id: <20210802062212.73220-2-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam4 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andre Przywara Using "unsigned long" for UNIX timestamps is never a good idea, and comparing the value of such a variable against U32_MAX does not do anything useful on 32-bit systems. Use the proper time64_t type when dealing with timestamps, and avoid cutting down the time range unnecessarily. This also fixes the flawed check for the alarm time being too far into the future. The check for this condition is actually somewhat theoretical, as the RTC counts till 2033 only anyways, and 2^32 seconds from now is not before the year 2157 - at which point I hope nobody will be using this hardware anymore. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/rtc/rtc-sun6i.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index adec1b14a8de..c551ebf0ac00 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -138,7 +138,7 @@ struct sun6i_rtc_dev { const struct sun6i_rtc_clk_data *data; void __iomem *base; int irq; - unsigned long alarm; + time64_t alarm; struct clk_hw hw; struct clk_hw *int_osc; @@ -510,10 +510,8 @@ static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); struct rtc_time *alrm_tm = &wkalrm->time; struct rtc_time tm_now; - unsigned long time_now = 0; - unsigned long time_set = 0; - unsigned long time_gap = 0; - int ret = 0; + time64_t time_now, time_set; + int ret; ret = sun6i_rtc_gettime(dev, &tm_now); if (ret < 0) { @@ -528,9 +526,7 @@ static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) return -EINVAL; } - time_gap = time_set - time_now; - - if (time_gap > U32_MAX) { + if ((time_set - time_now) > U32_MAX) { dev_err(dev, "Date too far in the future\n"); return -EINVAL; } @@ -539,7 +535,7 @@ static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) writel(0, chip->base + SUN6I_ALRM_COUNTER); usleep_range(100, 300); - writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); + writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER); chip->alarm = time_set; sun6i_rtc_setaie(wkalrm->enabled, chip); From patchwork Mon Aug 2 06:21:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90BA8C4338F for ; Mon, 2 Aug 2021 06:22:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6DD3B61050 for ; Mon, 2 Aug 2021 06:22:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229988AbhHBGWv (ORCPT ); Mon, 2 Aug 2021 02:22:51 -0400 Received: from smtpbg126.qq.com ([106.55.201.22]:64533 "EHLO smtpbg587.qq.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229792AbhHBGWv (ORCPT ); Mon, 2 Aug 2021 02:22:51 -0400 X-QQ-mid: bizesmtp41t1627885347tjehln8b Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:25 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: Izkt+D24Lu6ll/1ZEwgG2OWokI/c1EN9+wkh/u7N5VS1Mku0039Ik3TEsdAAa myCk1lhO8AwLEn5o6whvve7+nYXYMbl8aBsiCGTe7crHz2upzo7ikXAqSYyH4UQWHljsm2F tXNBqh+Rl6neFz9dPdh8jgSJvU/DPkf/LXe+tBkRGtCcjLceV0v+laUw4raqVJaqNDFWUDA SAdIKsP0Jw0nRnvqc4CTwBayKfeIGhvDP/YaNJWeKQx0FpC/Oqm92RqBhhoTG8MxaYvZ85j De9yHRPWWdgGoN245aPzLIwmyuB1RHk48T4RLlIxE3fpJry++lesvn80KCCliEhAdBUq9rm WO1xt4C7/5ILYXPZKU= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 02/17] rtc: sun6i: Add support for linear day storage Date: Mon, 2 Aug 2021 14:21:57 +0800 Message-Id: <20210802062212.73220-3-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andre Przywara Newer versions of the Allwinner RTC, as for instance found in the H616 SoC, no longer store a broken-down day/month/year representation in the RTC_DAY_REG, but just a linear day number. The user manual does not give any indication about the expected epoch time of this day count, but the BSP kernel uses the UNIX epoch, which allows easy support due to existing conversion functions in the kernel. Allow tagging a compatible string with a flag, and use that to mark those new RTCs. Then convert between a UNIX day number (converted into seconds) and the broken-down day representation using mktime64() and time64_to_tm() in the set_time/get_time functions. That enables support for the RTC in those new chips. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/rtc/rtc-sun6i.c | 69 +++++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index c551ebf0ac00..a980d4e7408d 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -110,6 +110,8 @@ #define SUN6I_YEAR_MIN 1970 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) +#define SECS_PER_DAY (24 * 3600ULL) + /* * There are other differences between models, including: * @@ -133,12 +135,15 @@ struct sun6i_rtc_clk_data { unsigned int has_auto_swt : 1; }; +#define RTC_LINEAR_DAY BIT(0) + struct sun6i_rtc_dev { struct rtc_device *rtc; const struct sun6i_rtc_clk_data *data; void __iomem *base; int irq; time64_t alarm; + unsigned long flags; struct clk_hw hw; struct clk_hw *int_osc; @@ -467,22 +472,30 @@ static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || (time != readl(chip->base + SUN6I_RTC_HMS))); + if (chip->flags & RTC_LINEAR_DAY) { + /* + * Newer chips store a linear day number, the manual + * does not mandate any epoch base. The BSP driver uses + * the UNIX epoch, let's just copy that, as it's the + * easiest anyway. + */ + rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); + } else { + rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); + rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; + rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); + + /* + * switch from (data_year->min)-relative offset to + * a (1900)-relative one + */ + rtc_tm->tm_year += SUN6I_YEAR_OFF; + } + rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); - rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); - rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date); - rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); - - rtc_tm->tm_mon -= 1; - - /* - * switch from (data_year->min)-relative offset to - * a (1900)-relative one - */ - rtc_tm->tm_year += SUN6I_YEAR_OFF; - return 0; } @@ -567,20 +580,25 @@ static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) u32 date = 0; u32 time = 0; - rtc_tm->tm_year -= SUN6I_YEAR_OFF; - rtc_tm->tm_mon += 1; - - date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | - SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | - SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); - - if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) - date |= SUN6I_LEAP_SET_VALUE(1); - time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); + if (chip->flags & RTC_LINEAR_DAY) { + /* The division will cut off the H:M:S part of rtc_tm. */ + date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); + } else { + rtc_tm->tm_year -= SUN6I_YEAR_OFF; + rtc_tm->tm_mon += 1; + + date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | + SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | + SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); + + if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) + date |= SUN6I_LEAP_SET_VALUE(1); + } + /* Check whether registers are writable */ if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, SUN6I_LOSC_CTRL_ACC_MASK, 50)) { @@ -674,6 +692,8 @@ static int sun6i_rtc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, chip); + chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); + chip->irq = platform_get_irq(pdev, 0); if (chip->irq < 0) return chip->irq; @@ -720,7 +740,10 @@ static int sun6i_rtc_probe(struct platform_device *pdev) return PTR_ERR(chip->rtc); chip->rtc->ops = &sun6i_rtc_ops; - chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ + if (chip->flags & RTC_LINEAR_DAY) + chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; + else + chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ ret = devm_rtc_register_device(chip->rtc); if (ret) From patchwork Mon Aug 2 06:21:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DC5AC4338F for ; Mon, 2 Aug 2021 06:31:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1695A60F4B for ; Mon, 2 Aug 2021 06:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232384AbhHBGbu (ORCPT ); Mon, 2 Aug 2021 02:31:50 -0400 Received: from smtpbg128.qq.com ([106.55.201.39]:56548 "EHLO smtpbg587.qq.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232428AbhHBGbr (ORCPT ); Mon, 2 Aug 2021 02:31:47 -0400 X-QQ-mid: bizesmtp41t1627885352t59cfljp Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:29 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: vLPYWrwZbqtrOYimloWC80mCd88KyGqnh5+mRCGmtELPdmXRolfov7pigmWm5 UcMMc1kruqGDfB8dF3zFwxrv55vXjltWPzJyOn5O4dvjgjCg/ZU5yRypx/T0HRBT3Wq8Hd0 2pDFFYVFTyo5vecpZsLW5nmFywYduc7P7azcQTDLefsTKkmqgAx/QJdGIHz92E7zSPZxXw4 QsykHj3HRBD5mgCWRFYU+eC46J7V8b+r/LLHr+4XfaLifWYjbJovMux0XTfB7wRsOy7AlKY nprp3HQu36knnVBQ61xr1q2GbLgMdDV5NY84+/MFAk82RhP80QHuy/VzAfqt9ecNEgjAuNp qk6s1yjX/WQq2CiKFI= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 03/17] rtc: sun6i: Add support for broken-down alarm registers Date: Mon, 2 Aug 2021 14:21:58 +0800 Message-Id: <20210802062212.73220-4-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam5 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andre Przywara Newer versions of the Allwinner RTC, for instance as found in the H616 SoC, not only store the current day as a linear number, but also change the way the alarm is handled: There are now two registers, that explicitly store the wakeup time, in the same format as the current time. Add support for that variant by writing the requested wakeup time directly into the registers, instead of programming the seconds left, as the old SoCs required. Signed-off-by: Andre Przywara Reviewed by: Jernej Skrabec --- drivers/rtc/rtc-sun6i.c | 57 +++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index a980d4e7408d..752bea949050 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -48,7 +48,8 @@ /* Alarm 0 (counter) */ #define SUN6I_ALRM_COUNTER 0x0020 -#define SUN6I_ALRM_CUR_VAL 0x0024 +/* This holds the remaining alarm seconds on older SoCs (current value) */ +#define SUN6I_ALRM_COUNTER_HMS 0x0024 #define SUN6I_ALRM_EN 0x0028 #define SUN6I_ALRM_EN_CNT_EN BIT(0) #define SUN6I_ALRM_IRQ_EN 0x002c @@ -523,32 +524,54 @@ static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); struct rtc_time *alrm_tm = &wkalrm->time; struct rtc_time tm_now; - time64_t time_now, time_set; + time64_t time_set; + u32 counter_val, counter_val_hms; int ret; - ret = sun6i_rtc_gettime(dev, &tm_now); - if (ret < 0) { - dev_err(dev, "Error in getting time\n"); - return -EINVAL; - } - time_set = rtc_tm_to_time64(alrm_tm); - time_now = rtc_tm_to_time64(&tm_now); - if (time_set <= time_now) { - dev_err(dev, "Date to set in the past\n"); - return -EINVAL; - } - if ((time_set - time_now) > U32_MAX) { - dev_err(dev, "Date too far in the future\n"); - return -EINVAL; + if (chip->flags & RTC_LINEAR_DAY) { + /* + * The alarm registers hold the actual alarm time, encoded + * in the same way (linear day + HMS) as the current time. + */ + counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | + SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | + SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); + /* The division will cut off the H:M:S part of alrm_tm. */ + counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); + } else { + /* The alarm register holds the number of seconds left. */ + time64_t time_now; + + ret = sun6i_rtc_gettime(dev, &tm_now); + if (ret < 0) { + dev_err(dev, "Error in getting time\n"); + return -EINVAL; + } + + time_now = rtc_tm_to_time64(&tm_now); + if (time_set <= time_now) { + dev_err(dev, "Date to set in the past\n"); + return -EINVAL; + } + if ((time_set - time_now) > U32_MAX) { + dev_err(dev, "Date too far in the future\n"); + return -EINVAL; + } + + counter_val = time_set - time_now; } sun6i_rtc_setaie(0, chip); writel(0, chip->base + SUN6I_ALRM_COUNTER); + if (chip->flags & RTC_LINEAR_DAY) + writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); usleep_range(100, 300); - writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER); + writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); + if (chip->flags & RTC_LINEAR_DAY) + writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); chip->alarm = time_set; sun6i_rtc_setaie(wkalrm->enabled, chip); From patchwork Mon Aug 2 06:22:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63DB9C4338F for ; Mon, 2 Aug 2021 06:31:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48E1960EEA for ; Mon, 2 Aug 2021 06:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231410AbhHBGbQ (ORCPT ); Mon, 2 Aug 2021 02:31:16 -0400 Received: from smtpbg604.qq.com ([59.36.128.82]:47546 "EHLO smtpbg604.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbhHBGbL (ORCPT ); Mon, 2 Aug 2021 02:31:11 -0400 X-QQ-mid: bizesmtp41t1627885358tbu3l0yk Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:37 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: vCa7dv7JIu4AIx2Tnge217fKbr8I+9aySDaTdWFJ3NmXbL2fQ9dSIbBGlM+83 ru1igvgEiL5Hy2fg6PqltX08K2mD8Pju4Ms6o744hzViRvCNdm2TIsx3USxZG4rUjGaEuvF xy6WmM/AVs9XK2yqUT1YVKiBA681i7WjdVUOb8/UIcL0Zjm80IAoXvqq/zLRT/KDrDHz3rg g0D0G84TcEt030BGvc9/lAO4uPLETSgv98VvSaxhfizck80Xb01rWXLQh721aenrTSHi1CA y2iwP2vas0ToE9IhYK4RYQI6aISrsEWcyJjybkRAxOHLr7sNGak8rNnlvPfZb1VyDW8tCi+ 8ezpdaX7hB0oWwYkmE= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 05/17] rtc: sun6i: add support for R329 RTC Date: Mon, 2 Aug 2021 14:22:00 +0800 Message-Id: <20210802062212.73220-6-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam4 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner R329 SoC has a RTC with similar clock control capability to H6, but its day storage changed to be linear, similar to the one in H616 RTC. Add support for it. Signed-off-by: Icenowy Zheng --- drivers/rtc/rtc-sun6i.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 752bea949050..06eca57e5215 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -386,6 +386,24 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node) CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", sun50i_h6_rtc_clk_init); +static const struct sun6i_rtc_clk_data sun50i_r329_rtc_data = { + .rc_osc_rate = 16000000, + .fixed_prescaler = 32, + .has_prescaler = 1, + .has_out_clk = 1, + .export_iosc = 1, + .has_losc_en = 1, + .has_auto_swt = 1, +}; + +static void __init sun50i_r329_rtc_clk_init(struct device_node *node) +{ + sun6i_rtc_clk_init(node, &sun50i_r329_rtc_data); +} + +CLK_OF_DECLARE_DRIVER(sun50i_r329_rtc_clk, "allwinner,sun50i-r329-rtc", + sun50i_r329_rtc_clk_init); + /* * The R40 user manual is self-conflicting on whether the prescaler is * fixed or configurable. The clock diagram shows it as fixed, but there @@ -791,6 +809,8 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = { { .compatible = "allwinner,sun8i-v3-rtc" }, { .compatible = "allwinner,sun50i-h5-rtc" }, { .compatible = "allwinner,sun50i-h6-rtc" }, + { .compatible = "allwinner,sun50i-r329-rtc", + .data = (void *)RTC_LINEAR_DAY }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); From patchwork Mon Aug 2 06:22:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D595AC4338F for ; Mon, 2 Aug 2021 06:27:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B259860EEA for ; Mon, 2 Aug 2021 06:27:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229734AbhHBG2F (ORCPT ); Mon, 2 Aug 2021 02:28:05 -0400 Received: from smtpbg127.qq.com ([109.244.180.96]:42861 "EHLO smtpbg.qq.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229988AbhHBG2E (ORCPT ); Mon, 2 Aug 2021 02:28:04 -0400 X-Greylist: delayed 309 seconds by postgrey-1.27 at vger.kernel.org; Mon, 02 Aug 2021 02:28:01 EDT X-QQ-mid: bizesmtp41t1627885361t7r18b0s Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:39 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: 7laTFqblRPgAJ6jR/WR92mkDWhvfBB2kGAde6cXqpA4eyp8AfURMplyUrtDME Dpsmawmn8jV9+0U0826Qi/gWSBxr61sYEYe7QvWf5GzUl8eGe1wSzF5VG+zf038g1xbHO73 iYEtFbYY0+GO119PmXdhgPwcYzN77mOsZOzlW2rFW9b6pTcd+POnMjAde2Px+cgO5ORhLPP mzcAGTmeaXgeAZOHFdRWDl0YlW1a/Xt/6dJ5JmHk1MuZN41LMlfhGsgYGqf+SgoWFhKGBL7 xl8lKmyFJ3UTbPB1ZKKzrOZYnMJoNeHoSJWP97aJq4+rMj0ZQdaBhXjYqimsDSJxt+L24LF saoVEYJZrgwdEMMASM= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 06/17] dt-bindings: pinctrl: document Allwinner R329 PIO and R-PIO Date: Mon, 2 Aug 2021 14:22:01 +0800 Message-Id: <20210802062212.73220-7-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner R329 have two pin controllers similar to previous Allwinner SoCs, PIO and R-PIO. Add compatible strings for them. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Acked-by: Maxime Ripard Reviewed-by: Samuel Holland --- .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index cce63c3cc463..802fba3fa34d 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -55,6 +55,8 @@ properties: - allwinner,sun50i-h6-r-pinctrl - allwinner,sun50i-h616-pinctrl - allwinner,sun50i-h616-r-pinctrl + - allwinner,sun50i-r329-pinctrl + - allwinner,sun50i-r329-r-pinctrl - allwinner,suniv-f1c100s-pinctrl - nextthing,gr8-pinctrl @@ -189,6 +191,7 @@ allOf: - allwinner,sun6i-a31-pinctrl - allwinner,sun6i-a31s-pinctrl - allwinner,sun50i-h6-pinctrl + - allwinner,sun50i-r329-pinctrl then: properties: @@ -204,6 +207,7 @@ allOf: - allwinner,sun8i-a83t-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-h5-pinctrl + - allwinner,sun50i-r329-r-pinctrl - allwinner,suniv-f1c100s-pinctrl then: From patchwork Mon Aug 2 06:22:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDEBDC4338F for ; Mon, 2 Aug 2021 06:31:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D721360EEA for ; Mon, 2 Aug 2021 06:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232357AbhHBGbi (ORCPT ); Mon, 2 Aug 2021 02:31:38 -0400 Received: from smtpbg127.qq.com ([109.244.180.96]:39282 "EHLO smtpbg.qq.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232306AbhHBGbi (ORCPT ); Mon, 2 Aug 2021 02:31:38 -0400 X-QQ-mid: bizesmtp41t1627885363tarqym8s Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:42 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: rqiGw5nOlbqS9WWmGx7IlP4daTMW21/M49Dn1NoBQC9uEtGJF6Z14UHsGGnXb w6k/GECuYp9TN4RSW6Q6+IY51J7HC7/Ti5jWXL12OddgTlfHZjfxmdYWKBEt4KA3+KOHPl9 DcUMeb1JmaEgFOe/ngLDbdUbzYCk5O+gyyPbD9Nno5Yac/A8RxksTt6pXp1aD57leclQlcr /H25LqdkvvYekVSIxIgIsJWAPdchP5ZHYgz05/dBkEgpHYRlPUlgQ/HOVuBEjPWeVAJY09Z ZbWk4AV5pFXiaggDMb5Hc3aq++wC4Y9EOf0cCR7cTZt/RdMOvDwjoc7fdyhJd2GUpW33pRW ovetlvPmN7ODr/pA0E= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Date: Mon, 2 Aug 2021 14:22:02 +0800 Message-Id: <20210802062212.73220-8-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner R329 SoC has two pin controllers similar to ones on previous SoCs, one in CPUX power domain and another in CPUS. This patch adds support for the CPUX domain pin controller. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c | 410 ++++++++++++++++++++ 3 files changed, 416 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 33751a6a0757..c662e8b1b351 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -129,4 +129,9 @@ config PINCTRL_SUN50I_H616_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_R329 + bool "Support for the Allwinner R329 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index d3440c42b9d6..e33f7c5f1ff9 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -25,5 +25,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o +obj-$(CONFIG_PINCTRL_SUN50I_R329) += pinctrl-sun50i-r329.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c new file mode 100644 index 000000000000..742f437ec0b6 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner R329 SoC pinctrl driver. + * + * Copyright (C) 2021 Sipeed + * based on the H616 pinctrl driver + * Copyright (C) 2020 Arm Ltd. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin r329_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM0 */ + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ + SUNXI_FUNCTION(0x5, "ledc"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */ + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ + SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM2 */ + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ + SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM3 */ + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ + SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM4 */ + SUNXI_FUNCTION(0x4, "i2s0_dout0"), + SUNXI_FUNCTION(0x5, "i2s0_din1"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM5 */ + SUNXI_FUNCTION(0x4, "i2s0_dout1"), + SUNXI_FUNCTION(0x5, "i2s0_din0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM6 */ + SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT2 */ + SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir"), /* TX */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM7 */ + SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT3 */ + SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir_tx"), + SUNXI_FUNCTION(0x3, "pwm"), /* PWM8 */ + SUNXI_FUNCTION(0x4, "ir_rx"), + SUNXI_FUNCTION(0x5, "ledc"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x3, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "spi0")), /* WP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc0")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x5, "boot_sel")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "sim0"), /* VPPEN */ + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ + SUNXI_FUNCTION(0x5, "mmc0"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "sim0"), /* VPPPP */ + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ + SUNXI_FUNCTION(0x5, "mmc0"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "sim0"), /* PWREN */ + SUNXI_FUNCTION(0x4, "uart"), /* TX */ + SUNXI_FUNCTION(0x5, "mmc0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "sim0"), /* CLK */ + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ + SUNXI_FUNCTION(0x5, "mmc0"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "sim0"), /* DATA */ + SUNXI_FUNCTION(0x4, "uart"), /* RX */ + SUNXI_FUNCTION(0x5, "mmc0"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "sim0"), /* RST */ + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ + SUNXI_FUNCTION(0x5, "mmc0"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "sim0"), /* DET */ + SUNXI_FUNCTION(0x4, "spdif_in"), + SUNXI_FUNCTION(0x5, "spdif_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1_clk"), + SUNXI_FUNCTION(0x3, "mmc1_d2"), + /* 0x4 is also mmc1_d2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1_cmd"), + SUNXI_FUNCTION(0x3, "mmc1_d3"), + SUNXI_FUNCTION(0x4, "mmc1_clk"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1_d0"), + SUNXI_FUNCTION(0x3, "mmc1_cmd"), + SUNXI_FUNCTION(0x4, "mmc1_d3"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1_d1"), + SUNXI_FUNCTION(0x3, "mmc1_clk"), + /* 0x4 is also mmc1_d1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1_d2"), + SUNXI_FUNCTION(0x3, "mmc1_d0"), + /* 0x4 is also mmc1_d0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1_d3"), + SUNXI_FUNCTION(0x3, "mmc1_d1"), + SUNXI_FUNCTION(0x4, "mmc1_cmd"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x5, "spi1"), /* HOLD/DBI-DCX/DBI-WRX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x5, "spi1"), /* WP/DBI-TE */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ledc"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ + SUNXI_FUNCTION(0x5, "spi1"), /* CS/DBI-CSX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ + SUNXI_FUNCTION(0x5, "spi1"), /* CLK/DBI-SCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x3, "i2s1_dout0"), + SUNXI_FUNCTION(0x4, "i2s1_din1"), + SUNXI_FUNCTION(0x5, "spi1"), /* MOSI/DBI-SDO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x3, "i2s1_dout1"), + SUNXI_FUNCTION(0x4, "i2s1_din0"), + SUNXI_FUNCTION(0x5, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS/DBI-CSX */ + SUNXI_FUNCTION(0x5, "pwm"), /* PWM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK/DBI-SCLK */ + SUNXI_FUNCTION(0x5, "pwm"), /* PWM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x3, "ledc"), /* DO */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI/DBI-SDO */ + SUNXI_FUNCTION(0x5, "ir"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ + SUNXI_FUNCTION(0x5, "ir"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ + SUNXI_FUNCTION(0x3, "spi1_cs"), /* CS/DBI-CSX */ + SUNXI_FUNCTION(0x4, "spi1_hold"), /* HOLD/DBI-DCX/DBI-WRX */ + SUNXI_FUNCTION(0x5, "pwm"), /* PWM2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ + SUNXI_FUNCTION(0x3, "spi1_clk"), /* CLK/DBI-SCLK */ + SUNXI_FUNCTION(0x4, "spi1_wp"), /* WP/DBI-TE */ + SUNXI_FUNCTION(0x5, "pwm"), /* PWM3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI/SPI-DBO */ + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x5, "pwm"), /* PWM4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x5, "pwm"), /* PWM5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "spi1"), /* WP/DBI-TE */ + SUNXI_FUNCTION(0x4, "ledc"), /* DO */ + SUNXI_FUNCTION(0x5, "ir"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x3, "spi1"), /* HOLD/DBI-DCX/DBI-WRX */ + SUNXI_FUNCTION(0x4, "spdif"), /* IN */ + SUNXI_FUNCTION(0x5, "ir"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */ +}; +static const unsigned int r329_irq_bank_map[] = { 1, 5, 6, 7 }; + +static const struct sunxi_pinctrl_desc r329_pinctrl_data = { + .pins = r329_pins, + .npins = ARRAY_SIZE(r329_pins), + .irq_banks = ARRAY_SIZE(r329_irq_bank_map), + .irq_bank_map = r329_irq_bank_map, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int r329_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, &r329_pinctrl_data); +} + +static const struct of_device_id r329_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-r329-pinctrl", }, + {} +}; + +static struct platform_driver r329_pinctrl_driver = { + .probe = r329_pinctrl_probe, + .driver = { + .name = "sun50i-r329-pinctrl", + .of_match_table = r329_pinctrl_match, + }, +}; +builtin_platform_driver(r329_pinctrl_driver); From patchwork Mon Aug 2 06:22:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFED0C4338F for ; Mon, 2 Aug 2021 06:23:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0D0F60FC1 for ; Mon, 2 Aug 2021 06:23:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232261AbhHBGXQ (ORCPT ); Mon, 2 Aug 2021 02:23:16 -0400 Received: from smtpbg126.qq.com ([106.55.201.22]:30952 "EHLO smtpbg587.qq.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232120AbhHBGXO (ORCPT ); Mon, 2 Aug 2021 02:23:14 -0400 X-QQ-mid: bizesmtp41t1627885373tao3kngl Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:51 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: uPKj8ga2w7E20dMsD3+/96w4c/h3ZOqSYyJmU+T7WrYuyJcdQRfYQwjVaUSPx Gdl3aykWwGUnC/1nigLruO7ZAtvsSj17fsoNkOki40QNtlUu/2Kt+beq7skwurxhR3TA3YU ff9qnvTi3rRzqKaanx4fYfEKe4XE4N4Z7E3d/6LBiBN6ew6cq7FDU1jax/DzcK0Q1Dvdh+f WIMMrxZhHk4QnjvCKJDsbLR2xc3Se4z5AmvrPogprvtmSZXapswCpN8/SjTkurgqDoWnpvs 1p1BNyhaDeCWy4OEhBWHRn/OaXbcfSw/wo+IeuobMO1Li4ZpGNTErJQdADei0FA3RrMELrJ ZIxR6kETUSEl9FWDxg= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Date: Mon, 2 Aug 2021 14:22:05 +0800 Message-Id: <20210802062212.73220-11-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner R329 has clock controls in PRCM, like other new Allwinner SoCs. Add support for them. This driver is added before the main CCU because PLLs are controlled by R-CCU on R329. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun50i-r329-r.c | 374 ++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-r329-r.h | 33 ++ include/dt-bindings/clock/sun50i-r329-r-ccu.h | 33 ++ include/dt-bindings/reset/sun50i-r329-r-ccu.h | 24 ++ 6 files changed, 470 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-r329-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-r329-r.h create mode 100644 include/dt-bindings/clock/sun50i-r329-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-r329-r-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index cd46d8853876..e49b2c2fa5b7 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -42,6 +42,11 @@ config SUN50I_H6_R_CCU default ARM64 && ARCH_SUNXI depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST +config SUN50I_R329_R_CCU + bool "Support for the Allwinner R329 PRCM CCU" + default ARM64 && ARCH_SUNXI + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST + config SUN4I_A10_CCU bool "Support for the Allwinner A10/A20 CCU" default MACH_SUN4I diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 96c324306d97..db338a2188fd 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o +obj-$(CONFIG_SUN50I_R329_R_CCU) += ccu-sun50i-r329-r.o obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-r329-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-r329-r.c new file mode 100644 index 000000000000..5413a701cb57 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun50i-r329-r.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Sipeed + * Based on the H616 CCU driver, which is: + * Copyright (c) 2020 Arm Ltd. + */ + +#include +#include +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" + +#include "ccu-sun50i-r329-r.h" + +/* + * The M factor is present in the register's description, but not in the + * frequency formula, and it's documented as "The bit is only for + * testing", so it's not modelled and then force to 0. + */ +#define SUN50I_R329_PLL_CPUX_REG 0x1000 +static struct ccu_mult pll_cpux_clk = { + .enable = BIT(31), + .lock = BIT(28), + .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12), + .common = { + .reg = 0x1000, + .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", + &ccu_mult_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +#define SUN50I_R329_PLL_PERIPH_REG 0x1010 +static struct ccu_nm pll_periph_base_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = 0x1010, + .hw.init = CLK_HW_INIT("pll-periph-base", "osc24M", + &ccu_nm_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static SUNXI_CCU_M(pll_periph_2x_clk, "pll-periph-2x", "pll-periph-base", + 0x1010, 16, 3, 0); +static SUNXI_CCU_M(pll_periph_800m_clk, "pll-periph-800m", "pll-periph-base", + 0x1010, 20, 3, 0); +static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph", + &pll_periph_2x_clk.common.hw, 2, 1, 0); + +#define SUN50I_R329_PLL_AUDIO0_REG 0x1020 +static struct ccu_sdm_setting pll_audio0_sdm_table[] = { + { .rate = 1548288000, .pattern = 0xc0070624, .m = 1, .n = 64 }, +}; + +static struct ccu_nm pll_audio0_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), + .m = _SUNXI_CCU_DIV(1, 1), + .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, + BIT(24), 0x1120, BIT(31)), + .common = { + .features = CCU_FEATURE_SIGMA_DELTA_MOD, + .reg = 0x1020, + .hw.init = CLK_HW_INIT("pll-audio0", "osc24M", + &ccu_nm_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static SUNXI_CCU_M(pll_audio0_div2_clk, "pll-audio0-div2", "pll-audio0", + 0x1020, 16, 3, 0); +static SUNXI_CCU_M(pll_audio0_div5_clk, "pll-audio0-div5", "pll-audio0", + 0x1020, 20, 3, 0); + +/* + * PLL-AUDIO1 has 3 dividers defined in the datasheet, however the + * BSP driver always has M0 = 1 and M1 = 2 (this is also the + * reset value in the register). + * + * Here just module it as NM clock, and force M0 = 1 and M1 = 2. + */ +#define SUN50I_R329_PLL_AUDIO1_REG 0x1030 +static struct ccu_sdm_setting pll_audio1_4x_sdm_table[] = { + { .rate = 22579200, .pattern = 0xc001288d, .m = 12, .n = 22 }, + { .rate = 24576000, .pattern = 0xc00126e9, .m = 12, .n = 24 }, + { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 }, + { .rate = 98304000, .pattern = 0xc00126e9, .m = 3, .n = 24 }, +}; +static struct ccu_nm pll_audio1_4x_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), + .m = _SUNXI_CCU_DIV(16, 6), + .fixed_post_div = 2, + .sdm = _SUNXI_CCU_SDM(pll_audio1_4x_sdm_table, + BIT(24), 0x1130, BIT(31)), + .common = { + .features = CCU_FEATURE_FIXED_POSTDIV | + CCU_FEATURE_SIGMA_DELTA_MOD, + .reg = 0x1030, + .hw.init = CLK_HW_INIT("pll-audio1-4x", "osc24M", + &ccu_nm_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static CLK_FIXED_FACTOR_HW(pll_audio1_2x_clk, "pll-audio1-2x", + &pll_audio1_4x_clk.common.hw, 2, 1, + CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR_HW(pll_audio1_clk, "pll-audio1", + &pll_audio1_4x_clk.common.hw, 4, 1, + CLK_SET_RATE_PARENT); + +static const char * const r_bus_parents[] = { "osc24M", "osc32k", "iosc", + "pll-periph-2x", + "pll-audio0-div2" }; +static SUNXI_CCU_MP_WITH_MUX(r_ahb_clk, "r-ahb", r_bus_parents, 0x000, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_MP_WITH_MUX(r_apb1_clk, "r-apb1", r_bus_parents, 0x00c, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_MP_WITH_MUX(r_apb2_clk, "r-apb2", r_bus_parents, 0x010, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_GATE(r_bus_gpadc_clk, "r-bus-gpadc", "r-apb1", + 0x0ec, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_ths_clk, "r-bus-ths", "r-apb1", 0x0fc, BIT(0), 0); + +static SUNXI_CCU_GATE(r_bus_dma_clk, "r-bus-dma", "r-apb1", 0x10c, BIT(0), 0); + +static const char * const r_pwm_parents[] = { "osc24M", "osc32k", "iosc" }; +static SUNXI_CCU_MUX_WITH_GATE(r_pwm_clk, "r-pwm", r_pwm_parents, 0x130, + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE(r_bus_pwm_clk, "r-bus-pwm", "r-apb1", 0x13c, BIT(0), 0); + +static const char * const r_audio_parents[] = { "pll-audio0-div5", "pll-audio0-div2", + "pll-audio1-1x", "pll-audio1-4x" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(r_codec_adc_clk, "r-codec-adc", r_audio_parents, 0x140, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_WITH_MUX_GATE(r_codec_dac_clk, "r-codec-dac", r_audio_parents, 0x144, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE(r_bus_codec_clk, "r-bus-codec", "r-apb1", + 0x14c, BIT(0), 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(r_dmic_clk, "r-dmic", r_audio_parents, 0x150, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE(r_bus_dmic_clk, "r-bus-dmic", "r-apb1", 0x15c, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_lradc_clk, "r-bus-lradc", "r-apb1", + 0x16c, BIT(0), 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(r_i2s_clk, "r-i2s", r_audio_parents, 0x170, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_WITH_MUX_GATE(r_i2s_asrc_clk, "r-i2s-asrc", + r_audio_parents, 0x174, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE(r_bus_i2s_clk, "r-bus-i2s", "r-apb1", 0x17c, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_uart_clk, "r-bus-uart", "r-apb2", 0x18c, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_i2c_clk, "r-bus-i2c", "r-apb2", 0x19c, BIT(0), 0); + +static const char * const r_ir_parents[] = { "osc32k", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(r_ir_clk, "r-ir", r_ir_parents, 0x1c0, + 0, 5, /* M */ + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE(r_bus_ir_clk, "r-bus-ir", "r-apb1", 0x1cc, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_msgbox_clk, "r-bus-msgbox", "r-apb1", + 0x1dc, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_spinlock_clk, "r-bus-spinlock", "r-apb1", + 0x1ec, BIT(0), 0); +static SUNXI_CCU_GATE(r_bus_rtc_clk, "r-bus-rtc", "r-ahb", + 0x20c, BIT(0), CLK_IS_CRITICAL); + +static struct ccu_common *sun50i_r329_r_ccu_clks[] = { + &pll_cpux_clk.common, + &pll_periph_base_clk.common, + &pll_periph_2x_clk.common, + &pll_periph_800m_clk.common, + &pll_audio0_clk.common, + &pll_audio0_div2_clk.common, + &pll_audio0_div5_clk.common, + &pll_audio1_4x_clk.common, + &r_ahb_clk.common, + &r_apb1_clk.common, + &r_apb2_clk.common, + &r_bus_gpadc_clk.common, + &r_bus_ths_clk.common, + &r_bus_dma_clk.common, + &r_pwm_clk.common, + &r_bus_pwm_clk.common, + &r_codec_adc_clk.common, + &r_codec_dac_clk.common, + &r_bus_codec_clk.common, + &r_dmic_clk.common, + &r_bus_dmic_clk.common, + &r_bus_lradc_clk.common, + &r_i2s_clk.common, + &r_i2s_asrc_clk.common, + &r_bus_i2s_clk.common, + &r_bus_uart_clk.common, + &r_bus_i2c_clk.common, + &r_ir_clk.common, + &r_bus_ir_clk.common, + &r_bus_msgbox_clk.common, + &r_bus_spinlock_clk.common, + &r_bus_rtc_clk.common, +}; + +static struct clk_hw_onecell_data sun50i_r329_r_hw_clks = { + .hws = { + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, + [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw, + [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.common.hw, + [CLK_PLL_PERIPH_800M] = &pll_periph_800m_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.hw, + [CLK_PLL_AUDIO0] = &pll_audio0_clk.common.hw, + [CLK_PLL_AUDIO0_DIV2] = &pll_audio0_div2_clk.common.hw, + [CLK_PLL_AUDIO0_DIV5] = &pll_audio0_div5_clk.common.hw, + [CLK_PLL_AUDIO1_4X] = &pll_audio1_4x_clk.common.hw, + [CLK_PLL_AUDIO1_2X] = &pll_audio1_2x_clk.hw, + [CLK_PLL_AUDIO1] = &pll_audio1_clk.hw, + [CLK_R_AHB] = &r_ahb_clk.common.hw, + [CLK_R_APB1] = &r_apb1_clk.common.hw, + [CLK_R_APB2] = &r_apb2_clk.common.hw, + [CLK_R_BUS_GPADC] = &r_bus_gpadc_clk.common.hw, + [CLK_R_BUS_THS] = &r_bus_ths_clk.common.hw, + [CLK_R_BUS_DMA] = &r_bus_dma_clk.common.hw, + [CLK_R_PWM] = &r_pwm_clk.common.hw, + [CLK_R_BUS_PWM] = &r_bus_pwm_clk.common.hw, + [CLK_R_CODEC_ADC] = &r_codec_adc_clk.common.hw, + [CLK_R_CODEC_DAC] = &r_codec_dac_clk.common.hw, + [CLK_R_BUS_CODEC] = &r_bus_codec_clk.common.hw, + [CLK_R_DMIC] = &r_dmic_clk.common.hw, + [CLK_R_BUS_DMIC] = &r_bus_dmic_clk.common.hw, + [CLK_R_BUS_LRADC] = &r_bus_lradc_clk.common.hw, + [CLK_R_I2S] = &r_i2s_clk.common.hw, + [CLK_R_I2S_ASRC] = &r_i2s_asrc_clk.common.hw, + [CLK_R_BUS_I2S] = &r_bus_i2s_clk.common.hw, + [CLK_R_BUS_UART] = &r_bus_uart_clk.common.hw, + [CLK_R_BUS_I2C] = &r_bus_i2c_clk.common.hw, + [CLK_R_IR] = &r_ir_clk.common.hw, + [CLK_R_BUS_IR] = &r_bus_ir_clk.common.hw, + [CLK_R_BUS_MSGBOX] = &r_bus_msgbox_clk.common.hw, + [CLK_R_BUS_SPINLOCK] = &r_bus_spinlock_clk.common.hw, + [CLK_R_BUS_RTC] = &r_bus_rtc_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun50i_r329_r_ccu_resets[] = { + [RST_R_BUS_GPADC] = { 0x0ec, BIT(16) }, + [RST_R_BUS_THS] = { 0x0fc, BIT(16) }, + [RST_R_BUS_DMA] = { 0x10c, BIT(16) }, + [RST_R_BUS_PWM] = { 0x13c, BIT(16) }, + [RST_R_BUS_CODEC] = { 0x14c, BIT(16) }, + [RST_R_BUS_DMIC] = { 0x15c, BIT(16) }, + [RST_R_BUS_LRADC] = { 0x16c, BIT(16) }, + [RST_R_BUS_I2S] = { 0x17c, BIT(16) }, + [RST_R_BUS_UART] = { 0x18c, BIT(16) }, + [RST_R_BUS_I2C] = { 0x19c, BIT(16) }, + [RST_R_BUS_IR] = { 0x1cc, BIT(16) }, + [RST_R_BUS_MSGBOX] = { 0x1dc, BIT(16) }, + [RST_R_BUS_SPINLOCK] = { 0x1ec, BIT(16) }, + [RST_R_BUS_RTC] = { 0x20c, BIT(16) }, +}; + +static const struct sunxi_ccu_desc sun50i_r329_r_ccu_desc = { + .ccu_clks = sun50i_r329_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_r329_r_ccu_clks), + + .hw_clks = &sun50i_r329_r_hw_clks, + + .resets = sun50i_r329_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_r329_r_ccu_resets), +}; + +static const u32 pll_regs[] = { + SUN50I_R329_PLL_CPUX_REG, + SUN50I_R329_PLL_PERIPH_REG, + SUN50I_R329_PLL_AUDIO0_REG, + SUN50I_R329_PLL_AUDIO1_REG, +}; + +static void __init sun50i_r329_r_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + int i; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%pOF: Could not map clock registers\n", node); + return; + } + + /* Enable the lock bits and the output enable bits on all PLLs */ + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { + val = readl(reg + pll_regs[i]); + val |= BIT(29) | BIT(27); + writel(val, reg + pll_regs[i]); + } + + /* + * Force the I/O dividers of PLL-AUDIO1 to reset default value + * + * See the comment before pll-audio1 definition for the reason. + */ + + val = readl(reg + SUN50I_R329_PLL_AUDIO1_REG); + val &= ~BIT(1); + val |= BIT(0); + writel(val, reg + SUN50I_R329_PLL_AUDIO1_REG); + + i = sunxi_ccu_probe(node, reg, &sun50i_r329_r_ccu_desc); + if (i) + pr_err("%pOF: probing clocks fails: %d\n", node, i); +} + +CLK_OF_DECLARE(sun50i_r329_r_ccu, "allwinner,sun50i-r329-r-ccu", + sun50i_r329_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-r329-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-r329-r.h new file mode 100644 index 000000000000..62cf65322116 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun50i-r329-r.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Sipeed + */ + +#ifndef _CCU_SUN50I_R329_R_H +#define _CCU_SUN50I_R329_R_H + +#include +#include + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_PERIPH_BASE 1 +#define CLK_PLL_PERIPH_2X 2 +#define CLK_PLL_PERIPH_800M 3 +#define CLK_PLL_PERIPH 4 +#define CLK_PLL_AUDIO0 5 +#define CLK_PLL_AUDIO0_DIV2 6 +#define CLK_PLL_AUDIO0_DIV5 7 +#define CLK_PLL_AUDIO1_4X 8 +#define CLK_PLL_AUDIO1_2X 9 +#define CLK_PLL_AUDIO1 10 +#define CLK_R_AHB 11 + +/* R_APB1 exported for PIO */ + +#define CLK_R_APB2 13 + +/* All module / bus gate clocks exported */ + +#define CLK_NUMBER (CLK_R_BUS_RTC + 1) + +#endif /* _CCU_SUN50I_R329_R_H */ diff --git a/include/dt-bindings/clock/sun50i-r329-r-ccu.h b/include/dt-bindings/clock/sun50i-r329-r-ccu.h new file mode 100644 index 000000000000..df9bc58de5c4 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-r329-r-ccu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Sipeed + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_R329_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_R329_R_CCU_H_ + +#define CLK_R_APB1 12 + +#define CLK_R_BUS_GPADC 14 +#define CLK_R_BUS_THS 15 +#define CLK_R_BUS_DMA 16 +#define CLK_R_PWM 17 +#define CLK_R_BUS_PWM 18 +#define CLK_R_CODEC_ADC 19 +#define CLK_R_CODEC_DAC 20 +#define CLK_R_BUS_CODEC 21 +#define CLK_R_DMIC 22 +#define CLK_R_BUS_DMIC 23 +#define CLK_R_BUS_LRADC 24 +#define CLK_R_I2S 25 +#define CLK_R_I2S_ASRC 26 +#define CLK_R_BUS_I2S 27 +#define CLK_R_BUS_UART 28 +#define CLK_R_BUS_I2C 29 +#define CLK_R_IR 30 +#define CLK_R_BUS_IR 31 +#define CLK_R_BUS_MSGBOX 32 +#define CLK_R_BUS_SPINLOCK 33 +#define CLK_R_BUS_RTC 34 + +#endif /* _DT_BINDINGS_CLK_SUN50I_R329_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-r329-r-ccu.h b/include/dt-bindings/reset/sun50i-r329-r-ccu.h new file mode 100644 index 000000000000..40644f2f21c6 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-r329-r-ccu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2021 Sipeed + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_R329_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_R329_R_CCU_H_ + +#define RST_R_BUS_GPADC 0 +#define RST_R_BUS_THS 1 +#define RST_R_BUS_DMA 2 +#define RST_R_BUS_PWM 3 +#define RST_R_BUS_CODEC 4 +#define RST_R_BUS_DMIC 5 +#define RST_R_BUS_LRADC 6 +#define RST_R_BUS_I2S 7 +#define RST_R_BUS_UART 8 +#define RST_R_BUS_I2C 9 +#define RST_R_BUS_IR 10 +#define RST_R_BUS_MSGBOX 11 +#define RST_R_BUS_SPINLOCK 12 +#define RST_R_BUS_RTC 13 + +#endif /* _DT_BINDINGS_RST_SUN50I_R329_R_CCU_H_ */ From patchwork Mon Aug 2 06:22:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92C06C4338F for ; Mon, 2 Aug 2021 06:23:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7997560FC1 for ; Mon, 2 Aug 2021 06:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232330AbhHBGXZ (ORCPT ); Mon, 2 Aug 2021 02:23:25 -0400 Received: from smtpbg126.qq.com ([106.55.201.22]:28000 "EHLO smtpbg587.qq.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232305AbhHBGXV (ORCPT ); Mon, 2 Aug 2021 02:23:21 -0400 X-QQ-mid: bizesmtp41t1627885378thkqeux2 Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:22:57 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: zuISFTXeVwLI7T7y7eeg4g78iC351nEVHKQd2b+SncmfD3a+XPdRldWBHL5MP U+jKj8T2vm+sT1R4NldxCktYHKAPu5c/UfCarfief8tPYl50Xoqzs4DSt5s9XXdwmmVL51Q b+VorZom+X2Q86oOr27dY8kNUaK6+/0ksH1sCse47cdnapwVWmzK9PpJ38dQbsdaVd0LIZH lX7J+3pJJAoKPXjyTbyBzy6sSf3JafkX/MJdLOvzY4+JvCDG7AWrICMCD4BYty3qHcVLYlL 1uMggGxxMV963YowffSGLScmf1pRDxMvCn0t8dbs9JCR4PUXG4Wd2+l6O8r3KYRlLM8711+ DOI7BmrqhOw0dTh7ok= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 12/17] dt-bindings: mmc: sunxi-mmc: add R329 MMC compatible string Date: Mon, 2 Aug 2021 14:22:07 +0800 Message-Id: <20210802062212.73220-13-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org R329 SoC has two MMC controllers similar to ones in the previous Allwinner SoCs. However, as R329 has no eMMC controller, the two MMC controllers look like a mixture of previous SoCs' ordinary MMC controller and eMMC controller. Add a compatible string for R329 MMC controllers. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Acked-by: Maxime Ripard --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 4f62ad6ce50c..3e8c3c747a9b 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -28,6 +28,7 @@ properties: - const: allwinner,sun50i-a64-mmc - const: allwinner,sun50i-a100-emmc - const: allwinner,sun50i-a100-mmc + - const: allwinner,sun50i-r329-mmc - items: - const: allwinner,sun8i-a83t-mmc - const: allwinner,sun7i-a20-mmc From patchwork Mon Aug 2 06:22:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 490461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC99BC432BE for ; Mon, 2 Aug 2021 06:31:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4CCF61050 for ; Mon, 2 Aug 2021 06:31:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232389AbhHBGbl (ORCPT ); Mon, 2 Aug 2021 02:31:41 -0400 Received: from smtpbg587.qq.com ([113.96.223.105]:36739 "EHLO smtpbg587.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232334AbhHBGbk (ORCPT ); Mon, 2 Aug 2021 02:31:40 -0400 X-QQ-mid: bizesmtp41t1627885384tved9odr Received: from localhost.localdomain (unknown [113.89.245.207]) by esmtp6.qq.com (ESMTP) with id ; Mon, 02 Aug 2021 14:23:03 +0800 (CST) X-QQ-SSF: 01100000002000206000B00A0000000 X-QQ-FEAT: QGWlG8nlCFgleCPruuQmzR0U8s4zkQHYElEYonj/YF2MwZnAezFr2N4+nxZx3 ows+kwHo5BfXQl8Uz8dKuxrt9r9Z85NPRio61rKxMxp8KoYlJkQy4pjRJJECQi8VSu0RxkF lxfnSfjYyEKWo10akpPVRdaetk0bijChQHOth8uP9+3xuyE1UJSY9Z5MZ7qW+p5gbsjB07K 7+AeeFVkKZ8AwEFezTQYIc31qntycD9bHvOWlJGO1rU/U5VmWLMwsnWpVLHE/yv7wg8qENw Bd7EZsBclM6J/aOim3b6B9XpHygc5Gi/DPfZxssHh/uA35+tZz7Ecgt7OLNlLVYsr8E0BRr w5KV1ymYde3AwEC5MA= X-QQ-GoodBg: 0 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 14/17] dt-bindings: arm: sunxi: add compatible strings for Sipeed MaixSense Date: Mon, 2 Aug 2021 14:22:09 +0800 Message-Id: <20210802062212.73220-15-icenowy@sipeed.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com> References: <20210802062212.73220-1-icenowy@sipeed.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:sipeed.com:qybgspam:qybgspam3 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sipeed MaixSense is an Allwinner R329 development kit based on Maix IIA SoM. Add compatible strings for it. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 889128acf49a..bce306908eff 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -444,6 +444,12 @@ properties: - const: haoyu,a10-marsboard - const: allwinner,sun4i-a10 + - description: Sipeed MaixSense + items: + - const: sipeed,maixsense + - const: sipeed,maix-iia + - const: allwinner,sun50i-r329 + - description: MapleBoard MP130 items: - const: mapleboard,mp130