From patchwork Tue Aug 3 10:16:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 490894 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp506041jap; Tue, 3 Aug 2021 03:17:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2mj/4CM0v0Vu9rjiM9Kp8LfXyyPep3japVZpEhH3viGISRFkkYQrBIA/xWLmNJd/w5AHK X-Received: by 2002:a05:6402:7c9:: with SMTP id u9mr24792842edy.387.1627985824589; Tue, 03 Aug 2021 03:17:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627985824; cv=none; d=google.com; s=arc-20160816; b=f0rC4DWRwm7RR1JqmOf8kbVycGSZyTu5NYvV9cNvb/ebo+fQoshqTBqR5LQ2G/HSMV Voz8xCFQFVMd4zQ+YH3K6m5stk/jGodtTx4CujmIXcHkI0IZ89kL4CoHjLFBWb5618c1 EGTMFffyL2lhrdXiewabvYVSJcA3COSGD9wzca3tVxA/g7NrOXdf21Fkbn1s//6d4aM/ iTVvkjzefgItGiNvJbN7OneBs8Lfn/74M8sqPkuIWBgBukRFiRCMS4Or71JEgxpw1Znq 6a6MocGwEO3BiwEtlL/T+gxE0ahN06p8kl+rb0OYjbDRLEITLpYDYSQAt6PwIGD3rA8c fXRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EzY4uoCv+IHNgvq1aFlTjsbb98p1R6pm524do6Rg7Dw=; b=HEN2/i9S5ld7VfQUqp1Onfs+PIUpAFVfWhZts/F82tvrVINW/F31Trk1Z/4wmcKeel RDvwCgiy8KQ0ke7JLWLJYs3TyP15B1/F+cNONE0P5gmJZSr4DTI2wawujQJWPxmstfQV Ze/vv1IyN2JNfYkkrZuPUo06X2nE0Kk139uQUKNmOdQOYZ6jEKs+exaV+H6g3PtNcJQs Fu/6ZpA7WHLCM1yoT/zPgGgXiaSJkT5DZsAISsHqLtOpBwVNczRHVO2KIMVZXknWr3Hu XgkLwPEwQwGCJjxb3xb2rxzOsKqZ6Tb/53awbulNVpd3QtXq5KSG9hzlN3Fiwg0nMk46 i9aA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zKuD44Y8; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, move the clock node to mdp device from where the votes are requested. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1796ae8372be..9e77a323b1cd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4148,9 +4148,8 @@ mdss: mdss@ae00000 { power-domains = <&dispcc MDSS_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; + clock-names = "iface", "core"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; assigned-clock-rates = <300000000>; @@ -4178,11 +4177,12 @@ mdss_mdp: mdp@ae01000 { <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; From patchwork Tue Aug 3 10:16:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 490893 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp506036jap; Tue, 3 Aug 2021 03:17:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxWhotrzUBhI+GzQn3nNbKpQYSxLI81zrRfHXtrJ31U/O8MxPGCmY80BXsfKAzUcARF90oc X-Received: by 2002:a05:6402:2714:: with SMTP id y20mr24808479edd.190.1627985824107; Tue, 03 Aug 2021 03:17:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627985824; cv=none; d=google.com; s=arc-20160816; b=Zpp3gBH+CoQtRGq+e9emFFf1FCQoMTHlVj+HFoBQcC2dP50lfqDjrAKpyDxv1qy84W 49fPsjBz0w2YMUii8Nx+WpK0hHIZVhlhq4nklyXj19Uio3YeM3CWVvFhvemcGJWtfWNp fUakZrarAp/TEISQxhk7TAe/szevz/5SLekVQHRmOgAShseqW9VYBxBhFBf2+DdCJsGc mULy7bTt+bJYXvgEu0SUylB0f+suE2uCyulB0A9w2Om7T/Szejc8uzEic9zU6w33LqBg FCFVQPMKwwMKYCbhhDt2MkEg588Jsfnwdd4FFw0jE8YuhK07Tsv+cE8lmoUaljc56AZj +GEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FsJoAIH4S+RjxCze2qp1zowJ52+FjRKDga6SkA/wG7k=; b=ctC0i61nwpqg0412xdGsPIGtvh+YyB0GvyDXIEIjLx4ZUZuPpk1oWszbktRgLdmGAA E3SkFyreIBoQ6euPiZaDH7etTi9bzn71ARKk4JrdoBnMVy9ViOjO2Alrk30LyHIKYJby uP+9rjSpFWK22QTSkbFDuGHN6TlGLrHh7wFJLh5KRInCwvDXdx8hwfvG4xIz+nhTTqGu xL+RhkQ7SHP9p2RdFo1OyF+FHN1xy8pPy8/+uNG+MFS2/o2UM9ICSvK0BKiS4hL4BvoS 7hUBKnY9LvUcJG6MKiUJRsWPlGNdiEHaEpDY0SsCQq9V8YR5ZwBlqMy5AWouGwwZ9ceJ C21Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LI7tJOw3; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, and since mdp device node already has the bus clock, remove the clock from the mdss device. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4798368b02ef..1df03c809d02 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2470,10 +2470,9 @@ mdss: mdss@ae00000 { power-domains = <&dispcc MDSS_GDSC>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "nrt_bus", "core"; + clock-names = "iface", "nrt_bus", "core"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; assigned-clock-rates = <460000000>;