From patchwork Fri Sep 21 10:21:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147191 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp627847ljw; Fri, 21 Sep 2018 03:23:12 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdbf/fiPr318cI89TZBQ6DQObq/bFZb6jTjTvoe0qoion4isQaczp48HO0jMmmk6Iw48ede0 X-Received: by 2002:a17:902:292b:: with SMTP id g40-v6mr43257651plb.223.1537525392543; Fri, 21 Sep 2018 03:23:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525392; cv=none; d=google.com; s=arc-20160816; b=Nuq0r64UETtFSOesCDzhfQuOJpSNrn53+IdqaT1QDMZEIXq6fSpi3IQ0NUOd6PL+T0 C6rZalBwIsRISR1BQQRNq+S3N0Z3v8/+Kkv3JXttIpE+VH1X5eR6/Ps6K2EELF1Uo+Fz NsDcucuwlUkoeKA0zhTgUvLqqxqjRUkA5AGvi7tAwHBbG+9l2jl0/jY9EMY3rrh03laX 5t4NM7nKhhPzqW7rT2togFd+teLJ3ZB6J87pOnVx9ZGwfoUvNA3NUx1jq9iJeMzp5K/t tOAlDlH+GP4AMOQ2E4AauYgnEYc2vIz5XypBbGX9+l5O0wtWN3JwrOoxlMa7o9UyxiLB uiTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=AaI+OUZrQckJEDBIOcs2LNPZPM6sJdBLjz7B6GKG/q8=; b=nYbB9UGXFCLF7HJY9QOiUiuP/YXGzGFYI6wFQVk1/gbdVsg7WUIr9HQooA/H39ciEJ VDDx/sMjrkIp3PUDa0wUFVxAsGq8SHWFlbdhtONiSpTDDTsBHVHdo/Kk3ZKpX63n3M+e kpsYytPLIr6QbkFR/rhf6MFdq6OL4mvh7GI6BcjKcpsb/sctt826FLGGzl9UnKe7EwS9 J/JUFppqG4qNJPARKD5KYp9/GL2nv5fhB5v785KJNJRUpJmKzLMY3E2h6IcZfpshza43 kTtoerMK0IuvNlcMfH6h1Tn4lfdh2WMLGfg72EIBpdYfCpab6xOCFeKcZvCFy3PpEdlm 7mbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ykbg04nT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 7-v6si25437828pgq.637.2018.09.21.03.23.12; Fri, 21 Sep 2018 03:23:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ykbg04nT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389697AbeIUQLU (ORCPT + 32 others); Fri, 21 Sep 2018 12:11:20 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51242 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389621AbeIUQLU (ORCPT ); Fri, 21 Sep 2018 12:11:20 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMchP032991; Fri, 21 Sep 2018 05:22:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525358; bh=AaI+OUZrQckJEDBIOcs2LNPZPM6sJdBLjz7B6GKG/q8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ykbg04nTQdWsf7ECi1I5PUBmnnoYKpClPfZpS1pZ2BBiQBENQcBhF6zw9EkrZC1e4 cZCkoxIpGdcYyowfkRTf5HArwC2go4AZy84OgmWWJy4GKZJZ5qAsTUhVjKTpfK08wb UrVqAYBwWsaYxrpz7vMKj7OmYtp9GBdpkzgUo3ag= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMcGv028922; Fri, 21 Sep 2018 05:22:38 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:38 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:38 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt8032280; Fri, 21 Sep 2018 05:22:34 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 04/40] PCI: keystone: Do not initiate link training multiple times Date: Fri, 21 Sep 2018 15:51:19 +0530 Message-ID: <20180921102155.22839-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 886bc5ceb5cc3ad4b219502d72 ("PCI: designware: Add generic dw_pcie_wait_for_link()") while adding a generic dw_pcie_wait_for_link() performed a special handling (initiate link training multiple times) for keystone which is not required. This also resulted in unncessarily waiting for more time to establish the link even when no PCI device is connected. Remove it and make it look similar to other dwc based PCIe drivers. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fec46cfccba5..aa7e706fc37d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -86,21 +86,18 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; - unsigned int retries; if (dw_pcie_link_up(pci)) { dev_info(dev, "Link already up\n"); return 0; } + ks_dw_pcie_initiate_link_train(ks_pcie); + /* check if the link is up or not */ - for (retries = 0; retries < 5; retries++) { - ks_dw_pcie_initiate_link_train(ks_pcie); - if (!dw_pcie_wait_for_link(pci)) - return 0; - } + if (!dw_pcie_wait_for_link(pci)) + return 0; dev_err(dev, "phy link never came up\n"); return -ETIMEDOUT; From patchwork Fri Sep 21 10:21:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147193 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628232ljw; Fri, 21 Sep 2018 03:23:39 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbQSZshpXiHxYxgUMYQoEEh9isXjGANLyEnWueBKKN57cBBxzwUhvc4onYVpgtifX9nFKE1 X-Received: by 2002:a17:902:7b97:: with SMTP id w23-v6mr43819784pll.66.1537525419440; Fri, 21 Sep 2018 03:23:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525419; cv=none; d=google.com; s=arc-20160816; b=tssNuMhtJY8XFDT2rjdduqluh+ScxNhfSzHo2VCjPNw83rBT5HbABT8b0bLJ08p7Cj JsotXkXLaAjG/RfbgRETzRHOf3CwlDkhELMYEw8O46B+/Io2Ueb6zsxgiQBwpWbsAPrd 2WdFHW/i7TG9alAKbN1TMk9QfZfrehfCq/xgXDsiw+3lwwgTCjl6OXEzZJR9ESp+2bw7 oQdRa3ge+U+x7TdgiEWsztcLG5mpsurQgKyKWT80oTCMZL6nEvcugxs4l2kPsWyVoayM CdKqarSdo+6val5oE3/wwalpK9XU8thD+b4PjrnkUjaWWw7e1JO7CrvFVTTqgIMAcngY XQag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=NL93FqjXfL5GmS7Q7CEcO9WJ0fDK7IYqMoegnb1ILGg=; b=vLJnD3ZbX/46icPDip4wmgEqbCNUCBdNwjN1z8N/TJNKkA5EBU9CbOwJB+lLN2Vjef hxFpdJD2OqyRAqqiUzwpoQLdWoxDhgaoQUiCUPQvyHrCmfwG1B8lU2F3H+NEwmK36baW Mg4Dlrj5jFD+s3XZAfD0X0wodQWeGKfxuuZzVMljxRU7Gz6VdnBNf+X/XpM2Zqcu7N5B 8SrSoaqAsLuY3LqtbzJ3WHqiA40Oa58I3mI+3DNLIW9FCnYPSi6hvGc3+OSOgZajm0yw M/ECR1tHkC++p3dZ559T45z1r4XrMZY6dlPz8RzTlgrBcM+w1VZ1WQGs2+UhEtdme5qO LEHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hCY2Sf3I; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id be5-v6si26648970plb.67.2018.09.21.03.23.39; Fri, 21 Sep 2018 03:23:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hCY2Sf3I; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389757AbeIUQLt (ORCPT + 32 others); Fri, 21 Sep 2018 12:11:49 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34992 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727554AbeIUQLs (ORCPT ); Fri, 21 Sep 2018 12:11:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMh5N030320; Fri, 21 Sep 2018 05:22:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525363; bh=NL93FqjXfL5GmS7Q7CEcO9WJ0fDK7IYqMoegnb1ILGg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hCY2Sf3IkOVIecI4m+NWXpJxekwQTDmLO2KQqqP0uYej6W1BTlkKq4SBjK9TSzwpb yeJCAxZMN+rsQwDXcpY89I8ekXliH0M1zrHVS57jvjgzz3Wws/z7rI9zQCwfJKRGHf cA63iWRjOlYpqdsbizmQWSVw5GiH84QkkAJVh9kU= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMgms017638; Fri, 21 Sep 2018 05:22:42 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:42 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:42 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEt9032280; Fri, 21 Sep 2018 05:22:38 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 05/40] PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() Date: Fri, 21 Sep 2018 15:51:20 +0530 Message-ID: <20180921102155.22839-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Remove unused "msi_intc_np" argument from ks_dw_pcie_host_init(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone-dw.c | 3 +-- drivers/pci/controller/dwc/pci-keystone.c | 2 +- drivers/pci/controller/dwc/pci-keystone.h | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c index 0682213328e9..4bd6c6e2b177 100644 --- a/drivers/pci/controller/dwc/pci-keystone-dw.c +++ b/drivers/pci/controller/dwc/pci-keystone-dw.c @@ -439,8 +439,7 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) * and call dw_pcie_v3_65_host_init() API to initialize the Keystone * PCI host controller. */ -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, - struct device_node *msi_intc_np) +int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index aa7e706fc37d..f87ade2de711 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -341,7 +341,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, } pp->ops = &keystone_pcie_host_ops; - ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np); + ret = ks_dw_pcie_host_init(ks_pcie); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; diff --git a/drivers/pci/controller/dwc/pci-keystone.h b/drivers/pci/controller/dwc/pci-keystone.h index 8a13da391543..4eacc263f157 100644 --- a/drivers/pci/controller/dwc/pci-keystone.h +++ b/drivers/pci/controller/dwc/pci-keystone.h @@ -41,8 +41,7 @@ void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie); void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset); void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie); irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie); -int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, - struct device_node *msi_intc_np); +int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie); int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, From patchwork Fri Sep 21 10:21:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147194 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628286ljw; Fri, 21 Sep 2018 03:23:43 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZsZsgE7pVOpdpiOwH0zsKHfI0cljuBN0oEerpxJsWU9uvADk+hP6PKGyRXxgQl1wFNod+8 X-Received: by 2002:a62:2119:: with SMTP id h25-v6mr46511453pfh.112.1537525422895; Fri, 21 Sep 2018 03:23:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525422; cv=none; d=google.com; s=arc-20160816; b=jliH3t7a2jPheIEDBCvBsuBNq9YcMamXogJQ9HnoOb99TxnKyeR93dCEyXC3GRs1KV cTW/rTRvZZq9JKUAUqDaPXtTs1o3uL42GDzxh2LbWIFOggSaZAa/+WgojRoWqGJGbEMA JpAtrSwFMy3BvTuBkP36bdbi4g6gQ0yi84ek/KFfv0+2G5ByAIALmHBAqbui/FIW5mQf KsaK6c9nleIvKFVR6YpP5lqvMYnytTUp3q8iSq/SvxATl+CClbaf7pb6a/+6XKsUs75x 110yR57VrGQGp0QNGxbgmERu96qirSEQtmlnJItNYcKgPHWGIwOnWu3/b2+7pGCjN9PV S67g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+JP9mVYOekfJBvJujjojWZ3FMQbKVAMaaTSl9wsQ4nA=; b=uOCJkk5YWEkMvveZycBj49Kj3JpiYI+sQr3+OkclW2Jfymr8CZwIeQeOgh9j5yGk3l y4e3vyZGDSK9bkmKvE4usiYAVGtyVL+PjIYUlxmW65kZDnWla+ZMhc2DJ4ok7KGiPCGk Cw5oLZpxTvcOTsHFtsXknApOAKnI5w1cg0Bs+e8VF01SMOsBe3cmLJ99KIQk6doiovZW UD4WVS41SBrBrXKM+kZMnWFmdhnYdm4lRz2rMTJfupWQaTEvjqJ0lWDpa1wM6NwOlVNe k1DdwPWlZKT5Oxd9Py86wLnLGhmo46qDgZIUpBgqMO80D8Vzp4y7fp0WCw3EExiU/Y1F /T1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=upjlIGZs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This will also be required for adding EP support. While at that also use BIT() for LTSSM_EN_VAL. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone-dw.c | 9 +++- drivers/pci/controller/dwc/pci-keystone.c | 51 +++++++++++--------- drivers/pci/controller/dwc/pci-keystone.h | 3 +- 3 files changed, 38 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c index 4bd6c6e2b177..ce399232cd99 100644 --- a/drivers/pci/controller/dwc/pci-keystone-dw.c +++ b/drivers/pci/controller/dwc/pci-keystone-dw.c @@ -21,7 +21,7 @@ #include "pci-keystone.h" /* Application register defines */ -#define LTSSM_EN_VAL 1 +#define LTSSM_EN_VAL BIT(0) #define LTSSM_STATE_MASK 0x1f #define LTSSM_STATE_L0 0x11 #define DBI_CS2_EN_VAL 0x20 @@ -418,7 +418,7 @@ int ks_dw_pcie_link_up(struct dw_pcie *pci) return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) +void ks_dw_pcie_stop_link(struct keystone_pcie *ks_pcie) { u32 val; @@ -426,6 +426,11 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) val = ks_dw_app_readl(ks_pcie, CMD_STATUS); val &= ~LTSSM_EN_VAL; ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +void ks_dw_pcie_start_link(struct keystone_pcie *ks_pcie) +{ + u32 val; /* Initiate Link Training */ val = ks_dw_app_readl(ks_pcie, CMD_STATUS); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index f87ade2de711..24afc691443b 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -40,6 +40,9 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +static int ks_pcie_start_link(struct dw_pcie *pci); +static void ks_pcie_stop_link(struct dw_pcie *pci); + static void quirk_limit_mrrs(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; @@ -83,26 +86,6 @@ static void quirk_limit_mrrs(struct pci_dev *dev) } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - - if (dw_pcie_link_up(pci)) { - dev_info(dev, "Link already up\n"); - return 0; - } - - ks_dw_pcie_initiate_link_train(ks_pcie); - - /* check if the link is up or not */ - if (!dw_pcie_wait_for_link(pci)) - return 0; - - dev_err(dev, "phy link never came up\n"); - return -ETIMEDOUT; -} - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { unsigned int irq = irq_desc_get_irq(desc); @@ -263,7 +246,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_pcie_establish_link(ks_pcie); ks_dw_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), @@ -279,7 +261,8 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); - return 0; + ks_pcie_start_link(pci); + return dw_pcie_wait_for_link(pci); } static const struct dw_pcie_host_ops keystone_pcie_host_ops = { @@ -358,7 +341,31 @@ static const struct of_device_id ks_pcie_of_match[] = { { }, }; +static int ks_pcie_start_link(struct dw_pcie *pci) +{ + struct device *dev = pci->dev; + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + if (dw_pcie_link_up(pci)) { + dev_WARN(dev, "Link already up\n"); + return 0; + } + + ks_dw_pcie_start_link(ks_pcie); + + return 0; +} + +static void ks_pcie_stop_link(struct dw_pcie *pci) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + ks_dw_pcie_stop_link(ks_pcie); +} + static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = ks_pcie_start_link, + .stop_link = ks_pcie_stop_link, .link_up = ks_dw_pcie_link_up, }; diff --git a/drivers/pci/controller/dwc/pci-keystone.h b/drivers/pci/controller/dwc/pci-keystone.h index 4eacc263f157..a66deab626aa 100644 --- a/drivers/pci/controller/dwc/pci-keystone.h +++ b/drivers/pci/controller/dwc/pci-keystone.h @@ -47,7 +47,8 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie); -void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie); +void ks_dw_pcie_start_link(struct keystone_pcie *ks_pcie); +void ks_dw_pcie_stop_link(struct keystone_pcie *ks_pcie); void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp); void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq); void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq); From patchwork Fri Sep 21 10:21:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147207 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629263ljw; Fri, 21 Sep 2018 03:24:49 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbuvaST0zjygZowjiuRlvsx9TSgS1RKkVkXaFbPNTQaUtZVEF/TXxoiTUJt9EoxRJV5Iick X-Received: by 2002:a17:902:b28:: with SMTP id 37-v6mr43997338plq.337.1537525489498; Fri, 21 Sep 2018 03:24:49 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id b3-v6si6006772pld.36.2018.09.21.03.24.49; Fri, 21 Sep 2018 03:24:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LTkQUKCO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390148AbeIUQM7 (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:59 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51450 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390105AbeIUQM6 (ORCPT ); Fri, 21 Sep 2018 12:12:58 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAMqtL033026; Fri, 21 Sep 2018 05:22:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525372; bh=Z+MFySZyPRhvCA1QI7nKFOZmPGi/x8HAq8zzjQbKEVk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LTkQUKCOlagYUO0TbDd/8oJIqhCEMMNILOSnKMNyymUCzPUuyqaHt9vLy54a1/DSy vLp9NKWLoesgXIfbkij005h7LCCN5AU9Y0mm7JgVsQCme/XfM9hIKFoYpkyRRtoilJ 8e3y9Pgk4MpxNHMpJWqIjxhxJOMtFyJWLqzHPJoo= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMq79017745; Fri, 21 Sep 2018 05:22:52 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:22:51 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:22:51 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtB032280; Fri, 21 Sep 2018 05:22:47 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 07/40] PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c Date: Fri, 21 Sep 2018 15:51:22 +0530 Message-ID: <20180921102155.22839-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Having two different files for keystone PCI driver doesn't serve any purpose. Merge pci-keystone-dw.c and pci-keystone.c into a single pci-keystone.c file and remove pci-keystone.h Signed-off-by: Kishon Vijay Abraham I --- The "CHECK:" warnings here by checkpatch.pl will be fixed in the later part of the series. MAINTAINERS | 2 +- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pci-keystone-dw.c | 488 ------------------ drivers/pci/controller/dwc/pci-keystone.c | 493 ++++++++++++++++++- drivers/pci/controller/dwc/pci-keystone.h | 57 --- 5 files changed, 494 insertions(+), 548 deletions(-) delete mode 100644 drivers/pci/controller/dwc/pci-keystone-dw.c delete mode 100644 drivers/pci/controller/dwc/pci-keystone.h -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index a5b256b25905..3101b2fa3449 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11172,7 +11172,7 @@ M: Murali Karicheri L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: drivers/pci/controller/dwc/*keystone* +F: drivers/pci/controller/dwc/pci-keystone.c PCI ENDPOINT SUBSYSTEM M: Kishon Vijay Abraham I diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 5d2ce72c7a52..fcf91eacfc63 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o -obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o +obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c deleted file mode 100644 index ce399232cd99..000000000000 --- a/drivers/pci/controller/dwc/pci-keystone-dw.c +++ /dev/null @@ -1,488 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DesignWare application register space functions for Keystone PCI controller - * - * Copyright (C) 2013-2014 Texas Instruments., Ltd. - * http://www.ti.com - * - * Author: Murali Karicheri - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pcie-designware.h" -#include "pci-keystone.h" - -/* Application register defines */ -#define LTSSM_EN_VAL BIT(0) -#define LTSSM_STATE_MASK 0x1f -#define LTSSM_STATE_L0 0x11 -#define DBI_CS2_EN_VAL 0x20 -#define OB_XLAT_EN_VAL 2 - -/* Application registers */ -#define CMD_STATUS 0x004 -#define CFG_SETUP 0x008 -#define OB_SIZE 0x030 -#define CFG_PCIM_WIN_SZ_IDX 3 -#define CFG_PCIM_WIN_CNT 32 -#define SPACE0_REMOTE_CFG_OFFSET 0x1000 -#define OB_OFFSET_INDEX(n) (0x200 + (8 * n)) -#define OB_OFFSET_HI(n) (0x204 + (8 * n)) - -/* IRQ register defines */ -#define IRQ_EOI 0x050 -#define IRQ_STATUS 0x184 -#define IRQ_ENABLE_SET 0x188 -#define IRQ_ENABLE_CLR 0x18c - -#define MSI_IRQ 0x054 -#define MSI0_IRQ_STATUS 0x104 -#define MSI0_IRQ_ENABLE_SET 0x108 -#define MSI0_IRQ_ENABLE_CLR 0x10c -#define IRQ_STATUS 0x184 -#define MSI_IRQ_OFFSET 4 - -/* Error IRQ bits */ -#define ERR_AER BIT(5) /* ECRC error */ -#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ -#define ERR_CORR BIT(3) /* Correctable error */ -#define ERR_NONFATAL BIT(2) /* Non-fatal error */ -#define ERR_FATAL BIT(1) /* Fatal error */ -#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */ -#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ - ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI) -#define ERR_IRQ_STATUS_RAW 0x1c0 -#define ERR_IRQ_STATUS 0x1c4 -#define ERR_IRQ_ENABLE_SET 0x1c8 -#define ERR_IRQ_ENABLE_CLR 0x1cc - -/* Config space registers */ -#define DEBUG0 0x728 - -#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) - -static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, - u32 *bit_pos) -{ - *reg_offset = offset % 8; - *bit_pos = offset >> 3; -} - -phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - return ks_pcie->app.start + MSI_IRQ; -} - -static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset) -{ - return readl(ks_pcie->va_app_base + offset); -} - -static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val) -{ - writel(val, ks_pcie->va_app_base + offset); -} - -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - u32 pending, vector; - int src, virq; - - pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); - - /* - * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit - * shows 1, 9, 17, 25 and so forth - */ - for (src = 0; src < 4; src++) { - if (BIT(src) & pending) { - vector = offset + (src << 3); - virq = irq_linear_revmap(pp->irq_domain, vector); - dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", - src, vector, virq); - generic_handle_irq(virq); - } - } -} - -void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) -{ - u32 reg_offset, bit_pos; - struct keystone_pcie *ks_pcie; - struct dw_pcie *pci; - - pci = to_dw_pcie_from_pp(pp); - ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - - ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), - BIT(bit_pos)); - ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); -} - -void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) -{ - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), - BIT(bit_pos)); -} - -void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) -{ - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), - BIT(bit_pos)); -} - -int ks_dw_pcie_msi_host_init(struct pcie_port *pp) -{ - return dw_pcie_allocate_domains(pp); -} - -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) -{ - int i; - - for (i = 0; i < PCI_NUM_INTX; i++) - ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); -} - -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - u32 pending; - int virq; - - pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); - - if (BIT(0) & pending) { - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); - dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); - generic_handle_irq(virq); - } - - /* EOI the INTx interrupt */ - ks_dw_app_writel(ks_pcie, IRQ_EOI, offset); -} - -void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) -{ - ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); -} - -irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) -{ - u32 status; - - status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; - if (!status) - return IRQ_NONE; - - if (status & ERR_FATAL_IRQ) - dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n", - status); - - /* Ack the IRQ; status bits are RW1C */ - ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status); - return IRQ_HANDLED; -} - -static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d) -{ -} - -static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d) -{ -} - -static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d) -{ -} - -static struct irq_chip ks_dw_pcie_legacy_irq_chip = { - .name = "Keystone-PCI-Legacy-IRQ", - .irq_ack = ks_dw_pcie_ack_legacy_irq, - .irq_mask = ks_dw_pcie_mask_legacy_irq, - .irq_unmask = ks_dw_pcie_unmask_legacy_irq, -}; - -static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d, - unsigned int irq, irq_hw_number_t hw_irq) -{ - irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip, - handle_level_irq); - irq_set_chip_data(irq, d->host_data); - - return 0; -} - -static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = { - .map = ks_dw_pcie_init_legacy_irq_map, - .xlate = irq_domain_xlate_onetwocell, -}; - -/** - * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask - * registers - * - * Since modification of dbi_cs2 involves different clock domain, read the - * status back to ensure the transition is complete. - */ -static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) -{ - u32 val; - - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); - - do { - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - } while (!(val & DBI_CS2_EN_VAL)); -} - -/** - * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode - * - * Since modification of dbi_cs2 involves different clock domain, read the - * status back to ensure the transition is complete. - */ -static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) -{ - u32 val; - - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); - - do { - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - } while (val & DBI_CS2_EN_VAL); -} - -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - u32 start = pp->mem->start, end = pp->mem->end; - int i, tr_size; - u32 val; - - /* Disable BARs for inbound access */ - ks_dw_pcie_set_dbi_mode(ks_pcie); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); - ks_dw_pcie_clear_dbi_mode(ks_pcie); - - /* Set outbound translation size per window division */ - ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); - - tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; - - /* Using Direct 1:1 mapping of RC <-> PCI memory space */ - for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { - ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); - ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); - start += tr_size; - } - - /* Enable OB translation */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); -} - -/** - * ks_pcie_cfg_setup() - Set up configuration space address for a device - * - * @ks_pcie: ptr to keystone_pcie structure - * @bus: Bus number the device is residing on - * @devfn: device, function number info - * - * Forms and returns the address of configuration space mapped in PCIESS - * address space 0. Also configures CFG_SETUP for remote configuration space - * access. - * - * The address space has two regions to access configuration - local and remote. - * We access local region for bus 0 (as RC is attached on bus 0) and remote - * region for others with TYPE 1 access when bus > 1. As for device on bus = 1, - * we will do TYPE 0 access as it will be on our secondary bus (logical). - * CFG_SETUP is needed only for remote configuration access. - */ -static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus, - unsigned int devfn) -{ - u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn); - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - u32 regval; - - if (bus == 0) - return pci->dbi_base; - - regval = (bus << 16) | (device << 8) | function; - - /* - * Since Bus#1 will be a virtual bus, we need to have TYPE0 - * access only. - * TYPE 1 - */ - if (bus != 1) - regval |= BIT(24); - - ks_dw_app_writel(ks_pcie, CFG_SETUP, regval); - return pp->va_cfg0_base; -} - -int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 *val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u8 bus_num = bus->number; - void __iomem *addr; - - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); - - return dw_pcie_read(addr + where, size, val); -} - -int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u8 bus_num = bus->number; - void __iomem *addr; - - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); - - return dw_pcie_write(addr + where, size, val); -} - -/** - * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization - * - * This sets BAR0 to enable inbound access for MSI_IRQ register - */ -void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - /* Configure and set up BAR0 */ - ks_dw_pcie_set_dbi_mode(ks_pcie); - - /* Enable BAR0 */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); - - ks_dw_pcie_clear_dbi_mode(ks_pcie); - - /* - * For BAR0, just setting bus address for inbound writes (MSI) should - * be sufficient. Use physical address to avoid any conflicts. - */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); -} - -/** - * ks_dw_pcie_link_up() - Check if link up - */ -int ks_dw_pcie_link_up(struct dw_pcie *pci) -{ - u32 val; - - val = dw_pcie_readl_dbi(pci, DEBUG0); - return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; -} - -void ks_dw_pcie_stop_link(struct keystone_pcie *ks_pcie) -{ - u32 val; - - /* Disable Link training */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - val &= ~LTSSM_EN_VAL; - ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); -} - -void ks_dw_pcie_start_link(struct keystone_pcie *ks_pcie) -{ - u32 val; - - /* Initiate Link Training */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); -} - -/** - * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware - * - * Ioremap the register resources, initialize legacy irq domain - * and call dw_pcie_v3_65_host_init() API to initialize the Keystone - * PCI host controller. - */ -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; - pp->va_cfg1_base = pp->va_cfg0_base; - - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - - /* Create legacy IRQ domain */ - ks_pcie->legacy_irq_domain = - irq_domain_add_linear(ks_pcie->legacy_intc_np, - PCI_NUM_INTX, - &ks_dw_pcie_legacy_irq_domain_ops, - NULL); - if (!ks_pcie->legacy_irq_domain) { - dev_err(dev, "Failed to add irq domain for legacy irqs\n"); - return -EINVAL; - } - - return dw_pcie_host_init(pp); -} diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 24afc691443b..65ff7a5566b4 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -25,13 +25,62 @@ #include #include "pcie-designware.h" -#include "pci-keystone.h" #define DRIVER_NAME "keystone-pcie" /* DEV_STAT_CTRL */ #define PCIE_CAP_BASE 0x70 +/* Application register defines */ +#define LTSSM_EN_VAL BIT(0) +#define LTSSM_STATE_MASK 0x1f +#define LTSSM_STATE_L0 0x11 +#define DBI_CS2_EN_VAL 0x20 +#define OB_XLAT_EN_VAL 2 + +/* Application registers */ +#define CMD_STATUS 0x004 +#define CFG_SETUP 0x008 +#define OB_SIZE 0x030 +#define CFG_PCIM_WIN_SZ_IDX 3 +#define CFG_PCIM_WIN_CNT 32 +#define SPACE0_REMOTE_CFG_OFFSET 0x1000 +#define OB_OFFSET_INDEX(n) (0x200 + (8 * n)) +#define OB_OFFSET_HI(n) (0x204 + (8 * n)) + +/* IRQ register defines */ +#define IRQ_EOI 0x050 +#define IRQ_STATUS 0x184 +#define IRQ_ENABLE_SET 0x188 +#define IRQ_ENABLE_CLR 0x18c + +#define MSI_IRQ 0x054 +#define MSI0_IRQ_STATUS 0x104 +#define MSI0_IRQ_ENABLE_SET 0x108 +#define MSI0_IRQ_ENABLE_CLR 0x10c +#define IRQ_STATUS 0x184 +#define MSI_IRQ_OFFSET 4 + +/* Error IRQ bits */ +#define ERR_AER BIT(5) /* ECRC error */ +#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ +#define ERR_CORR BIT(3) /* Correctable error */ +#define ERR_NONFATAL BIT(2) /* Non-fatal error */ +#define ERR_FATAL BIT(1) /* Fatal error */ +#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */ +#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ + ERR_NONFATAL | ERR_FATAL | ERR_SYS) +#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI) +#define ERR_IRQ_STATUS_RAW 0x1c0 +#define ERR_IRQ_STATUS 0x1c4 +#define ERR_IRQ_ENABLE_SET 0x1c8 +#define ERR_IRQ_ENABLE_CLR 0x1cc + +/* Config space registers */ +#define DEBUG0 0x728 + +#define MAX_MSI_HOST_IRQS 8 + /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -43,6 +92,448 @@ static int ks_pcie_start_link(struct dw_pcie *pci); static void ks_pcie_stop_link(struct dw_pcie *pci); +struct keystone_pcie { + struct dw_pcie *pci; + struct clk *clk; + /* PCI Device ID */ + u32 device_id; + int num_legacy_host_irqs; + int legacy_host_irqs[PCI_NUM_INTX]; + struct device_node *legacy_intc_np; + + int num_msi_host_irqs; + int msi_host_irqs[MAX_MSI_HOST_IRQS]; + struct device_node *msi_intc_np; + struct irq_domain *legacy_irq_domain; + struct device_node *np; + + int error_irq; + + /* Application register space */ + void __iomem *va_app_base; /* DT 1st resource */ + struct resource app; +}; + +static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, + u32 *bit_pos) +{ + *reg_offset = offset % 8; + *bit_pos = offset >> 3; +} + +static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + return ks_pcie->app.start + MSI_IRQ; +} + +static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset) +{ + return readl(ks_pcie->va_app_base + offset); +} + +static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val) +{ + writel(val, ks_pcie->va_app_base + offset); +} + +static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) +{ + struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; + struct device *dev = pci->dev; + u32 pending, vector; + int src, virq; + + pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); + + /* + * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit + * shows 1, 9, 17, 25 and so forth + */ + for (src = 0; src < 4; src++) { + if (BIT(src) & pending) { + vector = offset + (src << 3); + virq = irq_linear_revmap(pp->irq_domain, vector); + dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", + src, vector, virq); + generic_handle_irq(virq); + } + } +} + +static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) +{ + u32 reg_offset, bit_pos; + struct keystone_pcie *ks_pcie; + struct dw_pcie *pci; + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); + update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + + ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), + BIT(bit_pos)); + ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); +} + +static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) +{ + u32 reg_offset, bit_pos; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), + BIT(bit_pos)); +} + +static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +{ + u32 reg_offset, bit_pos; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), + BIT(bit_pos)); +} + +static int ks_dw_pcie_msi_host_init(struct pcie_port *pp) +{ + return dw_pcie_allocate_domains(pp); +} + +static void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) +{ + int i; + + for (i = 0; i < PCI_NUM_INTX; i++) + ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); +} + +static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, + int offset) +{ + struct dw_pcie *pci = ks_pcie->pci; + struct device *dev = pci->dev; + u32 pending; + int virq; + + pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); + + if (BIT(0) & pending) { + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); + dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); + generic_handle_irq(virq); + } + + /* EOI the INTx interrupt */ + ks_dw_app_writel(ks_pcie, IRQ_EOI, offset); +} + +static void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) +{ + ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); +} + +static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) +{ + u32 status; + + status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; + if (!status) + return IRQ_NONE; + + if (status & ERR_FATAL_IRQ) + dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n", + status); + + /* Ack the IRQ; status bits are RW1C */ + ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status); + return IRQ_HANDLED; +} + +static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d) +{ +} + +static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d) +{ +} + +static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d) +{ +} + +static struct irq_chip ks_dw_pcie_legacy_irq_chip = { + .name = "Keystone-PCI-Legacy-IRQ", + .irq_ack = ks_dw_pcie_ack_legacy_irq, + .irq_mask = ks_dw_pcie_mask_legacy_irq, + .irq_unmask = ks_dw_pcie_unmask_legacy_irq, +}; + +static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw_irq) +{ + irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, d->host_data); + + return 0; +} + +static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = { + .map = ks_dw_pcie_init_legacy_irq_map, + .xlate = irq_domain_xlate_onetwocell, +}; + +/** + * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask + * registers + * + * Since modification of dbi_cs2 involves different clock domain, read the + * status back to ensure the transition is complete. + */ +static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) +{ + u32 val; + + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); + + do { + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + } while (!(val & DBI_CS2_EN_VAL)); +} + +/** + * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode + * + * Since modification of dbi_cs2 involves different clock domain, read the + * status back to ensure the transition is complete. + */ +static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) +{ + u32 val; + + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); + + do { + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + } while (val & DBI_CS2_EN_VAL); +} + +static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; + u32 start = pp->mem->start, end = pp->mem->end; + int i, tr_size; + u32 val; + + /* Disable BARs for inbound access */ + ks_dw_pcie_set_dbi_mode(ks_pcie); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); + ks_dw_pcie_clear_dbi_mode(ks_pcie); + + /* Set outbound translation size per window division */ + ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); + + tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; + + /* Using Direct 1:1 mapping of RC <-> PCI memory space */ + for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { + ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); + ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); + start += tr_size; + } + + /* Enable OB translation */ + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); +} + +/** + * ks_pcie_cfg_setup() - Set up configuration space address for a device + * + * @ks_pcie: ptr to keystone_pcie structure + * @bus: Bus number the device is residing on + * @devfn: device, function number info + * + * Forms and returns the address of configuration space mapped in PCIESS + * address space 0. Also configures CFG_SETUP for remote configuration space + * access. + * + * The address space has two regions to access configuration - local and remote. + * We access local region for bus 0 (as RC is attached on bus 0) and remote + * region for others with TYPE 1 access when bus > 1. As for device on bus = 1, + * we will do TYPE 0 access as it will be on our secondary bus (logical). + * CFG_SETUP is needed only for remote configuration access. + */ +static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus, + unsigned int devfn) +{ + u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn); + struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; + u32 regval; + + if (bus == 0) + return pci->dbi_base; + + regval = (bus << 16) | (device << 8) | function; + + /* + * Since Bus#1 will be a virtual bus, we need to have TYPE0 + * access only. + * TYPE 1 + */ + if (bus != 1) + regval |= BIT(24); + + ks_dw_app_writel(ks_pcie, CFG_SETUP, regval); + return pp->va_cfg0_base; +} + +static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, + u32 *val) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u8 bus_num = bus->number; + void __iomem *addr; + + addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); + + return dw_pcie_read(addr + where, size, val); +} + +static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, + u32 val) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u8 bus_num = bus->number; + void __iomem *addr; + + addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); + + return dw_pcie_write(addr + where, size, val); +} + +/** + * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization + * + * This sets BAR0 to enable inbound access for MSI_IRQ register + */ +static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + /* Configure and set up BAR0 */ + ks_dw_pcie_set_dbi_mode(ks_pcie); + + /* Enable BAR0 */ + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); + + ks_dw_pcie_clear_dbi_mode(ks_pcie); + + /* + * For BAR0, just setting bus address for inbound writes (MSI) should + * be sufficient. Use physical address to avoid any conflicts. + */ + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); +} + +/** + * ks_dw_pcie_link_up() - Check if link up + */ +static int ks_dw_pcie_link_up(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, DEBUG0); + return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; +} + +static void ks_dw_pcie_stop_link(struct keystone_pcie *ks_pcie) +{ + u32 val; + + /* Disable Link training */ + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + val &= ~LTSSM_EN_VAL; + ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +static void ks_dw_pcie_start_link(struct keystone_pcie *ks_pcie) +{ + u32 val; + + /* Initiate Link Training */ + val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +/** + * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware + * + * Ioremap the register resources, initialize legacy irq domain + * and call dw_pcie_v3_65_host_init() API to initialize the Keystone + * PCI host controller. + */ +static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + struct resource *res; + + /* Index 0 is the config reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + /* + * We set these same and is used in pcie rd/wr_other_conf + * functions + */ + pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + pp->va_cfg1_base = pp->va_cfg0_base; + + /* Index 1 is the application reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + /* Create legacy IRQ domain */ + ks_pcie->legacy_irq_domain = + irq_domain_add_linear(ks_pcie->legacy_intc_np, + PCI_NUM_INTX, + &ks_dw_pcie_legacy_irq_domain_ops, + NULL); + if (!ks_pcie->legacy_irq_domain) { + dev_err(dev, "Failed to add irq domain for legacy irqs\n"); + return -EINVAL; + } + + return dw_pcie_host_init(pp); +} + static void quirk_limit_mrrs(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; diff --git a/drivers/pci/controller/dwc/pci-keystone.h b/drivers/pci/controller/dwc/pci-keystone.h deleted file mode 100644 index a66deab626aa..000000000000 --- a/drivers/pci/controller/dwc/pci-keystone.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Keystone PCI Controller's common includes - * - * Copyright (C) 2013-2014 Texas Instruments., Ltd. - * http://www.ti.com - * - * Author: Murali Karicheri - */ - -#define MAX_MSI_HOST_IRQS 8 - -struct keystone_pcie { - struct dw_pcie *pci; - struct clk *clk; - /* PCI Device ID */ - u32 device_id; - int num_legacy_host_irqs; - int legacy_host_irqs[PCI_NUM_INTX]; - struct device_node *legacy_intc_np; - - int num_msi_host_irqs; - int msi_host_irqs[MAX_MSI_HOST_IRQS]; - struct device_node *msi_intc_np; - struct irq_domain *legacy_irq_domain; - struct device_node *np; - - int error_irq; - - /* Application register space */ - void __iomem *va_app_base; /* DT 1st resource */ - struct resource app; -}; - -/* Keystone DW specific MSI controller APIs/definitions */ -void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset); -phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp); - -/* Keystone specific PCI controller APIs */ -void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie); -void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset); -void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie); -irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie); -int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie); -int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 val); -int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 *val); -void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie); -void ks_dw_pcie_start_link(struct keystone_pcie *ks_pcie); -void ks_dw_pcie_stop_link(struct keystone_pcie *ks_pcie); -void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp); -void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq); -void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq); -void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp); -int ks_dw_pcie_msi_host_init(struct pcie_port *pp); -int ks_dw_pcie_link_up(struct dw_pcie *pci); From patchwork Fri Sep 21 10:21:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147227 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp633012ljw; Fri, 21 Sep 2018 03:28:47 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ+ut3PSyf6jolMy3AtyO0Tyzt7+K+dXz9SkN2iDfAOKiZyiTLDnyLkQmghwu22baFvrkwf X-Received: by 2002:a63:fe49:: with SMTP id x9-v6mr10867185pgj.152.1537525727016; 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Fri, 21 Sep 2018 05:22:52 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 08/40] PCI: keystone: Cleanup MSI/legacy interrupt configuration and handling Date: Fri, 21 Sep 2018 15:51:23 +0530 Message-ID: <20180921102155.22839-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that all PCI keystone functionality has been moved to pci-keystone.c, cleanup MSI/legacy interrupt configuration and handling. *) Cleanup macros *) Remove unnecessary structure variables (required when 2 files are used) *) Remove ks_dw_pcie_legacy_irq_chip and use dummy_irq_chip *) Move request_irq of error irq from ks_add_pcie_port to ks_pcie_probe as error_irq is common to both host mode and device mode Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 392 +++++++++------------- 1 file changed, 150 insertions(+), 242 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 65ff7a5566b4..4554fdc6cce1 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -50,17 +50,16 @@ /* IRQ register defines */ #define IRQ_EOI 0x050 -#define IRQ_STATUS 0x184 -#define IRQ_ENABLE_SET 0x188 -#define IRQ_ENABLE_CLR 0x18c - #define MSI_IRQ 0x054 -#define MSI0_IRQ_STATUS 0x104 -#define MSI0_IRQ_ENABLE_SET 0x108 -#define MSI0_IRQ_ENABLE_CLR 0x10c -#define IRQ_STATUS 0x184 +#define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) +#define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) +#define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) #define MSI_IRQ_OFFSET 4 +#define IRQ_STATUS(n) (0x184 + ((n) << 4)) +#define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) +#define INTx_EN BIT(0) + /* Error IRQ bits */ #define ERR_AER BIT(5) /* ECRC error */ #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ @@ -79,8 +78,6 @@ /* Config space registers */ #define DEBUG0 0x728 -#define MAX_MSI_HOST_IRQS 8 - /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -97,30 +94,16 @@ struct keystone_pcie { struct clk *clk; /* PCI Device ID */ u32 device_id; - int num_legacy_host_irqs; - int legacy_host_irqs[PCI_NUM_INTX]; - struct device_node *legacy_intc_np; - - int num_msi_host_irqs; - int msi_host_irqs[MAX_MSI_HOST_IRQS]; + int msi_host_irq; struct device_node *msi_intc_np; struct irq_domain *legacy_irq_domain; struct device_node *np; - int error_irq; - /* Application register space */ void __iomem *va_app_base; /* DT 1st resource */ struct resource app; }; -static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, - u32 *bit_pos) -{ - *reg_offset = offset % 8; - *bit_pos = offset >> 3; -} - static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -139,31 +122,6 @@ static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val) writel(val, ks_pcie->va_app_base + offset); } -static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - u32 pending, vector; - int src, virq; - - pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); - - /* - * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit - * shows 1, 9, 17, 25 and so forth - */ - for (src = 0; src < 4; src++) { - if (BIT(src) & pending) { - vector = offset + (src << 3); - virq = irq_linear_revmap(pp->irq_domain, vector); - dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", - src, vector, virq); - generic_handle_irq(virq); - } - } -} - static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) { u32 reg_offset, bit_pos; @@ -172,11 +130,11 @@ static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) pci = to_dw_pcie_from_pp(pp); ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), - BIT(bit_pos)); - ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_dw_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); + ks_dw_app_writel(ks_pcie, IRQ_EOI, MSI_IRQ_OFFSET + reg_offset); } static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) @@ -185,8 +143,9 @@ static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_dw_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); } @@ -196,8 +155,9 @@ static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_dw_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); } @@ -206,34 +166,6 @@ static int ks_dw_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } -static void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) -{ - int i; - - for (i = 0; i < PCI_NUM_INTX; i++) - ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); -} - -static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, - int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - u32 pending; - int virq; - - pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); - - if (BIT(0) & pending) { - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); - dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); - generic_handle_irq(virq); - } - - /* EOI the INTx interrupt */ - ks_dw_app_writel(ks_pcie, IRQ_EOI, offset); -} - static void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -256,40 +188,6 @@ static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) return IRQ_HANDLED; } -static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d) -{ -} - -static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d) -{ -} - -static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d) -{ -} - -static struct irq_chip ks_dw_pcie_legacy_irq_chip = { - .name = "Keystone-PCI-Legacy-IRQ", - .irq_ack = ks_dw_pcie_ack_legacy_irq, - .irq_mask = ks_dw_pcie_mask_legacy_irq, - .irq_unmask = ks_dw_pcie_unmask_legacy_irq, -}; - -static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d, - unsigned int irq, irq_hw_number_t hw_irq) -{ - irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip, - handle_level_irq); - irq_set_chip_data(irq, d->host_data); - - return 0; -} - -static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = { - .map = ks_dw_pcie_init_legacy_irq_map, - .xlate = irq_domain_xlate_onetwocell, -}; - /** * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask * registers @@ -520,17 +418,6 @@ static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) ks_pcie->app = *res; - /* Create legacy IRQ domain */ - ks_pcie->legacy_irq_domain = - irq_domain_add_linear(ks_pcie->legacy_intc_np, - PCI_NUM_INTX, - &ks_dw_pcie_legacy_irq_domain_ops, - NULL); - if (!ks_pcie->legacy_irq_domain) { - dev_err(dev, "Failed to add irq domain for legacy irqs\n"); - return -EINVAL; - } - return dw_pcie_host_init(pp); } @@ -579,22 +466,32 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { + u32 reg; + u32 vector; + int pos; + int virq; unsigned int irq = irq_desc_get_irq(desc); struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); - u32 offset = irq - ks_pcie->msi_host_irqs[0]; + u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); - dev_dbg(dev, "%s, irq %d\n", __func__, irq); - - /* - * The chained irq handler installation would have replaced normal - * interrupt driver handler so we need to take care of mask/unmask and - * ack operation. - */ chained_irq_enter(chip, desc); - ks_dw_pcie_handle_msi_irq(ks_pcie, offset); + + reg = ks_dw_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); + for (pos = 0; pos < 4; pos++) { + if (!(reg & BIT(pos))) + continue; + + vector = offset + (pos << 3); + virq = irq_linear_revmap(pp->irq_domain, vector); + dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector, + virq); + generic_handle_irq(virq); + } + chained_irq_exit(chip, desc); } @@ -608,106 +505,124 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) */ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); + int i; + u32 reg; + int virq; struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; struct irq_chip *chip = irq_desc_get_chip(desc); - dev_dbg(dev, ": Handling legacy irq %d\n", irq); - - /* - * The chained irq handler installation would have replaced normal - * interrupt driver handler so we need to take care of mask/unmask and - * ack operation. - */ chained_irq_enter(chip, desc); - ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset); + + for (i = 0; i < PCI_NUM_INTX; i++) { + reg = ks_dw_app_readl(ks_pcie, IRQ_STATUS(i)); + if (!(reg & INTx_EN)) + continue; + + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, i); + generic_handle_irq(virq); + ks_dw_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN); + ks_dw_app_writel(ks_pcie, IRQ_EOI, i); + } + chained_irq_exit(chip, desc); } -static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie, - char *controller, int *num_irqs) +static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) { - int temp, max_host_irqs, legacy = 1, *host_irqs; struct device *dev = ks_pcie->pci->dev; - struct device_node *np_pcie = dev->of_node, **np_temp; - - if (!strcmp(controller, "msi-interrupt-controller")) - legacy = 0; - - if (legacy) { - np_temp = &ks_pcie->legacy_intc_np; - max_host_irqs = PCI_NUM_INTX; - host_irqs = &ks_pcie->legacy_host_irqs[0]; - } else { - np_temp = &ks_pcie->msi_intc_np; - max_host_irqs = MAX_MSI_HOST_IRQS; - host_irqs = &ks_pcie->msi_host_irqs[0]; - } + struct device_node *np = ks_pcie->np; + struct device_node *intc_np; + int irq_count; + int irq; + int i; + + if (!IS_ENABLED(CONFIG_PCI_MSI)) + return 0; - /* interrupt controller is in a child node */ - *np_temp = of_get_child_by_name(np_pcie, controller); - if (!(*np_temp)) { - dev_err(dev, "Node for %s is absent\n", controller); + intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); + if (!intc_np) { + dev_WARN(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } - temp = of_irq_count(*np_temp); - if (!temp) { - dev_err(dev, "No IRQ entries in %s\n", controller); - of_node_put(*np_temp); + irq_count = of_irq_count(intc_np); + if (!irq_count) { + dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); return -EINVAL; } - if (temp > max_host_irqs) - dev_warn(dev, "Too many %s interrupts defined %u\n", - (legacy ? "legacy" : "MSI"), temp); + for (i = 0; i < irq_count; i++) { + irq = irq_of_parse_and_map(intc_np, i); + if (!irq) + return -EINVAL; - /* - * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to - * 7 (MSI) - */ - for (temp = 0; temp < max_host_irqs; temp++) { - host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp); - if (!host_irqs[temp]) - break; + if (!ks_pcie->msi_host_irq) + ks_pcie->msi_host_irq = irq; + + irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, + ks_pcie); } - of_node_put(*np_temp); + return 0; +} - if (temp) { - *num_irqs = temp; - return 0; - } +static int ks_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); - return -EINVAL; + return 0; } -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) +static const struct irq_domain_ops ks_pcie_intx_domain_ops = { + .map = ks_pcie_intx_map, +}; + +static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) { + struct device *dev = ks_pcie->pci->dev; + struct irq_domain *legacy_irq_domain; + struct device_node *np = ks_pcie->np; + struct device_node *intc_np; + int irq_count; + int irq; int i; - /* Legacy IRQ */ - for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) { - irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i], + intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); + if (!intc_np) { + dev_WARN(dev, "legacy-interrupt-controller node is absent\n"); + return -EINVAL; + } + + irq_count = of_irq_count(intc_np); + if (!irq_count) { + dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); + return -EINVAL; + } + + for (i = 0; i < irq_count; i++) { + irq = irq_of_parse_and_map(intc_np, i); + if (!irq) + return -EINVAL; + irq_set_chained_handler_and_data(irq, ks_pcie_legacy_irq_handler, ks_pcie); } - ks_dw_pcie_enable_legacy_irqs(ks_pcie); - - /* MSI IRQ */ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) { - irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i], - ks_pcie_msi_irq_handler, - ks_pcie); - } + + legacy_irq_domain = irq_domain_add_linear(intc_np, PCI_NUM_INTX, + &ks_pcie_intx_domain_ops, + NULL); + if (!legacy_irq_domain) { + dev_err(dev, "Failed to add irq domain for legacy irqs\n"); + return -EINVAL; } + ks_pcie->legacy_irq_domain = legacy_irq_domain; - if (ks_pcie->error_irq > 0) - ks_dw_pcie_enable_error_irq(ks_pcie); + for (i = 0; i < PCI_NUM_INTX; i++) + ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); + + return 0; } /* @@ -734,11 +649,19 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + int ret; + + ret = ks_pcie_config_legacy_irq(ks_pcie); + if (ret) + return ret; + + ret = ks_pcie_config_msi_irq(ks_pcie); + if (ret) + return ret; dw_pcie_setup_rc(pp); ks_dw_pcie_setup_rc_app_regs(ks_pcie); - ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -783,44 +706,12 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, struct device *dev = &pdev->dev; int ret; - ret = ks_pcie_get_irq_controller_info(ks_pcie, - "legacy-interrupt-controller", - &ks_pcie->num_legacy_host_irqs); - if (ret) - return ret; - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - ret = ks_pcie_get_irq_controller_info(ks_pcie, - "msi-interrupt-controller", - &ks_pcie->num_msi_host_irqs); - if (ret) - return ret; - } - - /* - * Index 0 is the platform interrupt for error interrupt - * from RC. This is optional. - */ - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0); - if (ks_pcie->error_irq <= 0) - dev_info(dev, "no error IRQ defined\n"); - else { - ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler, - IRQF_SHARED, "pcie-error-irq", ks_pcie); - if (ret < 0) { - dev_err(dev, "failed to request error IRQ %d\n", - ks_pcie->error_irq); - return ret; - } - } - pp->ops = &keystone_pcie_host_ops; ret = ks_dw_pcie_host_init(ks_pcie); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; } - return 0; } @@ -878,6 +769,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) void __iomem *reg_p; struct phy *phy; int ret; + int irq; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -913,6 +805,20 @@ static int __init ks_pcie_probe(struct platform_device *pdev) devm_release_mem_region(dev, res->start, resource_size(res)); ks_pcie->np = dev->of_node; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "missing IRQ resource: %d\n", irq); + return irq; + } + + ret = devm_request_irq(dev, irq, pcie_err_irq_handler, IRQF_SHARED, + "ks-pcie-error-irq", ks_pcie); + if (ret < 0) { + dev_err(dev, "failed to request error IRQ %d\n", irq); + return ret; + } + platform_set_drvdata(pdev, ks_pcie); ks_pcie->clk = devm_clk_get(dev, "pcie"); if (IS_ERR(ks_pcie->clk)) { @@ -929,6 +835,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret < 0) goto fail_clk; + ks_dw_pcie_enable_error_irq(ks_pcie); + return 0; fail_clk: clk_disable_unprepare(ks_pcie->clk); From patchwork Fri Sep 21 10:21:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147210 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629414ljw; Fri, 21 Sep 2018 03:25:00 -0700 (PDT) X-Google-Smtp-Source: ANB0VdY3oEcKbeixGBaCufVb6ForEu2UfoVMxN0Y0JnbqUnbjsKISDxzuOXt+lMAHNSPyM1nmcLs X-Received: by 2002:a63:6507:: with SMTP id z7-v6mr9173230pgb.200.1537525500666; Fri, 21 Sep 2018 03:25:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525500; cv=none; d=google.com; s=arc-20160816; b=ugNxSTKPxpLEsw2YMHUhXDs8wYwlGVSw+Zq7eHKUJNAS7Pj82qG/kUeIli7tmFEbIE LtKF7/egLhK++VBke3J9KhjeNW5v2bjtbxzHoBP+j+viqZC230EMLGSFzPgf7tDZVQiO Fd7u49Rz66a7xcqcyMu1grBU6dJeNGQAyFYq75nIShDeg1CMcazK5eqiMidO+hi1/SUW 1d1RqjCBUKidifKdNbADjPriVVOa1rPzSNWx4HE8OJiTBY4KQ5HYBn7R0kbUZqzhsVKs II5+N43Baetxua26vIYJE+dFKQTqMl11dNVBaSPRjbwvhH8oEs1DRr/5FsC8FXKdEPky eAZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=yl0oTF1/HhKk61u2yHkpnvuMXIj9otZHZGKyLra6O+0=; b=e6WuqtxRLKdouAiJdHou1cIZQu8z/uxMH3ObpodAZdElNkUJwGcKv9wyuR1wTO7EkL gjGD/pichQqAsUVJD6n69MIEIuCHmnDkUOPJCFaXcNHkxcfoA5AYo6GcrMRUbfliVjE+ xaoGGWalDUK80aa/ejdICPq1/E9jTOJsNiQK0cUSgSQkjYJ9oVepTLP6HUW2e5Q0aL/2 P/Flp6fG4rMFFdqRmnlZex3Bdr6PQfJzxsADQEE7UZcee+6zZo4Mt8qbGNl4/WcGDkVy Pizt2OAy1nNuP+f7U+QF3xeqoQl1na3EGpgY3beAoVE8mIB8spDZabbxgxLbdsyperX1 V0Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="q/W6ls6l"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t123-v6si3996041pgc.662.2018.09.21.03.25.00; Fri, 21 Sep 2018 03:25:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="q/W6ls6l"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390208AbeIUQNK (ORCPT + 32 others); Fri, 21 Sep 2018 12:13:10 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54634 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389683AbeIUQNJ (ORCPT ); Fri, 21 Sep 2018 12:13:09 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAN2UJ032841; Fri, 21 Sep 2018 05:23:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525382; bh=yl0oTF1/HhKk61u2yHkpnvuMXIj9otZHZGKyLra6O+0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=q/W6ls6lAIbNoqZ8GBqZM1mSt85bxXSKY0IX3ciYuxpPT0Vw8+lLTUhk5FtQUYN07 8mpjWcytb4dE8/9tfgmUMG15iJa8liSRXr+pl84xlIG0KZ5ErCJNf0RXbo3K4kc+LK 50pKFIkP8cuni3I0s9NrWbRnmSyd6WDSjvefF8Yo= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAN22K029248; Fri, 21 Sep 2018 05:23:02 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:00 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:01 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtD032280; Fri, 21 Sep 2018 05:22:56 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 09/40] PCI: keystone: Remove redundant platform_set_drvdata Date: Fri, 21 Sep 2018 15:51:24 +0530 Message-ID: <20180921102155.22839-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Remove redundant platform_set_drvdata invocation in ks_pcie_probe(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 4554fdc6cce1..c54d18ea263a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -829,8 +829,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret) return ret; - platform_set_drvdata(pdev, ks_pcie); - ret = ks_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto fail_clk; From patchwork Fri Sep 21 10:21:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147218 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629949ljw; Fri, 21 Sep 2018 03:25:35 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdb7uvaTTWh6c0v4bKH8ffLIbUS4raKahiQNeA1CF9R+ED3sMXfizrQ5DayMG68zDn1WRJdK X-Received: by 2002:aa7:8591:: with SMTP id w17-v6mr45895345pfn.77.1537525535459; Fri, 21 Sep 2018 03:25:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525535; cv=none; d=google.com; s=arc-20160816; b=J7HgJDYyF+6LRoSJTRi0/bmVAZsl4snr4yEW4UBNsM3gMJ8wKw3FyuQnUJocz2OzdQ Qr2u60wKGuVb4XjyjivNdvTRBQCy33g9eGT7p14mNAl0+Do7RYU2LoB4e3AuZ+ryTA6/ x2mCAlYXoGazpvQC5imsjRXOzbYylkYspkADxC9csaSRkeXSjVW3rWnyazH5P75HzAL9 +DsrQuz0OTY71xnmIVDPjpKzrLoQGNTf1D2RhFNm2Xywqea17T4qQMZNWQCeOMxcPhIp wDnm88nF+RGfHKnooZ230YU1Jos/PDtSDilWUiSN/DZ0AmRIBQo7OcR2shovUUHAJsHN 0nNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TPl5IMlViKBCaxieQtiJ7+FoIJMiy7oEVTJetfB8h5Q=; b=iAgvZQgSnhuvUPsft5hd9Yi8RNAOEjtkL8JjyC+k5CMonbir/pda/p8CnDlMxUvEQV bOpT7zPN3xpEEWF2fOwf1qcscdKBGpYLe3iGhTe4BsWyR2AadG4hYsnIFOP1JfBVEjpK Unv4xxylomWREHTEFbwUcz8E2ETuX4f/Sujtbc3L5SWW6epIlErAMZHmofCeZy06jLgS 4FufDjche0HD5flG4CGJ5pf0FDc09iET6PCpH0hlEbvW1Dg11LdqxnT0gler4ldyGLOH DwSQ3UFAdfM9tNzH5WkgA75ntmIpf2eITh7a2UtAI/F2+/ib1NVh+UYRFiK0aDlKq1b/ ATfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dwNDCK3b; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Some function names begin with ks_dw_pcie_* and some function names begin with ks_pcie_*. Modify it so that all function names begin with ks_pcie_*. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 267 ++++++++++------------ 1 file changed, 120 insertions(+), 147 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index c54d18ea263a..e19ba065ebd5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -104,7 +104,7 @@ struct keystone_pcie { struct resource app; }; -static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) +static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -112,17 +112,18 @@ static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) return ks_pcie->app.start + MSI_IRQ; } -static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset) +static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) { return readl(ks_pcie->va_app_base + offset); } -static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val) +static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, + u32 val) { writel(val, ks_pcie->va_app_base + offset); } -static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) +static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) { u32 reg_offset, bit_pos; struct keystone_pcie *ks_pcie; @@ -133,11 +134,11 @@ static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp) reg_offset = irq % 8; bit_pos = irq >> 3; - ks_dw_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); - ks_dw_app_writel(ks_pcie, IRQ_EOI, MSI_IRQ_OFFSET + reg_offset); + ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); + ks_pcie_app_writel(ks_pcie, IRQ_EOI, MSI_IRQ_OFFSET + reg_offset); } -static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) { u32 reg_offset, bit_pos; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -145,11 +146,11 @@ static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) reg_offset = irq % 8; bit_pos = irq >> 3; - ks_dw_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), - BIT(bit_pos)); + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), + BIT(bit_pos)); } -static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) { u32 reg_offset, bit_pos; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -157,25 +158,25 @@ static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) reg_offset = irq % 8; bit_pos = irq >> 3; - ks_dw_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), - BIT(bit_pos)); + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), + BIT(bit_pos)); } -static int ks_dw_pcie_msi_host_init(struct pcie_port *pp) +static int ks_pcie_msi_host_init(struct pcie_port *pp) { return dw_pcie_allocate_domains(pp); } -static void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) +static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { - ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); + ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); } -static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) +static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) { u32 status; - status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; + status = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; if (!status) return IRQ_NONE; @@ -184,48 +185,48 @@ static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) status); /* Ack the IRQ; status bits are RW1C */ - ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status); + ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, status); return IRQ_HANDLED; } /** - * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask + * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask * registers * * Since modification of dbi_cs2 involves different clock domain, read the * status back to ensure the transition is complete. */ -static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) +static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) { u32 val; - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); do { - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); } while (!(val & DBI_CS2_EN_VAL)); } /** - * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode + * ks_pcie_clear_dbi_mode() - Disable DBI mode * * Since modification of dbi_cs2 involves different clock domain, read the * status back to ensure the transition is complete. */ -static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) +static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) { u32 val; - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); do { - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); } while (val & DBI_CS2_EN_VAL); } -static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) +static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; @@ -234,26 +235,26 @@ static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) u32 val; /* Disable BARs for inbound access */ - ks_dw_pcie_set_dbi_mode(ks_pcie); + ks_pcie_set_dbi_mode(ks_pcie); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); - ks_dw_pcie_clear_dbi_mode(ks_pcie); + ks_pcie_clear_dbi_mode(ks_pcie); /* Set outbound translation size per window division */ - ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); + ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; /* Using Direct 1:1 mapping of RC <-> PCI memory space */ for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { - ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); - ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); + ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); + ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); start += tr_size; } /* Enable OB translation */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); } /** @@ -294,13 +295,13 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus, if (bus != 1) regval |= BIT(24); - ks_dw_app_writel(ks_pcie, CFG_SETUP, regval); + ks_pcie_app_writel(ks_pcie, CFG_SETUP, regval); return pp->va_cfg0_base; } -static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 *val) +static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, + u32 *val) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -312,9 +313,9 @@ static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, return dw_pcie_read(addr + where, size, val); } -static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 val) +static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, + u32 val) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -327,23 +328,23 @@ static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, } /** - * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization + * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization * * This sets BAR0 to enable inbound access for MSI_IRQ register */ -static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) +static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); /* Configure and set up BAR0 */ - ks_dw_pcie_set_dbi_mode(ks_pcie); + ks_pcie_set_dbi_mode(ks_pcie); /* Enable BAR0 */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); - ks_dw_pcie_clear_dbi_mode(ks_pcie); + ks_pcie_clear_dbi_mode(ks_pcie); /* * For BAR0, just setting bus address for inbound writes (MSI) should @@ -353,9 +354,9 @@ static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) } /** - * ks_dw_pcie_link_up() - Check if link up + * ks_pcie_link_up() - Check if link up */ -static int ks_dw_pcie_link_up(struct dw_pcie *pci) +static int ks_pcie_link_up(struct dw_pcie *pci) { u32 val; @@ -363,65 +364,7 @@ static int ks_dw_pcie_link_up(struct dw_pcie *pci) return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } -static void ks_dw_pcie_stop_link(struct keystone_pcie *ks_pcie) -{ - u32 val; - - /* Disable Link training */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - val &= ~LTSSM_EN_VAL; - ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); -} - -static void ks_dw_pcie_start_link(struct keystone_pcie *ks_pcie) -{ - u32 val; - - /* Initiate Link Training */ - val = ks_dw_app_readl(ks_pcie, CMD_STATUS); - ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); -} - -/** - * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware - * - * Ioremap the register resources, initialize legacy irq domain - * and call dw_pcie_v3_65_host_init() API to initialize the Keystone - * PCI host controller. - */ -static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; - pp->va_cfg1_base = pp->va_cfg0_base; - - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - - return dw_pcie_host_init(pp); -} - -static void quirk_limit_mrrs(struct pci_dev *dev) +static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; struct pci_dev *bridge; @@ -462,7 +405,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev) } } } -DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { @@ -480,7 +423,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); - reg = ks_dw_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); + reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); for (pos = 0; pos < 4; pos++) { if (!(reg & BIT(pos))) continue; @@ -514,14 +457,14 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); for (i = 0; i < PCI_NUM_INTX; i++) { - reg = ks_dw_app_readl(ks_pcie, IRQ_STATUS(i)); + reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(i)); if (!(reg & INTx_EN)) continue; virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, i); generic_handle_irq(virq); - ks_dw_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN); - ks_dw_app_writel(ks_pcie, IRQ_EOI, i); + ks_pcie_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN); + ks_pcie_app_writel(ks_pcie, IRQ_EOI, i); } chained_irq_exit(chip, desc); @@ -620,7 +563,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) ks_pcie->legacy_irq_domain = legacy_irq_domain; for (i = 0; i < PCI_NUM_INTX; i++) - ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); + ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); return 0; } @@ -630,8 +573,8 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) * bus error instead of returning 0xffffffff. This handler always returns 0 * for this kind of faults. */ -static int keystone_pcie_fault(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) +static int ks_pcie_fault(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) { unsigned long instr = *(unsigned long *) instruction_pointer(regs); @@ -661,7 +604,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_dw_pcie_setup_rc_app_regs(ks_pcie); + ks_pcie_setup_rc_app_regs(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -672,46 +615,69 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ - hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0, + hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); ks_pcie_start_link(pci); return dw_pcie_wait_for_link(pci); } -static const struct dw_pcie_host_ops keystone_pcie_host_ops = { - .rd_other_conf = ks_dw_pcie_rd_other_conf, - .wr_other_conf = ks_dw_pcie_wr_other_conf, +static const struct dw_pcie_host_ops ks_pcie_host_ops = { + .rd_other_conf = ks_pcie_rd_other_conf, + .wr_other_conf = ks_pcie_wr_other_conf, .host_init = ks_pcie_host_init, - .msi_set_irq = ks_dw_pcie_msi_set_irq, - .msi_clear_irq = ks_dw_pcie_msi_clear_irq, - .get_msi_addr = ks_dw_pcie_get_msi_addr, - .msi_host_init = ks_dw_pcie_msi_host_init, - .msi_irq_ack = ks_dw_pcie_msi_irq_ack, - .scan_bus = ks_dw_pcie_v3_65_scan_bus, + .msi_set_irq = ks_pcie_msi_set_irq, + .msi_clear_irq = ks_pcie_msi_clear_irq, + .get_msi_addr = ks_pcie_get_msi_addr, + .msi_host_init = ks_pcie_msi_host_init, + .msi_irq_ack = ks_pcie_msi_irq_ack, + .scan_bus = ks_pcie_v3_65_scan_bus, }; -static irqreturn_t pcie_err_irq_handler(int irq, void *priv) +static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { struct keystone_pcie *ks_pcie = priv; - return ks_dw_pcie_handle_error_irq(ks_pcie); + return ks_pcie_handle_error_irq(ks_pcie); } -static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, - struct platform_device *pdev) +static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; + struct resource *res; int ret; - pp->ops = &keystone_pcie_host_ops; - ret = ks_dw_pcie_host_init(ks_pcie); + /* Index 0 is the config reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + /* + * We set these same and is used in pcie rd/wr_other_conf + * functions + */ + pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + pp->va_cfg1_base = pp->va_cfg0_base; + + /* Index 1 is the application reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + pp->ops = &ks_pcie_host_ops; + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; } + return 0; } @@ -723,8 +689,20 @@ static const struct of_device_id ks_pcie_of_match[] = { { }, }; +static void ks_pcie_stop_link(struct dw_pcie *pci) +{ + u32 val; + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + /* Disable Link training */ + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + val &= ~LTSSM_EN_VAL; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + static int ks_pcie_start_link(struct dw_pcie *pci) { + u32 val; struct device *dev = pci->dev; struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); @@ -733,22 +711,17 @@ static int ks_pcie_start_link(struct dw_pcie *pci) return 0; } - ks_dw_pcie_start_link(ks_pcie); + /* Initiate Link Training */ + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); return 0; } -static void ks_pcie_stop_link(struct dw_pcie *pci) -{ - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - ks_dw_pcie_stop_link(ks_pcie); -} - -static const struct dw_pcie_ops dw_pcie_ops = { +static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, - .link_up = ks_dw_pcie_link_up, + .link_up = ks_pcie_link_up, }; static int __exit ks_pcie_remove(struct platform_device *pdev) @@ -780,7 +753,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return -ENOMEM; pci->dev = dev; - pci->ops = &dw_pcie_ops; + pci->ops = &ks_pcie_dw_pcie_ops; ks_pcie->pci = pci; @@ -812,7 +785,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return irq; } - ret = devm_request_irq(dev, irq, pcie_err_irq_handler, IRQF_SHARED, + ret = devm_request_irq(dev, irq, ks_pcie_err_irq_handler, IRQF_SHARED, "ks-pcie-error-irq", ks_pcie); if (ret < 0) { dev_err(dev, "failed to request error IRQ %d\n", irq); @@ -829,11 +802,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret) return ret; - ret = ks_add_pcie_port(ks_pcie, pdev); + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto fail_clk; - ks_dw_pcie_enable_error_irq(ks_pcie); + ks_pcie_enable_error_irq(ks_pcie); return 0; fail_clk: From patchwork Fri Sep 21 10:21:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147217 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629916ljw; Fri, 21 Sep 2018 03:25:33 -0700 (PDT) X-Google-Smtp-Source: ACcGV60p6OEbIM4aajLUcp+apK2sZh+GG69cwxsa4hz0QDTrGJom5QUHSsFJnY44U6d277iH79r2 X-Received: by 2002:a17:902:9f97:: with SMTP id g23-v6mr547781plq.68.1537525533192; Fri, 21 Sep 2018 03:25:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525533; cv=none; d=google.com; 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 4dd17de549a7..2030ee0dc4f9 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -19,6 +19,9 @@ pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines +ti,syscon-pcie-id : phandle to the device control module required to set device + id and vendor id. + Example: pcie_msi_intc: msi-interrupt-controller { interrupt-controller; From patchwork Fri Sep 21 10:21:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147196 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628460ljw; Fri, 21 Sep 2018 03:23:56 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZD8ZiApIFZbGqvoFfEsk3WdYhShy4chb9+wyIpN9fpNnFByfL6V0mQPc5Qkaym0BbnykoO X-Received: by 2002:a63:ee56:: with SMTP id n22-v6mr40900568pgk.402.1537525436836; Fri, 21 Sep 2018 03:23:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525436; cv=none; d=google.com; s=arc-20160816; b=p+ekhTDmdmcdG1EYskfH58eKe5QGLqB+IudiDLAMyfs2re0xLkjaCm+dj+hnVx9pAi lV/MotHkEa/AZhy/2yhNzSHZkj13OLeevOtYah6JGacdhDus0YwTSnzynC4OPTbHtwNE dWU/3Dz61TnHbqnf50t3jrBOqcZRidL5IeI4ROmma2FKg2GRDOvmeat5bqgQyvSTl+uD X0lZbIkiuzco9gnt3T516fzWZcrdKd+28bo/t8Xv/zQefL3GtjbDF+SjWd0RtCSb84T3 PFHWIBp/6QHQadUUVKreWI24NNl7dSwSkNeaQ+JBKoK/pV+x7WE/kQfZZBcfvE8XzeXo faoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=H3avG6EwoSzk6QdC4/XcOvo10vwjEICQqWTGY5kVX/s=; b=A9S/CNvstUxngZuLB8BQ2r0K8dqIl7oM35ogfv3H2kenhVHLbKRP5oo5tBOCZMCFd1 SUXjLNNRLrDXhq5GW+HxOr6JlqTbN4a4kTBM6T4AEms4y/rFj2uC1kKdCbZtXdwCDI+U dUzOVnDHmxqnzfuuFdy/aQc5XjzAG9xyqG9JDCclP7XioYDdA609hai5SRhZY2QCqeEp ClhLx1ACkEdJnoN1V4L7QN9cyIF7jPPKBIZ+aZhbTDTeLHJwvV9uL4FJkd2TkVs7u9Al EUxDnKoHPFDzep9P++uJFIAAXCj37TlILzOEEwKJfxrR6e7tVD1q2lXJ0xFib3O2XFAB jzFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=HFzUdRN+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fix it here by using syscon APIs to get device id from control module. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 46 +++++++++++++++-------- 1 file changed, 31 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e19ba065ebd5..505e13b1197d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -15,12 +15,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include @@ -28,6 +30,9 @@ #define DRIVER_NAME "keystone-pcie" +#define PCIE_VENDORID_MASK 0xffff +#define PCIE_DEVICEID_SHIFT 16 + /* DEV_STAT_CTRL */ #define PCIE_CAP_BASE 0x70 @@ -92,8 +97,6 @@ static void ks_pcie_stop_link(struct dw_pcie *pci); struct keystone_pcie { struct dw_pcie *pci; struct clk *clk; - /* PCI Device ID */ - u32 device_id; int msi_host_irq; struct device_node *msi_intc_np; struct irq_domain *legacy_irq_domain; @@ -588,6 +591,29 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) +{ + int ret; + unsigned int id; + struct regmap *devctrl_regs; + struct dw_pcie *pci = ks_pcie->pci; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; + + devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); + if (IS_ERR(devctrl_regs)) + return PTR_ERR(devctrl_regs); + + ret = regmap_read(devctrl_regs, 0, &id); + if (ret) + return ret; + + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + + return 0; +} + static int __init ks_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -608,8 +634,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); - /* update the Vendor ID */ - writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID); + ret = ks_pcie_init_id(ks_pcie); + if (ret < 0) + return ret; /* * PCIe access errors that result into OCP errors are caught by ARM as @@ -738,8 +765,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; - struct resource *res; - void __iomem *reg_p; struct phy *phy; int ret; int irq; @@ -768,15 +793,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } - /* index 2 is to read PCI DEVICE_ID */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); - reg_p = devm_ioremap_resource(dev, res); - if (IS_ERR(reg_p)) - return PTR_ERR(reg_p); - ks_pcie->device_id = readl(reg_p) >> 16; - devm_iounmap(dev, reg_p); - devm_release_mem_region(dev, res->start, resource_size(res)); - ks_pcie->np = dev->of_node; irq = platform_get_irq(pdev, 0); From patchwork Fri Sep 21 10:21:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147195 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628418ljw; Fri, 21 Sep 2018 03:23:53 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdb7OF9nUQTyq3kbF4QmBeo+IjeWf+8yGn0Edh2i1vlzjBL8TNSdOi7aD0kytT7IiGV56RLZ X-Received: by 2002:a63:4745:: with SMTP id w5-v6mr41623164pgk.140.1537525432886; Fri, 21 Sep 2018 03:23:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525432; cv=none; d=google.com; s=arc-20160816; b=x4EsQUHMx5yobP6KT5/KC4rLhuZ++m1Qp7hmGFKApgdkd+OXMOzuVZ6K601oEO3duZ zlyWx5UiMOtwk2DBEPJwxiVjMbszosQdg8ox+jonVmIMFA+EdSeN257wI3EB1KypRxmt wkBuM8Q92Re0rjsahDG5b4nXM28n/zuPHAoh6u2b/2zfDE2v/kv0We9gLoLwv61H6apk Oio55y/i7k0V4hXAxKVlbJUaxmWQOHdh2oU94L9FgaQ93WTkystyH8zBvDQvDxVV0tKA aHke8f1TR+GtoJsOOU32KwCMvT5TV3hhN4uqKixgEllSukMV/DoXI/7hv3tU4+kZyLHL puBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HPgjlX5taw7ZtR4to3Xv2wCqCwxm6AbKhwmyuCfZ5x4=; b=TAN93n9W9cYUKz2XKYTe/KHSlmcRNpH6ZTk1cAMt0T3X4aoQ8KfqP6nRSfRqQGM/Eg FAGMOy5QV9PFJfZQErV3GCNr3x4YBO6xVIZ7sM3vV/6sIgy8QPIZEkzMr8K64aIx5zJL 7Yct4X52iZ/E2bXJX29x9xP0U7wHWgXbp3k0CLZ2lIogh8PKSnDeo9FUEGP8/8uoyQ9x cGkXTZ/gocZOCrq7FJes6cuNjoQ8GTq/jnkpQfCKgAvFa+ShBWJBpFy57jYLA7R11eVb O024ryGmoxpIZOuEnnr70aPz0DtlBOjESS4ouLepeU2a/n7pJx5CmncvTqMYS9UH7QSn D3MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BF3iIMyL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 From patchwork Fri Sep 21 10:21:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147228 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp633194ljw; Fri, 21 Sep 2018 03:29:00 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda+RQcD1jQWAc2AVmLZrY0/V4M5zOe2dHZ0ABnGo9i3e7UR7izNhwFuUq/eutZ8nsae7Mn5 X-Received: by 2002:a62:9402:: with SMTP id m2-v6mr45267054pfe.3.1537525740503; Fri, 21 Sep 2018 03:29:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525740; cv=none; d=google.com; s=arc-20160816; b=yh2EE2/8dCJ9YE6Dk+U3oWxuGgOFLUImp42RWHKOcnE70x9ApYAohjC6YSbUADluyv kIL++7V/WIfMA1EuWY6x7kFY2+87TMufB1L51gwWXplZbs4i7nEXvVWvX2yE0dAFBF3d yteP8cKLRbUUCXICl6u93vtAqahEMHWuH9Xzt2ygu2t51DqfV6VkwflAIBbU5aO+AgTQ +wh+WtM4mB67pOdtJ52Ifids9mcq9D7Hzw4ej31LB5r/GjDjkubJn4zKfh+ouVsAOcof V5eszY8YhepthB/xTwa+zPdw6a77f0pVuYMa2eNL4hXqbockDASygdQSpTa0rZd4YU48 qj5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=KRjdjQ5hcy7QKZ5B8r6m0BycFYn2BHKtUqCgGLjIzAI=; b=Uei2f6tTpi8+ms6hIXIvYaU/Fn0PdXIVNMRJhMI7pSKMnm4ITA9rjC2vMjWpwuDmVk fiPzYfJcoIXy33b4ggyBBPjPUq4f3bilvcxF6RUw89sH/jdxweJQamzlbtHKzEIfZedo a0RCykolOqH8v2MXshPs595pbD2VwmcvP6+DiFIw4OtSWEO/fQGXbtTuXJAM7iTdFIRP Hxju7JC79I+/lXxwVgpq3EKjYnvr65h6EaVRjDtutwt57qakwV0qQunS4+f25BBMKH3M x879FmONovpZSbbLm9qEY47n+tIGrRXlH7HxPdR3d7zJSYe0Gq7j4S8lwuPjuQjdQft4 F5+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TATuFq3P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 31-v6si28838737pla.129.2018.09.21.03.29.00; Fri, 21 Sep 2018 03:29:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TATuFq3P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389837AbeIUQMJ (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:09 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54548 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727554AbeIUQMI (ORCPT ); Fri, 21 Sep 2018 12:12:08 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANP2l032903; Fri, 21 Sep 2018 05:23:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525405; bh=KRjdjQ5hcy7QKZ5B8r6m0BycFYn2BHKtUqCgGLjIzAI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TATuFq3PCJdQaawgDQLViVQv0o9wUcp9YQzm45Mk6CHFQIDYlyPCww3fUVPNh8xsT OZlsI4ngDgpR7YMmhmObSGvZT9aPmznXWMU2WsVKtAcJPXneH1qTLhv+jQo3tZ4gQt XwkIPVe3CuyHTQFfw95jUJ8h36E174thq65TC7mI= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANPAa029983; Fri, 21 Sep 2018 05:23:25 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:25 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:25 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtI032280; Fri, 21 Sep 2018 05:23:20 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 14/40] PCI: keystone: Use platform_get_resource_byname to get memory resources Date: Fri, 21 Sep 2018 15:51:29 +0530 Message-ID: <20180921102155.22839-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use platform_get_resource_byname() instead of platform_get_resource() which uses index to get memory resources. While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since pci-keystone driver has never worked out of the box in mainline kernel, dt backward compatibility is ignored. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 505e13b1197d..fe522b8c981f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -49,7 +49,6 @@ #define OB_SIZE 0x030 #define CFG_PCIM_WIN_SZ_IDX 3 #define CFG_PCIM_WIN_CNT 32 -#define SPACE0_REMOTE_CFG_OFFSET 0x1000 #define OB_OFFSET_INDEX(n) (0x200 + (8 * n)) #define OB_OFFSET_HI(n) (0x204 + (8 * n)) @@ -677,21 +676,19 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + pp->va_cfg1_base = pp->va_cfg0_base; - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); ks_pcie->va_app_base = devm_ioremap_resource(dev, res); if (IS_ERR(ks_pcie->va_app_base)) return PTR_ERR(ks_pcie->va_app_base); From patchwork Fri Sep 21 10:21:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147197 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628530ljw; Fri, 21 Sep 2018 03:24:01 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZUKPKQfnVjd2CHJbA5guqvG90Ult9tJ89PY7f+J+X8A1gWH14G/xY289KLu3e0eNOQaT6p X-Received: by 2002:a17:902:7205:: with SMTP id ba5-v6mr4696542plb.15.1537525441712; Fri, 21 Sep 2018 03:24:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525441; cv=none; d=google.com; s=arc-20160816; b=nL18Zcp1bVAEwCx1gBJBTa4RGBa97ESUUOllKrAD2L1SEbtvtzOm80qHECxvS+XyNc A3f5ho2n71BUu9rgxLaUQ5nn/qsMWA9pLVVeQy+Wpn5rmjmG583sZnREMUz4iiroCUOq DcyD+dx6AzR8thcWqzAuLLezqmxOorwLtnHC2q/vbGzKBbFCQGvemv/Sx6qO8+BkbZVy qkU3erymx/ZNRCpedRxZaOncMdG8QFzfTY9aIEGaqR5kuyK/07xr85TtmxMxhAjlumq1 3BMwNay25evs8fDjNU/9tpQRkQAZfTiYudNKpKRJpKQxLiJZ2OUa4azEg4UJwYklU2+e QwyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=g3JaPOStkKoEr3p7W5xTkdmOc+nnnrI10AWpPhzBLpY=; b=lkUqB+8l+AzIZt2AYv9Ec6O2FJaJ/F5XmRafXsLvOqTgcyALtxmRoOnj8hpd4oGUEq hMgU7sAkS3KQSRObg4VDKLYhwe1QLWrmN+q6fJtyR9DDiF8v3FrAxy9pMS2jBT5TfrBR vO5C6l0QN3XUSxbfgjdK05sxnI28EtIv4svieQ0szQ3LR29n1Fe1r9O3asoHShm2wCkF JS4CTJRINmhBxpKCdhpZnNYyALgS1L2iDiSdNQ/I6+aEk4o/tadZSTMrjH9GHpgL2F8K 3BPLhOUX8BeL5ImwhAZu/32UABJf5vz/sxGCrFf1l5qNvhonDu7EGTh8wpiZQx3OQsI6 PAug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=na9kILPe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r4-v6si11041953pfb.257.2018.09.21.03.24.01; Fri, 21 Sep 2018 03:24:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=na9kILPe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389867AbeIUQMK (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:10 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35046 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389815AbeIUQMJ (ORCPT ); Fri, 21 Sep 2018 12:12:09 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANUUK030455; Fri, 21 Sep 2018 05:23:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525410; bh=g3JaPOStkKoEr3p7W5xTkdmOc+nnnrI10AWpPhzBLpY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=na9kILPezSe4Y944bTJjEY5MkZTmeBubAdnaMKwrNPPEKVGLXoo+48DJOkc49MuOU IXM8jvKsOrwA0aRpz1g4ba+1+Mt7XoC0G1aSmlPA/eX2SP01O6bhV7mfHrbE7uoMK8 yGvOQyj+qiPZvcFqh3LXuzRJh+Tq56F2PqSX5ThQ= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANUvf018699; Fri, 21 Sep 2018 05:23:30 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:30 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:30 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtJ032280; Fri, 21 Sep 2018 05:23:25 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 15/40] PCI: keystone: Cleanup PHY handling Date: Fri, 21 Sep 2018 15:51:30 +0530 Message-ID: <20180921102155.22839-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Cleanup PHY handling by using devm_phy_optional_get to get PHYs if the PHYs are optional, creating a device link between the PHY device and the controller device and disable PHY on error cases here. Also invoke phy_reset() as part of enabling PHY. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 133 +++++++++++++++++++--- 1 file changed, 115 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fe522b8c981f..b013776d9256 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -96,6 +96,9 @@ static void ks_pcie_stop_link(struct dw_pcie *pci); struct keystone_pcie { struct dw_pcie *pci; struct clk *clk; + int num_lanes; + struct phy **phy; + struct device_link **link; int msi_host_irq; struct device_node *msi_intc_np; struct irq_domain *legacy_irq_domain; @@ -748,23 +751,62 @@ static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .link_up = ks_pcie_link_up, }; -static int __exit ks_pcie_remove(struct platform_device *pdev) +static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { - struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); + int num_lanes = ks_pcie->num_lanes; - clk_disable_unprepare(ks_pcie->clk); + while (num_lanes--) { + phy_power_off(ks_pcie->phy[num_lanes]); + phy_exit(ks_pcie->phy[num_lanes]); + } +} + +static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) +{ + int i; + int ret; + int num_lanes = ks_pcie->num_lanes; + + for (i = 0; i < num_lanes; i++) { + ret = phy_reset(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret = phy_init(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret = phy_power_on(ks_pcie->phy[i]); + if (ret < 0) { + phy_exit(ks_pcie->phy[i]); + goto err_phy; + } + } return 0; + +err_phy: + while (--i >= 0) { + phy_power_off(ks_pcie->phy[i]); + phy_exit(ks_pcie->phy[i]); + } + + return ret; } static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; - struct phy *phy; + struct device_link **link; + struct phy **phy; + u32 num_lanes; + char name[10]; int ret; int irq; + int i; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -777,43 +819,76 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; - ks_pcie->pci = pci; + ret = of_property_read_u32(np, "num-lanes", &num_lanes); + if (ret) + num_lanes = 1; - /* initialize SerDes Phy if present */ - phy = devm_phy_get(dev, "pcie-phy"); - if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER) - return PTR_ERR(phy); + phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); + if (!phy) + return -ENOMEM; - if (!IS_ERR_OR_NULL(phy)) { - ret = phy_init(phy); - if (ret < 0) - return ret; + link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i = 0; i < num_lanes; i++) { + snprintf(name, sizeof(name), "pcie-phy%d", i); + phy[i] = devm_phy_optional_get(dev, name); + if (IS_ERR(phy[i])) { + ret = PTR_ERR(phy[i]); + goto err_link; + } + + if (!phy[i]) + continue; + + link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + ret = -EINVAL; + goto err_link; + } } - ks_pcie->np = dev->of_node; + ks_pcie->num_lanes = num_lanes; + ks_pcie->phy = phy; + + ret = ks_pcie_enable_phy(ks_pcie); + if (ret) { + dev_err(dev, "failed to enable phy\n"); + goto err_link; + } + + ks_pcie->pci = pci; + ks_pcie->link = link; + ks_pcie->np = np; + ks_pcie->num_lanes = num_lanes; + ks_pcie->phy = phy; irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource: %d\n", irq); - return irq; + ret = irq; + goto err_get_irq; } ret = devm_request_irq(dev, irq, ks_pcie_err_irq_handler, IRQF_SHARED, "ks-pcie-error-irq", ks_pcie); if (ret < 0) { dev_err(dev, "failed to request error IRQ %d\n", irq); - return ret; + goto err_get_irq; } platform_set_drvdata(pdev, ks_pcie); ks_pcie->clk = devm_clk_get(dev, "pcie"); if (IS_ERR(ks_pcie->clk)) { dev_err(dev, "Failed to get pcie rc clock\n"); - return PTR_ERR(ks_pcie->clk); + ret = PTR_ERR(ks_pcie->clk); + goto err_get_irq; } + ret = clk_prepare_enable(ks_pcie->clk); if (ret) - return ret; + goto err_get_irq; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) @@ -825,9 +900,31 @@ static int __init ks_pcie_probe(struct platform_device *pdev) fail_clk: clk_disable_unprepare(ks_pcie->clk); +err_get_irq: + ks_pcie_disable_phy(ks_pcie); + +err_link: + while (--i >= 0 && link[i]) + device_link_del(link[i]); + return ret; } +static int __exit ks_pcie_remove(struct platform_device *pdev) +{ + struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); + struct device_link **link = ks_pcie->link; + int num_lanes = ks_pcie->num_lanes; + + clk_disable_unprepare(ks_pcie->clk); + ks_pcie_disable_phy(ks_pcie); + + while (num_lanes--) + device_link_del(link[num_lanes]); + + return 0; +} + static struct platform_driver ks_pcie_driver __refdata = { .probe = ks_pcie_probe, .remove = __exit_p(ks_pcie_remove), From patchwork Fri Sep 21 10:21:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147198 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628576ljw; 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[209.132.180.67]) by mx.google.com with ESMTP id o11-v6si5357431pgl.16.2018.09.21.03.24.03; Fri, 21 Sep 2018 03:24:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZTaVyzVo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389906AbeIUQMN (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:13 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51360 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389870AbeIUQML (ORCPT ); Fri, 21 Sep 2018 12:12:11 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANZ6S033283; Fri, 21 Sep 2018 05:23:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525415; bh=foMA9sXY1vSacErr421Q9aMno8mL1g6LWM8DFq/dpjM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZTaVyzVoc7eqaZ47d1prlUYPAJr58HuwN2IaRCJNjoOmL9HVeHW/CRBz8uZ4XxchB t59bPDm+EnIVadP6fRBkFGpL9tqPP0uI0sMcjkl+tFFzaQqO6IM2bbmmk0b/fi/HkI Y3TgMVM0lJsCQtk7ynLsk4xdYI2AqxarK5f2aMwk= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANZid018768; Fri, 21 Sep 2018 05:23:35 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:35 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:35 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtK032280; Fri, 21 Sep 2018 05:23:30 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 16/40] PCI: keystone: Invoke pm_runtime APIs to enable clock Date: Fri, 21 Sep 2018 15:51:31 +0530 Message-ID: <20180921102155.22839-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Invoke pm_runtime APIs to enable clocks and remove explicit clock enabling using clk_prepare_enable(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 29 +++++++++++------------ 1 file changed, 14 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b013776d9256..f230344e1f4e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -95,7 +95,6 @@ static void ks_pcie_stop_link(struct dw_pcie *pci); struct keystone_pcie { struct dw_pcie *pci; - struct clk *clk; int num_lanes; struct phy **phy; struct device_link **link; @@ -879,26 +878,25 @@ static int __init ks_pcie_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, ks_pcie); - ks_pcie->clk = devm_clk_get(dev, "pcie"); - if (IS_ERR(ks_pcie->clk)) { - dev_err(dev, "Failed to get pcie rc clock\n"); - ret = PTR_ERR(ks_pcie->clk); - goto err_get_irq; - } - ret = clk_prepare_enable(ks_pcie->clk); - if (ret) - goto err_get_irq; + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) - goto fail_clk; + goto err_get_sync; ks_pcie_enable_error_irq(ks_pcie); return 0; -fail_clk: - clk_disable_unprepare(ks_pcie->clk); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); err_get_irq: ks_pcie_disable_phy(ks_pcie); @@ -915,10 +913,11 @@ static int __exit ks_pcie_remove(struct platform_device *pdev) struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); struct device_link **link = ks_pcie->link; int num_lanes = ks_pcie->num_lanes; + struct device *dev = &pdev->dev; - clk_disable_unprepare(ks_pcie->clk); + pm_runtime_put(dev); + pm_runtime_disable(dev); ks_pcie_disable_phy(ks_pcie); - while (num_lanes--) device_link_del(link[num_lanes]); From patchwork Fri Sep 21 10:21:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147226 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp632783ljw; Fri, 21 Sep 2018 03:28:32 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZHUQ6uk2L1F+MYmoHi0aKsXrvERjGk2STgnTMYe2Ww2BX3vCFzmUSKqpTGTAxj7k7yYFey X-Received: by 2002:a17:902:6501:: with SMTP id b1-v6mr44142554plk.31.1537525712432; Fri, 21 Sep 2018 03:28:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525712; cv=none; d=google.com; s=arc-20160816; b=Lnht5vWQCC0bRN0kcM1z2/eTm0dxnBoNQb6wn7GAcm1i2AFHHuMzbkSqaPZ3yUHf2p 6B+e5ccP40hkFK/eIlJE/6UlCMk06aG24vEpXimYPvHEXaiTbbafeAx2X96WU2nLozc3 4q4mcI63Je2J020fbmRbT2pHAljnALTz0CZc+ITIVLrXBhLauK0yeHyRuRhXwODHcjs7 UGeVixzidglT/DEoKT8kJuW6R88ecg/d4Cp1R2h/5TL4fzIOenyHdJ3Nk0S+0ct3IY5i D0xqJCAYYLCRFCyvMptiGH7RG65e2+ZiPc2/8W6L8s87sYS15NJIVV9FD+B+83D1Kqvh i9OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dOWDR36pioDR/ZSigw8rJelA/kEL89WVadMViv1+T0A=; b=worIWQYj7xOJLrYZhe9xX9cDT9Mpw6qreT2zLndJNw97Dqgh+mJ/eJoGdalBUHXmTF H2vOcPefytQzBNVZK7k9YDqysBRTAb8KRlSpqUYDn1d2elSSlLJIgF/2Cst5ZskfjkyQ 1l7fwJOr1x0atakef3ygBxwheYvh+7YmIH5Vnq83ZTJLUo5YYRduL32koXHjNjNjuRsE qgc9k7K2m6Zdz4cedKy5hCIxBbbQloAeamfo2Z/VXmglpzoR4GFUzHQ4OkfUi41FogAY keB0sIDJUjQJrUX/hlbqX08gnp4HFnVggqKTWNACtGDDtzCM/o1kzJk77afJgwnIDVz0 dg6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Q7dw3roj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 70 +++++++---------------- 1 file changed, 20 insertions(+), 50 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index f230344e1f4e..3ead1162235f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -45,7 +45,13 @@ /* Application registers */ #define CMD_STATUS 0x004 + #define CFG_SETUP 0x008 +#define CFG_BUS(x) (((x) & 0xff) << 16) +#define CFG_DEVICE(x) (((x) & 0x1f) << 8) +#define CFG_FUNC(x) ((x) & 0x7) +#define CFG_TYPE1 BIT(24) + #define OB_SIZE 0x030 #define CFG_PCIM_WIN_SZ_IDX 3 #define CFG_PCIM_WIN_CNT 32 @@ -261,60 +267,21 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); } -/** - * ks_pcie_cfg_setup() - Set up configuration space address for a device - * - * @ks_pcie: ptr to keystone_pcie structure - * @bus: Bus number the device is residing on - * @devfn: device, function number info - * - * Forms and returns the address of configuration space mapped in PCIESS - * address space 0. Also configures CFG_SETUP for remote configuration space - * access. - * - * The address space has two regions to access configuration - local and remote. - * We access local region for bus 0 (as RC is attached on bus 0) and remote - * region for others with TYPE 1 access when bus > 1. As for device on bus = 1, - * we will do TYPE 0 access as it will be on our secondary bus (logical). - * CFG_SETUP is needed only for remote configuration access. - */ -static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus, - unsigned int devfn) -{ - u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn); - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - u32 regval; - - if (bus == 0) - return pci->dbi_base; - - regval = (bus << 16) | (device << 8) | function; - - /* - * Since Bus#1 will be a virtual bus, we need to have TYPE0 - * access only. - * TYPE 1 - */ - if (bus != 1) - regval |= BIT(24); - - ks_pcie_app_writel(ks_pcie, CFG_SETUP, regval); - return pp->va_cfg0_base; -} - static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u8 bus_num = bus->number; - void __iomem *addr; + u32 reg; - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); + reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | + CFG_FUNC(PCI_FUNC(devfn)); + if (bus->parent->number != pp->root_bus_nr) + reg |= CFG_TYPE1; + ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); - return dw_pcie_read(addr + where, size, val); + return dw_pcie_read(pp->va_cfg0_base + where, size, val); } static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, @@ -323,12 +290,15 @@ static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u8 bus_num = bus->number; - void __iomem *addr; + u32 reg; - addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); + reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | + CFG_FUNC(PCI_FUNC(devfn)); + if (bus->parent->number != pp->root_bus_nr) + reg |= CFG_TYPE1; + ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); - return dw_pcie_write(addr + where, size, val); + return dw_pcie_write(pp->va_cfg0_base + where, size, val); } /** From patchwork Fri Sep 21 10:21:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147199 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628651ljw; Fri, 21 Sep 2018 03:24:08 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbDEbciktRZ6zlA5KEd6ivXr9aAtSypNAHsrLnSXP5DG1ZxamJEIHO0yuORN71xoxgpjO2k X-Received: by 2002:a17:902:4381:: with SMTP id j1-v6mr42550179pld.227.1537525448193; Fri, 21 Sep 2018 03:24:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525448; cv=none; d=google.com; s=arc-20160816; b=HbskYOoFqlUA3BzckMTiRSe5zLcM932Hixp6rgI29c3XsLL6fEFHF1X12KPQst0Oov I2/TM7PhuzcPFRz3RSeLMO7+gRUDSLxWyLM8beHn1Y3g3ONxdS2MAifyz6AZLyFW4BTx yeB/52QKQK/r+1SbqVFipddXwZU8lSjUm46UbY5NhRMBkTwrtnbYs7Pde/0WhudNJT2a MOJBwIDYPydsNd1+K99vyHjK83+FWnl7WDG4kF1yqUh6IZX8SgHPq0UCMGZ1/KR5n3oJ T25SeKuN3EzAL1MLVJjL4FRs9Ec7PRXWsJ2990oEFv5NAob8ID12cwT0DkwMMA+eIXNF +Pkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=aLOPdoi1dv1LS3olqchzfw2j8dRX8NpDokKZcMrJhcI=; b=fLmjTfOwgTsXzAjTJbpToQu24I41Swfbq5xW1Zju+5RnOv2hQPJd6hRh4ic6tXkMNl nNAY/cuzeXz8hpjB8ve0Oj4HlG53QaXnwQqeQ2IfLWepiAiDqaR170lptwpa+39+MdtF VKKEZ8FqEDSEs+D4i52gu7vMVq2NEaQXJCWNS8RHciFBKaBdi2SRwAripaLQMBPPFZG0 GMxpFH43qPbbrkX0ckgUplNTDPZZIsvMiO5ShUtnTQp6CVKSMvS3HhsStJg/TDYvLg2P kR0oqPKlXz9Mw4BXQ//i+G7/eYvbWTsY55oX9TJiIt69b4ngF5a2+d8Q87I+gEc3/x08 T50Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VwuDKgWw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Also cleanup memory space configuration here by adding macros for constants. While at that also use BIT() macro for OB_XLAT_EN_VAL. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 86 +++++++++++++---------- 1 file changed, 49 insertions(+), 37 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 3ead1162235f..d5304c4a1eb5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -41,7 +41,7 @@ #define LTSSM_STATE_MASK 0x1f #define LTSSM_STATE_L0 0x11 #define DBI_CS2_EN_VAL 0x20 -#define OB_XLAT_EN_VAL 2 +#define OB_XLAT_EN_VAL BIT(1) /* Application registers */ #define CMD_STATUS 0x004 @@ -53,10 +53,7 @@ #define CFG_TYPE1 BIT(24) #define OB_SIZE 0x030 -#define CFG_PCIM_WIN_SZ_IDX 3 -#define CFG_PCIM_WIN_CNT 32 -#define OB_OFFSET_INDEX(n) (0x200 + (8 * n)) -#define OB_OFFSET_HI(n) (0x204 + (8 * n)) +#define OB_WIN_SIZE 8 /* 8MB */ /* IRQ register defines */ #define IRQ_EOI 0x050 @@ -85,6 +82,11 @@ #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_IRQ_ENABLE_CLR 0x1cc +#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) +#define OB_ENABLEN BIT(0) + +#define OB_OFFSET_HI(n) (0x204 + (8 * (n))) + /* Config space registers */ #define DEBUG0 0x728 @@ -102,6 +104,7 @@ static void ks_pcie_stop_link(struct dw_pcie *pci); struct keystone_pcie { struct dw_pcie *pci; int num_lanes; + u32 num_viewport; struct phy **phy; struct device_link **link; int msi_host_irq; @@ -236,37 +239,6 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) } while (val & DBI_CS2_EN_VAL); } -static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - u32 start = pp->mem->start, end = pp->mem->end; - int i, tr_size; - u32 val; - - /* Disable BARs for inbound access */ - ks_pcie_set_dbi_mode(ks_pcie); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); - ks_pcie_clear_dbi_mode(ks_pcie); - - /* Set outbound translation size per window division */ - ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); - - tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; - - /* Using Direct 1:1 mapping of RC <-> PCI memory space */ - for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { - ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); - ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); - start += tr_size; - } - - /* Enable OB translation */ - val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); - ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); -} - static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) @@ -562,6 +534,33 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +static void ks_pcie_setup_mem_space(struct keystone_pcie *ks_pcie) +{ + u32 val; + u32 num_viewport = ks_pcie->num_viewport; + struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; + u64 start = pp->mem->start; + u64 end = pp->mem->end; + int i; + + val = ilog2(OB_WIN_SIZE); + ks_pcie_app_writel(ks_pcie, OB_SIZE, val); + + /* Using Direct 1:1 mapping of RC <-> PCI memory space */ + for (i = 0; i < num_viewport && (start < end); i++) { + ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), + lower_32_bits(start) | OB_ENABLEN); + ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), + upper_32_bits(start)); + start += OB_WIN_SIZE; + } + + val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); + val |= OB_XLAT_EN_VAL; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); +} + static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) { int ret; @@ -601,7 +600,12 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_pcie_setup_rc_app_regs(ks_pcie); + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); + ks_pcie_clear_dbi_mode(ks_pcie); + + ks_pcie_setup_mem_space(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -770,6 +774,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + u32 num_viewport; struct phy **phy; u32 num_lanes; char name[10]; @@ -788,6 +793,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; + ret = of_property_read_u32(np, "num-viewport", &num_viewport); + if (ret < 0) { + dev_err(dev, "unable to read *num-viewport* property\n"); + return ret; + } + ret = of_property_read_u32(np, "num-lanes", &num_lanes); if (ret) num_lanes = 1; @@ -831,6 +842,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->link = link; ks_pcie->np = np; ks_pcie->num_lanes = num_lanes; + ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; irq = platform_get_irq(pdev, 0); From patchwork Fri Sep 21 10:21:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147200 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628841ljw; Fri, 21 Sep 2018 03:24:21 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZdaU+lOlG1bN921SkrI45UWeD+UxJTcLbWD2grLOHyBWxZa7UJAMuX5iMDHWLeqNGb2jqi X-Received: by 2002:a63:fc07:: with SMTP id j7-v6mr40612529pgi.1.1537525460940; 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[209.132.180.67]) by mx.google.com with ESMTP id v61-v6si26995490plb.448.2018.09.21.03.24.20; Fri, 21 Sep 2018 03:24:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iTm1mbld; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390013AbeIUQMa (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:30 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35098 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389593AbeIUQM3 (ORCPT ); Fri, 21 Sep 2018 12:12:29 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANr3c030515; Fri, 21 Sep 2018 05:23:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525433; bh=WEywuUrRC8xwixfpR6xUMddJoaV2XLaFqJWCxARGqp4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iTm1mbldLKmFlacCbfFV4kwhBKNH9qCKTdFyhcBbmzwWNAQtqGu6UJ770JuLsJxz3 SN8RE3QnJ2mYoccoOtzug7RH6Huw/syt85R3UbuGVyDOZCvk9bvkoN4BALNe1FYrgK 2/+GiPCF/cWMuYmSbhA6nRRw9iRnnIIvrJu34bEM= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANrkt030309; Fri, 21 Sep 2018 05:23:53 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:53 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:53 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtO032280; Fri, 21 Sep 2018 05:23:49 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 20/40] PCI: keystone: Cleanup ks_pcie_link_up() Date: Fri, 21 Sep 2018 15:51:35 +0530 Message-ID: <20180921102155.22839-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_link_up() uses registers from the designware core to get the status of the link. Move the register defines to pcie-designware.h and cleanup ks_pcie_link_up(). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 10 +++------- drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 728b1e0db314..240c39c58b0f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -38,8 +38,6 @@ /* Application register defines */ #define LTSSM_EN_VAL BIT(0) -#define LTSSM_STATE_MASK 0x1f -#define LTSSM_STATE_L0 0x11 #define DBI_CS2 BIT(5) #define OB_XLAT_EN_VAL BIT(1) @@ -87,9 +85,6 @@ #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) -/* Config space registers */ -#define DEBUG0 0x728 - /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -308,8 +303,9 @@ static int ks_pcie_link_up(struct dw_pcie *pci) { u32 val; - val = dw_pcie_readl_dbi(pci, DEBUG0); - return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); + val &= PORT_LOGIC_LTSSM_STATE_MASK; + return (val == PORT_LOGIC_LTSSM_STATE_L0); } static void ks_pcie_quirk(struct pci_dev *dev) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 96126fd8403c..a4d939536faf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -37,6 +37,10 @@ #define PORT_LINK_MODE_4_LANES (0x7 << 16) #define PORT_LINK_MODE_8_LANES (0xf << 16) +#define PCIE_PORT_DEBUG0 0x728 +#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f +#define PORT_LOGIC_LTSSM_STATE_L0 0x11 + #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) From patchwork Fri Sep 21 10:21:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147201 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628938ljw; Fri, 21 Sep 2018 03:24:26 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbnQmCARB1jDviC422w9muNniXHIY2Dyd051Y26/055kpHDOn64sfBf97E8yAa/ANkc1Lrq X-Received: by 2002:a17:902:820a:: with SMTP id x10-v6mr43839604pln.261.1537525466056; Fri, 21 Sep 2018 03:24:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525466; cv=none; d=google.com; s=arc-20160816; b=oiY/Xqpb/794XVVvzxCR8QtekiMDh9P9WpiEJpDix4FPIGmtoQQbwruHuSfvh1SiiS +jkCck1ohjbHONQFyjOG4xEX+JeYEWuAroWihZTTMidwwfcGj0KtNuudOvsZLKl6O9fu kn+bcn8cbKyLY87H/fwPpAbqbDkogvMo7wv0iUvWWBfvj1qcZz20FV9i879Aq0hbaS/p gZx12kIIlZyitvi4xLxZTt0f8HsYRm7LjJlIFzsO9XIkWutSJsNbQYSX66nt1FPrVAzA KdrZFSpLsGzVXH/cl4Yw9T9r3W+89oggeknNeXJ/ZLuIHKlAx01+1zKAnTaSQQGX0nwg 1O2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=JS8XxeiLDwlWjMuWVe6AENveVa8okkl8KrO0t1BBcnw=; b=ew09kgoH6nGrJXuJTgG9LPJUFJu37IyA1+Yhx66ahYPymmiPMfXunFhVurTUg6aUrv yyA7YcX2I62Ou/fbU8k2jWHv5epS8Rx04pPKLZZaSuvTBqCuIGmMuUWYnfFwwh0cJL0g oqBpItgoTygHuJc/2IHXrPzp0fI3G4IWFMoElipn5sFl47FGSIOGJMKvYL/9zoLbkK6d l0w+WL8eP0V3f2IJe9sGfTqcuH5WsMQKjzO08t6A8rANxT1fM0WW2UeSK3NhOOL8+aib +lcVfJW/eRWhZk1i1D2jwlwGpAzfrypLul2HbQqDtogzLJ7LFT+y4FDyQM6WCR5ic0hp 2WBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NXNlI2iH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p7-v6si26017065plo.159.2018.09.21.03.24.25; Fri, 21 Sep 2018 03:24:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NXNlI2iH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390050AbeIUQMe (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:34 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51406 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390016AbeIUQMd (ORCPT ); Fri, 21 Sep 2018 12:12:33 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LANwdd033358; Fri, 21 Sep 2018 05:23:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525438; bh=JS8XxeiLDwlWjMuWVe6AENveVa8okkl8KrO0t1BBcnw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NXNlI2iH7IZY4U/SQ1UYE5vnYHF9vSqt0NJEbAtwBm2HaVPFS5CAeM7+QzOD2uNTI hljwJDGKsGEKeeKSx1ZeDlwLzDmgab+Z1qIw54DoV0GirZ1cHastPIv4d3ALjp3Ecg BWhvSJ0X34qQQSGXojVsi1Se0q4209csvmFrYAnU= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LANwHA019071; Fri, 21 Sep 2018 05:23:58 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:23:58 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:23:57 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtP032280; Fri, 21 Sep 2018 05:23:53 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 21/40] PCI: keystone: Add debug error message for all errors Date: Fri, 21 Sep 2018 15:51:36 +0530 Message-ID: <20180921102155.22839-22-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 025dd3daeda77f61a280da87ae701 ("PCI: keystone: Add error IRQ handler") added dev_err() message only for ERR_AXI and ERR_FATAL. Add debug error message for ERR_SYS, ERR_NONFATAL, ERR_CORR and ERR_AER here. While at that avoid using ERR_IRQ_STATUS_RAW and use ERR_IRQ_STATUS instead. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 45 +++++++++++++---------- 1 file changed, 25 insertions(+), 20 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 240c39c58b0f..a3dec74da70c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -74,8 +74,6 @@ #define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI) -#define ERR_IRQ_STATUS_RAW 0x1c0 #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_IRQ_ENABLE_CLR 0x1cc @@ -180,23 +178,6 @@ static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); } -static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) -{ - u32 status; - - status = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; - if (!status) - return IRQ_NONE; - - if (status & ERR_FATAL_IRQ) - dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n", - status); - - /* Ack the IRQ; status bits are RW1C */ - ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, status); - return IRQ_HANDLED; -} - /** * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask * registers @@ -636,9 +617,33 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { + u32 reg; struct keystone_pcie *ks_pcie = priv; + struct device *dev = ks_pcie->pci->dev; - return ks_pcie_handle_error_irq(ks_pcie); + reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); + + if (reg & ERR_SYS) + dev_err(dev, "System Error\n"); + + if (reg & ERR_FATAL) + dev_err(dev, "Fatal Error\n"); + + if (reg & ERR_NONFATAL) + dev_dbg(dev, "Non Fatal Error\n"); + + if (reg & ERR_CORR) + dev_dbg(dev, "Correctable Error\n"); + + if (reg & ERR_AXI) + dev_err(dev, "AXI tag lookup fatal Error\n"); + + if (reg & ERR_AER) + dev_err(dev, "ECRC Error\n"); + + ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); + + return IRQ_HANDLED; } static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, From patchwork Fri Sep 21 10:21:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147202 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp628972ljw; Fri, 21 Sep 2018 03:24:29 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaDOHn7bLRic96V5/6SirWlYP5fNgo1gdj6vm8bvZfXadDMToEYNqrVV3QxL0tPd6z+p/5O X-Received: by 2002:a63:3e8b:: with SMTP id l133-v6mr39826779pga.355.1537525469160; Fri, 21 Sep 2018 03:24:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525469; cv=none; d=google.com; s=arc-20160816; b=S37d4ulxfU60RjcaCzXF6hW56vQVFSgU+ZC/GhIY8IWL9nxa+8GhMj6jglui9ir2c0 kzGyYg/LdAsWtYCWrgxkrGHQFhRKoYhKEUeiDN0m9HBdNIYmEDNH6pyl11VvdBS3L53w Fd2RJ8lQ/pfQwIEtFkl9xMCRx8QlYSAkmPARxGVOnr/EmyxE6dESETp2emDBnYMAglBO N32diZeXwWTaqqlONtEDTrl2xVc+Q75CS6mcGg5ygxA9GI972qcCIWslPRzd6OZDHQ54 ADBrM6M5QZ/U5zrJ986jYj39mLkOZUnVBKIvc+X0aJ6aytmq5vnHS4CDXQviBL7Svi4x smcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=K31ChqNjRu5l1S0E4b+jKiReLdWou1lCpsnq9Pl7H2I=; b=BF9Ux0BU39EX0WtBMckKKPftUQdVI2TckXZBtEk2lR79CV06fEp5+F/DM4J7FfGKzh tN2djq33aVjl8kI82OfGMGmGh6CfuMRtYDA8+pgylfGWGj78HfE9s9wkMrxNZSAcKW/J qp1dx0b13rUndUv3b++WNMTlFgOm+ep5VerjJan5k8qQEUwBuZD862GjSim1sf7aiEqT H22CXn2iUmo3eLYzgh9M8kIexOJWZ1NW7JBR7ZhmaTg4OrLoWGzvfdu+spr2/UWbAX8i M5r0IT5Nv14Q42mvhIainFH9epXoFGKqtw3bx0NUa0v6ek5ZbNllHSElTp1MW4wUd0wC XFaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gbvuMQDf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x12-v6si26076698plv.315.2018.09.21.03.24.28; Fri, 21 Sep 2018 03:24:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gbvuMQDf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390078AbeIUQMj (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:39 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54608 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389313AbeIUQMi (ORCPT ); Fri, 21 Sep 2018 12:12:38 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAO3qH032966; Fri, 21 Sep 2018 05:24:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525443; bh=K31ChqNjRu5l1S0E4b+jKiReLdWou1lCpsnq9Pl7H2I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gbvuMQDfJGS9EWAjQQ6DD0kSzkHrnqRwOFC1htINNpsqtHl8RI3z5J6BfM1kTWCZS LcAZL8qVRWZSe7Gd3xBi+832cNYTTeEx6xfmD230tutvhSrJpcckCqpTwwe+bvQPFQ rfikHPGK8jbQzp7OtYcGpsYj0DfGW07rGlqIIpQA= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAO2qP019252; Fri, 21 Sep 2018 05:24:02 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:02 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:02 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtQ032280; Fri, 21 Sep 2018 05:23:58 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 22/40] PCI: keystone: Reorder header file in alphabetical order Date: Fri, 21 Sep 2018 15:51:37 +0530 Message-ID: <20180921102155.22839-23-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Reorder header file in alphabetical order. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index a3dec74da70c..b1dfaea29530 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -9,19 +9,19 @@ * Implementation based on pci-exynos.c and pcie-designware.c */ -#include #include #include +#include #include +#include #include -#include #include #include -#include #include +#include #include -#include #include +#include #include #include #include From patchwork Fri Sep 21 10:21:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147203 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629050ljw; Fri, 21 Sep 2018 03:24:33 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYhZCL1sOfm3WMJ5ZM8BefKkLdNArJvR1fyjPoEvhHeyz59ArPRJKiyqKk8wxOXgW5VvhwA X-Received: by 2002:a62:bd4:: with SMTP id 81-v6mr46104827pfl.67.1537525473018; Fri, 21 Sep 2018 03:24:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525473; cv=none; d=google.com; s=arc-20160816; b=c7LZ6ty61SbKnChEpzpj0tYTDvcoOrw6E0VhY5kN5b5MDtNxPN1mOQKvWaaDmFlvkT UvXbtdWZ3c/8pXPpTVg4p+m+nkGo34WocBK2Moc+qevM8cwSeM+BwBO7TifYVCg2sVhw EZJcc/3Vo79NzeWMaNTfHaeuQUDPf+x/5hjoZ1vLRPw0m0dxKSgENzIH/rSHKpsoiGO9 eDaCMilsgB5bDQ0nG8ZRUNadauVxTDgTn+ZCA0ClRkguUZNBvY6FnhZjeXPbZaLbS4MA uE8Z7Ink2Yn8sqmNR/dXOch1HbDkw9K+2bHnDJ+vTb0T/6H2IL3xj1D5CkIeND4R8DxM S7bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WfasnAWlcLsVQTlj7zbQefyfmRm0OJVS8gwd8Y4RkZE=; b=j8Xg2FSywCvN1wwOK0Y5A7Ds4j6ScHSCJ7xaYY5GLxJa1SNyXW8DrQCpHikumMoUWU 9myGx/tTX5KFlvKxTqpZGwNWRRd2xXlDPFSgqYZJcTnai7YyEEbbEZE+mCBYm/tsU8oc BjH7DsH0CHhcE8akRHlCjM1o949mnI4N8qDpIpzAnlN2ZfZaa/7f8uaGEE/ROsCxPLJ3 vASpei5KeXrctdmeqShZnAQKa6F6XI0CJ+/uCji7xNw2OZdfXTq6VHge3hf6AgL8Kqjv 1eOQuxnlk6xKvwIkpF0gYslsCirBQr761L2rVXdYSepkV3786nBhcMoS2Xa6rLR/hfzN qOCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SrRhTJTz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Cleanup macros defined in pci-keystone.c by removing unused macros, grouping the macros and aligning it properly. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 41 +++++++++-------------- 1 file changed, 16 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b1dfaea29530..75d007148804 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -28,21 +28,14 @@ #include "pcie-designware.h" -#define DRIVER_NAME "keystone-pcie" - #define PCIE_VENDORID_MASK 0xffff #define PCIE_DEVICEID_SHIFT 16 -/* DEV_STAT_CTRL */ -#define PCIE_CAP_BASE 0x70 - -/* Application register defines */ -#define LTSSM_EN_VAL BIT(0) -#define DBI_CS2 BIT(5) -#define OB_XLAT_EN_VAL BIT(1) - /* Application registers */ #define CMD_STATUS 0x004 +#define LTSSM_EN_VAL BIT(0) +#define OB_XLAT_EN_VAL BIT(1) +#define DBI_CS2 BIT(5) #define CFG_SETUP 0x008 #define CFG_BUS(x) (((x) & 0xff) << 16) @@ -65,18 +58,16 @@ #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) #define INTx_EN BIT(0) -/* Error IRQ bits */ -#define ERR_AER BIT(5) /* ECRC error */ -#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ -#define ERR_CORR BIT(3) /* Correctable error */ -#define ERR_NONFATAL BIT(2) /* Non-fatal error */ -#define ERR_FATAL BIT(1) /* Fatal error */ -#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */ -#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ - ERR_NONFATAL | ERR_FATAL | ERR_SYS) #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 -#define ERR_IRQ_ENABLE_CLR 0x1cc +#define ERR_AER BIT(5) /* ECRC error */ +#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ +#define ERR_CORR BIT(3) /* Correctable error */ +#define ERR_NONFATAL BIT(2) /* Non-fatal error */ +#define ERR_FATAL BIT(1) /* Fatal error */ +#define ERR_SYS BIT(0) /* System error */ +#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ + ERR_NONFATAL | ERR_FATAL | ERR_SYS) #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) #define OB_ENABLEN BIT(0) @@ -84,12 +75,12 @@ #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) /* PCIE controller device IDs */ -#define PCIE_RC_K2HK 0xb008 -#define PCIE_RC_K2E 0xb009 -#define PCIE_RC_K2L 0xb00a -#define PCIE_RC_K2G 0xb00b +#define PCIE_RC_K2HK 0xb008 +#define PCIE_RC_K2E 0xb009 +#define PCIE_RC_K2L 0xb00a +#define PCIE_RC_K2G 0xb00b -#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) static int ks_pcie_start_link(struct dw_pcie *pci); static void ks_pcie_stop_link(struct dw_pcie *pci); From patchwork Fri Sep 21 10:21:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147204 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629137ljw; Fri, 21 Sep 2018 03:24:40 -0700 (PDT) X-Google-Smtp-Source: ACcGV634h2J4MqELIDoQt8vJ5stKtBvdn8h4F3dnM9nmj9yTW1Rkn5J5MARREm4AQ7nJLtWwPran X-Received: by 2002:a17:902:b7c2:: with SMTP id v2-v6mr865474plz.238.1537525479996; Fri, 21 Sep 2018 03:24:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525479; cv=none; d=google.com; s=arc-20160816; b=V9OFNuwsae4W0XK/1ZPdf57++FE2Jkzk3WYSH82f6Re5Lhz5be/jimOkW54l7eOwAM eJJpQqD8wwRw4nMvE7ffsNmifA6etZF+xkYmE7BlXhG+hk2O6eqSOYJ2v8Htxf+bSU+s AvB1JAmsepp+1+1TCET82kZFsEr51q08GuojImi3jiv0FKFz38CY1qyOdH/qXFaUr9Vw UJuoibelg9AifgaJPUFGcMo+PbfwZU28tO0Ao0/wMHyQClQ34nOoz7j2wxBgAucnGaJ+ U2QD08HcwIs2VACeoUBLpSHBRpaifA9EBijuDDPJLNyrfwb42hoEKClDzQENA0Ot2hmL SAuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=eN2QjYF7XPN5wdQWDOgORmztfTZi1+IN0RnaI/q47uM=; b=dBsKjuOr4Nxv7R/xUA+U1+QpUn3a/HYmf/tjK4nOrS0XemHxjo/7k3PtBGDIdlgJWp nDx9W+VsLTNhEpI+usED6JqrVicAE/mjejMBLfYvOXmAQgmfGQEjZFxlmgn/Nvo9H8P+ pYsGnrfF4tqI81KBCdrUCnVh9RyybFoEJAu14wb4wtX0k+j602RtfjNcOW7mlkZW5M7d hpL09M1ZzF4k37mxZ8RDdNK5ojBYiU7T7ya9wAEdym3aZe+ci3J//+pFG2DfBDWZTDkd pvegSK2CHbSjRcBt1d9f/XFi5N6xDWJ3CR70c7RzFFBYpp2vfDITXomI71T44TlkWcSC 1vCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mUYoOwvO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v12-v6si25919894pfm.341.2018.09.21.03.24.39; Fri, 21 Sep 2018 03:24:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mUYoOwvO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390100AbeIUQMu (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:50 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35152 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727776AbeIUQMt (ORCPT ); Fri, 21 Sep 2018 12:12:49 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOCEU030588; Fri, 21 Sep 2018 05:24:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525452; bh=eN2QjYF7XPN5wdQWDOgORmztfTZi1+IN0RnaI/q47uM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mUYoOwvOuF4LdCFoLhYliXtHs9zuYOSfzR388fCluI4435BPzRQms35ZdS4cjG+/b 87Dlt47vHmJvxbyQdB5ByAWBdHRbWwAQ3aIeWnc6m/rLID4rrbTFEctCDN5a5K8QMC ST2WiPaQ9LMlAmjn9JMYShQGvhYFS1+F5oH4oTsg= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOCdB019982; Fri, 21 Sep 2018 05:24:12 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:12 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:12 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtS032280; Fri, 21 Sep 2018 05:24:07 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 24/40] PCI: keystone: Move initializations to appropriate places Date: Fri, 21 Sep 2018 15:51:39 +0530 Message-ID: <20180921102155.22839-25-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Move host specific platform_get_resource to ks_add_pcie_port and the common platform_get_resource (applicable to both host and endpoint) to probe. This is in preparation for adding endpoint support to pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 75d007148804..13e865f82f96 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -646,11 +646,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) @@ -658,13 +653,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -768,6 +756,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct resource *res; + void __iomem *base; u32 num_viewport; struct phy **phy; u32 num_lanes; @@ -784,6 +774,19 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); + base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; From patchwork Fri Sep 21 10:21:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147205 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629191ljw; Fri, 21 Sep 2018 03:24:44 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdadc0EgiqgxPd7TzYgzO53x6J03SXKJXwwGQVb8e3LLF3EayZsDrwqR+pYogpRKtrFIFLIX X-Received: by 2002:a62:5a01:: with SMTP id o1-v6mr46193231pfb.0.1537525484234; Fri, 21 Sep 2018 03:24:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525484; cv=none; d=google.com; s=arc-20160816; b=KmeVX8oo+ZFRjXoxSfwap10lqKRlUoHDOnjlFQjQJk/p7zGrMMqrjCIC2FWcFiEBXw wiw6haosErSaYFHp3G9jg1ylgVEeZLwerotCXV9uy5fOzcTqmMX2rQVqVJQfbdXPte+D Hy5QvnbyMbb5uPVO1h61JkdrgCK3eeTUkNwmReDhsz+YlF5pN2itdH3vQWh8CXCsoxFZ OrtAaqAg991e4S4aNaH5ykDjmCOZ4ypSbIN/PyDky4HDZ9y0+raEp1jWNXHDqZR7n0jz /2KpJqiLNRv8eXhgsWkQbsiMBAAp7cF/v2ZAu6XYHexCruIAacSeBbNsH18PyjmuZu6/ LODQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Oy9h1kP8jbCXe+8kD93AkYommSwhxCLq/ir/s6HONHk=; b=cPv/vullIHQEK83Av+czj5v85CNT0J5BWVYZkolnE3aJf8BEc8VlZsNb7WXyBUwMRW YbLf50IztAPlL98NrKUZ8X9/mhnwma8N2XXVPDBVLeL6SUlNHNi7olQWixyzLjjZnl6r u+xWzb0JbtB+cezmKoAl8laeo2XeGPdKKSy8zkXvhNhvwORNDqmMqSPIxfRTc4x8eBLQ Nldcxx+BupweFbTwXvM8E885Eh7OGh/tBAeRi3X5XjqOT3P+x3+bfHKNlerSqQfhEsAW 2iZygF0+8qakl+FnG/4G7ugLixdIWIQwNu3J+NrhR5ooqxZ43ATexIfIJ0Lj/r5ofunO OFvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TTDsla0+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 85-v6si27681083pgh.381.2018.09.21.03.24.43; Fri, 21 Sep 2018 03:24:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TTDsla0+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390117AbeIUQMy (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:54 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54622 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727776AbeIUQMx (ORCPT ); Fri, 21 Sep 2018 12:12:53 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOGCI033032; Fri, 21 Sep 2018 05:24:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525457; bh=Oy9h1kP8jbCXe+8kD93AkYommSwhxCLq/ir/s6HONHk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TTDsla0+qw0fOos7SiyBlN9shgEmejgPp2Prs4yaOEVXQ+nYTswognIYWoINtOTR8 LDvksH6Y/BD7ncQ66JYTt+yUIOx+eCjrHn5O21gxGGoG0ZahBd8DvYwEqwMLE3ScaS m7l4sjKbuu/DcleMh2dhpz5d9k2m73KFi89YdWIk= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOGZD030984; Fri, 21 Sep 2018 05:24:16 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:16 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:16 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtT032280; Fri, 21 Sep 2018 05:24:12 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 25/40] dt-bindings: PCI: Add dt-binding to configure PCIe mode Date: Fri, 21 Sep 2018 15:51:40 +0530 Message-ID: <20180921102155.22839-26-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon register that should be used to configure PCIe in RC mode or EP mode. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 3a551687cfa2..8ee07197a063 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -23,6 +23,8 @@ pcie_msi_intc : Interrupt controller device node for MSI IRQ chip ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. +ti,syscon-pcie-mode : phandle to the device control module required to configure + PCI in either RC mode or EP mode. Example: pcie_msi_intc: msi-interrupt-controller { From patchwork Fri Sep 21 10:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147206 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629248ljw; Fri, 21 Sep 2018 03:24:47 -0700 (PDT) X-Google-Smtp-Source: ANB0VdawmlyfB7gVT9LYZIh3J7JiVRXwS4Q2x4OCMw+slo3dQzjxzD6EdDnYkCmS6WYJGGICvJNW X-Received: by 2002:a63:91:: with SMTP id 139-v6mr40953698pga.389.1537525487724; Fri, 21 Sep 2018 03:24:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525487; cv=none; d=google.com; s=arc-20160816; b=CETEulD/GL7bKwJcwLyokOPu0gwjlbMrmtxnPPNcfSy12zXzSWLdVs63EaBpDHeE5u FJ+vVE1qwlNwNMwwnT809VmwUuzY5vhNHOJYeH5J9/YN3iiKIAgoIV0z1woWVqcfega9 BvuhJaM870VDI6yErH4dSNAFP374lEEdXMCREc4S+5r2DNVIZwxiyyGd7o+Vb9TDbzXv L2nt0bNxHBegyocIhfQX0fyqsEsRQ5HZYBLnUBWn8gFvO1yUuxUHLwShZgpFMBC3dPBe /jZzdrFsDilIEyPMdbuknNevWftLf2t00Ddm9KQrBU3Lan1YzC/giLvzpx3mmWnjvhYD ruNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Zb1pEq/7Y0jRAn9nRMQL9/laMZOm8SQbSboCqJYQG+M=; b=Tp7lhg+u1AzSg1QdWjQ4fuqmeb0SEtzStn00Kqh6nTxhmRCHk0rrVkY7A/EKM4NPmm kHRbbc/g9tqEg49W9ILoMCuXdjFvrBXL1K8HS9M9T2IdAQ+DPc1SX8foZvdkQ1lfJ9SH 4lUtGSMupYONhkeovnK2X5clEmrDGvCZSe6zQ6ZsaCcvpKLt9ZkdDClrPchpbAyc/CwN jObe6k5th7q4yX75dEf4pu/efOPt20tG1ihk9/P83vCsCVZhZwpoTP9ASj3EE7goEfE6 +mZorlLdommm93pYOrHBlF/ouTjoVDkLZZzYbjhwVOqubVSXeTm0HAg7vQ1LUhJ9+/V4 5PzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Qr9/RnDd"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b3-v6si6006772pld.36.2018.09.21.03.24.47; Fri, 21 Sep 2018 03:24:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Qr9/RnDd"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390133AbeIUQM5 (ORCPT + 32 others); Fri, 21 Sep 2018 12:12:57 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35170 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727776AbeIUQM5 (ORCPT ); Fri, 21 Sep 2018 12:12:57 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOL1B030608; Fri, 21 Sep 2018 05:24:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525461; bh=Zb1pEq/7Y0jRAn9nRMQL9/laMZOm8SQbSboCqJYQG+M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Qr9/RnDd2oJjpm7qzfzWh3Picr00OuO8n75xmCyyI60rZH2AgodXim8eJeQP51tH4 pLQ0qRrl2ZvkQkULaTuVwsgeipw6aEXDVXXj6ioLVMfD8LFBMN7xVBWhfS0miOFdMK NCoNHGE0+JZsPyaluoQj7at25ftRYRelwrnYEjWU= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOLGK031053; Fri, 21 Sep 2018 05:24:21 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:20 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:20 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtU032280; Fri, 21 Sep 2018 05:24:16 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 26/40] PCI: keystone: Explicitly set the PCIe mode Date: Fri, 21 Sep 2018 15:51:41 +0530 Message-ID: <20180921102155.22839-27-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 13e865f82f96..e8328039a017 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -80,6 +80,15 @@ #define PCIE_RC_K2L 0xb00a #define PCIE_RC_K2G 0xb00b +#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) +#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) + +#define EP 0x0 +#define LEG_EP 0x1 +#define RC 0x2 + +#define KS_PCIE_SYSCLOCKOUTEN BIT(0) + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) static int ks_pcie_start_link(struct dw_pcie *pci); @@ -749,6 +758,30 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) return ret; } +static int ks_pcie_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; + val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -865,6 +898,10 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Fri Sep 21 10:21:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147208 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629323ljw; Fri, 21 Sep 2018 03:24:53 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbHw/BGtRj6d8utRzyz1PrcG3nFpdhtBgZ39voBGUSQtgZ2m9hJTLwlc/6FsvjpRmYL6r0E X-Received: by 2002:a17:902:70cb:: with SMTP id l11-v6mr8569811plt.330.1537525493835; Fri, 21 Sep 2018 03:24:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525493; cv=none; d=google.com; s=arc-20160816; b=GxHtD7AIfZzuWauWvqEDD1MFkUOm34bwtdCeJY6QEdm4CykvFCuPXSeEOsls5uSIt6 TW1DhM+QFNM0DVTMPVp9yGzC1wacy4vDJ0b8xKHkrKilhY8dhisnyRkt/Cl/bHT/Rk4W Esz94XF6aDxdnrG/BiDEUcE7ysbRnsSyTW+2ZFVLkasBlvgjGuXqDoM/huO7x7KSqIRa y+ZOdl+9MviD9vdhQOxfBRYYtHwXEQhN9GjQobrTumkPq4nTdfDjjFsAfo0XF+qXikJf ZnE+3hGB67OMlAe/fyucvGiHjDbV02Iu3SN+TRjh4idw0ZimAcfHgDt2bK+2bW37Na9r VcTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; b=G6+r+R1pU8/U3QvwL4cgm4HIyxuQgH9MViQ2rPQX/BKmhLDE10rANq3L97Gw4JRkyo D8y+daZjugLgy072IPAeSwFh+YglKt6y3NchVdgLrNusLNWHPXkI4Vix8eA+1BFolMWE kJotwVLTxgVuA1jl9kdohLpSNB9qLZPA1fvOV7Zq+ArTxQhi6mWhk+DN7y+B6iT4UTM2 oerrIlw+IPtdQ6IV4hHHWoxK3q6bGfy04JLFK3PT95QqKszqRjUKa4mgZpwPl1ec1Rs8 gifDuY1g8cY3y6z8/cnGQUV68wL1x7X1QzInQEWCXJ0liDyKNI2ElMUGAl0UXVF4rsdf wIZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nu3TGxlw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m13-v6si24991863pgh.360.2018.09.21.03.24.53; Fri, 21 Sep 2018 03:24:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nu3TGxlw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390162AbeIUQND (ORCPT + 32 others); Fri, 21 Sep 2018 12:13:03 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51460 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389684AbeIUQND (ORCPT ); Fri, 21 Sep 2018 12:13:03 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOPt8033430; Fri, 21 Sep 2018 05:24:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525465; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nu3TGxlwvzyx0/kTwPWT5AxpJh6sV+J2isg9XuGPciFnbOh16Bpzzuv0zdrx+is8N zGc2bIDfxCKPp6bPfGDYYnPZCtdHBYLaCxSgGICNRAzIO71fbL9MIG4eEXVuPGxtNY u1hIhqulWQPveX2YkxlH5zarRT/lNY398NLuVO2c= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOPkd031145; Fri, 21 Sep 2018 05:24:25 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:25 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:25 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtV032280; Fri, 21 Sep 2018 05:24:21 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 27/40] dt-bindings: PCI: Document "atu" reg-names Date: Fri, 21 Sep 2018 15:51:42 +0530 Message-ID: <20180921102155.22839-28-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document "atu" reg-names required to get the register space for ATU in Synopsys designware core version >= 4.80. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index c124f9bc11f3..5561a1c060d0 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -4,8 +4,11 @@ Required properties: - compatible: "snps,dw-pcie" for RC mode; "snps,dw-pcie-ep" for EP mode; -- reg: Should contain the configuration address space. -- reg-names: Must be "config" for the PCIe configuration space. +- reg: For designware cores version < 4.80 contains the configuration + address space. For designware core version >= 4.80, contains + the configuration and ATU address space +- reg-names: Must be "config" for the PCIe configuration space and "atu" for + the ATU address space. (The old way of getting the configuration address space from "ranges" is deprecated and should be avoided.) - num-lanes: number of lanes to use From patchwork Fri Sep 21 10:21:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147209 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629385ljw; Fri, 21 Sep 2018 03:24:58 -0700 (PDT) X-Google-Smtp-Source: ANB0VdY6WMkC2iB3LTIyKcTOld57BUBeaCXKPfItDsoVeYZGH9WELeNVqbtC2N3QlE6+dkW88Svy X-Received: by 2002:a63:5d55:: with SMTP id o21-v6mr11102369pgm.349.1537525498471; Fri, 21 Sep 2018 03:24:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525498; cv=none; d=google.com; s=arc-20160816; b=hiGB1SzZL+Ys/Ww5lACNNLz31O2oRkTW7aZQuwXzuYE6xWyYaJ+dZFa3D4bLQeV0eg S3us7DIKtSuaSBKTXLrzOrAT2bFfPLWF6WhikvQODPPYeEEk8Ciwvh52knTUf6wGoGnb tUm6YIdwgqMDml6/g9+/hId+KNozscP88OhzVGr4bFv8HlGxiGy/lP99bprLJn2XRa7l 54Esd35tg+CFBuB4yeKEbp9MNWr2vxRiIQ6aVj/E/8P5lExM9Ptm1R0sCcfDwNmfjvOF czW0hiSAIuPzZOsnStCYj6nDOJbUugw4anXWPOzNK+m4GS3imOmmG+Ik6VDh4B6JCaMV BsXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=lrM5p9gl6xq0tRPN/0eVFbRAoC6BfUDx/ZoZuhmyQWw=; b=mLjKFNT4YMEK5Q5ZgXaxp/94c0rNSdIOZZsPD7tdpQlcJW8JpHKjhzbh7o9/P60JpN jtmBzyT3GTGIt2F/qSoMqYVI0hjIiymF62x7N5I8D3fvKY2lWsSaw3SU08EuFL0zEhvt 36IrH8+mb2sEg6Ob3a2iyOjp5YoYVOT+OOu7OJ0h+YPrBoFr6P32EFxl67JhMfcBFtKT Fb2xEjb8S9pKIq1cClYDNRpvwqiK7IeHpAoN86ReEK9KxgphM81MaYtSAhBLoDFxsouM K0yAnK6/41ZI2qj9bFxYlQ0p8fVDUmAGf9Bq9ROoz+T3CAcb9g+7xHd1dZdW4FB7CmPN g+lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Cz9HnDJT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a140-v6si29096171pfa.61.2018.09.21.03.24.58; Fri, 21 Sep 2018 03:24:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Cz9HnDJT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390191AbeIUQNI (ORCPT + 32 others); Fri, 21 Sep 2018 12:13:08 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46398 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389686AbeIUQNI (ORCPT ); Fri, 21 Sep 2018 12:13:08 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOUae008046; Fri, 21 Sep 2018 05:24:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525470; bh=lrM5p9gl6xq0tRPN/0eVFbRAoC6BfUDx/ZoZuhmyQWw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Cz9HnDJTngdfKatgwJA4nl2k2qzMtp8NqD1sBixgqmL4CUFsYlbjn1oUTowbBdhq+ A8vDu8ErnzGx+KSu4jH+qVIWA2N598+jgt6QLDYdd0VZDOrZHYUIimDkluNU0oHzRZ b1fWtASpC663tVWccOivb3FsvIcoRAzbjNFJhD0o= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOUG2031206; Fri, 21 Sep 2018 05:24:30 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:30 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:30 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtW032280; Fri, 21 Sep 2018 05:24:25 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 28/40] PCI: dwc: Fix ATU identification for designware version >= 4.80 Date: Fri, 21 Sep 2018 15:51:43 +0530 Message-ID: <20180921102155.22839-29-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which hasn't populated the version member, the old method of identification will still be used. Since identifying if iATU is enabled or not is specific to both host mode and device mode, setting of iatu_unroll_enabled is moved from pcie-designware-host.c to pcie-designware.c Use the register space having reg-names as "atu" for the ATU address space. For platforms which hasn't populated atu register space, use the existing hard coded address. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-host.c | 16 ------ drivers/pci/controller/dwc/pcie-designware.c | 50 +++++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 9 ++-- 3 files changed, 52 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 29a05759a294..37ea4f7e77b0 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -637,17 +637,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) -{ - u32 val; - - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); - if (val == 0xffffffff) - return 1; - - return 0; -} - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val, ctrl, num_ctrls; @@ -694,11 +683,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 778c4f76a884..881f9c3786ae 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -92,16 +92,27 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + void __iomem *base = pci->atu_base; + u32 val; + int ret; + + ret = dw_pcie_read(base + offset + reg, 0x4, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); - return dw_pcie_readl_dbi(pci, offset + reg); + return val; } static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, u32 val) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); + void __iomem *base = pci->atu_base; + int ret; - dw_pcie_writel_dbi(pci, offset + reg, val); + ret = dw_pcie_write(base + offset + reg, 0x4, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); } static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, @@ -186,16 +197,27 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index); + void __iomem *base = pci->atu_base; + u32 val; + int ret; + + ret = dw_pcie_read(base + offset + reg, 0x4, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); - return dw_pcie_readl_dbi(pci, offset + reg); + return val; } static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, u32 val) { u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index); + void __iomem *base = pci->atu_base; + int ret; - dw_pcie_writel_dbi(pci, offset + reg, val); + ret = dw_pcie_write(base + offset + reg, 0x4, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); } static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, @@ -339,6 +361,17 @@ int dw_pcie_link_up(struct dw_pcie *pci) (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); } +static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + if (val == 0xffffffff) + return 1; + + return 0; +} + void dw_pcie_setup(struct dw_pcie *pci) { int ret; @@ -347,6 +380,15 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; + if (pci->version >= 0x480A || (!pci->version && + dw_pcie_iatu_unroll_enabled(pci))) { + pci->iatu_unroll_enabled = true; + if (!pci->atu_base) + pci->atu_base = pci->dbi_base + PCIE_ATU_BASE_OFFSET; + } + dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + "enabled" : "disabled"); + ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) lanes = 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a4d939536faf..b8ff37d1563b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -85,6 +85,7 @@ * iATU Unroll-specific register definitions * From 4.80 core version the address translation will be made by unroll */ +#define PCIE_ATU_BASE_OFFSET (0x3 << 20) #define PCIE_ATU_UNR_REGION_CTRL1 0x00 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 #define PCIE_ATU_UNR_LOWER_BASE 0x08 @@ -95,10 +96,10 @@ /* Register address builder */ #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ - ((0x3 << 20) | ((region) << 9)) + ((region) << 9) -#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ - ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) +#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ + (((region) << 9) | (0x1 << 8)) #define MAX_MSI_IRQS 256 #define MAX_MSI_IRQS_PER_CTRL 32 @@ -220,11 +221,13 @@ struct dw_pcie { struct device *dev; void __iomem *dbi_base; void __iomem *dbi_base2; + void __iomem *atu_base; u32 num_viewport; u8 iatu_unroll_enabled; struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; + unsigned int version; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Fri Sep 21 10:21:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147212 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629594ljw; Fri, 21 Sep 2018 03:25:12 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaJZy8Aj8o4grAwObkdQ1SyeTNYwo+YyUH9dos8kuvYfd2lgIC9P/ZJdGEseZgTL652vP9Z X-Received: by 2002:a17:902:b492:: with SMTP id y18-v6mr6362095plr.208.1537525511972; Fri, 21 Sep 2018 03:25:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525511; cv=none; d=google.com; s=arc-20160816; b=ZTh1K2oCTQIfxCqC0QrLzbdhCOAT0ODmzOTqxSLXOYd3klNQsaQHCfsE9OkABVMZOE bj4eNgZGfME8oTByR+eAbPvhzC6KfWhj4JiQB2u8OfWOljfQrXZ5mS1RkOWWbqdOtRUe p3xs4Qj+/IWCpbV0aS4gcRyzqzQrNEMRhxkqjL7iTKriqqcWJEdV7W0XC4jEJ9glF0je eGqThJFzfrL+vKrv+AZSzeoEdJNjaJqBKQtLqqF+p/neWvAeg4SgTn3TOEP1SHFkncOT MxteLQllQbxVjIrKznf6fk26u6BZV5k8waUBWixDuE2EFVPnK7do1S1lF1aN6UtXyloF rHCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ctc4e/xsmLuyHnBieUhBknnPJYfDslzVYzZW978E0Bk=; b=aFOKR/pRJeFyjO6sCyVWp6mYgFSRuDB9k43ev7ATQPmfi+X5Huwk7d7ac6GTskP8ax kfPgBC1bvWFRGM8znwinc88QptMN6tyXeY3hGoz4WGDl11KjdSnFeFLO1nh9Pm+4xPKw yCL0FCRxdGhV1fflLd8FMxaWXnuS3mFS+KOp9GCypVBFFPtiZokgYrCWx7gWalFI/YL3 lo5siUiqSmfJw1eAiVYGL0j8BRf6nYZG3tgL7jtpQcEO6a55rAv9aneCDg8Uckl7UZad 8YrF7eQxQXd7F3kxFoJaXNKTqprIXV3YWa1XEGDU6MIDTaxaYED8xx/+V1X9S6Kz0r6P B9uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GEPsVoNB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Since pci-keystone.c will be used for AM65X platforms which is an ARM64 platform, allow hook_fault_code to be compiled only for ARM32. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e8328039a017..91337e9c87a5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -493,6 +493,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return 0; } +#ifdef CONFIG_ARM /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -512,6 +513,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +#endif static void ks_pcie_setup_mem_space(struct keystone_pcie *ks_pcie) { @@ -592,12 +594,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; +#ifdef CONFIG_ARM /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); +#endif ks_pcie_start_link(pci); return dw_pcie_wait_for_link(pci); From patchwork Fri Sep 21 10:21:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147221 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp631549ljw; Fri, 21 Sep 2018 03:27:16 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYvZ9xm/uaQjiTANb+ASa1UIPc+07cGyz0q7UlWuXEE9CU3PV4ZopPXGD+gsjYUzZcfHQev X-Received: by 2002:a17:902:158b:: with SMTP id m11-v6mr43757497pla.102.1537525636141; Fri, 21 Sep 2018 03:27:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525636; cv=none; d=google.com; s=arc-20160816; b=qI3dKwMLLrYZ77DBffmG8LLE193zBUHsK5Kh9kTsjaXdOdhpyPXC5Z+c39KLLwWKST XHgDJZUi09v4QYKQZXg6yeRp1sn8uEOu9ihP91rhtpRP/WAvhpYbLQ7L87KK+iNONQ8E 8kYykC1HyVRW+KfvzSZKcu8Q+j9FB072/dOJX4rTc5Xhc5/e6ewTEKk7P6CyWbfhwUOB D6yyVPSRzV83ncp9Hun6jMcdR0y0wjFCKd6he1KHTHvfOMx747V9/qhf03D/B8rxuOEb zqZ9Bg9b071rG7nSsXgMcJPLNyLKFcXh+XgDxut9nJDT6ldZkammTMJx2BMuRslyWvCR bhjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dX0AnoHumpKjN/Hxuc1DnDN/uBYu6jOtQe3dNmu6KNI=; b=eK1cdM1KwQF2bWur7TgLBsOn0OI+rt5NMA18foLmbuA2rvjd9CXQBuAVxVQhECGCcK JbdTBit6V4NCPRRiv2EGj1dClBM86DIupAA8rCut0zPesaDYe92v7ljgWY4e19zFlY8h 5N9acCId1A5fuvUIihzpU1DqPlKuQhug5/Nv7QpNeykV5lGbqhEkXh1f9+fgxtLQf6fC WlWR0BZxcbzo/Albkq8Vml0MsO3FXirQBgIdg7w859yt+faCu7/tpFncvOAn2XK18qqa 1GLltiV8xYEXHec3NqxCDJZCBoiEcDhS28qeXf3hlgGRV1JlAFqBOp/qdLbrIrgQaTwP adpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=l0FHH5vw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 8ee07197a063..5c60e911b8b1 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -11,7 +11,8 @@ described here as well as properties that are not applicable. Required Properties:- -compatibility: "ti,keystone-pcie" +compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC + Should be "ti,am654-pcie-rc" for RC on AM654x SoC reg: Three register ranges as listed in the reg-names property reg-names: "dbics" for the DesignWare PCIe registers, "app" for the TI specific application registers, "config" for the @@ -20,6 +21,9 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines + (required if the compatible is "ti,keystone-pcie") +msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt + (required if the compatible is "ti,am654-pcie-rc". ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. 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Fri, 21 Sep 2018 05:24:43 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtZ032280; Fri, 21 Sep 2018 05:24:39 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 31/40] PCI: keystone: Add support for PCIe in AM654x Platforms Date: Fri, 21 Sep 2018 15:51:46 +0530 Message-ID: <20180921102155.22839-32-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 118 +++++++++++++++++++--- 2 files changed, 107 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194240a5..42f5bfa0f2fe 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -104,7 +104,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) + depends on ARCH_KEYSTONE || ARCH_K3 || (ARM && COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST help diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 91337e9c87a5..fe7daab6a518 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -89,11 +90,19 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) +#define AM654_PCIE_DEV_TYPE_MASK 0x3 +#define AM654_WIN_SIZE SZ_64K + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) static int ks_pcie_start_link(struct dw_pcie *pci); static void ks_pcie_stop_link(struct dw_pcie *pci); +struct ks_pcie_of_data { + const struct dw_pcie_host_ops *host_ops; + unsigned int version; +}; + struct keystone_pcie { struct dw_pcie *pci; int num_lanes; @@ -173,6 +182,16 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + + dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n"); + + return 0; +} + static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -409,6 +428,8 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); if (!intc_np) { + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + return 0; dev_WARN(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } @@ -520,11 +541,16 @@ static void ks_pcie_setup_mem_space(struct keystone_pcie *ks_pcie) u32 val; u32 num_viewport = ks_pcie->num_viewport; struct dw_pcie *pci = ks_pcie->pci; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; struct pcie_port *pp = &pci->pp; u64 start = pp->mem->start; u64 end = pp->mem->end; int i; + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + return; + val = ilog2(OB_WIN_SIZE); ks_pcie_app_writel(ks_pcie, OB_SIZE, val); @@ -559,8 +585,10 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) if (ret) return ret; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -619,6 +647,11 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .scan_bus = ks_pcie_v3_65_scan_bus, }; +static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { + .host_init = ks_pcie_host_init, + .msi_host_init = ks_pcie_am654_msi_host_init, +}; + static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { u32 reg; @@ -666,7 +699,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); @@ -676,14 +708,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } -static const struct of_device_id ks_pcie_of_match[] = { - { - .type = "pci", - .compatible = "ti,keystone-pcie", - }, - { }, -}; - static void ks_pcie_stop_link(struct dw_pcie *pci) { u32 val; @@ -786,13 +810,59 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } +static int ks_pcie_am654_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = AM654_PCIE_DEV_TYPE_MASK; + val = RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + +static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { + .host_ops = &ks_pcie_am654_host_ops, + .version = 0x490A, +}; + +static const struct of_device_id ks_pcie_of_match[] = { + { + .type = "pci", + .compatible = "ti,keystone-pcie", + }, + { + .data = &ks_pcie_am654_rc_of_data, + .compatible = "ti,am654-pcie-rc", + }, + { }, +}; + static int __init ks_pcie_probe(struct platform_device *pdev) { + const struct dw_pcie_host_ops *host_ops = &ks_pcie_host_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct ks_pcie_of_data *data; + const struct of_device_id *match; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; + unsigned int version = 0x365A; struct device_link **link; + void __iomem *atu_base; struct resource *res; void __iomem *base; u32 num_viewport; @@ -803,6 +873,13 @@ static int __init ks_pcie_probe(struct platform_device *pdev) int irq; int i; + match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); + data = (struct ks_pcie_of_data *)match->data; + if (data) { + version = data->version; + host_ops = data->host_ops; + } + ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) return -ENOMEM; @@ -826,6 +903,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; + pci->version = version; ret = of_property_read_u32(np, "num-viewport", &num_viewport); if (ret < 0) { @@ -902,10 +980,26 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; + if (pci->version >= 0x480A) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atu_base)) { + ret = PTR_ERR(atu_base); + goto err_get_sync; + } + + pci->atu_base = atu_base; + + ret = ks_pcie_am654_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } else { + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Fri Sep 21 10:21:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147215 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629819ljw; Fri, 21 Sep 2018 03:25:26 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ9YWX12Fr6nvu0IR2dGFShSypLKJ744ORKtQpGiSu6f2ZBiZ33XeVgMXW9b6h32SZUmyIq X-Received: by 2002:a17:902:261:: with SMTP id 88-v6mr18302719plc.331.1537525526463; Fri, 21 Sep 2018 03:25:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525526; cv=none; d=google.com; s=arc-20160816; b=YGLLAQTT+ExI8XMa82X+m2Zk+GM+9jU6yAyHFCuMYAF2iFW8C7/zMyu5ph1Vv3mNGy XHd0FjFyHG9yecMG6qbHU6yOOpdyYljdwNi7ZVq/MBJkeQS7EQbms2I79XZdzz/Y8y9U 5Z4NsGb+OUGiwLH0r7yQwk5hcpLOW9yehhBZES17JPOO4SE5VZPvWGvzec1q7EoshUqX WThH5nzUX6STvLl92mwGQLQVn9MDlXHE94/pFUvUksgzXOwaGgaGE8XZ304EBhDgaKeM 36aqRYohCioygkulS++4CRxHwUZEGvJ3fvWkuiuSZMqYGChkaAhMORPa0dpvofnfZZ3P Yr2A== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id z2-v6si3990553plo.412.2018.09.21.03.25.26; Fri, 21 Sep 2018 03:25:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xhe2jzcn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390269AbeIUQNg (ORCPT + 32 others); Fri, 21 Sep 2018 12:13:36 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35238 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQNf (ORCPT ); Fri, 21 Sep 2018 12:13:35 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAOvJT030831; Fri, 21 Sep 2018 05:24:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525497; bh=hTj4z+hpEufzsKQNKD0NN4HsHu5h+fwjTFRnXwdZf70=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xhe2jzcn4/KUrJdmm13oBgvEKgXGNcH4W/naq7pUBXDQvQGKDFDAGG1ubV7MhSlZH 3OWaYcRHeL39b48398hmRlkSyYQiASxWSqIjPdKyGhJcf5labgXOqi6RdsUAicO0zU QQ6xr4E/gEPyO2ZVeenJiURv4UdR0h+P29zZIFrw= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAOv1V031543; Fri, 21 Sep 2018 05:24:57 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:24:57 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:24:57 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtc032280; Fri, 21 Sep 2018 05:24:52 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 34/40] phy: ti: Add a new SERDES driver for TI's AM654x SoC Date: Fri, 21 Sep 2018 15:51:49 +0530 Message-ID: <20180921102155.22839-35-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 will be added later. SERDES in am654x has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/Kconfig | 11 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-am654-serdes.c | 513 ++++++++++++++++++++++++++++++ 3 files changed, 525 insertions(+) create mode 100644 drivers/phy/ti/phy-am654-serdes.c -- 2.17.1 diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 20503562666c..8a556649de68 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -20,6 +20,17 @@ config PHY_DM816X_USB help Enable this for dm816x USB to work. +config PHY_AM654_SERDES + tristate "TI AM654 SERDES support" + depends on OF && ARCH_K3 || COMPILE_TEST + select GENERIC_PHY + select MULTIPLEXER + select REGMAP_MMIO + select MUX_MMIO + help + This option enables support for TI AM654 SerDes PHY used for + PCIe. + config OMAP_CONTROL_PHY tristate "OMAP CONTROL PHY Driver" depends on ARCH_OMAP2PLUS || COMPILE_TEST diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile index 9f361756eaf2..0df18acbbb60 100644 --- a/drivers/phy/ti/Makefile +++ b/drivers/phy/ti/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o diff --git a/drivers/phy/ti/phy-am654-serdes.c b/drivers/phy/ti/phy-am654-serdes.c new file mode 100644 index 000000000000..1a6216e7c69e --- /dev/null +++ b/drivers/phy/ti/phy-am654-serdes.c @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * PCIe SERDES driver for AM654x SoC + * + * Copyright (C) 2018 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMU_R07C 0x7c +#define CMU_MASTER_CDN_O BIT(24) + +#define COMLANE_R138 0xb38 +#define CONFIG_VERSION_REG_MASK GENMASK(23, 16) +#define CONFIG_VERSION_REG_SHIFT 16 +#define VERSION 0x70 + +#define COMLANE_R190 0xb90 +#define L1_MASTER_CDN_O BIT(9) + +#define COMLANE_R194 0xb94 +#define CMU_OK_I_0 BIT(19) + +#define SERDES_CTRL 0x1fd0 +#define POR_EN BIT(29) + +#define WIZ_LANEXCTL_STS 0x1fe0 +#define TX0_ENABLE_OVL BIT(31) +#define TX0_ENABLE_MASK GENMASK(30, 29) +#define TX0_ENABLE_SHIFT 29 +#define TX0_DISABLE_STATE 0x0 +#define TX0_SLEEP_STATE 0x1 +#define TX0_SNOOZE_STATE 0x2 +#define TX0_ENABLE_STATE 0x3 +#define RX0_ENABLE_OVL BIT(15) +#define RX0_ENABLE_MASK GENMASK(14, 13) +#define RX0_ENABLE_SHIFT 13 +#define RX0_DISABLE_STATE 0x0 +#define RX0_SLEEP_STATE 0x1 +#define RX0_SNOOZE_STATE 0x2 +#define RX0_ENABLE_STATE 0x3 + +#define WIZ_PLL_CTRL 0x1ff4 +#define PLL_ENABLE_OVL BIT(31) +#define PLL_ENABLE_MASK GENMASK(30, 29) +#define PLL_ENABLE_SHIFT 29 +#define PLL_DISABLE_STATE 0x0 +#define PLL_SLEEP_STATE 0x1 +#define PLL_SNOOZE_STATE 0x2 +#define PLL_ENABLE_STATE 0x3 +#define PLL_OK BIT(28) + +#define PLL_LOCK_TIME 100000 /* in microseconds */ +#define SLEEP_TIME 100 /* in microseconds */ + +#define LANE_USB3 0x0 +#define LANE_PCIE0_LANE0 0x1 + +#define LANE_PCIE1_LANE0 0x0 +#define LANE_PCIE0_LANE1 0x1 + +#define SERDES_NUM_CLOCKS 3 + +struct serdes_am654_clk_mux { + struct clk_hw hw; + struct regmap *regmap; + unsigned int reg; + int *table; + u32 mask; + u8 shift; +}; + +#define to_serdes_am654_clk_mux(_hw) \ + container_of(_hw, struct serdes_am654_clk_mux, hw) + +static struct regmap_config serdes_am654_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +struct serdes_am654 { + struct regmap *regmap; + struct device *dev; + struct mux_control *control; + bool busy; + u32 type; + struct device_node *of_node; + struct clk_onecell_data clk_data; + struct clk *clks[SERDES_NUM_CLOCKS]; +}; + +static int serdes_am654_enable_pll(struct serdes_am654 *phy) +{ + u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK; + u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT); + + regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val); + + return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val, + val & PLL_OK, 1000, PLL_LOCK_TIME); +} + +static void serdes_am654_disable_pll(struct serdes_am654 *phy) +{ + u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK; + + regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, 0); +} + +static int serdes_am654_enable_txrx(struct serdes_am654 *phy) +{ + u32 mask; + u32 val; + + /* Enable TX */ + mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK; + val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT); + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val); + + /* Enable RX */ + mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK; + val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT); + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val); + + return 0; +} + +static int serdes_am654_disable_txrx(struct serdes_am654 *phy) +{ + u32 mask; + + /* Disable TX */ + mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK; + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0); + + /* Disable RX */ + mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK; + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0); + + return 0; +} + +static int serdes_am654_power_on(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + struct device *dev = phy->dev; + int ret; + u32 val; + + ret = serdes_am654_enable_pll(phy); + if (ret) { + dev_err(dev, "Failed to enable PLL\n"); + return ret; + } + + ret = serdes_am654_enable_txrx(phy); + if (ret) { + dev_err(dev, "Failed to enable TX RX\n"); + return ret; + } + + return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val, + val & CMU_OK_I_0, SLEEP_TIME, + PLL_LOCK_TIME); +} + +static int serdes_am654_power_off(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + + serdes_am654_disable_txrx(phy); + serdes_am654_disable_pll(phy); + + return 0; +} + +static int serdes_am654_init(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + u32 mask; + u32 val; + + mask = CONFIG_VERSION_REG_MASK; + val = VERSION << CONFIG_VERSION_REG_SHIFT; + regmap_update_bits(phy->regmap, COMLANE_R138, mask, val); + + val = CMU_MASTER_CDN_O; + regmap_update_bits(phy->regmap, CMU_R07C, val, val); + + val = L1_MASTER_CDN_O; + regmap_update_bits(phy->regmap, COMLANE_R190, val, val); + + return 0; +} + +static int serdes_am654_reset(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + u32 val; + + val = POR_EN; + regmap_update_bits(phy->regmap, SERDES_CTRL, val, val); + mdelay(1); + regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0); + + return 0; +} + +struct phy *serdes_am654_xlate(struct device *dev, struct of_phandle_args + *args) +{ + struct serdes_am654 *am654_phy; + struct phy *phy; + int ret; + + phy = of_phy_simple_xlate(dev, args); + if (IS_ERR(phy)) + return phy; + + am654_phy = phy_get_drvdata(phy); + if (am654_phy->type != args->args[0] && am654_phy->busy) + return ERR_PTR(-EBUSY); + + ret = mux_control_select(am654_phy->control, args->args[1]); + if (ret) { + dev_err(dev, "Failed to select SERDES Lane Function\n"); + return ERR_PTR(ret); + } + + am654_phy->busy = true; + am654_phy->type = args->args[0]; + + return phy; +} + +static const struct phy_ops ops = { + .reset = serdes_am654_reset, + .init = serdes_am654_init, + .power_on = serdes_am654_power_on, + .power_off = serdes_am654_power_off, + .owner = THIS_MODULE, +}; + +static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw) +{ + struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); + unsigned int num_parents = clk_hw_get_num_parents(hw); + struct regmap *regmap = mux->regmap; + unsigned int reg = mux->reg; + unsigned int val; + int i; + + regmap_read(regmap, reg, &val); + val >>= mux->shift; + val &= mux->mask; + + for (i = 0; i < num_parents; i++) + if (mux->table[i] == val) + return i; + + pr_err("Failed to find a parent of %s clock\n", hw->init->name); + + return 0; +} + +static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); + struct regmap *regmap = mux->regmap; + unsigned int reg = mux->reg; + int val; + int ret; + + val = mux->table[index]; + + if (val == -1) + return -EINVAL; + + val <<= mux->shift; + ret = regmap_update_bits(regmap, reg, mux->mask << mux->shift, val); + + return ret; +} + +static const struct clk_ops serdes_am654_clk_mux_ops = { + .set_parent = serdes_am654_clk_mux_set_parent, + .get_parent = serdes_am654_clk_mux_get_parent, +}; + +static int mux_table[SERDES_NUM_CLOCKS][3] = { + /* + * The entries represent values for selecting between + * {left input, external reference clock, right input} + * Only one of Left Output or Right Output should be used since + * both left and right output clock uses the same bits and modifying + * one clock will impact the other. + */ + { BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */ + { -1, BIT(3), BIT(1) }, /* Mux of Left Output */ + { BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */ +}; + +static int mux_mask[SERDES_NUM_CLOCKS] = { 0x5, 0xa, 0xa }; + +static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, + const char *clock_name, int clock_num) +{ + struct device_node *node = am654_phy->of_node; + struct device *dev = am654_phy->dev; + struct serdes_am654_clk_mux *mux; + struct device_node *regmap_node; + const char **parent_names; + struct clk_init_data init; + unsigned int num_parents; + struct regmap *regmap; + const __be32 *addr; + unsigned int reg; + struct clk *clk; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0); + of_node_put(regmap_node); + if (!regmap_node) { + dev_err(dev, "Fail to get serdes-clk node\n"); + return -ENODEV; + } + + regmap = syscon_node_to_regmap(regmap_node->parent); + if (IS_ERR(regmap)) { + dev_err(dev, "Fail to get Syscon regmap\n"); + return PTR_ERR(regmap); + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + addr = of_get_address(regmap_node, 0, NULL, NULL); + if (!addr) + return -EINVAL; + + reg = be32_to_cpu(*addr); + + init.ops = &serdes_am654_clk_mux_ops; + init.flags = CLK_SET_RATE_NO_REPARENT; + init.parent_names = parent_names; + init.num_parents = num_parents; + init.name = clock_name; + + mux->table = mux_table[clock_num]; + mux->regmap = regmap; + mux->reg = reg; + mux->shift = 4; + mux->mask = mux_mask[clock_num]; + mux->hw.init = &init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + am654_phy->clks[clock_num] = clk; + + return 0; +} + +static const struct of_device_id serdes_am654_id_table[] = { + { + .compatible = "ti,phy-am654-serdes", + }, + {} +}; +MODULE_DEVICE_TABLE(of, serdes_am654_id_table); + +static int serdes_am654_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct clk_onecell_data *clk_data; + struct serdes_am654 *am654_phy; + struct mux_control *control; + const char *clock_name; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + struct phy *phy; + int ret; + int i; + + am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL); + if (!am654_phy) + return -ENOMEM; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "serdes"); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to initialize regmap\n"); + return PTR_ERR(regmap); + } + + control = devm_mux_control_get(dev, NULL); + if (IS_ERR(control)) + return PTR_ERR(control); + + am654_phy->dev = dev; + am654_phy->of_node = node; + am654_phy->regmap = regmap; + am654_phy->control = control; + + platform_set_drvdata(pdev, am654_phy); + + for (i = 0; i < SERDES_NUM_CLOCKS; i++) { + ret = of_property_read_string_index(node, "clock-output-names", + i, &clock_name); + if (ret) { + dev_err(dev, "Failed to get clock name\n"); + return ret; + } + + ret = serdes_am654_clk_register(am654_phy, clock_name, i); + if (ret) { + dev_err(dev, "Failed to initialize clock %s\n", + clock_name); + return ret; + } + } + + clk_data = &am654_phy->clk_data; + clk_data->clks = am654_phy->clks; + clk_data->clk_num = SERDES_NUM_CLOCKS; + ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (ret) + return ret; + + pm_runtime_enable(dev); + + phy = devm_phy_create(dev, NULL, &ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, am654_phy); + phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate); + if (IS_ERR(phy_provider)) { + ret = PTR_ERR(phy_provider); + goto clk_err; + } + + return 0; + +clk_err: + of_clk_del_provider(node); + + return ret; +} + +static int serdes_am654_remove(struct platform_device *pdev) +{ + struct serdes_am654 *am654_phy = platform_get_drvdata(pdev); + struct device_node *node = am654_phy->of_node; + + pm_runtime_disable(&pdev->dev); + of_clk_del_provider(node); + + return 0; +} + +static struct platform_driver serdes_am654_driver = { + .probe = serdes_am654_probe, + .remove = serdes_am654_remove, + .driver = { + .name = "phy-am654", + .of_match_table = serdes_am654_id_table, + }, +}; +module_platform_driver(serdes_am654_driver); + +MODULE_ALIAS("platform:phy-am654"); +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TI AM654x SERDES driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Sep 21 10:21:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147222 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp631746ljw; Fri, 21 Sep 2018 03:27:28 -0700 (PDT) X-Google-Smtp-Source: ANB0VdahcTE635SKUt+zy3JWqZjT2Fl8uECHIF022SjGMMGyitgHN1l+bgZxFA7MTHRcJhBAWVjQ X-Received: by 2002:a17:902:5617:: with SMTP id h23-v6mr43984326pli.324.1537525648491; Fri, 21 Sep 2018 03:27:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525648; cv=none; d=google.com; s=arc-20160816; b=oU3UIWQM+wJtB9y+t6rQemdeXz+L2HOnScDhWIQu6gymcMB9n+qfvQTGOTaqu9BsT3 f57kyNyFzAk7d9hqXfPnSqUmEUJ9g27OWbSoCOhFr42rXT+XEXgppz184BAaMH+IXx9O C3IdbJiN5AGoGB+Xuvw5G0VaJoDwCQzyCNvlyyKMx3SYANPeD7xr0lz5cNvn8rMoSBXA Uoh7gGCsZLmwK4x86x50MUJ/FTT5qypLAcvokwWowxYDLSm3lP9Kr12K5Wee9CYKS0b8 Q6WMUFJTQKFEpee55z9jJ7h42p6miZYIWM0UTL85DXLsmIYK4/HKGKQSqa57IQ9sX7EX eBRQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id o66-v6si28058695pfb.125.2018.09.21.03.27.28; Fri, 21 Sep 2018 03:27:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Vct+aCZK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389807AbeIUQPj (ORCPT + 32 others); Fri, 21 Sep 2018 12:15:39 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35388 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389559AbeIUQPi (ORCPT ); Fri, 21 Sep 2018 12:15:38 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAP2MC030867; Fri, 21 Sep 2018 05:25:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525502; bh=G6U5swdLtcxz5b7VzXF2rNiaT43Ewb5qqlJuWNULZ/c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Vct+aCZK3/TP7Gy127AtJeTTOnKxpcSkLgnHhs+L6Hm3itokCGMUAILJ3lytbEkfr jZMDOd1fuTtGnicF1aaP4h5oNglLkMj+fThi/NaMEk4JJOnLximKFMmwNL9tfPbw+U 8WCV+CdgexjeiOLmKWjR9HdvYr8lNhasGioTdSeg= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAP2JM020796; Fri, 21 Sep 2018 05:25:02 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:25:01 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:25:01 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtd032280; Fri, 21 Sep 2018 05:24:57 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , , Sekhar Nori Subject: [RFC PATCH 35/40] ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e Date: Fri, 21 Sep 2018 15:51:50 +0530 Message-ID: <20180921102155.22839-36-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the updated binding to describe PCIe in k2e. (The older binding has never worked in upstream kernel since serdes driver was never upstreamed). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/keystone-k2e.dtsi | 15 ++++++++------- arch/arm/boot/dts/keystone.dtsi | 18 ++++++++++++++---- 2 files changed, 22 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 085e7326ea8e..d9945d600c95 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -136,20 +136,21 @@ }; pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; + compatible = "ti,keystone-pcie", "snps,dw-pcie"; + reg = <0x21020000 0x1000>, <0x21021000 0x1000>, <0x21022000 0x1000>; + reg-names = "app", "dbics", "config"; clocks = <&clkpcie1>; - clock-names = "pcie"; + clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x60000000 0x60000000 - 0 0x10000000>; - + ranges = <0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie_mode>; status = "disabled"; device_type = "pci"; num-lanes = <2>; + num-viewport = <32>; bus-range = <0x00 0xff>; - /* error interrupt */ interrupts = ; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index c298675a29a5..0245fe854367 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -93,6 +93,16 @@ #size-cells = <1>; ranges = <0x0 0x02620000 0x1000>; + pcie_devid: pcie-devid@128 { + compatible = "syscon"; + reg = <0x00000128 0x4>; + }; + + pcie_mode: pcie-mode@14c { + compatible = "syscon"; + reg = <0x0000014c 0x4>; + }; + kirq0: keystone_irq@2a0 { compatible = "ti,keystone-irq"; reg = <0x2a0 0x4>; @@ -297,13 +307,13 @@ pcie0: pcie@21800000 { compatible = "ti,keystone-pcie", "snps,dw-pcie"; + reg = <0x21800000 0x1000>, <0x21801000 0x1000>, <0x21802000 0x1000>; + reg-names = "app", "dbics", "config"; clocks = <&clkpcie>; - clock-names = "pcie"; + clock-names = "fck"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; - ranges = <0x82000000 0 0x50000000 0x50000000 - 0 0x10000000>; + ranges = <0x82000000 0 0x50000000 0x50000000 0 0x10000000>; status = "disabled"; device_type = "pci"; From patchwork Fri Sep 21 10:21:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147216 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629885ljw; Fri, 21 Sep 2018 03:25:31 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdasm6Q+bcAnUL+6SWaRiDsY50nj/pynJFRwi2s582HRCYBlUfGcUmASLLFA9iSkEvWJM31X X-Received: by 2002:a63:2541:: with SMTP id l62-v6mr10560265pgl.343.1537525531163; Fri, 21 Sep 2018 03:25:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525531; cv=none; d=google.com; s=arc-20160816; b=T5GziT14AUWhOHJNfTEJ9z3mhgvG7kbOZzWiVAmuGKL06rKCkCXVZUMhWPYgWvemfJ F7JwN85oZWC3DHipgVj21C8yaUDXYJL9P4jNXlRaTNa2bYM7nCHpRM8eg4zcB5YUba5y Vv1Qy0wzHIlNavX5afSvvT/DC+UAXPeEePf24AHwM+i6A+g84XwanIjDctT4IIZqUhGT RmGCxG+a3E0uVXRw6ubkZuDgruFcRTgRon5C4PI67a4BDFtvw0mIgQ0yqoom5YYRFfv9 hej0SJb6VtUTP0ErHnT9NgNWKer0o7GSe5z7Ow/v6gcEUCYblamJXV798VAqM8t4qRHm 4Fsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=oXmEv3zbJKHI1VttjoVtSvRnozSnUYt2kr8MS+fRUlw=; b=aGgE5p4pzZgx9HYY/4fM9YVN2klPlxuzgsBDFhdr47dilUsD4c6R5m/nl0cD4CE0Up dqPdza5vvBlqQYpFxYpfHa3+4J1QIU3rCkBU9RfPIIpMmq8k/Z6ssx1Eh3l/pRgF2dXV xqMZ3s9LFzVEZQCvXiQExJbKMlvpsNz9lfQhLLB3ios6A6fv1nlS6zzDT/nN2YpBeEoB rC3aeQ25KQRLFMsDk+lyiCcuTLvz4WHJVfSwpgxfz7LYHiRjOBNQ/VhJRI8bAWHz46dc 0gbygIYvTJ/LfjnTvBCpy0mJm7H9TyU9lndC/stRoUMY8XQjpBP+bzG52UOaVIchNUtD xajQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Re3B76MC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64-v6si7138752pgb.476.2018.09.21.03.25.30; Fri, 21 Sep 2018 03:25:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Re3B76MC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390283AbeIUQNl (ORCPT + 32 others); Fri, 21 Sep 2018 12:13:41 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51542 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389264AbeIUQNk (ORCPT ); Fri, 21 Sep 2018 12:13:40 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAP6A1033570; Fri, 21 Sep 2018 05:25:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525506; bh=oXmEv3zbJKHI1VttjoVtSvRnozSnUYt2kr8MS+fRUlw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Re3B76MCmwzUr5IOuEAPKWPlkF+ZLpbJiWCP+VMk9vMTrtALBvuyE5vbRnWI/AMWB snd7JXBZ6yQu5at3sz5RkC+blw9daORvsiQWhxddI+ZVAFe6R9t7FNTChohgEWf0yf g8D5u8CBqa0EFb0/BJY4XMB77RU6R56cXpeStC6I= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAP6El032092; Fri, 21 Sep 2018 05:25:06 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:25:06 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:25:06 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEte032280; Fri, 21 Sep 2018 05:25:02 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 36/40] arm64: dts: k3-am6: Add "socionext, synquacer-pre-its" property to gic_its Date: Fri, 21 Sep 2018 15:51:51 +0530 Message-ID: <20180921102155.22839-37-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org GIC_ITS used in AM65x platform has the same configuration as that of GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its" property to get PCI MSI working. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index adcd6341e40c..2df4acb198bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -24,6 +24,7 @@ gic_its: gic-its@18200000 { compatible = "arm,gic-v3-its"; reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; msi-controller; #msi-cells = <1>; }; From patchwork Fri Sep 21 10:21:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147219 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp629991ljw; Fri, 21 Sep 2018 03:25:37 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYXvHKGYCrtEji7yBW4idoc41X4lPxbxsrkZVEr8XMHCiKnX/RAm0Dm3MajkpJkt9w/Zf8N X-Received: by 2002:a63:1a1a:: with SMTP id a26-v6mr40787775pga.449.1537525537820; Fri, 21 Sep 2018 03:25:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525537; cv=none; d=google.com; s=arc-20160816; b=S01BddiZ/r0ILqRKXROturS801Aj/S2LVFfslWtk/qgkmnLqaGvcW+jSSQm8FYiNbV j2PFMHUVqRRIW3hbvAbXVuzmhgzsyBvI7hFaH4OHXTWJAWXxOw3zf224CFUzL9gK5w5k ld0ot/llFFX5al/r/xjL9kBLLYkEtyjDMndwNFJlJCe8c6FcuyFlOPyINZy8nNA7M83O Pst2X83o1fqrjNU5NxJndt3SKsd+pqHe3urXvfM7XZsnuNAq+mgcUBJGdQ71dDNxiceA IuIJ8tvYvnu8U0S5jdqfxBNP2xQYY0AEv0QWHlVOLvQhDP1JlSjmShuG5GxhrS1ff1mO b79w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+EYr+DKnTLrhAJbl6n8B3m2RDG0kHLAobqVuL07Op2E=; b=krobtZTqCV8FxwBtmxsuDICk45xlNdBkufNqz/hUxsYdBA8TCOCRJOelgjooOC439m +Uj/A1BCgoahIgb5F+Nsd0TzpfFnLW2UrWeLFskIjqO/vx1TgD7ppQeDN8ABVTmYiBdw J0J2146/8u41Vmiqo1Gm88n+++4tik1SFyccO6somuz6rowkYjlt6iix3p56/wQC2Y9I bY/nLfsBllap2mhs0rV7ZwVVtlHXwGG7q210VlsR4YJRrpcE8BhkdWTIU0IXgRdcfdzI ArWiC1tQjZa1IsZ6ZwoPqJmMcrem5GanlX90ExRv+8nWnlxqRKpFdkfNIvr2sXwn10Pp u/Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DBry1INq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Benoit Parrot Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 2df4acb198bd..957c9125a453 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -6,6 +6,11 @@ */ &cbass_main { + scm_conf: scm_conf@100000 { + compatible = "syscon"; + reg = <0 0x00100000 0 0x1c000>; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; From patchwork Fri Sep 21 10:21:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147223 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp631972ljw; Fri, 21 Sep 2018 03:27:41 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbldIbZey6f9AazQ1uC+bYhMu1HxDvqytnAcoTsb8lwQdWRBFdyK6tgQIA7NTehsaGwaDsV X-Received: by 2002:a63:6283:: with SMTP id w125-v6mr39713857pgb.83.1537525661738; Fri, 21 Sep 2018 03:27:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525661; cv=none; d=google.com; s=arc-20160816; b=vhHXIhYpIgAJWTQnm3jiTVJkq5b610/sJu8QmPpQsSqevYGIIwc8P/xSzzcxBBbcDA lGSDG3rkN/3/3JjGDUL6f5auZjr1MJFlutbjeti4HH+XoEgUxHeyByY4GGYzcSUlKz0J L8CqpRxL9E8m0dRCsX7jp10ePNt1noummkBWBMK/wG6k0e4XPiJK8auYeFsv4cT8/FEG qJM7DGRhg0z7xM83e0qXhOrZAt/8cEi3jB+epmwp4BvKWVLIFnp3xpwdGagsXPcmpUAd Xt1Lz6ycjV4KQD2k1MLn3F/l2sxbP6R/5sY6BfpRfreiF3zDwHf1/gBT1CX+JFB12LOl sPLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=o42oR+cPzXSXz2nnwYCWDDPfzIB1x+eMkvxWlBXLaII=; b=qVkve0pR6IxMwvrJExEdjH08XDvOZ/mUgdmGfEuhORgGZutnUcceOUICNfRYifArTn NyrUKgmb8ZWDqCsLiKcYs9Csa6mjIMl2vNC+0jfAr5HEfS+ztLjLOORlWQCA3ZrnEMPR CHj+Js0FyDxctBizqawCD/YzWuciP9pScmZw4aESwbhJR/vR5+BAhrcuE28E/vUQP//k 3JbHWpajcD14SIX1YoUud8DTzRMAyQDqgbdjK3hV51pq7SaGK4g/LUYzEdZiLVaezFjb v9yW+4ZRRHMRSSi/4YXhe6lOPIgBLXB+/l2k6AhQGqie0FJUP8+QHuQmtXfLZnc8FI4H wRHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BAU5Bher; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r15-v6si5006666pgh.88.2018.09.21.03.27.41; Fri, 21 Sep 2018 03:27:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BAU5Bher; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390060AbeIUQPw (ORCPT + 32 others); Fri, 21 Sep 2018 12:15:52 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:54806 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389559AbeIUQPv (ORCPT ); Fri, 21 Sep 2018 12:15:51 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8LAPFDA033166; Fri, 21 Sep 2018 05:25:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1537525515; bh=o42oR+cPzXSXz2nnwYCWDDPfzIB1x+eMkvxWlBXLaII=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BAU5Bherd0RDmlZd6/0Drqx+b9lQiiTTq5eEYnRpobjX3keF+XiPkNf22MDpU3+1q Xz7ve5boMmrp0nBAAcxFzeFVHLlrLc+Z3zRb8AR2BUUNi57o4T2A5khWfCDKuqH5aL 6WDd6CLU5+RNSROmPoCVPGjBMvJVHSlMGhQHfxf0= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAPFqM021583; Fri, 21 Sep 2018 05:25:15 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 21 Sep 2018 05:25:15 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 21 Sep 2018 05:25:15 -0500 Received: from a0393678ub.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8LAMEtg032280; Fri, 21 Sep 2018 05:25:11 -0500 From: Kishon Vijay Abraham I To: Jingoo Han , Joao Pinto , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Murali Karicheri , Kishon Vijay Abraham I , CC: Mark Rutland , Santosh Shilimkar , Tero Kristo , Nishanth Menon , , , , Subject: [RFC PATCH 38/40] arm64: dts: k3-am6: Add mux-controller dt node required for muxing SERDES Date: Fri, 21 Sep 2018 15:51:53 +0530 Message-ID: <20180921102155.22839-39-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180921102155.22839-1-kishon@ti.com> References: <20180921102155.22839-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mux-controller dt node as a child node of scm_conf. This is required for muxing SERDES between USB, PCIe and ICSS2 SGMII. While at that also add "simple-mfd" compatible string to scm_conf dt node so that mux-controller device gets created. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 957c9125a453..4379c370f6f8 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -7,8 +7,15 @@ &cbass_main { scm_conf: scm_conf@100000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; + + serdes_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ + <0x4090 0x3>; /* SERDES1 lane select */ + }; }; gic500: interrupt-controller@1800000 { From patchwork Fri Sep 21 10:21:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147224 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp632036ljw; Fri, 21 Sep 2018 03:27:46 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda0heRKDKjkm3Y+P4YIDu312zuTdnwPA5IseAYd9s7Uaz/8KM6ubJUcchg5iZ0nnsu2ypvf X-Received: by 2002:a17:902:7d83:: with SMTP id a3-v6mr43924240plm.0.1537525666339; Fri, 21 Sep 2018 03:27:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525666; cv=none; d=google.com; s=arc-20160816; b=WXi4xPJ75lLZQprEeD9BCl7Oar8pk6OUrlvyL86bAG9EAdG3Zwl/CllPnZaiMq0MIa xQAsYX8588ua2a/EXjGpHshtyrnsZ97ncIbO9Me48mj3V08USqqtqR3AYvO9VwlPqtzp fXFTMN5TLuQLZCZ7NELxsFj9BmAT3Uwv+qQ+vlNVvhmBLd/oKHm2HsypjKX+x9HCp/Lu orE9gHN+qxapmFjqQYwaD9IMHJkCSVtab/pPXFSB7lTRhWVfeGzqPZJydorgq5PFjk1/ IUoczd42OELEowF/mdmj23jv4DEyiFam3k+boYgeMpQMHD3eyWznErC+q7Bu8kPVuwDO 9Xuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Hx6wSR+rqqvmzg8ziF4Yx5EsYxtHEdd50Pac9BsuRBs=; b=Gk7+qAooQ4LUwUna8nRw6mVa7WrTdoOqFAwL9XHMVQxVRpS529o/97pw2iHm2PPWOg a5irX9D7QQ+QX3zPa36ubqmMyPtDtwJTB7f+ly1iisUdAEDs/HzPeKLoUTOJMG1ltX80 vxZevNbonx6CilwweVVfa44/h0ji+cq7/qDUzlYgImMTL4Se2t04jHEPulNOj1oVpOuL hfWXfgdrJqd8Butcgi3MBWy05ZojoexjuwQDSRlb3TeMVeiAR4K5DSWHtBmcPV68X9v6 tVX+RQlqGQ8dglq2iNtiduk+ioIsxnbmWYxe9WUZj2blLMBJbcG3QPEAwULmOeTdYSs/ dT9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=R7EMEBgb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 4379c370f6f8..b08d15fa110e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -4,11 +4,25 @@ * * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include &cbass_main { scm_conf: scm_conf@100000 { compatible = "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x00100000 0x1c000>; + + serdes0_clk: serdes_clk@4080 { + compatible = "syscon"; + reg = <0x00004080 0x4>; + }; + + serdes1_clk: serdes_clk@4090 { + compatible = "syscon"; + reg = <0x00004090 0x4>; + }; serdes_mux: mux-controller { compatible = "mmio-mux"; @@ -53,6 +67,38 @@ interrupts = ; }; + serdes0: serdes@900000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x900000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 153>; + clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; + clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; + ti,serdes-clk = <&serdes0_clk>; + #clock-cells = <1>; + mux-controls = <&serdes_mux 0>; + status = "disabled"; + }; + + serdes1: serdes@910000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x910000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 154>; + clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; + clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; + assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; + ti,serdes-clk = <&serdes1_clk>; + #clock-cells = <1>; + mux-controls = <&serdes_mux 1>; + status = "disabled"; + }; + main_uart0: serial@2800000 { compatible = "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; From patchwork Fri Sep 21 10:21:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 147225 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp632104ljw; Fri, 21 Sep 2018 03:27:51 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbG9evbb97KUWs7tKmL1HgMDrhkAqllSF48q1p8+kZZmFWCKxjoM6hSLHgjQ6qnfLXIGJ4O X-Received: by 2002:a65:5b48:: with SMTP id y8-v6mr41533416pgr.125.1537525671321; Fri, 21 Sep 2018 03:27:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537525671; cv=none; d=google.com; s=arc-20160816; b=mxchWIkQJYJKthHppPp5XASn5nZPuVb7FYvsF6GAp12DcRUKA7K6yT2tqA10yTsAk1 LqZqgP7J8E3KaZhIMdAczPEt6XBjMRQ9+/w7vS3v6hVKcBF2ZQkkNFsRDxReUj79x3JY 1pRUVtXq1LalDW/jHsL7GMZsJsG3nIDJSRDHxPuKX0rtpdQA/o/gwJqQv7UwTkXLcaea 5mBfDIr8TiOaBOdKVLcWczZn/AXZObjCUnrPAdgdnPWa7pFIlrM6OVp4cvUNftfAwf6r odAJdx3J3i1rb1sOmbrvtU58OZS61NRF4Y/uh9yfgEL4RGuM7MIlrANgfWEuaKm+DpGU GEyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XDj+mFJD+CB99IbCn09zPB+O+0SrSz7pxE0ENLfnd3U=; b=kArbNQLhFxN8XBrfoy4MIhx0nY32xmv4YbSW/BmYUbq7w3Tlrx+2IhgzI8cxPb1aua qBtbYAjdHpYaxx0+VswH+bIxsrcfuw32gnnIdgzhhXGcsbRDF6W05u3Smc8Rk/V0OqSa Nb9JHr8PcprjcJVQe/ZddCfP0HP75DzzHaFkVrQOYOOSISzrr7mwWXzafMeaTqNputTO Jr0aMj3L6poL0hAo+Q78jX5xHNHSk3PjjwXBFCO3xo6r7MhlOD+mfr3wWQG5luETVego mUgYhYlwl1RFeQOcaq7a2SIi2m6J9Rz9DggORCzpOh/AxVxJH2tm7dOirwkJUxiAO4Y9 5lng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CEDLZ0Y5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 83 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 2 files changed, 84 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index b08d15fa110e..0a5d74a8eef4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -14,6 +14,21 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; + pcie0_mode: pcie-mode@4060 { + compatible = "syscon"; + reg = <0x00004060 0x4>; + }; + + pcie1_mode: pcie-mode@4070 { + compatible = "syscon"; + reg = <0x00004070 0x4>; + }; + + pcie_devid: pcie-devid@210 { + compatible = "syscon"; + reg = <0x00000210 0x4>; + }; + serdes0_clk: serdes_clk@4080 { compatible = "syscon"; reg = <0x00004080 0x4>; @@ -128,4 +143,72 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + pcie0_rc: pcie@5500000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 120>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 + 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie0_mode>; + bus-range = <0x0 0xff>; + device_type = "pci"; + num-lanes = <1>; + num-ob-windows = <16>; + num-viewport = <16>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */ + <0 0 0 2 &pcie0_intc 0>, /* INT B */ + <0 0 0 3 &pcie0_intc 0>, /* INT C */ + <0 0 0 4 &pcie0_intc 0>; /* INT D */ + msi-map = <0x0 &gic_its 0x0 0x10000>; + status = "disabled"; + + pcie0_intc: legacy-interrupt-controller@1 { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + + pcie1_rc: pcie@5600000 { + compatible = "ti,am654-pcie-rc"; + reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu"; + power-domains = <&k3_pds 121>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 + 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; + ti,syscon-pcie-id = <&pcie_devid>; + ti,syscon-pcie-mode = <&pcie1_mode>; + bus-range = <0x0 0xff>; + status = "disabled"; + device_type = "pci"; + num-lanes = <1>; + num-ob-windows = <16>; + num-viewport = <16>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + msi-map = <0x0 &gic_its 0x10000 0x10000>; + + pcie1_intc: legacy-interrupt-controller@1 { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3d4bf369d030..b87081765894 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -61,6 +61,7 @@ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ + <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ /* MCUSS Range */ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,