From patchwork Thu Aug 5 14:07:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AF3CC4338F for ; Thu, 5 Aug 2021 14:14:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7574661159 for ; Thu, 5 Aug 2021 14:14:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241943AbhHEOOY (ORCPT ); Thu, 5 Aug 2021 10:14:24 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.84]:16724 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240281AbhHEOOV (ORCPT ); Thu, 5 Aug 2021 10:14:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172481; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=rPNTJrLe19MJRB8ku5y1SEic4/RUeQD5hNIQa1PLh1Y=; b=aILFzPK7rF1aoLOA01Hw+nkODO9T+yCvYPaE1BP179oEUNV/v8s0rJoJmHGviArHIv /nXXgM4kbPyoBabrmiPfrgN7mXYwuPrWMmwlaEh2+EVhg42OkDLihCgcOtEf2caV5fkx 7LtS91lpuAr8oXvRJt8GdOTESPsfFDJmK9Y1zPZGQwbmkKrVvvuXUNWQ2BYiIRrKAjiM ceIwd2+SpJzsy/KmKvl2nkHboHVXE9Mm7DMdW03Ye51OJ7Gi46jNyrfiP0prZviH3YLq kcUgciBB8RJS3spujLB9XWtmERVYG3+HATPpHNKHeUG4D3ClLTDAvauHddiFlL35iKJP 7ndA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E80781 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:00 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 1/8] drm/bridge: synopsis: Add mode_fixup and bridge timings support Date: Thu, 5 Aug 2021 16:07:50 +0200 Message-Id: <15187eccabf39561de226acd8be40b93503cac49.1628172477.git.hns@goldelico.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Boddie The platform-specific configuration structure is augmented with mode_fixup and timings members so that specialisations of the Synopsys driver can introduce mode flags and bus flags. Signed-off-by: Paul Boddie Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 16 ++++++++++++++++ include/drm/bridge/dw_hdmi.h | 5 +++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index e7c7c9b9c646f..e8499eb11328c 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2810,6 +2810,19 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, return mode_status; } +static bool +dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct dw_hdmi *hdmi = bridge->driver_private; + + if (hdmi->plat_data->mode_fixup) + return hdmi->plat_data->mode_fixup(bridge, mode, adjusted_mode); + + return true; +} + static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *orig_mode, const struct drm_display_mode *mode) @@ -2883,6 +2896,7 @@ static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { .atomic_disable = dw_hdmi_bridge_atomic_disable, .mode_set = dw_hdmi_bridge_mode_set, .mode_valid = dw_hdmi_bridge_mode_valid, + .mode_fixup = dw_hdmi_bridge_mode_fixup, .detect = dw_hdmi_bridge_detect, .get_edid = dw_hdmi_bridge_get_edid, }; @@ -3364,6 +3378,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, #ifdef CONFIG_OF hdmi->bridge.of_node = pdev->dev.of_node; #endif + if (plat_data->timings) + hdmi->bridge.timings = plat_data->timings; memset(&pdevinfo, 0, sizeof(pdevinfo)); pdevinfo.parent = dev; diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index 6a5716655619b..677137445d534 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -8,6 +8,7 @@ #include +struct drm_bridge; struct drm_display_info; struct drm_display_mode; struct drm_encoder; @@ -140,6 +141,10 @@ struct dw_hdmi_plat_data { enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *info, const struct drm_display_mode *mode); + bool (*mode_fixup)(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); + const struct drm_bridge_timings *timings; /* Vendor PHY support */ const struct dw_hdmi_phy_ops *phy_ops; From patchwork Thu Aug 5 14:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79579C4320E for ; Thu, 5 Aug 2021 14:14:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5EC8A61154 for ; Thu, 5 Aug 2021 14:14:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241566AbhHEOOQ (ORCPT ); Thu, 5 Aug 2021 10:14:16 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.172]:25229 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240281AbhHEOOQ (ORCPT ); Thu, 5 Aug 2021 10:14:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172482; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=PNoL+uPVa/EtHg8cMcNNaXbR5Yr+tlsCZB8IjNiOBAo=; b=BYI6GFQiQ0/O6qeruCCHcB2wP1mr7YZxWz0Z5h73o1GumChAnyLoomlS6dlUfIrltM Tk6OukO7+yOd9FyA5Cchdi1EqXMYnpnZ5tR+YOBa0Eeuj+Rs2GskyiJdgkWmuaMRbWs0 26BXQDfsZbJxvuNfFUBR2mn/uOip8SLevjcEnRO88rIEQAvl9eDuhCHt2fOQIlJT9dvY gYdQpl9j01wJZvfSaW9DAL2uRtjhWqv8o0hJMWxTE5Q7vNw7lna4cd/w6HIaI3ggfrTt hQEqZJbGIvOP9FP40mwrCyhA6vVsJAbc8pb6InGEcv8h0kxjoZDprZI6SYoRxOCldUeS jbJg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E81782 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:01 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 2/8] drm/ingenic: Add jz4780 Synopsys HDMI driver Date: Thu, 5 Aug 2021 16:07:51 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Boddie A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 HDMI support. This requires a new driver, plus device tree and configuration modifications. Signed-off-by: Paul Boddie Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- drivers/gpu/drm/ingenic/Kconfig | 9 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 121 ++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig index 3b57f8be007c4..4c7d311fbefff 100644 --- a/drivers/gpu/drm/ingenic/Kconfig +++ b/drivers/gpu/drm/ingenic/Kconfig @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU The Image Processing Unit (IPU) will appear as a second primary plane. +config DRM_INGENIC_DW_HDMI + bool "Ingenic specific support for Synopsys DW HDMI" + depends on MACH_JZ4780 + select DRM_DW_HDMI + help + Choose this option to enable Synopsys DesignWare HDMI based driver. + If you want to enable HDMI on Ingenic JZ4780 based SoC, you should + select this option.. + endif diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile index d313326bdddbb..3db9888a6c046 100644 --- a/drivers/gpu/drm/ingenic/Makefile +++ b/drivers/gpu/drm/ingenic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o ingenic-drm-y = ingenic-drm-drv.o ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c new file mode 100644 index 0000000000000..61e7a57d7cec1 --- /dev/null +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2019, 2020 Paul Boddie + * + * Derived from dw_hdmi-imx.c with i.MX portions removed. + * Probe and remove operations derived from rcar_dw_hdmi.c. + */ + +#include +#include +#include + +#include +#include + +static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = { + { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } }, + { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } }, + { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } }, + { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } }, + { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } } +}; + +static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = { + /*pixelclk bpp8 bpp10 bpp12 */ + { 54000000, { 0x091c, 0x091c, 0x06dc } }, + { 58400000, { 0x091c, 0x06dc, 0x06dc } }, + { 72000000, { 0x06dc, 0x06dc, 0x091c } }, + { 74250000, { 0x06dc, 0x0b5c, 0x091c } }, + { 118800000, { 0x091c, 0x091c, 0x06dc } }, + { 216000000, { 0x06dc, 0x0b5c, 0x091c } }, + { ~0UL, { 0x0000, 0x0000, 0x0000 } }, +}; + +/* + * Resistance term 133Ohm Cfg + * PREEMP config 0.00 + * TX/CK level 10 + */ +static const struct dw_hdmi_phy_config ingenic_phy_config[] = { + /*pixelclk symbol term vlev */ + { 216000000, 0x800d, 0x0005, 0x01ad}, + { ~0UL, 0x0000, 0x0000, 0x0000} +}; + +static enum drm_mode_status +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->clock < 13500) + return MODE_CLOCK_LOW; + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */ + if (mode->clock > 216000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static bool +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + + return true; +} + +static const struct drm_bridge_timings ingenic_dw_hdmi_timings = { + .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, +}; + +static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = { + .mpll_cfg = ingenic_mpll_cfg, + .cur_ctr = ingenic_cur_ctr, + .phy_config = ingenic_phy_config, + .mode_valid = ingenic_dw_hdmi_mode_valid, + .mode_fixup = ingenic_dw_hdmi_mode_fixup, + .timings = &ingenic_dw_hdmi_timings, +}; + +static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = { + { .compatible = "ingenic,jz4780-dw-hdmi" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids); + +static int ingenic_dw_hdmi_probe(struct platform_device *pdev) +{ + struct dw_hdmi *hdmi; + + hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data); + if (IS_ERR(hdmi)) + return PTR_ERR(hdmi); + + platform_set_drvdata(pdev, hdmi); + + return 0; +} + +static int ingenic_dw_hdmi_remove(struct platform_device *pdev) +{ + struct dw_hdmi *hdmi = platform_get_drvdata(pdev); + + dw_hdmi_remove(hdmi); + + return 0; +} + +static struct platform_driver ingenic_dw_hdmi_driver = { + .probe = ingenic_dw_hdmi_probe, + .remove = ingenic_dw_hdmi_remove, + .driver = { + .name = "dw-hdmi-ingenic", + .of_match_table = ingenic_dw_hdmi_dt_ids, + }, +}; + +struct platform_driver *ingenic_dw_hdmi_driver_ptr = &ingenic_dw_hdmi_driver; From patchwork Thu Aug 5 14:07:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FB3DC4320A for ; Thu, 5 Aug 2021 14:14:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4484760238 for ; Thu, 5 Aug 2021 14:14:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240318AbhHEOOQ (ORCPT ); Thu, 5 Aug 2021 10:14:16 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.102]:27702 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240121AbhHEOOQ (ORCPT ); Thu, 5 Aug 2021 10:14:16 -0400 X-Greylist: delayed 345 seconds by postgrey-1.27 at vger.kernel.org; Thu, 05 Aug 2021 10:14:15 EDT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172482; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=Xd4Ow7UQR8vN93lIKdP4aP3NQNR6paMvzex82nFNjl8=; b=PNVlmYtX5Ak5oysu3AsUdNOi4HhQwyUS5153cU6cHGkVGlnvnQFsn726hxO2Cgcwq+ pUUxMazeTOUPHpTT6LkQeMhzkediRjtRGzZVs0uX5NsJkxXeZeZ64CPR0289g+SX8uui Yo2ZNyXHtXZZdKJnutR7J/r80gbU4W5Usw+20B7hCUFVVtK/uLoZCyLmU2OzLPUgshJb rxODcwRViwaXobCkDWIu4DCfQsENajTagwd7O/KsO3PV8Oz8ffvUwmXJnHlb+tTNrVzi 4PxkmmIJdfZHURyPpcBGbLzMXTkchiOJdRcuy16vt/6DnAILDAjo9iNfb/1H5GUqDdGT 2oiA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E82783 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:02 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 3/8] drm/ingenic: Add support for JZ4780 and HDMI output Date: Thu, 5 Aug 2021 16:07:52 +0200 Message-Id: <263a207d2aeb8bc95aa8464212dcc9b225548f4f.1628172477.git.hns@goldelico.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Boddie Add support for the LCD controller present on JZ4780 SoCs. This SoC uses 8-byte descriptors which extend the current 4-byte descriptors used for other Ingenic SoCs. Also, add special handling for HDMI-A connectors. For some reason, only the primary planes are working properly. As soon as the overlay plane is enabled things go south :P Tested on MIPS Creator CI20 board. Signed-off-by: Paul Boddie Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 163 ++++++++++++++++++++-- drivers/gpu/drm/ingenic/ingenic-drm.h | 52 +++++++ 2 files changed, 200 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 5244f47634777..a2d103ae46833 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -56,13 +56,27 @@ struct ingenic_dma_hwdescs { u16 palette[256] __aligned(16); }; +struct ingenic_dma_hwdesc_ext { + struct ingenic_dma_hwdesc base; + u32 offsize; + u32 pagewidth; + u32 cpos; + u32 dessize; +} __packed; + struct jz_soc_info { bool needs_dev_clk; bool has_osd; bool map_noncoherent; + bool has_alpha; + bool has_pcfg; + bool has_recover; + bool has_rgbc; + unsigned int hwdesc_size; unsigned int max_width, max_height; const u32 *formats_f0, *formats_f1; unsigned int num_formats_f0, num_formats_f1; + unsigned int max_reg; }; struct ingenic_drm { @@ -118,12 +132,11 @@ static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) } } -static const struct regmap_config ingenic_drm_regmap_config = { +static struct regmap_config ingenic_drm_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, - .max_register = JZ_REG_LCD_SIZE1, .writeable_reg = ingenic_drm_writeable_reg, }; @@ -582,7 +595,39 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, hwdesc = &priv->dma_hwdescs->hwdesc_f1; hwdesc->addr = addr; - hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); + hwdesc->cmd = JZ_LCD_CMD_FRM_ENABLE | JZ_LCD_CMD_EOF_IRQ | + (width * height * cpp / 4); + + if (priv->soc_info->hwdesc_size == sizeof(struct ingenic_dma_hwdesc_ext)) { + struct ingenic_dma_hwdesc_ext *hwdesc_ext; + + /* Extended 8-byte descriptor */ + hwdesc_ext = (struct ingenic_dma_hwdesc_ext *) hwdesc; + hwdesc_ext->cpos = 0; + hwdesc_ext->offsize = 0; + hwdesc_ext->pagewidth = 0; + + switch (newstate->fb->format->format) { + case DRM_FORMAT_XRGB1555: + hwdesc_ext->cpos |= JZ_LCD_CPOS_RGB555; + fallthrough; + case DRM_FORMAT_RGB565: + hwdesc_ext->cpos |= JZ_LCD_CPOS_BPP_15_16; + break; + case DRM_FORMAT_XRGB8888: + hwdesc_ext->cpos |= JZ_LCD_CPOS_BPP_18_24; + break; + } + hwdesc_ext->cpos |= JZ_LCD_CPOS_PREMULTIPLY_LCD | + (3 << JZ_LCD_CPOS_COEFFICIENT_OFFSET); + + hwdesc_ext->dessize = + (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) | + (((height - 1) & JZ_LCD_DESSIZE_HEIGHT_MASK) << + JZ_LCD_DESSIZE_HEIGHT_OFFSET) | + (((width - 1) & JZ_LCD_DESSIZE_WIDTH_MASK) << + JZ_LCD_DESSIZE_WIDTH_OFFSET); + } if (drm_atomic_crtc_needs_modeset(crtc_state)) { fourcc = newstate->fb->format->format; @@ -612,8 +657,12 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode = &crtc_state->adjusted_mode; struct drm_connector *conn = conn_state->connector; struct drm_display_info *info = &conn->display_info; + u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; unsigned int cfg, rgbcfg = 0; + if (info->num_bus_formats) + bus_format = info->bus_formats[0]; + priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; if (priv->panel_is_sharp) { @@ -623,6 +672,13 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; } + if (priv->soc_info->has_recover) + cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN; + + /* CI20: set use of the 8-word descriptor and OSD foreground usage. */ + if (priv->soc_info->hwdesc_size == sizeof(struct ingenic_dma_hwdesc_ext)) + cfg |= JZ_LCD_CFG_DESCRIPTOR_8; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; if (mode->flags & DRM_MODE_FLAG_NVSYNC) @@ -639,7 +695,7 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, else cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; } else { - switch (*info->bus_formats) { + switch (bus_format) { case MEDIA_BUS_FMT_RGB565_1X16: cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; break; @@ -665,19 +721,23 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); } -static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static int +ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { struct drm_display_info *info = &conn_state->connector->display_info; struct drm_display_mode *mode = &crtc_state->adjusted_mode; + switch (conn_state->connector->connector_type) { + case DRM_MODE_CONNECTOR_TV: + case DRM_MODE_CONNECTOR_HDMIA: + return 0; + } + if (info->num_bus_formats != 1) return -EINVAL; - if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) - return 0; - switch (*info->bus_formats) { case MEDIA_BUS_FMT_RGB888_3X8: case MEDIA_BUS_FMT_RGB888_3X8_DELTA: @@ -924,7 +984,7 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) drm->mode_config.min_width = 0; drm->mode_config.min_height = 0; drm->mode_config.max_width = soc_info->max_width; - drm->mode_config.max_height = 4095; + drm->mode_config.max_height = soc_info->max_height; drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; @@ -934,6 +994,7 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) return PTR_ERR(base); } + ingenic_drm_regmap_config.max_register = soc_info->max_reg; priv->map = devm_regmap_init_mmio(dev, base, &ingenic_drm_regmap_config); if (IS_ERR(priv->map)) { @@ -966,7 +1027,6 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) if (!priv->dma_hwdescs) return -ENOMEM; - /* Configure DMA hwdesc for foreground0 plane */ dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); @@ -1147,7 +1207,26 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) /* Enable OSD if available */ if (soc_info->has_osd) - regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); + + if (soc_info->has_alpha) + regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_ALPHAEN); + + /* Magic values from the vendor kernel for the priority thresholds. */ + if (soc_info->has_pcfg) + regmap_write(priv->map, JZ_REG_LCD_PCFG, + JZ_LCD_PCFG_PRI_MODE | + JZ_LCD_PCFG_HP_BST_16 | + (511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) | + (400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) | + (256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET)); + + /* RGB output control may be superfluous. */ + if (soc_info->has_rgbc) + regmap_write(priv->map, JZ_REG_LCD_RGBC, + JZ_LCD_RGBC_RGB_FORMAT_ENABLE | + JZ_LCD_RGBC_ODD_LINE_RGB | + JZ_LCD_RGBC_EVEN_LINE_RGB); mutex_init(&priv->clk_mutex); priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; @@ -1296,41 +1375,75 @@ static const struct jz_soc_info jz4740_soc_info = { .needs_dev_clk = true, .has_osd = false, .map_noncoherent = false, + .has_pcfg = false, + .has_recover = false, + .has_rgbc = false, + .hwdesc_size = sizeof(struct ingenic_dma_hwdesc), .max_width = 800, .max_height = 600, .formats_f1 = jz4740_formats, .num_formats_f1 = ARRAY_SIZE(jz4740_formats), /* JZ4740 has only one plane */ + .max_reg = JZ_REG_LCD_SIZE1, }; static const struct jz_soc_info jz4725b_soc_info = { .needs_dev_clk = false, .has_osd = true, .map_noncoherent = false, + .has_pcfg = false, + .has_recover = false, + .has_rgbc = false, + .hwdesc_size = sizeof(struct ingenic_dma_hwdesc), .max_width = 800, .max_height = 600, .formats_f1 = jz4725b_formats_f1, .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), .formats_f0 = jz4725b_formats_f0, .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), + .max_reg = JZ_REG_LCD_SIZE1, }; static const struct jz_soc_info jz4770_soc_info = { .needs_dev_clk = false, .has_osd = true, .map_noncoherent = true, + .has_pcfg = false, + .has_recover = false, + .has_rgbc = false, + .hwdesc_size = sizeof(struct ingenic_dma_hwdesc), .max_width = 1280, .max_height = 720, .formats_f1 = jz4770_formats_f1, .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), .formats_f0 = jz4770_formats_f0, .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), + .max_reg = JZ_REG_LCD_SIZE1, +}; + +static const struct jz_soc_info jz4780_soc_info = { + .needs_dev_clk = true, + .has_osd = true, + .has_alpha = true, + .has_pcfg = true, + .has_recover = true, + .has_rgbc = true, + .hwdesc_size = sizeof(struct ingenic_dma_hwdesc_ext), + .max_width = 4096, + .max_height = 4096, + /* REVISIT: do we support formats different from jz4770? */ + .formats_f1 = jz4770_formats_f1, + .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), + .formats_f0 = jz4770_formats_f0, + .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), + .max_reg = JZ_REG_LCD_PCFG, }; static const struct of_device_id ingenic_drm_of_match[] = { { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, + { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); @@ -1349,13 +1462,31 @@ static int ingenic_drm_init(void) { int err; + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) { + err = platform_driver_register(ingenic_dw_hdmi_driver_ptr); + if (err) + return err; + } + if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { err = platform_driver_register(ingenic_ipu_driver_ptr); if (err) - return err; + goto err_hdmi_unreg; } - return platform_driver_register(&ingenic_drm_driver); + err = platform_driver_register(&ingenic_drm_driver); + if (err) + goto err_ipu_unreg; + + return 0; + +err_ipu_unreg: + if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) + platform_driver_unregister(ingenic_ipu_driver_ptr); +err_hdmi_unreg: + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) + platform_driver_unregister(ingenic_dw_hdmi_driver_ptr); + return err; } module_init(ingenic_drm_init); @@ -1363,6 +1494,8 @@ static void ingenic_drm_exit(void) { platform_driver_unregister(&ingenic_drm_driver); + if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) + platform_driver_unregister(ingenic_dw_hdmi_driver_ptr); if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) platform_driver_unregister(ingenic_ipu_driver_ptr); } diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h b/drivers/gpu/drm/ingenic/ingenic-drm.h index 22654ac1dde1c..7e55a88243e28 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm.h +++ b/drivers/gpu/drm/ingenic/ingenic-drm.h @@ -44,8 +44,11 @@ #define JZ_REG_LCD_XYP1 0x124 #define JZ_REG_LCD_SIZE0 0x128 #define JZ_REG_LCD_SIZE1 0x12c +#define JZ_REG_LCD_PCFG 0x2c0 #define JZ_LCD_CFG_SLCD BIT(31) +#define JZ_LCD_CFG_DESCRIPTOR_8 BIT(28) +#define JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN BIT(25) #define JZ_LCD_CFG_PS_DISABLE BIT(23) #define JZ_LCD_CFG_CLS_DISABLE BIT(22) #define JZ_LCD_CFG_SPL_DISABLE BIT(21) @@ -63,6 +66,7 @@ #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) #define JZ_LCD_CFG_18_BIT BIT(7) +#define JZ_LCD_CFG_24_BIT BIT(6) #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 @@ -132,6 +136,7 @@ #define JZ_LCD_CMD_SOF_IRQ BIT(31) #define JZ_LCD_CMD_EOF_IRQ BIT(30) #define JZ_LCD_CMD_ENABLE_PAL BIT(28) +#define JZ_LCD_CMD_FRM_ENABLE BIT(26) #define JZ_LCD_SYNC_MASK 0x3ff @@ -153,6 +158,7 @@ #define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) #define JZ_LCD_OSDC_OSDEN BIT(0) +#define JZ_LCD_OSDC_ALPHAEN BIT(2) #define JZ_LCD_OSDC_F0EN BIT(3) #define JZ_LCD_OSDC_F1EN BIT(4) @@ -176,6 +182,51 @@ #define JZ_LCD_SIZE01_WIDTH_LSB 0 #define JZ_LCD_SIZE01_HEIGHT_LSB 16 +#define JZ_LCD_DESSIZE_ALPHA_OFFSET 24 +#define JZ_LCD_DESSIZE_HEIGHT_OFFSET 12 +#define JZ_LCD_DESSIZE_WIDTH_OFFSET 0 +#define JZ_LCD_DESSIZE_HEIGHT_MASK 0xfff +#define JZ_LCD_DESSIZE_WIDTH_MASK 0xfff + +/* TODO: 4,5 and 7 match the above BPP */ +#define JZ_LCD_CPOS_BPP_15_16 (4 << 27) +#define JZ_LCD_CPOS_BPP_18_24 (5 << 27) +#define JZ_LCD_CPOS_BPP_30 (7 << 27) +#define JZ_LCD_CPOS_RGB555 BIT(30) +#define JZ_LCD_CPOS_PREMULTIPLY_LCD BIT(26) +#define JZ_LCD_CPOS_COEFFICIENT_OFFSET 24 + +#define JZ_LCD_RGBC_RGB_PADDING BIT(15) +#define JZ_LCD_RGBC_RGB_PADDING_FIRST BIT(14) +#define JZ_LCD_RGBC_422 BIT(8) +#define JZ_LCD_RGBC_RGB_FORMAT_ENABLE BIT(7) +#define JZ_LCD_RGBC_ODD_LINE_MASK (0x7 << 4) +#define JZ_LCD_RGBC_ODD_LINE_RGB (0 << 4) +#define JZ_LCD_RGBC_ODD_LINE_RBG (1 << 4) +#define JZ_LCD_RGBC_ODD_LINE_GRB (2 << 4) +#define JZ_LCD_RGBC_ODD_LINE_GBR (3 << 4) +#define JZ_LCD_RGBC_ODD_LINE_BRG (4 << 4) +#define JZ_LCD_RGBC_ODD_LINE_BGR (5 << 4) +#define JZ_LCD_RGBC_EVEN_LINE_MASK (0x7 << 0) +#define JZ_LCD_RGBC_EVEN_LINE_RGB 0 +#define JZ_LCD_RGBC_EVEN_LINE_RBG 1 +#define JZ_LCD_RGBC_EVEN_LINE_GRB 2 +#define JZ_LCD_RGBC_EVEN_LINE_GBR 3 +#define JZ_LCD_RGBC_EVEN_LINE_BRG 4 +#define JZ_LCD_RGBC_EVEN_LINE_BGR 5 + +#define JZ_LCD_PCFG_PRI_MODE BIT(31) +#define JZ_LCD_PCFG_HP_BST_4 (0 << 28) +#define JZ_LCD_PCFG_HP_BST_8 (1 << 28) +#define JZ_LCD_PCFG_HP_BST_16 (2 << 28) +#define JZ_LCD_PCFG_HP_BST_32 (3 << 28) +#define JZ_LCD_PCFG_HP_BST_64 (4 << 28) +#define JZ_LCD_PCFG_HP_BST_16_CONT (5 << 28) +#define JZ_LCD_PCFG_HP_BST_DISABLE (7 << 28) +#define JZ_LCD_PCFG_THRESHOLD2_OFFSET 18 +#define JZ_LCD_PCFG_THRESHOLD1_OFFSET 9 +#define JZ_LCD_PCFG_THRESHOLD0_OFFSET 0 + struct device; struct drm_plane; struct drm_plane_state; @@ -187,5 +238,6 @@ void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); bool ingenic_drm_map_noncoherent(const struct device *dev); extern struct platform_driver *ingenic_ipu_driver_ptr; +extern struct platform_driver *ingenic_dw_hdmi_driver_ptr; #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ From patchwork Thu Aug 5 14:07:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8063FC43214 for ; Thu, 5 Aug 2021 14:14:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6665860238 for ; Thu, 5 Aug 2021 14:14:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241940AbhHEOOX (ORCPT ); Thu, 5 Aug 2021 10:14:23 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.101]:16574 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241912AbhHEOOU (ORCPT ); Thu, 5 Aug 2021 10:14:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172483; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=7GSF524XRGutxpaRL6DFfJqyF0DFQEzvjjQ9jeOGxB0=; b=BooYge95UZsrYoIy4hqoHstoAWQXqvPa0IXyxpHwMtSYd+THqrTcanwHTJKfhkiLFh zfoVpvqtIYgQ5yB2a/ni1wSH5lJBdTtooRDVLhhlR+dUdBBST0R4j9cU9kvukAN0LgTA SfvO92RZK4PFlDibiLrkAPUSS+KY3QQ0BUeF9talW+LYrXxxwF/qjg+HpLxsDhLKvZ1U V2CIu9l4O81AlPH90GhPbRJkIYLmCBWPaSCzhvEaOrYx+WnG8f3IcU6cixMEZ0f8T7vP gQxFNRwhi2AYRngs2AFj9RIhNQe+LjHCNqpnEG4QkQEkDM7rrGUGECOJxyZNf1HG/vUQ Sx5Q== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E82784 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:02 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org, Rob Herring Subject: [PATCH v2 4/8] dt-bindings: display: Add ingenic-jz4780-hdmi DT Schema Date: Thu, 5 Aug 2021 16:07:53 +0200 Message-Id: <0eee16fbffd34319a9ade49d39c12b005568ef57.1628172477.git.hns@goldelico.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sam Ravnborg Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC. Based on .txt binding from Zubair Lutfullah Kakakhel Signed-off-by: Sam Ravnborg Signed-off-by: H. Nikolaus Schaller Cc: Rob Herring Cc: devicetree@vger.kernel.org --- .../bindings/display/ingenic-jz4780-hdmi.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml new file mode 100644 index 0000000000000..a545ff8704ebd --- /dev/null +++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/ingenic-jz4780-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic JZ4780 HDMI Transmitter + +maintainers: + - H. Nikolaus Schaller + +description: | + The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4 + TX controller IP with accompanying PHY IP. + +allOf: + - $ref: panel/panel-common.yaml# + +properties: + compatible: + items: + - const: ingenic,jz4780-hdmi + + reg: + maxItems: 1 + description: the address & size of the LCD controller registers + + reg-io-width: + const: 4 + + interrupts: + maxItems: 1 + description: Specifies the interrupt provided by parent + + clocks: + maxItems: 2 + description: Clock specifiers for isrf and iahb clocks + + clock-names: + items: + - const: isfr + - const: iahb + + ddc-i2c-bus: true + ports: true + +required: + - compatible + - clocks + - clock-names + - ports + - reg-io-width + +additionalProperties: false + +examples: + - | + #include + + hdmi: hdmi@10180000 { + compatible = "ingenic,jz4780-hdmi"; + reg = <0x10180000 0x8000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c4>; + interrupt-parent = <&intc>; + interrupts = <3>; + clocks = <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_AHB0>; + clock-names = "isfr", "iahb"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&jz4780_out_hdmi>; + }; + }; + }; + }; + +... From patchwork Thu Aug 5 14:07:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FC26C432BE for ; Thu, 5 Aug 2021 14:14:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 55CBA61156 for ; Thu, 5 Aug 2021 14:14:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230181AbhHEOOR (ORCPT ); Thu, 5 Aug 2021 10:14:17 -0400 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.101]:20634 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240121AbhHEOOR (ORCPT ); Thu, 5 Aug 2021 10:14:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172484; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=K0sFdrnmJtU+HNf5UqSpAGXxaDpXX2cDTnFEZZMJfDU=; b=XolgD4QWcXvg1GfDR4Z3iFZtT4W0u9Zx++3vA8KDNyyHcf7L3SeBY9QRBCT9mCLvBM 1kYboOqKMIvnxzdsEAlaS2UXaF+niHQa1JRRNvHGmOSQcWJX6XJa07Cq7Ikj+V+hCT4H 4V6IXpU1AxHEK5cEc1OhLgrR712Pq1k+PDSBOXiNX1oBx/DOyRKRBBV1BONduVIpyPkA /WsUpQTtW+8pX+LYhhLn2JJ6R0jT5kiG0DowE2d0TezGxqiExgzB4e9RA7tMYMHCJwvV Dq05p84v0kz9WMPWAfPy+4azQbOLL1rlpurZ90/eh2ZHO4O6DDa2D0ddy6ZrgcjMQ/Yb xSvA== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E83785 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:03 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 5/8] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller Date: Thu, 5 Aug 2021 16:07:54 +0200 Message-Id: <4784fa1d458e64024b10822f22d83c3f0e518408.1628172477.git.hns@goldelico.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Boddie A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 HDMI support. This requires a new driver, plus device tree and configuration modifications. Signed-off-by: Paul Boddie Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index 9e34f433b9b58..4cbc6a4db6cda 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -424,6 +424,51 @@ i2c4: i2c@10054000 { status = "disabled"; }; + hdmi: hdmi@10180000 { + compatible = "ingenic,jz4780-dw-hdmi"; + reg = <0x10180000 0x8000>; + reg-io-width = <4>; + + clocks = <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_AHB0>; + clock-names = "isfr" , "iahb"; + + assigned-clocks = <&cgu JZ4780_CLK_HDMI>; + assigned-clock-rates = <27000000>; + + interrupt-parent = <&intc>; + interrupts = <3>; + + /* ddc-i2c-bus = <&i2c4>; */ + + status = "disabled"; + }; + + lcdc0: lcdc0@13050000 { + compatible = "ingenic,jz4780-lcd"; + reg = <0x13050000 0x1800>; + + clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>; + clock-names = "lcd", "lcd_pclk"; + + interrupt-parent = <&intc>; + interrupts = <31>; + + status = "disabled"; + }; + + lcdc1: lcdc1@130a0000 { + compatible = "ingenic,jz4780-lcd"; + reg = <0x130a0000 0x1800>; + + clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>; + clock-names = "lcd", "lcd_pclk"; + + interrupt-parent = <&intc>; + interrupts = <31>; + + status = "disabled"; + }; + nemc: nemc@13410000 { compatible = "ingenic,jz4780-nemc", "simple-mfd"; reg = <0x13410000 0x10000>; From patchwork Thu Aug 5 14:07:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7673BC4320A for ; Thu, 5 Aug 2021 14:14:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6399061155 for ; Thu, 5 Aug 2021 14:14:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241956AbhHEOOY (ORCPT ); Thu, 5 Aug 2021 10:14:24 -0400 Received: from mo4-p04-ob.smtp.rzone.de ([85.215.255.120]:32780 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241955AbhHEOOV (ORCPT ); Thu, 5 Aug 2021 10:14:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172484; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=c/7kMwv6t15ZsEIxHiem9O0XiNG0vvEI86p1Tw6MO/o=; b=PDsEcp8Ei/qnpdYefIkQzooJ2dIoV+5pDl+RjXwn6mZu8kz/66UPqbp5vSF/AWLkSq LYzansy1qKGYgVrZuMp4Jy5Ki7VZxjU9TcjNmmOuX45PQ8Xxhvpygc+C1ogBn5qxApcd AvJ2N62O9zGJpisfg+Ico3b0C8xnKJDN0bcZdWhuqCY2Q2dKA/rsCynLxj3z7UCugpWJ UFNfP018AvCYguHPxxHD180r+bj1UXPar9rDsYX7anYdCIv9iLvynP3A7d5qscD7Bh17 Lvj5wvCY7qwxPQSY9Cf8zhit+6+Yxfy3wtPbr+qN4hSp8bXHi05RVqLoYSucnCnMJiKR PhLQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E84786 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:04 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 6/8] MIPS: DTS: CI20: add HDMI setup Date: Thu, 5 Aug 2021 16:07:55 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Paul Boddie We need to hook up * HDMI power regulator * HDMI connector * DDC pinmux * HDMI and LCD endpoint connections Signed-off-by: Paul Boddie Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/ci20.dts | 64 +++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index a688809beebca..9e87b1169dbdc 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -78,6 +78,28 @@ eth0_power: fixedregulator@0 { enable-active-high; }; + hdmi_power: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "hdmi_power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpa 25 GPIO_ACTIVE_LOW>; + enable-active-high; + regulator-always-on; + }; + + hdmi_out: connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&dw_hdmi_out>; + }; + }; + }; + ir: ir { compatible = "gpio-ir-receiver"; gpios = <&gpe 3 GPIO_ACTIVE_LOW>; @@ -506,6 +528,12 @@ pins_i2c4: i2c4 { bias-disable; }; + pins_hdmi_ddc: hdmi_ddc { + function = "hdmi-ddc"; + groups = "hdmi-ddc"; + bias-disable; + }; + pins_nemc: nemc { function = "nemc"; groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe"; @@ -536,3 +564,39 @@ pins_mmc1: mmc1 { bias-disable; }; }; + +&hdmi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_hdmi_ddc>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dw_hdmi_in: endpoint { + remote-endpoint = <&lcd_out>; + }; + }; + + port@1 { + reg = <1>; + dw_hdmi_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; +}; + +&lcdc0 { + status = "okay"; + + port { + lcd_out: endpoint { + remote-endpoint = <&dw_hdmi_in>; + }; + }; +}; From patchwork Thu Aug 5 14:07:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C846C43216 for ; Thu, 5 Aug 2021 14:14:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E597D61154 for ; Thu, 5 Aug 2021 14:14:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240121AbhHEOOS (ORCPT ); Thu, 5 Aug 2021 10:14:18 -0400 Received: from mo4-p04-ob.smtp.rzone.de ([85.215.255.122]:15790 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241558AbhHEOOR (ORCPT ); Thu, 5 Aug 2021 10:14:17 -0400 X-Greylist: delayed 346 seconds by postgrey-1.27 at vger.kernel.org; Thu, 05 Aug 2021 10:14:17 EDT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172485; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=haIqt6GlUDch6wOoawc5NT0KlRKMAzO5+gFOCg+ophI=; b=CvWwifqBBkVJTVNTD43Q5t6Vfye2VcaxSmuBKVm8w8WuYWfbr17Zy+iQUJkQEEqfuZ 2PGS8FAgYR+v+SOmSXRVpbSWj2EaFdajoxsVLyx+egXI2HvComGFlU0DQHsRKcTUggd8 XOewEh3mer8Qp12RsNMgNb4mVYGoDrKamXJRHZ6YziD7/YWK5ODIns0j1ixZQKWcVM8x wJfdOIS3l7/r1f1xpHQWgBQP+COgPe2J3FJtNDWTMVHCq1OziAQK9UQ/6u5xDMFdzwki 7FnFlw1WhiAOqCdNADwus1pVbfphG/1smaZx9bVGa5euKxEwZxWcFdACedqIsuG6EzXi N8ZQ== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E84788 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:04 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 7/8] MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780 Date: Thu, 5 Aug 2021 16:07:56 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable CONFIG options as modules. Signed-off-by: Ezequiel Garcia Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index ab7ebb0668340..9d47163011ab6 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -98,7 +98,14 @@ CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m +CONFIG_DRM=m +CONFIG_DRM_INGENIC=m +CONFIG_DRM_INGENIC_DW_HDMI=y # CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set # CONFIG_HID is not set CONFIG_USB=y CONFIG_USB_STORAGE=y From patchwork Thu Aug 5 14:07:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 492966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B50FC4338F for ; Thu, 5 Aug 2021 14:14:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E436060238 for ; Thu, 5 Aug 2021 14:14:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241619AbhHEOOS (ORCPT ); Thu, 5 Aug 2021 10:14:18 -0400 Received: from mo4-p04-ob.smtp.rzone.de ([81.169.146.178]:17421 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240281AbhHEOOR (ORCPT ); Thu, 5 Aug 2021 10:14:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1628172486; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Cc:Date: From:Subject:Sender; bh=CliIVqvNzA/bGBlLAYmf7rIejrGR22i5z/kGrFUsuDU=; b=aQQJPEJ0jCM1iMaL2MFUfRGIIzKEaRcDNf2tGiFM8NcjZCfz4p8vQhjt1lrN7k83ZO BzAU7bAQB9qHCReArzr1c6eZ37KgHwnTGuom6o8amMiIRiaD6CzR3lexc1yketsDJ/Jg pIF7LOcdEkFt83UmjT+B1Z+Aoas3a6BwuStYAzUjWVtM1AIDYeiEiC30DeuJaIjTkK12 dEduqK0sP6iJghpdd/R5/cmb1H9RTxOFL47/C8jmtBLJKxB7OIZeELY0TjU2sBEBHQJb MM/BWyMduC99sODYMs4Lx+Lwpd9KaVCIb4CMIanxDUVLhkiSzvEboTPjsPUg6/AjtFml TKJg== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0lByOdbLzk=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 47.31.0 DYNA|AUTH) with ESMTPSA id Q02727x75E85789 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Thu, 5 Aug 2021 16:08:05 +0200 (CEST) From: "H. Nikolaus Schaller" To: Paul Cercueil , Rob Herring , Mark Rutland , Thomas Bogendoerfer , "H. Nikolaus Schaller" , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Paul Boddie , Jonas Karlman , dri-devel@lists.freedesktop.org Subject: [PATCH v2 8/8] [RFC] drm/ingenic: convert to component framework for jz4780 hdmi Date: Thu, 5 Aug 2021 16:07:57 +0200 Message-Id: <77554dd2612f418f6ab74a8be06c82b71410e0e6.1628172477.git.hns@goldelico.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch attempts to convert the ingenic-dw-hdmi driver into a version that uses the component framework. Unfortunately the new version does not work. Debugging shows that ingenic_dw_hdmi_bind() is never called. Suggestions for reasons and fixes are welcome. Signed-off-by: Paul Boddie Co-authored-by: Paul Boddie Signed-off-by: H. Nikolaus Schaller --- drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 57 ++++++++++++++++++----- 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c index 61e7a57d7cec1..a5ba0b69baa8c 100644 --- a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c @@ -1,17 +1,24 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. - * Copyright (C) 2019, 2020 Paul Boddie + * Copyright (C) 2019, 2020, 2021 Paul Boddie * * Derived from dw_hdmi-imx.c with i.MX portions removed. - * Probe and remove operations derived from rcar_dw_hdmi.c. */ +#include #include #include #include #include #include +#include +#include + +struct ingenic_dw_hdmi_encoder { + struct drm_encoder encoder; + struct dw_hdmi *hdmi; +}; static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = { { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } }, @@ -87,24 +94,52 @@ static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids); -static int ingenic_dw_hdmi_probe(struct platform_device *pdev) +static int ingenic_dw_hdmi_bind(struct device *dev, struct device *master, + void *data) { - struct dw_hdmi *hdmi; + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = data; + struct drm_encoder *enc; + struct ingenic_dw_hdmi_encoder *hdmi_encoder; - hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data); - if (IS_ERR(hdmi)) - return PTR_ERR(hdmi); + hdmi_encoder = drmm_simple_encoder_alloc(drm, struct ingenic_dw_hdmi_encoder, + encoder, DRM_MODE_ENCODER_TMDS); + if (IS_ERR(hdmi_encoder)) + return PTR_ERR(hdmi_encoder); - platform_set_drvdata(pdev, hdmi); + enc = &hdmi_encoder->encoder; + drm_encoder_helper_add(enc, NULL); + hdmi_encoder->hdmi = dw_hdmi_bind(pdev, enc, &ingenic_dw_hdmi_plat_data); + + if (IS_ERR(hdmi_encoder->hdmi)) + return PTR_ERR(hdmi_encoder->hdmi); + + dev_set_drvdata(dev, hdmi_encoder->hdmi); return 0; } -static int ingenic_dw_hdmi_remove(struct platform_device *pdev) +static void ingenic_dw_hdmi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct dw_hdmi *hdmi = dev_get_drvdata(dev); + + dw_hdmi_unbind(hdmi); +} + +static const struct component_ops ingenic_dw_hdmi_ops = { + .bind = ingenic_dw_hdmi_bind, + .unbind = ingenic_dw_hdmi_unbind, +}; + +static int ingenic_dw_hdmi_probe(struct platform_device *pdev) { - struct dw_hdmi *hdmi = platform_get_drvdata(pdev); + return component_add(&pdev->dev, &ingenic_dw_hdmi_ops); +} - dw_hdmi_remove(hdmi); +static int ingenic_dw_hdmi_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &ingenic_dw_hdmi_ops); return 0; }