From patchwork Fri Aug 6 15:21:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492841 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp423350jap; Fri, 6 Aug 2021 08:21:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkDVpMA/6RBf1plGgCGgxzr8UDT4HO+32Ugnr3SiR0MGhBQzGKBRSO2Ado9+6XPLMcHjiX X-Received: by 2002:a05:6402:2043:: with SMTP id bc3mr13645405edb.62.1628263314520; Fri, 06 Aug 2021 08:21:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628263314; cv=none; d=google.com; s=arc-20160816; b=EOakLyDs27Pio0A1AltzX30WH4BKU8aJRNehd7mNuZP6tG0huCxdVQzEgOfOXGqF7J rN4rq7XZQ2hp9XBZ5XjoSHI5oZKEfvVFJmRgY1Iqi+QjPhUTLWpuxWCCgPYbq359eV61 JfKUA9aLvhqI8IajNpK6JOA25/+KMAZy/HfPH/MvkCIhYqwN2nAAZksZ9ILyLgDGBDlW v7WH9elXGToqo92WahNr1W1C5Ai7JeaaryQ1a1oS2DthDoMV3DnnljcnFSSxaTEoPoFO TrksS4kskVuLVkfWVmpNh7KVkIZj24cccM5NaqQCYPL6H3IJLRF7aT5AbuZSmjXSguHE u0ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=STuelqivOnZa8VRkRK+ew1QSDD7r5w5Z8u4aGP2OxYA=; b=JXF1x/cvm2/yrHY73K58TEps3jQnYXu3lk8Dx1a4CWGd1Y3JtFh0a8Bj4copMRRNA2 J+zbDpc+pgrhU2BS0q8yKoYrBfPqzbVK59bgJ0Vr1xGJ3PbL7Q8+Pl1lxrcV5TvWM43n M4AoJkFLx07b9T5biBCG+BSE2ykgf4RzKrhgxvOGqjS+VaiSYF42kkllhELvSk0b8pbw FyoiBL4NGGzPojFGxAne24XD4rY39wk+Ze83pFbewO0qBLPGDMjGoMaRUoCEy/az3bSO Dn0XpSWYGFFuBcoIAXGh9WfmWAmyQ0ZY9Fb6XjVRNKpQwcHQR/TuCJ6oTFBiyH6mli0r Zltw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mnyT35mN; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u15si9530543edt.211.2021.08.06.08.21.54; Fri, 06 Aug 2021 08:21:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mnyT35mN; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244362AbhHFPWI (ORCPT + 2 others); Fri, 6 Aug 2021 11:22:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244335AbhHFPWI (ORCPT ); Fri, 6 Aug 2021 11:22:08 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 749EAC06179A for ; Fri, 6 Aug 2021 08:21:51 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id m18so1127525ljo.1 for ; Fri, 06 Aug 2021 08:21:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=STuelqivOnZa8VRkRK+ew1QSDD7r5w5Z8u4aGP2OxYA=; b=mnyT35mN8VvOlTxEChcB0LEUKSCo5I0GC1WGXJI638du0CxgmTv2F5Cd2A8gvjcbi1 tVeX/Y19Qsd45v0r3DlLlBL27BgNI4JDt4jR+wK1XYUcjr7IzuJc9YLftama6wToBwxK 8/SLexk+u+Rwr9mas2DiwKzge2RT6T3nsJR/MxopX3BW5Uv0UDy554Ux6gmK2qol2YJc f7FZ0t0FFJDxjUxz7Ew4p9BAFwJMRoCGAvbCGTjPuK/DELnh3A4Pk+iFbLPndnoiYUe2 OsAiuUn5Q9EinY99lqaIhfumaF+nPG1aONl2/0hD8zVMJZTMuIx4QjNvcaLVMyO3QMkN 6jnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=STuelqivOnZa8VRkRK+ew1QSDD7r5w5Z8u4aGP2OxYA=; b=DbWLvNjR0cSlDCcWVu60usPER7T2Rz2F5CeChZePPrKp3TzJ5AEvQJ7ycjHgzsgUy2 +YCqqB0OxxNJvBhMC4Ma2vi+FwsMHh0Zf5Si8tSmCaPt4Gcr/D7I0w3YxvZ2DODNbG0R NkDsUQVUXUcgca0EvHcpl/kR4bhLaFS9TX9SQHHDhLbu4SMR3QB1KuxmCj63kNEKlkUt 3zA6TIwclgPKxTjIdXZ6atZ7A520z7K4XWSO4YYp1ZTfEirQxOyX7/z4a4aZkmlBrV2t 5tSl4ueaFhzHvu+TLgR0nmaptmpU/SUGo0RF78em7yWxHgujpuStIQjesYCdJJCw+WFw OZEw== X-Gm-Message-State: AOAM533BAFBqiK+imRT1ceQwCDbX6WpHbfvsNUSYJBpPFy4+mcAq74/U mqZ7P4LNlgUkY5sem7y0ZKcF1w== X-Received: by 2002:a2e:557:: with SMTP id 84mr7003003ljf.507.1628263309656; Fri, 06 Aug 2021 08:21:49 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id c3sm862252lfi.199.2021.08.06.08.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:49 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: pinctrl: samsung: Add Exynos850 doc Date: Fri, 6 Aug 2021 18:21:39 +0300 Message-Id: <20210806152146.16107-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Document compatible string for Exynos850 SoC. Nothing else is changed, as Exynos850 SoC uses already existing samsung pinctrl driver. Signed-off-by: Sam Protsenko --- Changes in v2: - This patch was made the first in the series Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 38a1416fd2cd..e7a1b1880375 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -22,6 +22,7 @@ Required Properties: - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. + - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. From patchwork Fri Aug 6 15:21:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 493142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40128C19F38 for ; Fri, 6 Aug 2021 15:21:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D497611ED for ; Fri, 6 Aug 2021 15:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244375AbhHFPWM (ORCPT ); Fri, 6 Aug 2021 11:22:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244380AbhHFPWJ (ORCPT ); Fri, 6 Aug 2021 11:22:09 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC768C06179A for ; Fri, 6 Aug 2021 08:21:52 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id g13so18592678lfj.12 for ; Fri, 06 Aug 2021 08:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=khXkhKyU/DguseIJ+nWbqK0XZk3XU5Ivr52Y6srFBWM=; b=EtIc77DmJbqKnQJIWYRtOQGBtdEOlPiWSm/7xnVVcy7JknD3CdKvslWp3AGkQRBEQx HCSzbTLvC6z2yAA7koctC0UZAMMEWbuF7UlS3LfEYzbOkTryV7Hg7xPWfsbzaiFscbt4 3tdWlq3mFwR/PPerK6eXVadQ5qJ4tsLx8X4yNgaswq90SLM1Cw79uHRwAWqcjhEsWF9J rEf3r9oL3mU4Xg9ZpP7t6ngxrHCzimWAg51h1sHTV+zDoiKZQ0qX+7z4WdhSHVLds9JD +MWN2+JnhCo5q8QaO1ghvhrbg8NThHo4FJdr0puZcXmhzHOx3Ye+KxRFps04xwdYQpoS 03Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=khXkhKyU/DguseIJ+nWbqK0XZk3XU5Ivr52Y6srFBWM=; b=daXrukneQrSvHMAR6SYTsCELZAyQoGW3fr1kZzuzwctWIiA2eIyvkCbKrGrWuTJCK2 M5aVSJklvWjvr5OqLKGoHASDHivNWaDmIp608oX/Y7Za4oRvCV6y94R/BAoeNFdl6/xM BYMpLTt3BXnhYZYpnptyGOji/q8ORiYQY4pmJNQiq0nHeXQtNmYKAKwvEDCv0KlIqSMr s752vpebRfU5VptVMErxIoLR/+24BxAnAtcebHgccPd52TqimgSJL6kErRAyAI2GVPBu fUm1WiTdJOmV8Vb9d2TyCubS7TOAFh1+0wZ29mwOI2I+iXmxLATYxbJTTvnd3g/7ezxx chwA== X-Gm-Message-State: AOAM532IIG6G43tJrEeRjgl/Et41XC7shXGroMQrZR5gB2n/kDhwe2hC 2b+7vD0dKW80/SucqmeIMvVlLQ== X-Google-Smtp-Source: ABdhPJyxg6GaGbLMkZwjLA8fAQXHnddb0YeS6qpKY3u+VA+x+opkr9tyGGtasS8WMrwOaBiYfacdkA== X-Received: by 2002:ac2:511a:: with SMTP id q26mr7794829lfb.521.1628263311324; Fri, 06 Aug 2021 08:21:51 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id p8sm738022ljn.108.2021.08.06.08.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:50 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 2/8] pinctrl: samsung: Add Exynos850 SoC specific data Date: Fri, 6 Aug 2021 18:21:40 +0300 Message-Id: <20210806152146.16107-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko --- Changes in v2: - Removed .suspend/.resume callbacks, as retention registers are not implemented yet for Exynos850 - Removed .eint_gpio_init for AUD domain, as there are no external interrupts available for that domain .../pinctrl/samsung/pinctrl-exynos-arm64.c | 116 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 +++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 148 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b6e56422a700..3157bdf0233c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos850_pin_banks0[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTN(3, 0x0A0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos850_pin_banks1[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS9_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS9_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS9_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS9_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS9_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS9_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static struct samsung_pin_bank_data exynos850_pin_banks2[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static struct samsung_pin_bank_data exynos850_pin_banks3[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static struct samsung_pin_bank_data exynos850_pin_banks4[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static struct samsung_pin_bank_data exynos850_pin_banks5[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS9_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS9_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS9_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C), + EXYNOS9_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS9_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14), + EXYNOS9_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18), + EXYNOS9_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C), + EXYNOS9_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index da1ec13697e7..595086f2d5dd 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -108,6 +108,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS9_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2975b4369f32..2a0fc63516f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index de44f8ec330b..4c2149e9c544 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; From patchwork Fri Aug 6 15:21:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 492844 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp423513jap; Fri, 6 Aug 2021 08:22:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzEE6G0yD5FB0zzFJmSXIZwJKQFvSEN6rzg2IWUzLTKdR8q2Wtz1PfieCaSGNqubOqddwj0 X-Received: by 2002:a50:da0e:: with SMTP id z14mr13850852edj.73.1628263323843; Fri, 06 Aug 2021 08:22:03 -0700 (PDT) ARC-Seal: i=1; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko --- Changes in v2: - None Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index f064e5b76cf1..2940afb874b3 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -26,6 +26,7 @@ properties: - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart + - samsung,exynos850-uart reg: maxItems: 1 From patchwork Fri Aug 6 15:21:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 493556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE906C432BE for ; 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Fri, 06 Aug 2021 08:21:54 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id u18sm87339ljj.2.2021.08.06.08.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:53 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 4/8] tty: serial: samsung: Init USI to keep clocks running Date: Fri, 6 Aug 2021 18:21:42 +0300 Message-Id: <20210806152146.16107-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org UART block is a part of USI (Universal Serial Interface) IP-core in Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to enable one of three types of serial interface: UART, SPI or I2C. That's possible because USI shares almost all internal circuits within each protocol. USI also provides some additional registers so it's possible to configure it. One USI register called USI_OPTION has reset value of 0x0. Because of this the clock gating behavior is controlled by hardware (HWACG = Hardware Auto Clock Gating), which simply means the serial won't work after reset as is. In order to make it work, USI_OPTION[2:1] bits must be set to 0b01, so that HWACG is controlled manually (by software). Bits meaning: - CLKREQ_ON = 1: clock is continuously provided to IP - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with CLKREQ_ON = 1) USI is not present on older chips, like s3c2410, s3c2412, s3c2440, s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field '.has_usi' was added to struct s3c24xx_uart_info. USI registers will be only actually accessed when '.has_usi' field is set to "1". This feature is needed for further serial enablement on Exynos850, but some other new Exynos chips (like Exynos9810) may benefit from this feature as well. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - Non-intrusive modification of USI registers - Improved comments - Rearranged USI register definitions to conform with existing style drivers/tty/serial/samsung_tty.c | 32 +++++++++++++++++++++++++++++++- include/linux/serial_s3c.h | 9 +++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 9fbc61151c2e..b8034c1168e0 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -65,6 +65,7 @@ enum s3c24xx_port_type { struct s3c24xx_uart_info { char *name; enum s3c24xx_port_type type; + unsigned int has_usi; unsigned int port_type; unsigned int fifosize; unsigned long rx_fifomask; @@ -1352,6 +1353,28 @@ static int apple_s5l_serial_startup(struct uart_port *port) return ret; } +static void exynos_usi_init(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct s3c24xx_uart_info *info = ourport->info; + unsigned int val; + + if (!info->has_usi) + return; + + /* Clear the software reset of USI block (it's set at startup) */ + val = rd_regl(port, USI_CON); + val &= ~USI_CON_RESET_MASK; + wr_regl(port, USI_CON, val); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating (for Rx mode) */ + val = rd_regl(port, USI_OPTION); + val &= ~USI_OPTION_HWACG_MASK; + val |= USI_OPTION_HWACG_CLKREQ_ON; + wr_regl(port, USI_OPTION, val); +} + /* power power management control */ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, @@ -1379,6 +1402,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, if (!IS_ERR(ourport->baudclk)) clk_prepare_enable(ourport->baudclk); + exynos_usi_init(port); break; default: dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); @@ -2102,6 +2126,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, if (ret) pr_warn("uart: failed to enable baudclk\n"); + exynos_usi_init(port); + /* Keep all interrupts masked and cleared */ switch (ourport->info->type) { case TYPE_S3C6400: @@ -2750,10 +2776,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { #endif #if defined(CONFIG_ARCH_EXYNOS) -#define EXYNOS_COMMON_SERIAL_DRV_DATA \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi) \ .info = &(struct s3c24xx_uart_info) { \ .name = "Samsung Exynos UART", \ .type = TYPE_S3C6400, \ + .has_usi = _has_usi, \ .port_type = PORT_S3C6400, \ .has_divslot = 1, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ @@ -2773,6 +2800,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .has_fracval = 1, \ } \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA \ + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0) + static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { EXYNOS_COMMON_SERIAL_DRV_DATA, .fifosize = { 256, 64, 16, 16 }, diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index f6c3323fc4c5..cf0de4a86640 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -27,6 +27,15 @@ #define S3C2410_UERSTAT (0x14) #define S3C2410_UFSTAT (0x18) #define S3C2410_UMSTAT (0x1C) +#define USI_CON (0xC4) +#define USI_OPTION (0xC8) + +#define USI_CON_RESET (1<<0) +#define USI_CON_RESET_MASK (1<<0) + +#define USI_OPTION_HWACG_CLKREQ_ON (1<<1) +#define USI_OPTION_HWACG_CLKSTOP_ON (1<<2) +#define USI_OPTION_HWACG_MASK (3<<1) #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) From patchwork Fri Aug 6 15:21:43 2021 Content-Type: text/plain; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko --- Changes in v2: - Added Reviewed-by tag by Krzysztof Kozlowski drivers/tty/serial/samsung_tty.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index b8034c1168e0..130bdc978e93 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2816,8 +2816,8 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) #else -#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL -#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL +#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE From patchwork Fri Aug 6 15:21:44 2021 Content-Type: text/plain; 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Fri, 06 Aug 2021 08:21:57 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 6/8] tty: serial: samsung: Add Exynos850 SoC data Date: Fri, 6 Aug 2021 18:21:44 +0300 Message-Id: <20210806152146.16107-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add serial driver data for Exynos850 SoC. This driver data is basically reusing EXYNOS_COMMON_SERIAL_DRV_DATA, which is common for all Exynos chips, but also enables USI init, which was added in previous commit: "tty: serial: samsung: Init USI to keep clocks running". Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - Fixed default fifo sizes drivers/tty/serial/samsung_tty.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 130bdc978e93..a069e7bb858f 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2813,11 +2813,19 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { .fifosize = { 64, 256, 16, 256 }, }; +static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(1), + .fifosize = { 256, 64, 64, 64 }, +}; + #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data) + #else #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE @@ -2873,6 +2881,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "s5l-uart", .driver_data = S5L_SERIAL_DRV_DATA, + }, { + .name = "exynos850-uart", + .driver_data = EXYNOS850_SERIAL_DRV_DATA, }, { }, }; @@ -2896,6 +2907,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, { .compatible = "apple,s5l-uart", .data = (void *)S5L_SERIAL_DRV_DATA }, + { .compatible = "samsung,exynos850-uart", + .data = (void *)EXYNOS850_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); From patchwork Fri Aug 6 15:21:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 493555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CA70C432BE for ; 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Fri, 06 Aug 2021 08:21:59 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id c3sm862281lfi.199.2021.08.06.08.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 08:21:58 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 7/8] clk: samsung: Add Exynos850 clock driver stub Date: Fri, 6 Aug 2021 18:21:45 +0300 Message-Id: <20210806152146.16107-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org For now it's just a stub driver to make the serial driver work. Later it will be implemented properly. This driver doesn't really change clocks, only registers the UART clock as a fixed-rate clock. Without this clock driver the UART driver won't work, as it's trying to obtain "uart" clock and fails if it's not able to. In order to get a functional serial console we have to implement that minimal clock driver with "uart" clock. It's not necessary to actually configure clocks, as those are already configured in bootloader, so kernel can rely on that for now. Signed-off-by: Sam Protsenko --- Changes in v2: - Used hard coded clock indexes, as clock bindings were removed; will add clock bindings back (reimplemented) once proper clock driver is ready - Removed .data = 0 for exynos850-oscclk, as it's in BSS section - Removed comma for terminator {} - Made exynos850_clk_init() static - Removed checking np for NULL, as it's already done in of_iomap() drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos850.c | 64 +++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos850.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 028b2e27a37e..c46cf11e4d0b 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c new file mode 100644 index 000000000000..36c7c7fe7cf0 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos850.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Common Clock Framework support for Exynos850 SoC. + */ + +#include +#include +#include +#include +#include + +#include "clk.h" + +/* Will be extracted to bindings header once proper clk driver is implemented */ +#define OSCCLK 1 +#define DOUT_UART 2 +#define CLK_NR_CLKS 3 + +/* Fixed rate clocks generated outside the SoC */ +static struct samsung_fixed_rate_clock exynos850_fixed_rate_ext_clks[] __initdata = { + FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000), +}; + +/* + * Model the UART clock as a fixed-rate clock for now, to make serial driver + * work. This clock is already configured in the bootloader. + */ +static const struct samsung_fixed_rate_clock exynos850_peri_clks[] __initconst = { + FRATE(DOUT_UART, "DOUT_UART", NULL, 0, 200000000), +}; + +static const struct of_device_id ext_clk_match[] __initconst = { + { .compatible = "samsung,exynos850-oscclk" }, + {} +}; + +static void __init exynos850_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + struct samsung_clk_provider *ctx; + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); + if (!ctx) + panic("%s: unable to allocate ctx\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, + exynos850_fixed_rate_ext_clks, + ARRAY_SIZE(exynos850_fixed_rate_ext_clks), + ext_clk_match); + + samsung_clk_register_fixed_rate(ctx, exynos850_peri_clks, + ARRAY_SIZE(exynos850_peri_clks)); + + samsung_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(exynos850_clk, "samsung,exynos850-clock", exynos850_clk_init); From patchwork Fri Aug 6 15:21:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 493139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0AA3C4320A for ; Fri, 6 Aug 2021 15:22:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9002A61181 for ; Fri, 6 Aug 2021 15:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244401AbhHFPXN (ORCPT ); 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Fri, 06 Aug 2021 08:22:00 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , =?utf-8?q?Pawe=C5=82_Chmiel?= Cc: Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: exynos: Add Exynos850 SoC support Date: Fri, 6 Aug 2021 18:21:46 +0300 Message-Id: <20210806152146.16107-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210806152146.16107-1-semen.protsenko@linaro.org> References: <20210806152146.16107-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Samsung Exynos850 is ARMv8-based mobile-oriented SoC. This patch adds minimal SoC support by including next Device Tree nodes: 1. Octa cores (Cortex-A55), supporting PSCI v1.0 2. ARM architecture timer (armv8-timer) 3. Interrupt controller (GIC-400) 4. Clock controller node (using stub driver for now) 5. Pinctrl nodes for GPIO 6. Serial node Signed-off-by: Sam Protsenko --- Changes in v2: * Commit message: - Documented added dts features instead of CPU features * exynos850-usi.dtsi: - Removed, moved everything to exynos850.dtsi * exynos850.dtsi: - Root node: - Added comment about engineering name (Exynos3830) - Renamed pinctrl nodes, adding domain names - Used hard coded IRQ numbers instead of named constants everywhere - Added soc node, moved next nodes there: gic, clock, pinctrls and serial - Used address-cells=1 for soc node and removed unneeded 0x0 from reg properties - Moved exynos850-pinctrl.dtsi include line to the end of exynos850.dtsi - Coding style fixes - cpus: - Used address-cells=1 for cpus node - Renamed cpu@0001 to cpu@1, and so on - Left only "arm,cortex-a55" for cpus compatible - Renamed reg = <0x0001> to <0x1> for cpus - armv8 timer: - Add comment about missing HV timer IRQ to armv8 timer node - Removed not existing properties from armv8 timer node - Fixed cpu number in CPU_MASK() - Removed obsolete clock-frequency property - GIC: - Fixed GIC type to be GIC-400 - Fixed size of GIC's 2nd region to be 0x2000 - serial node: - Hard coded clock number for serial_0 for now; will replace with named const once proper clock driver is implemented - Removed gate_uart_clk0 clock from serial_0, as that clock is not supported in serial driver anyway (yet) - clock node: - Fixed clock controller node name (@0x12.. -> @12..) * exynos850-pinctrl.dtsi: - Referenced pinctrl nodes instead of defining those again in root node - Fixed interrupt-cells (3 -> 2) - Fixed USI related comments for pin config nodes - Removed decon_f_te_* and fm_lna_en nodes (won't be used) - Reordered pin config nodes by pin numbers - Improved all comments - Used existing named constants for pin-function and pin-pud - Fixed node names (used hyphens instead of underscore) - Fixed warnings found in W=1 build .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 256 ++++++ 2 files changed, 1004 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..ba5d5f33e2f6 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_bus: i2c5-bus { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_bus: i2c6-bus { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: UART */ + uart0_bus: uart0-bus { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_bus: hsi2c3-bus { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_bus_single: uart1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_bus_dual: uart1-bus-dual { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: SPI function */ + spi1_bus: spi1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi1_cs: spi1-cs { + samsung,pins = "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi1_cs_func: spi1-cs-func { + samsung,pins = "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_bus: hsi2c4-bus { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_bus_single: uart2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_bus_dual: uart2-bus-dual { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: SPI function */ + spi2_bus: spi2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi2_cs: spi2-cs { + samsung,pins = "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi2_cs_func: spi2-cs-func { + samsung,pins = "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_aud { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk: aud-codec-mclk { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle: aud-codec-mclk-idle { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_bus: aud-i2s0-bus { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_idle: aud-i2s0-idle { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_bus: aud-i2s1-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_idle: aud-i2s1-idle { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus: aud-fm-bus { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_idle: aud-fm-idle { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <1>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <4>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <5>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpf2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpf2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_pins_as_pdn: sd2-pins-as-pdn { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_core { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <1>; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_nreset: sd0-nreset { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; +}; + +&pinctrl_peri { + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* USI: HSI2C0 */ + hsi2c0_bus: hsi2c0-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: HSI2C1 */ + hsi2c1_bus: hsi2c1-bus { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: HSI2C2 */ + hsi2c2_bus: hsi2c2-bus { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: SPI */ + spi0_bus: spi0-bus { + samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi0_cs: spi0-cs { + samsung,pins = "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi0_cs_func: spi0-cs-func { + samsung,pins = "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + sensor_mclk0_in: sensor-mclk0-in { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_out: sensor-mclk0-out { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_fn: sensor-mclk0-fn { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_in: sensor-mclk1-in { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_in: sensor-mclk2-in { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_out: sensor-mclk2-out { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_fn: sensor-mclk2-fn { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + xclkout: xclkout { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi new file mode 100644 index 000000000000..9d8c1402685e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos based board files can include this file and provide + * values for board specific bindings. + */ + +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + serial0 = &serial_0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = , + , + , + ; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = ; + }; + + clock: clock-controller@120e0000 { + compatible = "samsung,exynos850-clock"; + reg = <0x120e0000 0x8000>; + #clock-cells = <1>; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + /* USI: UART */ + serial_0: uart@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&clock 2>; + clock-names = "uart"; + status = "disabled"; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi"