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CAT:NONE; SFS:(4636009)(346002)(376002)(39860400002)(396003)(136003)(36840700001)(46966006)(70586007)(336012)(2616005)(82310400003)(8676002)(426003)(70206006)(478600001)(5660300002)(36860700001)(356005)(47076005)(86362001)(7696005)(83380400001)(6666004)(81166007)(4326008)(2906002)(82740400003)(26005)(186003)(54906003)(8936002)(316002)(16526019)(110136005)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2021 16:59:51.8800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bc6eb3f-2a14-46d1-039d-08d958fb9b8b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4705 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta Introduce nhi_check_quirks() routine to handle any vendor specific quirks to manage a hardware specific implementation. On Intel system, the USB4 controller requires the REG_DMA_MISC_INT_AUTO_CLEAR to be set. Hence handle it accordingly as per the USB4 specification via a quirk. Fixes: 046bee1f9ab8 ("thunderbolt: Add MSI-X support") Suggested-by: Mika Westerberg Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 18 ++++++++++++++---- include/linux/thunderbolt.h | 1 + 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index fa44332..7979638 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -43,6 +43,12 @@ static int ring_interrupt_index(struct tb_ring *ring) return bit; } +static void nhi_check_quirks(struct tb_nhi *nhi) +{ + if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) + nhi->quirks |= REG_DMA_MISC_INT_AUTO_CLEAR; +} + /* * ring_interrupt_active() - activate/deactivate interrupts for a single ring * @@ -70,10 +76,12 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) * Ask the hardware to clear interrupt status bits automatically * since we already know which interrupt was triggered. */ - misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); - if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { - misc |= REG_DMA_MISC_INT_AUTO_CLEAR; - iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); + if (ring->nhi->quirks & REG_DMA_MISC_INT_AUTO_CLEAR) { + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); + if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { + misc |= REG_DMA_MISC_INT_AUTO_CLEAR; + iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); + } } ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; @@ -1190,6 +1198,8 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!nhi->tx_rings || !nhi->rx_rings) return -ENOMEM; + nhi_check_quirks(nhi); + res = nhi_init_msi(nhi); if (res) { dev_err(&pdev->dev, "cannot enable MSI, aborting\n"); diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index e7c96c3..2144123 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -480,6 +480,7 @@ struct tb_nhi { bool going_away; struct work_struct interrupt_work; u32 hop_count; + u32 quirks; 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Fri, 6 Aug 2021 16:59:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none; linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT035.mail.protection.outlook.com (10.13.177.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4394.16 via Frontend Transport; Fri, 6 Aug 2021 16:59:56 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 6 Aug 2021 11:59:53 -0500 From: Sanjay R Mehta To: , , , CC: , , , , Sanjay R Mehta Subject: [PATCH v3 2/4] thunderbolt: Handle ring interrupt by reading intr status Date: Fri, 6 Aug 2021 11:59:06 -0500 Message-ID: <1628269148-51355-3-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> References: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a3965214-9e9d-4101-f94a-08d958fb9e61 X-MS-TrafficTypeDiagnostic: BY5PR12MB5557: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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CAT:NONE; SFS:(4636009)(346002)(39860400002)(396003)(376002)(136003)(46966006)(36840700001)(36756003)(336012)(82310400003)(86362001)(82740400003)(478600001)(6666004)(54906003)(316002)(36860700001)(110136005)(81166007)(8936002)(426003)(16526019)(2906002)(4326008)(7696005)(2616005)(186003)(5660300002)(26005)(47076005)(356005)(70206006)(83380400001)(70586007)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2021 16:59:56.6442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3965214-9e9d-4101-f94a-08d958fb9e61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5557 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta As per USB4 specification by default "Disable ISR Auto-Clear" bit is set to zero and the Tx/Rx ring interrupt status needs to be cleared. Hence handle it by reading the "Interrupt status" register in the ISR. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index 7979638..56ac343 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -385,11 +385,25 @@ void tb_ring_poll_complete(struct tb_ring *ring) } EXPORT_SYMBOL_GPL(tb_ring_poll_complete); +static void check_and_clear_intr_status(struct tb_ring *ring) +{ + if (!(ring->nhi->quirks & REG_DMA_MISC_INT_AUTO_CLEAR)) { + if (ring->is_tx) + ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE); + else + ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE + + 4 * (ring->nhi->hop_count / 32)); + } +} + static irqreturn_t ring_msix(int irq, void *data) { struct tb_ring *ring = data; spin_lock(&ring->nhi->lock); + check_and_clear_intr_status(ring); spin_lock(&ring->lock); __ring_interrupt(ring); spin_unlock(&ring->lock); From patchwork Fri Aug 6 16:59:07 2021 Content-Type: text/plain; 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Fri, 6 Aug 2021 17:00:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none; linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT003.mail.protection.outlook.com (10.13.177.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4394.16 via Frontend Transport; Fri, 6 Aug 2021 17:00:02 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 6 Aug 2021 11:59:58 -0500 From: Sanjay R Mehta To: , , , CC: , , , , Sanjay R Mehta Subject: [PATCH v3 3/4] thunderbolt: Skip port init for control adapter(0) Date: Fri, 6 Aug 2021 11:59:07 -0500 Message-ID: <1628269148-51355-4-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> References: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c78ba28-23d7-4bca-3868-08d958fba1a7 X-MS-TrafficTypeDiagnostic: MW3PR12MB4508: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; 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CAT:NONE; SFS:(4636009)(396003)(39860400002)(136003)(376002)(346002)(36840700001)(46966006)(81166007)(70206006)(2906002)(36756003)(26005)(82740400003)(356005)(426003)(4326008)(5660300002)(70586007)(2616005)(7696005)(6666004)(86362001)(186003)(54906003)(16526019)(82310400003)(316002)(336012)(4744005)(47076005)(110136005)(478600001)(8676002)(36860700001)(8936002)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2021 17:00:02.1342 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c78ba28-23d7-4bca-3868-08d958fba1a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4508 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta Adapter (0) is control adapter and as per USB4 spec in "Section 1.8", "Control Adapters do not have an Adapter Configuration Space". Hence skip port initialization for adapter (0). Fixes: e6b245ccd524 ("thunderbolt: Add support for host and device NVM firmware upgrade") Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 83b1ef3..6447876 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2740,7 +2740,7 @@ int tb_switch_add(struct tb_switch *sw) return ret; } - for (i = 0; i <= sw->config.max_port_number; i++) { + for (i = 1; i <= sw->config.max_port_number; i++) { if (sw->ports[i].disabled) { tb_port_dbg(&sw->ports[i], "disabled by eeprom\n"); continue; From patchwork Fri Aug 6 16:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjay R Mehta X-Patchwork-Id: 493563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42475C4338F for ; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT003.mail.protection.outlook.com (10.13.177.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4394.16 via Frontend Transport; Fri, 6 Aug 2021 17:00:06 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 6 Aug 2021 12:00:03 -0500 From: Sanjay R Mehta To: , , , CC: , , , , Sanjay R Mehta Subject: [PATCH v3 4/4] thunderbolt: Fix port linking by checking all adapters Date: Fri, 6 Aug 2021 11:59:08 -0500 Message-ID: <1628269148-51355-5-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> References: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ed3bbda6-13c6-4ec0-ec80-08d958fba46d X-MS-TrafficTypeDiagnostic: BN6PR12MB1602: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; 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CAT:NONE; SFS:(4636009)(376002)(396003)(346002)(136003)(39860400002)(36840700001)(46966006)(54906003)(26005)(70586007)(70206006)(8936002)(2906002)(356005)(4326008)(2616005)(8676002)(83380400001)(426003)(81166007)(82740400003)(5660300002)(86362001)(66574015)(186003)(16526019)(82310400003)(36860700001)(110136005)(36756003)(47076005)(7696005)(316002)(336012)(478600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2021 17:00:06.7919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed3bbda6-13c6-4ec0-ec80-08d958fba46d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1602 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta In tb_switch_default_link_ports(), while linking of ports, only odd-numbered ports (1,3,5..) are considered and even-numbered ports are not considered. AMD host router has lane adapters at 2 & 3 and link ports at adapter-2 is not considered due to which lane bonding gets disabled. Hence added a fix such that all ports are considered during linking of ports. Fixes: 0d46c08d1ed4 ("thunderbolt: Add default linking between lane adapters if not provided by DROM") Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/switch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index 6447876..5c3d4bd 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2456,7 +2456,7 @@ static void tb_switch_default_link_ports(struct tb_switch *sw) { int i; - for (i = 1; i <= sw->config.max_port_number; i += 2) { + for (i = 1; i <= sw->config.max_port_number; i++) { struct tb_port *port = &sw->ports[i]; struct tb_port *subordinate;