From patchwork Tue Sep 25 17:20:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147515 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp987545lji; Tue, 25 Sep 2018 10:23:16 -0700 (PDT) X-Google-Smtp-Source: ACcGV63RZMk4EbGQFvPdzZ/+BH8Solh1aOGaoGu62JLIlA99SNvJf06pj5EcC5ZsBk/XN1FjTqqn X-Received: by 2002:a02:c7d1:: with SMTP id s17-v6mr1984175jao.27.1537896196550; Tue, 25 Sep 2018 10:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537896196; cv=none; d=google.com; s=arc-20160816; b=OpjTrsHsO77Ddu8i27bLpTES7ss4Ht4waNID0fPsbRYtxF3NNkvs2bKUp/0Hd2pWjE llgnCAPo075gyDp5INFVMDidwOb0irB+qFKWpp0AnaAy4zsanuXzqX0tvRviL297Fa0Q 7wkwOzuPGk2LFbLbZ3geD4PaL4CdNm856Zxhn6Mlf8SLDgelUa7TVXZBOi18rAyMHkk1 ECspP6cwIDODc+ItG/hbqe0O515CZTNEX2+vRl/mYEYP+grpjXen6oPA8yTCLPri7pgd 7On1OfPq4o6tZRUUQQmOktyn2Snqw44oIYwVgi7OmggJC2bm2afxPPDl7ArOFNwXHv7Q CL2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=96wDaMr60MeqLREVWPgznJFf6IQyOjNNtSLdoPb7eVA=; b=HAMzLgn8HxrGRkuUbOKvLwQnhqcFvTJ4wwx4P/u+iQy7GcKI9Kb5Gf17oZzJqC4C2N iHPRcaaSQVmtwUN1aJBsvMXqIwwnAzr0eQ1+LjXL24GEYSyrPTe3DdVI2NWvq6qt5+0j auRT/3vAPXTTh387YqE2uHQX9ph686TZ6INL/HMbv+gD2skm/JIyT8/9SmIn4U9VEuDs ixTeHgLaw7RN9XMINT4m/S9B8/Hts28Fy3CY6MyK7OnWAD83J6BpWJgN5nRESCTcUvD3 xyJkvzy4tbogfrERU6EVuwZLOxaABN94eiYRJMlDOZ4DO18KlrTfC5S/7/rWG6AVTgwk YpkA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e17-v6si1711220itf.105.2018.09.25.10.23.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r14-0004AW-QW; Tue, 25 Sep 2018 17:20:54 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r13-0004A9-SJ for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:53 +0000 X-Inumbo-ID: 0c147c4c-c0e7-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 0c147c4c-c0e7-11e8-a8a5-bc764e045a96; Tue, 25 Sep 2018 19:18:40 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A49415AD; Tue, 25 Sep 2018 10:20:51 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A0213F5BD; Tue, 25 Sep 2018 10:20:50 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:38 +0100 Message-Id: <20180925172043.20248-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 1/6] xen/arm: smccc-1.1: Make return values unsigned long X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Marc Zyngier An unfortunate consequence of having a strong typing for the input values to the SMC call is that it also affects the type of the return values, limiting r0 to 32 bits and r{1,2,3} to whatever was passed as an input. Let's turn everything into "unsigned long", which satisfies the requirements of both architectures, and allows for the full range of return values. Reported-by: Stefano Stabellini Signed-off-by: Marc Zyngier Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr reviewed-by --- xen/include/asm-arm/smccc.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 74c13f8419..a31d67a1de 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -119,35 +119,35 @@ struct arm_smccc_res { #define __declare_arg_0(a0, res) \ struct arm_smccc_res *___res = res; \ - register uin32_t r0 asm("r0") = a0; \ + register unsigned long r0 asm("r0") = (uint32_t)a0;\ register unsigned long r1 asm("r1"); \ register unsigned long r2 asm("r2"); \ register unsigned long r3 asm("r3") #define __declare_arg_1(a0, a1, res) \ struct arm_smccc_res *___res = res; \ - register uint32_t r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r0 asm("r0") = (uint32_t)a0;\ + register unsigned long r1 asm("r1") = a1; \ register unsigned long r2 asm("r2"); \ register unsigned long r3 asm("r3") #define __declare_arg_2(a0, a1, a2, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r0 asm("r0") = (uint32_t)a0;\ + register unsigned long r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2") = a2; \ register unsigned long r3 asm("r3") #define __declare_arg_3(a0, a1, a2, a3, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ - register typeof(a3) r3 asm("r3") = a3 + register unsigned long r0 asm("r0") = (uint32_t)a0;\ + register unsigned long r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") = a3 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ __declare_arg_3(a0, a1, a2, a3, res); \ - register typeof(a4) r4 asm("r4") = a4 + register unsigned long r4 asm("r4") = a4 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ From patchwork Tue Sep 25 17:20:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147518 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp987621lji; Tue, 25 Sep 2018 10:23:20 -0700 (PDT) X-Google-Smtp-Source: ACcGV60RBb+s2s/cuVT4PpDEsHJmhJ7MMY5KNyKvwEeAGVUJY28QhWgwJ56PafTdBCn2rJ/nfB55 X-Received: by 2002:a6b:3902:: with SMTP id g2-v6mr1882109ioa.168.1537896200318; Tue, 25 Sep 2018 10:23:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537896200; cv=none; d=google.com; s=arc-20160816; b=eoilnWnMbcGn1196U/MTyAbZEUa2Itgm4564YtcclV6W5t+gMPfO2dXOx7dXGkWD0A sRoGkiYBV6BR9+qMDcQsqXynZoZXmO4X8ZERrTg8aD2eyxnZhvp2uVF2YeIM8K/6ptpv jieSVjzogKbgL43wvEISShcBIAh6qWk0a41/CQ+Dz/XgC6qp7kUsQnilAVUZj2aBbfr7 IaL5ypOVp2NHTqJ17fb2xhXAWbUDJV46/1i39OShcwz96Xv4TFY3Xv6BmRIvhgl8rvJw cit97lGUKGQeILmADN5Z97STjbwgrGIP+wlwZPpHbap9lFyJvrYetJgz+3MNERU/mjQM tbUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=luLtggTCDSCx1e1f2mufN0YZXkwateQaEOgGF6AN5YY=; b=JYS1/9XGLO7iVSH/HLFRNJkHk3M7ZUo+BAaF/5iaTEKTKQDi3cscNmtRE0Uvq+zNOa ZIAre66O4x4QDLkkM1g0Bha71NZl5G4+OpqtbLm+kLwPKUvIpZm9U9VJXACU/gs/l+g7 ild4m1gw9WcGrZKOL6s/iMnUTSxPK6gr3YGy7lqXjjVwAQpgK4iMqmLv3nhbWuHm68qc RpDqGEHkH1+6+1exIH8jc5wQqKRKfb6JoC/EfvuHC93nwgdjNgk0ABUXPAAzf4iH1l8t s5HFB6KP+z2Pw4zk2AxpvxmM+A/HBRkYWrB31hOlTy6AQVSCOr7nZtnyZ040306wgbKP qh1Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id j206-v6si2039264iof.77.2018.09.25.10.23.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r14-0004AP-G0; Tue, 25 Sep 2018 17:20:54 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r13-0004A8-Rx for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:53 +0000 X-Inumbo-ID: 0cc4fc0a-c0e7-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 0cc4fc0a-c0e7-11e8-a8a5-bc764e045a96; Tue, 25 Sep 2018 19:18:41 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B34B07A9; Tue, 25 Sep 2018 10:20:52 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C62943F5BD; Tue, 25 Sep 2018 10:20:51 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:39 +0100 Message-Id: <20180925172043.20248-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 2/6] xen/arm: smccc-1.1: Handle function result as parameters X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Marc Zyngier If someone has the silly idea to write something along those lines: extern u64 foo(void); void bar(struct arm_smccc_res *res) { arm_smccc_1_1_smc(0xbad, foo(), res); } they are in for a surprise, as this gets compiled as: 0000000000000588 : 588: a9be7bfd stp x29, x30, [sp, #-32]! 58c: 910003fd mov x29, sp 590: f9000bf3 str x19, [sp, #16] 594: aa0003f3 mov x19, x0 598: aa1e03e0 mov x0, x30 59c: 94000000 bl 0 <_mcount> 5a0: 94000000 bl 0 5a4: aa0003e1 mov x1, x0 5a8: d4000003 smc #0x0 5ac: b4000073 cbz x19, 5b8 5b0: a9000660 stp x0, x1, [x19] 5b4: a9010e62 stp x2, x3, [x19, #16] 5b8: f9400bf3 ldr x19, [sp, #16] 5bc: a8c27bfd ldp x29, x30, [sp], #32 5c0: d65f03c0 ret 5c4: d503201f nop The call to foo "overwrites" the x0 register for the return value, and we end up calling the wrong secure service. A solution is to evaluate all the parameters before assigning anything to specific registers, leading to the expected result: 0000000000000588 : 588: a9be7bfd stp x29, x30, [sp, #-32]! 58c: 910003fd mov x29, sp 590: f9000bf3 str x19, [sp, #16] 594: aa0003f3 mov x19, x0 598: aa1e03e0 mov x0, x30 59c: 94000000 bl 0 <_mcount> 5a0: 94000000 bl 0 5a4: aa0003e1 mov x1, x0 5a8: d28175a0 mov x0, #0xbad 5ac: d4000003 smc #0x0 5b0: b4000073 cbz x19, 5bc 5b4: a9000660 stp x0, x1, [x19] 5b8: a9010e62 stp x2, x3, [x19, #16] 5bc: f9400bf3 ldr x19, [sp, #16] 5c0: a8c27bfd ldp x29, x30, [sp], #32 5c4: d65f03c0 ret Reported-by: Stefano Stabellini Signed-off-by: Marc Zyngier Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/include/asm-arm/smccc.h | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index a31d67a1de..648bef28bd 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -125,41 +125,51 @@ struct arm_smccc_res { register unsigned long r3 asm("r3") #define __declare_arg_1(a0, a1, res) \ + typeof(a1) __a1 = a1; \ struct arm_smccc_res *___res = res; \ register unsigned long r0 asm("r0") = (uint32_t)a0;\ - register unsigned long r1 asm("r1") = a1; \ + register unsigned long r1 asm("r1") = __a1; \ register unsigned long r2 asm("r2"); \ register unsigned long r3 asm("r3") #define __declare_arg_2(a0, a1, a2, res) \ + typeof(a1) __a1 = a1; \ + typeof(a2) __a2 = a2; \ struct arm_smccc_res *___res = res; \ register unsigned long r0 asm("r0") = (uint32_t)a0;\ - register unsigned long r1 asm("r1") = a1; \ - register unsigned long r2 asm("r2") = a2; \ + register unsigned long r1 asm("r1") = __a1; \ + register unsigned long r2 asm("r2") = __a2; \ register unsigned long r3 asm("r3") #define __declare_arg_3(a0, a1, a2, a3, res) \ + typeof(a1) __a1 = a1; \ + typeof(a2) __a2 = a2; \ + typeof(a3) __a3 = a3; \ struct arm_smccc_res *___res = res; \ register unsigned long r0 asm("r0") = (uint32_t)a0;\ - register unsigned long r1 asm("r1") = a1; \ - register unsigned long r2 asm("r2") = a2; \ - register unsigned long r3 asm("r3") = a3 + register unsigned long r1 asm("r1") = __a1; \ + register unsigned long r2 asm("r2") = __a2; \ + register unsigned long r3 asm("r3") = __a3 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + typeof(a4) __a4 = a4; \ __declare_arg_3(a0, a1, a2, a3, res); \ - register unsigned long r4 asm("r4") = a4 + register unsigned long r4 asm("r4") = __a4 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + typeof(a5) __a5 = a5; \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register typeof(a5) r5 asm("r5") = a5 + register typeof(a5) r5 asm("r5") = __a5 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + typeof(a6) __a6 = a6; \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register typeof(a6) r6 asm("r6") = a6 + register typeof(a6) r6 asm("r6") = __a6 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + typeof(a7) __a7 = a7; \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register typeof(a7) r7 asm("r7") = a7 + register typeof(a7) r7 asm("r7") = __a7 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) From patchwork Tue Sep 25 17:20:40 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id n70-v6si1910012ion.245.2018.09.25.10.23.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r16-0004Au-4B; Tue, 25 Sep 2018 17:20:56 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r14-0004Aa-VJ for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:54 +0000 X-Inumbo-ID: 0d8db9c2-c0e7-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 0d8db9c2-c0e7-11e8-a8a5-bc764e045a96; Tue, 25 Sep 2018 19:18:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CFB415AD; Tue, 25 Sep 2018 10:20:54 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EFAA83F5BD; Tue, 25 Sep 2018 10:20:52 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:40 +0100 Message-Id: <20180925172043.20248-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 3/6] xen/arm: add SMC wrapper that is compatible with SMCCC v1.0 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Volodymyr Babchuk Existing SMC wrapper call_smc() allows only 4 parameters and returns only one value. This is enough for existing use in PSCI code, but TEE mediator will need a call that is fully compatible with ARM SMCCC v1.0. This patch adds a wrapper for both arm32 and arm64. In the case of arm32, the wrapper is just an alias to the ARM SMCCC v1.1 as the convention is the same. CC: "Edgar E. Iglesias" Signed-off-by: Volodymyr Babchuk [julien: Rework the wrapper to make it closer to SMCC 1.1 wrapper] Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/asm-offsets.c | 5 ++++ xen/arch/arm/arm64/smc.S | 32 +++++++++++++++++++++++++ xen/include/asm-arm/smccc.h | 51 +++++++++++++++++++++++++++++++++++++++- 4 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm64/smc.S diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index bb5c610b2a..c4f3a28a0d 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -8,6 +8,7 @@ obj-y += domain.o obj-y += entry.o obj-y += insn.o obj-$(CONFIG_LIVEPATCH) += livepatch.o +obj-y += smc.o obj-y += smpboot.o obj-y += traps.o obj-y += vfp.o diff --git a/xen/arch/arm/arm64/asm-offsets.c b/xen/arch/arm/arm64/asm-offsets.c index 62833d8c8b..280ddb55bf 100644 --- a/xen/arch/arm/arm64/asm-offsets.c +++ b/xen/arch/arm/arm64/asm-offsets.c @@ -10,6 +10,7 @@ #include #include #include +#include #define DEFINE(_sym, _val) \ asm volatile ("\n.ascii\"==>#define " #_sym " %0 /* " #_val " */<==\"" \ @@ -51,6 +52,10 @@ void __dummy__(void) BLANK(); OFFSET(INITINFO_stack, struct init_info, stack); + + BLANK(); + OFFSET(SMCCC_RES_a0, struct arm_smccc_res, a0); + OFFSET(SMCCC_RES_a2, struct arm_smccc_res, a2); } /* diff --git a/xen/arch/arm/arm64/smc.S b/xen/arch/arm/arm64/smc.S new file mode 100644 index 0000000000..b0752be57e --- /dev/null +++ b/xen/arch/arm/arm64/smc.S @@ -0,0 +1,32 @@ +/* + * xen/arch/arm/arm64/smc.S + * + * Wrapper for Secure Monitors Calls + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/* + * void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, + * register_t a3, register_t a4, register_t a5, + * register_t a6, register_t a7, + * struct arm_smccc_res *res) + */ +ENTRY(__arm_smccc_1_0_smc) + smc #0 + ldr x4, [sp] + cbz x4, 1f /* No need to store the result */ + stp x0, x1, [x4, #SMCCC_RES_a0] + stp x2, x3, [x4, #SMCCC_RES_a2] +1: + ret diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 648bef28bd..1ed6cbaa48 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -207,7 +207,56 @@ struct arm_smccc_res { *___res = (typeof(*___res)){r0, r1, r2, r3}; \ } while ( 0 ) -#endif +/* + * The calling convention for arm32 is the same for both SMCCC v1.0 and + * v1.1. + */ +#ifdef CONFIG_ARM_32 +#define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) +#else + +void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, + register_t a3, register_t a4, register_t a5, + register_t a6, register_t a7, + struct arm_smccc_res *res); + +/* Macros to handle variadic parameter for SMCCC v1.0 helper */ +#define __arm_smccc_1_0_smc_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __arm_smccc_1_0_smc(a0, a1, a2, a3, a4, a5, a6, a7, res) + +#define __arm_smccc_1_0_smc_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __arm_smccc_1_0_smc_7(a0, a1, a2, a3, a4, a5, a6, 0, res) + +#define __arm_smccc_1_0_smc_5(a0, a1, a2, a3, a4, a5, res) \ + __arm_smccc_1_0_smc_6(a0, a1, a2, a3, a4, a5, 0, res) + +#define __arm_smccc_1_0_smc_4(a0, a1, a2, a3, a4, res) \ + __arm_smccc_1_0_smc_5(a0, a1, a2, a3, a4, 0, res) + +#define __arm_smccc_1_0_smc_3(a0, a1, a2, a3, res) \ + __arm_smccc_1_0_smc_4(a0, a1, a2, a3, 0, res) + +#define __arm_smccc_1_0_smc_2(a0, a1, a2, res) \ + __arm_smccc_1_0_smc_3(a0, a1, a2, 0, res) + +#define __arm_smccc_1_0_smc_1(a0, a1, res) \ + __arm_smccc_1_0_smc_2(a0, a1, 0, res) + +#define __arm_smccc_1_0_smc_0(a0, res) \ + __arm_smccc_1_0_smc_1(a0, 0, res) + +#define ___arm_smccc_1_0_smc_count(count, ...) \ + __arm_smccc_1_0_smc_ ## count(__VA_ARGS__) + +#define __arm_smccc_1_0_smc_count(count, ...) \ + ___arm_smccc_1_0_smc_count(count, __VA_ARGS__) + +#define arm_smccc_1_0_smc(...) \ + __arm_smccc_1_0_smc_count(__count_args(__VA_ARGS__), __VA_ARGS__) + +#endif /* CONFIG_ARM_64 */ + +#endif /* __ASSEMBLY__ */ /* * Construct function identifier from call type (fast or standard), From patchwork Tue Sep 25 17:20:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147514 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp987359lji; Tue, 25 Sep 2018 10:23:04 -0700 (PDT) X-Google-Smtp-Source: ACcGV63Ysuxks66Ex0IFYzs76C0GZkRDB+62AD9V97pHHiTKwy8cexUT+XzsKe96W2VQeEPmZIaL X-Received: by 2002:a24:1013:: with SMTP id 19-v6mr1667340ity.141.1537896184079; Tue, 25 Sep 2018 10:23:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537896184; cv=none; d=google.com; s=arc-20160816; b=nKNaGEoNOPyMwUp0Wz0UCLVU+8TLbZqaYVmiKmGcwulT+VGhGiDLqoRoCv+YKbVIR7 R9q+qJLLeQ3XEXAWDcMm5Lri+jR+YTXMHuYN5NaUstnaWOqQGnIVyzulvQf+NkFfOVXT HTC5B1VqN1XDFHJdPxm8IfIEwav09k0OiTBU5LwH08M4FFpBvusGBqh/3xoBaQjHnBK8 kx6jrkkVNZwtqzlBhZeZJnMPa11gvTJOj7FxCoJRRQFjqG1GwzjWpdCvUOIgnVyzSD+b 8kfpWjs8M18/e07LgzoCOS/Gzum80slW/nhg5QTX+X/cuV5HIX4Hfz7raupgLry/AILq nK1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=fuP275Aei9SsYHD16C2EdYWFnQpMU28/ZnkxthUc8dI=; b=0LCloLHsklUjsjX+0S9n1c5ygAp+ky0FeRJFYdqWZm2TAfE1SkrrYgsgSAkMyVXFr9 OOF2REqXYYVCwNeo/HBslzl5aR6h2jPbSiOVIJXVuxEvmQ7mlWiOWtwPaM3ilVpaX2OQ 21CLdXyasMAi29uoJ62/an44sjEVzc0CVgBIT4wVFwTKASMyk7mrY7dE+uRz/O5F6Fpr ippw4/wOZGPbPAEsNdO5MJKfqNB/LdIX7LCqi7ouURxkRuEthCc9kXqIFqoNT2CBWUFK OzGTDwtJj52cGI+9GoY3iLBPQqHppXcxNHz7bjiBXZKbWwnxSUKL1iWkC29RcHUP4ZOl nnwA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w4-v6si1890488ioa.62.2018.09.25.10.23.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r16-0004BL-MZ; Tue, 25 Sep 2018 17:20:56 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r15-0004Aj-Rc for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:55 +0000 X-Inumbo-ID: 83a8f17e-c0e7-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 83a8f17e-c0e7-11e8-a6a9-d7ebe60f679a; Tue, 25 Sep 2018 17:22:01 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35CCD7A9; Tue, 25 Sep 2018 10:20:55 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 48DEA3F5BD; Tue, 25 Sep 2018 10:20:54 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:41 +0100 Message-Id: <20180925172043.20248-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 4/6] xen/arm: cpufeature: Add helper to check constant caps X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some capababilities are set right during boot and will never change afterwards. At the moment, the function cpu_have_caps will check whether the cap is enabled from the memory. It is possible to avoid the load from the memory by using an ALTERNATIVE. With that the check is just reduced to 1 instruction. Signed-off-by: Julien Grall --- This is the static key for the poor. At some point we might want to introduce something similar to static key in Xen. Changes in v2: - Use unlikely --- xen/include/asm-arm/cpufeature.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 3de6b54301..c6cbc2ec84 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -63,6 +63,18 @@ static inline bool cpus_have_cap(unsigned int num) return test_bit(num, cpu_hwcaps); } +/* System capability check for constant cap */ +#define cpus_have_const_cap(num) ({ \ + bool __ret; \ + \ + asm volatile (ALTERNATIVE("mov %0, #0", \ + "mov %0, #1", \ + num) \ + : "=r" (__ret)); \ + \ + unlikely(__ret); \ + }) + static inline void cpus_set_cap(unsigned int num) { if (num >= ARM_NCAPS) From patchwork Tue Sep 25 17:20:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147516 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp987584lji; Tue, 25 Sep 2018 10:23:19 -0700 (PDT) X-Google-Smtp-Source: ACcGV63BDDKkHnvo5ae5pFfnjhXTp5/awe+skkIN9h3DYOkdMJ7yMhp+io7Q/3Za5K0lQtgAc1Rw X-Received: by 2002:a6b:2985:: with SMTP id p127-v6mr1741790iop.95.1537896199032; Tue, 25 Sep 2018 10:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537896199; cv=none; d=google.com; s=arc-20160816; b=HeffPPRuFXWUSHw1LZaZfWDlTMTJYfyWtLKXmbll/wC4iVc4T1cjn+w/MY5unLL9En 0qPpswVOHDtIRj8t724V/5JQszyc89H9jkqi6jjB4ZZfP2CoFVqYwgXXWq18zI64kCOQ b/R8BsEPiShoyuTgaDpl6/aV/8BdgnB3wecoTJdHnc0pMf7+5CsbYIT+11vS0E1oo1om gB9ZP44KNfXZ0R523+fbCX3ly5xnevnI/TdmsWtrjaNN+2x9s4oMuGv5QRuHBo8opfws mz8vfK+2S0+4C4Q1ZGYUoITLJbJyh4U9z2hw81ZaJXrbrGdY6rgCWyATUCoeePG6L+zn 9w0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=LftVdSeA48w8v+Qoqb621InPwmhq6+H2MHtj1G61u50=; b=ycIjhHece9mUsY9NGi7rxaIWlYnJNQVVJEZ7samRm0Yz+ry4I0O624G5bFCin/wJox XAbRqkAZlDKt1ahtFeFgMLruk8qCPM6cAaxzU1KcysA6MmrUh/ZB7JDDzgFVcCRDDzUE 7+WnmPE1C/ORQZaKLlwKYZU9Stp+E7og0H8JnBd3JeNlHAfeoUuggfcKbvHzBMGippUV qAzuLkV3t7/lAVQQUS+TNFWNgfexNbgJE3+AWvGheeJf/NUVh6l6oAcxJwqwqRm7966x O1bNH+YH7vP8aNYzEYJEc3KwLGwr6ahOYBeUrNNtm4AX68ahPovlZylRpzlPCpptF2Wj YO6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q124-v6si1939357iod.118.2018.09.25.10.23.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r18-0004C2-1j; Tue, 25 Sep 2018 17:20:58 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r17-0004BU-1n for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:57 +0000 X-Inumbo-ID: 845b2730-c0e7-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 845b2730-c0e7-11e8-a6a9-d7ebe60f679a; Tue, 25 Sep 2018 17:22:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F07515AD; Tue, 25 Sep 2018 10:20:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71F0E3F5BD; Tue, 25 Sep 2018 10:20:55 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:42 +0100 Message-Id: <20180925172043.20248-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 5/6] xen/arm: smccc: Add wrapper to automatically select the calling convention X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Volodymyr Babchuk --- Changes in v2: - Invert the condition - Add missing includes --- xen/arch/arm/psci.c | 4 ++++ xen/include/asm-arm/cpufeature.h | 3 ++- xen/include/asm-arm/smccc.h | 11 +++++++++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 3cf5ecf0f3..941eec921b 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -118,6 +119,9 @@ static void __init psci_init_smccc(void) smccc_ver = ret; } + if ( smccc_ver >= SMCCC_VERSION(1, 1) ) + cpus_set_cap(ARM_SMCCC_1_1); + printk(XENLOG_INFO "Using SMC Calling Convention v%u.%u\n", SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); } diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index c6cbc2ec84..2d82264427 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -44,8 +44,9 @@ #define SKIP_CTXT_SWITCH_SERROR_SYNC 6 #define ARM_HARDEN_BRANCH_PREDICTOR 7 #define ARM_SSBD 8 +#define ARM_SMCCC_1_1 9 -#define ARM_NCAPS 9 +#define ARM_NCAPS 10 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 1ed6cbaa48..126399dd70 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#include +#include + #define SMCCC_VERSION_MAJOR_SHIFT 16 #define SMCCC_VERSION_MINOR_MASK \ ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) @@ -213,6 +216,7 @@ struct arm_smccc_res { */ #ifdef CONFIG_ARM_32 #define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) +#define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) #else void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, @@ -254,6 +258,13 @@ void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, #define arm_smccc_1_0_smc(...) \ __arm_smccc_1_0_smc_count(__count_args(__VA_ARGS__), __VA_ARGS__) +#define arm_smccc_smc(...) \ + do { \ + if ( cpus_have_const_cap(ARM_SMCCC_1_1) ) \ + arm_smccc_1_1_smc(__VA_ARGS__); \ + else \ + arm_smccc_1_0_smc(__VA_ARGS__); \ + } while ( 0 ) #endif /* CONFIG_ARM_64 */ #endif /* __ASSEMBLY__ */ From patchwork Tue Sep 25 17:20:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147517 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp987597lji; Tue, 25 Sep 2018 10:23:19 -0700 (PDT) X-Google-Smtp-Source: ACcGV613gEmNbXfzo3OfS7wYNih/s9ci0mDXFGhWENNoWOBp+frr6cZ/rMJSQTgP0nJTkYLruj8L X-Received: by 2002:a6b:ab87:: with SMTP id u129-v6mr1921474ioe.30.1537896199511; Tue, 25 Sep 2018 10:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537896199; cv=none; d=google.com; s=arc-20160816; b=Ftx/VifQk4p4lWtj0douGQxWzCewB4wZ0McPO7suODUeacVUgqFZIi3CbBHxi7UPGs e+WYeNzNEJXujPvnmUhsH56trJyUTYI5bIXboEqm8UyQ1/X1z1V0KYCX3wtfbsEUzgME kIp55r/u5+URhdYZhSpg+i+jd32e6KiuwKze1a8u9UsDoOjKqxIwQR90QEmcsk+iI/L4 iSo/DAd9QBPEzqTEQSDNAZQlGm7AwBWn5wu+LwhaKPf9+5lws80mVg9z6Xe0i9ZyYQl8 puOsb/bfCJrkzGRBEVUldriwsz0XGUNSM5ZSau/N7nhq+tQNUE4RnJrql6Y3Yxuv0rk9 Zycg== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id u12-v6si1725927ite.70.2018.09.25.10.23.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r1A-0004E8-C7; Tue, 25 Sep 2018 17:21:00 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r19-0004DN-8T for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:59 +0000 X-Inumbo-ID: 8510f6f1-c0e7-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 8510f6f1-c0e7-11e8-a6a9-d7ebe60f679a; Tue, 25 Sep 2018 17:22:03 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 882C97A9; Tue, 25 Sep 2018 10:20:57 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B28C3F5BD; Tue, 25 Sep 2018 10:20:56 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:43 +0100 Message-Id: <20180925172043.20248-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 6/6] xen/arm: Replace call_smc with arm_smccc_smc X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" call_smc is a subset of arm_smccc_smc. Rather than having 2 methods to do SMCCC call, replace all call to the former by the later. Signed-off-by: Julien Grall --- xen/arch/arm/Makefile | 1 - xen/arch/arm/platforms/exynos5.c | 3 ++- xen/arch/arm/platforms/seattle.c | 4 ++-- xen/arch/arm/psci.c | 37 +++++++++++++++++++++++++------------ xen/arch/arm/smc.S | 21 --------------------- xen/include/asm-arm/processor.h | 3 --- 6 files changed, 29 insertions(+), 40 deletions(-) delete mode 100644 xen/arch/arm/smc.S diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index b9b141dc84..37fa8268b3 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -39,7 +39,6 @@ obj-y += processor.o obj-y += psci.o obj-y += setup.o obj-y += shutdown.o -obj-y += smc.o obj-y += smp.o obj-y += smpboot.o obj-y += sysctl.o diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index c15ecf80f5..e2c0b7b878 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -26,6 +26,7 @@ #include #include #include +#include static bool secure_firmware; @@ -249,7 +250,7 @@ static int exynos5_cpu_up(int cpu) iounmap(power); if ( secure_firmware ) - call_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); + arm_smccc_smc(SMC_CMD_CPU1BOOT, cpu, NULL); return cpu_up_send_sgi(cpu); } diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seattle.c index 893cc17972..64cc1868c2 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initconst = */ static void seattle_system_reset(void) { - call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET, NULL); } static void seattle_system_off(void) { - call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF, NULL); } PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 941eec921b..02737e6caa 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -42,42 +42,53 @@ uint32_t smccc_ver; static uint32_t psci_cpu_on_nr; +#define PSCI_RET(res) ((int32_t)(res).a0) + int call_psci_cpu_on(int cpu) { - return call_smc(psci_cpu_on_nr, cpu_logical_map(cpu), __pa(init_secondary), 0); + struct arm_smccc_res res; + + arm_smccc_smc(psci_cpu_on_nr, cpu_logical_map(cpu), __pa(init_secondary), + &res); + + return (int32_t)res.a0; } void call_psci_cpu_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) { - int errno; + struct arm_smccc_res res; /* If successfull the PSCI cpu_off call doesn't return */ - errno = call_smc(PSCI_0_2_FN32_CPU_OFF, 0, 0, 0); + arm_smccc_smc(PSCI_0_2_FN32_CPU_OFF, &res); panic("PSCI cpu off failed for CPU%d err=%d\n", smp_processor_id(), - errno); + PSCI_RET(res)); } } void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF, NULL); } void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET, NULL); } static int __init psci_features(uint32_t psci_func_id) { + struct arm_smccc_res res; + if ( psci_ver < PSCI_VERSION(1, 0) ) return PSCI_NOT_SUPPORTED; - return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); + arm_smccc_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, NULL); + + return PSCI_RET(res); } static int __init psci_is_smc_method(const struct dt_device_node *psci) @@ -112,11 +123,11 @@ static void __init psci_init_smccc(void) if ( psci_features(ARM_SMCCC_VERSION_FID) != PSCI_NOT_SUPPORTED ) { - uint32_t ret; + struct arm_smccc_res res; - ret = call_smc(ARM_SMCCC_VERSION_FID, 0, 0, 0); - if ( ret != ARM_SMCCC_NOT_SUPPORTED ) - smccc_ver = ret; + arm_smccc_smc(ARM_SMCCC_VERSION_FID, &res); + if ( PSCI_RET(res) != ARM_SMCCC_NOT_SUPPORTED ) + smccc_ver = PSCI_RET(res); } if ( smccc_ver >= SMCCC_VERSION(1, 1) ) @@ -165,6 +176,7 @@ static int __init psci_init_0_2(void) { /* sentinel */ }, }; int ret; + struct arm_smccc_res res; if ( acpi_disabled ) { @@ -186,7 +198,8 @@ static int __init psci_init_0_2(void) } } - psci_ver = call_smc(PSCI_0_2_FN32_PSCI_VERSION, 0, 0, 0); + arm_smccc_smc(PSCI_0_2_FN32_PSCI_VERSION, &res); + psci_ver = PSCI_RET(res); /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ if ( psci_ver != PSCI_VERSION(0, 2) && PSCI_VERSION_MAJOR(psci_ver) != 1 ) diff --git a/xen/arch/arm/smc.S b/xen/arch/arm/smc.S deleted file mode 100644 index b8f182272a..0000000000 --- a/xen/arch/arm/smc.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * xen/arch/arm/smc.S - * - * Wrapper for Secure Monitors Calls - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -ENTRY(call_smc) - smc #0 - ret diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 222a02dd99..8016cf306f 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -812,9 +812,6 @@ void vcpu_regs_hyp_to_user(const struct vcpu *vcpu, void vcpu_regs_user_to_hyp(struct vcpu *vcpu, const struct vcpu_guest_core_regs *regs); -int call_smc(register_t function_id, register_t arg0, register_t arg1, - register_t arg2); - void do_trap_hyp_serror(struct cpu_user_regs *regs); void do_trap_guest_serror(struct cpu_user_regs *regs);