From patchwork Mon Oct 1 12:46:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147906 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3866676lji; Mon, 1 Oct 2018 05:49:02 -0700 (PDT) X-Google-Smtp-Source: ACcGV615tyh5j7PySVfc6AU7SyxeZTC98F1UjvC1VWli9Ul66KtTt3Um/o490fK/93g5uMcxO/ZL X-Received: by 2002:a24:1c04:: with SMTP id c4-v6mr3709807itc.77.1538398142037; Mon, 01 Oct 2018 05:49:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538398142; cv=none; d=google.com; s=arc-20160816; b=OUMfilpRpRm5qTEo0viUzydD4E4bNIOsqU4l7Tv3SUI+WA7ogGgQtmItx/yjuoEX6D 873qYThVkXm+wYNcetRUUe2BR7zMXjr1auakhK0i+pP2/FJk99jeY9+YEnUEmLFJiGCj T+PJeGA6ap6vGd59sVUBI+xyjElviVLtaZCE7lm4N379kEGhzv7KcxGGmuuSxxnNEpF4 AfQu+pU+CxHvezIoSU6PSXXvVf9zSScieWjiZI/8WhHH4DO+/BQ5Z0drErXEUSvauKlK +MfxqEj7wwZBNrAN9iX00kkpeoaoFSm9cENjFSVCH3AFshxiUBd2v1nRQZ2JdhfPUu4v q2Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=0FzYu6ry0Il5VNOAfNkLU4Vkt6fVWBoYaWfR0gQNY4Q=; b=aBK2U/DQn6XsEPV8kBVoB0NJDB2L+G7bY47qnWF/pUOQo0pISYjwvyyIkZUJK8/SS1 l08E77BndYwkDihnn0EO2LUEDGw4VhAlP/LBZbvnPR+RlcRuqfI0S5e1UvZCjDNh56tn +rECTC3oSBdFbAlpdzxgEUUrfxEuDAv/3NvGhtpJBlH41nmFtL7JWs2y5gDqZ9UD7D3Q BK46aT3aS6306d2m7UvePBSlPTRv2yedy8TWeMxSpiXuqA1O6Ll2nYXXRjcJFRw5rfnP e38zHmtv0PvcA5Q0qwA7aosrbxyLeR8ExhLG/Dk8mxJEKGLfEQElgW/sq+PsLPnV+fu/ R47g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e64-v6si7205084iof.263.2018.10.01.05.49.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 01 Oct 2018 05:49:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g6xbB-0008JG-Gs; Mon, 01 Oct 2018 12:46:53 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g6xbA-0008Il-7a for xen-devel@lists.xen.org; Mon, 01 Oct 2018 12:46:52 +0000 X-Inumbo-ID: 3bbc1b41-c578-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 3bbc1b41-c578-11e8-a6a9-d7ebe60f679a; Mon, 01 Oct 2018 12:48:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B8A11596; Mon, 1 Oct 2018 05:46:51 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.emea.arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 585153F5A0; Mon, 1 Oct 2018 05:46:50 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 1 Oct 2018 13:46:38 +0100 Message-Id: <20181001124639.22885-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181001124639.22885-1-julien.grall@arm.com> References: <20181001124639.22885-1-julien.grall@arm.com> Subject: [Xen-devel] [[PATCH v3] 3/4] xen/arm: smccc: Add wrapper to automatically select the calling convention X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Volodymyr Babchuk --- Changes in v3: - Add Stefano's and Volodymyr's reviewed-by Changes in v2: - Invert the condition - Add missing includes --- xen/arch/arm/psci.c | 4 ++++ xen/include/asm-arm/cpufeature.h | 3 ++- xen/include/asm-arm/smccc.h | 11 +++++++++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 3cf5ecf0f3..941eec921b 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -118,6 +119,9 @@ static void __init psci_init_smccc(void) smccc_ver = ret; } + if ( smccc_ver >= SMCCC_VERSION(1, 1) ) + cpus_set_cap(ARM_SMCCC_1_1); + printk(XENLOG_INFO "Using SMC Calling Convention v%u.%u\n", SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); } diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index c6cbc2ec84..2d82264427 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -44,8 +44,9 @@ #define SKIP_CTXT_SWITCH_SERROR_SYNC 6 #define ARM_HARDEN_BRANCH_PREDICTOR 7 #define ARM_SSBD 8 +#define ARM_SMCCC_1_1 9 -#define ARM_NCAPS 9 +#define ARM_NCAPS 10 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 1ed6cbaa48..126399dd70 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#include +#include + #define SMCCC_VERSION_MAJOR_SHIFT 16 #define SMCCC_VERSION_MINOR_MASK \ ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) @@ -213,6 +216,7 @@ struct arm_smccc_res { */ #ifdef CONFIG_ARM_32 #define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) +#define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) #else void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, @@ -254,6 +258,13 @@ void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, #define arm_smccc_1_0_smc(...) \ __arm_smccc_1_0_smc_count(__count_args(__VA_ARGS__), __VA_ARGS__) +#define arm_smccc_smc(...) \ + do { \ + if ( cpus_have_const_cap(ARM_SMCCC_1_1) ) \ + arm_smccc_1_1_smc(__VA_ARGS__); \ + else \ + arm_smccc_1_0_smc(__VA_ARGS__); \ + } while ( 0 ) #endif /* CONFIG_ARM_64 */ #endif /* __ASSEMBLY__ */