From patchwork Tue Aug 17 07:45:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AA54C4320A for ; Tue, 17 Aug 2021 07:46:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E26C60EBC for ; Tue, 17 Aug 2021 07:46:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238649AbhHQHqr (ORCPT ); Tue, 17 Aug 2021 03:46:47 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:47498 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238627AbhHQHqq (ORCPT ); Tue, 17 Aug 2021 03:46:46 -0400 X-UUID: fb60b2d7a8fa4cd9a547ff61193cda31-20210817 X-UUID: fb60b2d7a8fa4cd9a547ff61193cda31-20210817 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 301300522; Tue, 17 Aug 2021 15:46:08 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:07 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2, 01/12] dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC Date: Tue, 17 Aug 2021 15:45:46 +0800 Message-ID: <20210817074557.30953-2-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the binding documentation for topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Signed-off-by: Sam Shih Acked-by: Rob Herring --- v2: remove compatiable string 'mt7986-sgmiisys' --- .../devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 1 + .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++ .../devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 + 5 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index ea827e8763de..3fa755866528 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - "mediatek,mt7629-apmixedsys" + - "mediatek,mt7986-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 6b7e8067e7aa..0502db73686b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7629-ethsys", "syscon" + - "mediatek,mt7986-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index eb3523c7a7be..f66bd720571d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt7629-infracfg", "syscon" + - "mediatek,mt7986-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index 30cb645c0e54..29ca7a10b315 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -8,6 +8,8 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" - "mediatek,mt7629-sgmiisys", "syscon" + - "mediatek,mt7986-sgmiisys_0", "syscon" + - "mediatek,mt7986-sgmiisys_1", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 5ce7578cf274..b82422bb717f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -14,6 +14,7 @@ Required Properties: - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - "mediatek,mt7629-topckgen" + - "mediatek,mt7986-topckgen", "syscon" - "mediatek,mt8135-topckgen" - "mediatek,mt8167-topckgen", "syscon" - "mediatek,mt8173-topckgen" From patchwork Tue Aug 17 07:45:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82306C4320A for ; Tue, 17 Aug 2021 07:46:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6488660F41 for ; Tue, 17 Aug 2021 07:46:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238455AbhHQHq7 (ORCPT ); Tue, 17 Aug 2021 03:46:59 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:47712 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238627AbhHQHqx (ORCPT ); Tue, 17 Aug 2021 03:46:53 -0400 X-UUID: 1b42b9fe307c410291382c8dc4638a05-20210817 X-UUID: 1b42b9fe307c410291382c8dc4638a05-20210817 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 473499933; Tue, 17 Aug 2021 15:46:16 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:14 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2,03/12] clk: mediatek: add mt7986 clock support Date: Tue, 17 Aug 2021 15:45:48 +0800 Message-ID: <20210817074557.30953-4-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MT7986 clock support, include topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Signed-off-by: Sam Shih --- v2: applied the comment suggested by reviewers: - splited basic clock driver to apmixed, topckgen, and infracfg - removed 1:1 factor clock - renamed factor clock for easier to understand --- drivers/clk/mediatek/Kconfig | 17 ++ drivers/clk/mediatek/Makefile | 4 + drivers/clk/mediatek/clk-mt7986-apmixed.c | 78 +++++ drivers/clk/mediatek/clk-mt7986-eth.c | 132 +++++++++ drivers/clk/mediatek/clk-mt7986-infracfg.c | 198 +++++++++++++ drivers/clk/mediatek/clk-mt7986-topckgen.c | 319 +++++++++++++++++++++ 6 files changed, 748 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt7986-apmixed.c create mode 100644 drivers/clk/mediatek/clk-mt7986-eth.c create mode 100644 drivers/clk/mediatek/clk-mt7986-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt7986-topckgen.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 886e2d9fced5..28d8a07d5139 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS This driver supports MediaTek MT7629 HIFSYS clocks providing to PCI-E and USB. +config COMMON_CLK_MT7986 + bool "Clock driver for MediaTek MT7986" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK + help + This driver supports MediaTek MT7986 basic clocks and clocks + required for various periperals found on MediaTek. + +config COMMON_CLK_MT7986_ETHSYS + bool "Clock driver for MediaTek MT7986 ETHSYS" + depends on COMMON_CLK_MT7986 + default COMMON_CLK_MT7986 + help + This driver add support for clocks for Ethernet and SGMII + required on MediaTek MT7986 SoC. + config COMMON_CLK_MT8135 bool "Clock driver for MediaTek MT8135" depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3b0c2be73824..cab2b8764500 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o +obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o +obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o +obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c new file mode 100644 index 000000000000..0925d61b55f2 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-1.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +#define MT7986_PLL_FMAX (2500UL * MHZ) +#define CON0_MT7986_RST_BAR BIT(27) + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + _div_table, _parent_name) \ + { \ + .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, .flags = _flags, \ + .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \ + .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, .div_table = _div_table, \ + .parent_name = _parent_name, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ + "clkxtal") + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32, + 0x0200, 4, 0, 0x0204, 0), + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, + 0x0210, 4, 0, 0x0214, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, + 0x0220, 4, 0, 0x0224, 0), + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32, + 0x0230, 4, 0, 0x0234, 0), + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0, + 32, 0x0240, 4, 0, 0x0244, 0), + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32, + 0x0250, 4, 0, 0x0254, 0), + PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260, + 4, 0, 0x0264, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, + 0x0278, 4, 0, 0x027c, 0), +}; + +static void __init mtk_apmixedsys_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7986-apmixedsys", + mtk_apmixedsys_init); diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c new file mode 100644 index 000000000000..495d023ccad7 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs sgmii0_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii0_clks[] __initconst = { + GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), + GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), + GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), + GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5), +}; + +static const struct mtk_gate_regs sgmii1_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii1_clks[] __initconst = { + GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), + GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), + GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), + GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5), +}; + +static const struct mtk_gate_regs eth_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = ð_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate eth_clks[] __initconst = { + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), + GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), +}; + +static void __init mtk_sgmiisys_0_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); + + mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0", + mtk_sgmiisys_0_init); + +static void __init mtk_sgmiisys_1_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); + + mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1", + mtk_sgmiisys_1_init); + +static void __init mtk_ethsys_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); + + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init); diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/mediatek/clk-mt7986-infracfg.c new file mode 100644 index 000000000000..35e16c28966a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-1.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +static DEFINE_SPINLOCK(mt7986_clk_lock); + +static const struct mtk_fixed_factor infra_divs[] __initconst = { + FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2), +}; + +static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", + "uart_sel" }; + +static const char *const infra_spi_parents[] __initconst = { "i2c_sel", + "spi_sel" }; + +static const char *const infra_pwm_bsel_parents[] __initconst = { + "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel" +}; + +static const char *const infra_pcie_parents[] __initconst = { + "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel" +}; + +static const struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", + infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", + infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", + infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1, + -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, + 2, -1, -1, -1), + /* MODULE_CLK_SEL_1 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", + infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, + -1, -1, -1), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra2_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate infra_clks[] __initconst = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0), + GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1), + GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), + GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), + GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), + GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6), + GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7), + GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8), + GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), + GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10), + GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11), + GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13), + GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", + 14), + GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15), + GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16), + GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24), + GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), + GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), + GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1), + GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), + GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), + GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), + GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8), + GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9), + GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2", + 10), + GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), + GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), + GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2", + 13), + GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2", + 14), + GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15), + GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16), + GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel", + 17), + GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel", + 18), + GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2", + 19), + GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20), + GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21), + GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0), + GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2", + 1), + GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2), + GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3), + GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12), + GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal", + 13), + GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14), + GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15), +}; + +static void __init mtk_infracfg_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + + ARRAY_SIZE(infra_clks); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return; + } + + clk_data = mtk_alloc_clk_data(nr); + mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, + &mt7986_clk_lock, clk_data); + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt7986-infracfg", mtk_infracfg_init); diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c new file mode 100644 index 000000000000..0a376044d290 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-1.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih + * Author: Wenzhen Yu + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include +#include + +static DEFINE_SPINLOCK(mt7986_clk_lock); + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), + FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), +}; + +static const struct mtk_fixed_factor top_divs[] __initconst = { + /* XTAL */ + FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), + FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), + FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), + /* MPLL */ + FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), + FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), + FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), + FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), + /* MMPLL */ + FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), + FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), + FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), + FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), + FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), + /* APLL2 */ + FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), + /* NET1PLL */ + FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), + FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), + FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), + FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), + FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), + FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), + /* NET2PLL */ + FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), + FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), + FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), + /* WEDMCUPLL */ + FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, + 10), +}; + +static const char *const nfi1x_parents[] __initconst = { "top_xtal", + "top_mmpll_d8", + "top_net1pll_d8_d2", + "top_net2pll_d3_d2", + "top_mpll_d4", + "top_mmpll_d8_d2", + "top_wedmcupll_d5_d2", + "top_mpll_d8" }; + +static const char *const spinfi_parents[] __initconst = { + "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", + "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", + "top_mmpll_d3_d8", "top_mpll_d8" +}; + +static const char *const spi_parents[] __initconst = { + "top_xtal", "top_mpll_d2", "top_mmpll_d8", + "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", + "top_mpll_d4", "top_wedmcupll_d5_d2" +}; + +static const char *const uart_parents[] __initconst = { "top_xtal", + "top_mpll_d8", + "top_mpll_d8_d2" }; + +static const char *const pwm_parents[] __initconst = { + "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" +}; + +static const char *const i2c_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" +}; + +static const char *const pextp_tl_ck_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" +}; + +static const char *const emmc_250m_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d2" +}; + +static const char *const emmc_416m_parents[] __initconst = { "top_xtal", + "mpll" }; + +static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", + "top_mpll_d8_d2" }; + +static const char *const dramc_md32_parents[] __initconst = { "top_xtal", + "top_mpll_d2" }; + +static const char *const sysaxi_parents[] __initconst = { "top_xtal", + "top_net1pll_d8_d2", + "top_net2pll_d4" }; + +static const char *const sysapb_parents[] __initconst = { "top_xtal", + "top_mpll_d3_d2", + "top_net2pll_d4_d2" }; + +static const char *const arm_db_main_parents[] __initconst = { + "top_xtal", "top_net2pll_d3_d2" +}; + +static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", + "top_xtal" }; + +static const char *const netsys_parents[] __initconst = { "top_xtal", + "top_mmpll_d4" }; + +static const char *const netsys_500m_parents[] __initconst = { + "top_xtal", "top_net1pll_d5" +}; + +static const char *const netsys_mcu_parents[] __initconst = { + "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", + "top_net1pll_d5" +}; + +static const char *const netsys_2x_parents[] __initconst = { + "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" +}; + +static const char *const sgm_325m_parents[] __initconst = { "top_xtal", + "sgmpll" }; + +static const char *const sgm_reg_parents[] __initconst = { + "top_xtal", "top_net1pll_d8_d4" +}; + +static const char *const a1sys_parents[] __initconst = { "top_xtal", + "top_apll2_d4" }; + +static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", + "top_mmpll_d2" }; + +static const char *const eip_b_parents[] __initconst = { "top_xtal", + "net2pll" }; + +static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", + "top_mpll_d8_d2" }; + +static const char *const a_tuner_parents[] __initconst = { "top_xtal", + "top_apll2_d4", + "top_mpll_d8_d2" }; + +static const char *const u2u3_sys_parents[] __initconst = { + "top_xtal", "top_net1pll_d5_d4" +}; + +static const char *const da_u2_refsel_parents[] __initconst = { + "top_xtal", "top_mmpll_u2phy" +}; + +static const struct mtk_mux top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, + 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, + 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, + 0x004, 0x008, 16, 3, 23, 0x1C0, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, + 0x014, 0x018, 0, 2, 7, 0x1C0, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, + 0x014, 0x018, 8, 2, 15, 0x1C0, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, + 0x014, 0x018, 16, 2, 23, 0x1C0, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", + pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, + 31, 0x1C0, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", + emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, + 0x1C0, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", + emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, + 0x1C0, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", + f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, + 0x1C0, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, + 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, + 0x1C0, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, + 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, + 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", + arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, + 31, 0x1C0, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", + arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, + 0x1C0, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, + 23, 0x1C0, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", + netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, + 0x1C0, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", + netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, + 0x1C0, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", + sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, + 0x1C0, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", + sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, + 0x1C0, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", + conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, + 0x1C0, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, + 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", + f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, + 0x1C0, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", + f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, + 0x1C0, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", + f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, + 0x1C0, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", + a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, + 0x1C0, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, + 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", + u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, + 0x1C4, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", + u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, + 0x1C4, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", + da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, + 23, 0x1C4, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", + da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, + 31, 0x1C4, 4), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", + sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, + 0x1C4, 5), +}; + +static void __init mtk_topckgen_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + + ARRAY_SIZE(top_muxes); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return; + } + + clk_data = mtk_alloc_clk_data(nr); + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, + &mt7986_clk_lock, clk_data); + + clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]); + clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); +} +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7986-topckgen", mtk_topckgen_init); From patchwork Tue Aug 17 07:45:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99165C4320A for ; Tue, 17 Aug 2021 07:46:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 84E8C60F5E for ; Tue, 17 Aug 2021 07:46:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238951AbhHQHrF (ORCPT ); Tue, 17 Aug 2021 03:47:05 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:49282 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234779AbhHQHrA (ORCPT ); Tue, 17 Aug 2021 03:47:00 -0400 X-UUID: 1576c2985ca245b4873d502c9a261f40-20210817 X-UUID: 1576c2985ca245b4873d502c9a261f40-20210817 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 161453402; Tue, 17 Aug 2021 15:46:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:21 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2,05/12] dt-bindings: pinctrl: update bindings for MT7986 SoC Date: Tue, 17 Aug 2021 15:45:50 +0800 Message-ID: <20210817074557.30953-6-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This updates bindings for MT7986 pinctrl driver. The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih --- v2 : deleted the redundant description of mt7986a/mt7986b --- .../bindings/pinctrl/pinctrl-mt7622.txt | 170 ++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt index 7a7aca1ed705..4711dfb2ea77 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt @@ -4,6 +4,8 @@ Required properties for the root node: - compatible: Should be one of the following "mediatek,mt7622-pinctrl" for MT7622 SoC "mediatek,mt7629-pinctrl" for MT7629 SoC + "mediatek,mt7986a-pinctrl" for MT7986a SoC + "mediatek,mt7986b-pinctrl" for MT7986b SoC - reg: offset and length of the pinctrl space - gpio-controller: Marks the device node as a GPIO controller. @@ -455,6 +457,174 @@ Valid values for groups are: "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 +== Valid values for pins, function and groups on MT7986a and MT7986b == + +Valid values for pins are: +pins can be referenced via the pin names as the below table shown and the +related physical number is also put ahead of those names which helps cross +references to pins between groups to know whether pins assignment conflict +happens among devices try to acquire those available pins. + + Pin #: Valid values for pins + ----------------------------- + PIN 0: "SYS_WATCHDOG" + PIN 1: "WF2G_LED" + PIN 2: "WF5G_LED" + PIN 3: "I2C_SCL" + PIN 4: "I2C_SDA" + PIN 5: "GPIO_0" + PIN 6: "GPIO_1" + PIN 7: "GPIO_2" + PIN 8: "GPIO_3" + PIN 9: "GPIO_4" + PIN 10: "GPIO_5" + PIN 11: "GPIO_6" + PIN 12: "GPIO_7" + PIN 13: "GPIO_8" + PIN 14: "GPIO_9" + PIN 15: "GPIO_10" + PIN 16: "GPIO_11" + PIN 17: "GPIO_12" + PIN 18: "GPIO_13" + PIN 19: "GPIO_14" + PIN 20: "GPIO_15" + PIN 21: "PWM0" + PIN 22: "PWM1" + PIN 23: "SPI0_CLK" + PIN 24: "SPI0_MOSI" + PIN 25: "SPI0_MISO" + PIN 26: "SPI0_CS" + PIN 27: "SPI0_HOLD" + PIN 28: "SPI0_WP" + PIN 29: "SPI1_CLK" + PIN 30: "SPI1_MOSI" + PIN 31: "SPI1_MISO" + PIN 32: "SPI1_CS" + PIN 33: "SPI2_CLK" + PIN 34: "SPI2_MOSI" + PIN 35: "SPI2_MISO" + PIN 36: "SPI2_CS" + PIN 37: "SPI2_HOLD" + PIN 38: "SPI2_WP" + PIN 39: "UART0_RXD" + PIN 40: "UART0_TXD" + PIN 41: "PCIE_PERESET_N" + PIN 42: "UART1_RXD" + PIN 43: "UART1_TXD" + PIN 44: "UART1_CTS" + PIN 45: "UART1_RTS" + PIN 46: "UART2_RXD" + PIN 47: "UART2_TXD" + PIN 48: "UART2_CTS" + PIN 49: "UART2_RTS" + PIN 50: "EMMC_DATA_0" + PIN 51: "EMMC_DATA_1" + PIN 52: "EMMC_DATA_2" + PIN 53: "EMMC_DATA_3" + PIN 54: "EMMC_DATA_4" + PIN 55: "EMMC_DATA_5" + PIN 56: "EMMC_DATA_6" + PIN 57: "EMMC_DATA_7" + PIN 58: "EMMC_CMD" + PIN 59: "EMMC_CK" + PIN 60: "EMMC_DSL" + PIN 61: "EMMC_RSTB" + PIN 62: "PCM_DTX" + PIN 63: "PCM_DRX" + PIN 64: "PCM_CLK" + PIN 65: "PCM_FS" + PIN 66: "MT7531_INT" + PIN 67: "SMI_MDC" + PIN 68: "SMI_MDIO" + PIN 69: "WF0_DIG_RESETB" + PIN 70: "WF0_CBA_RESETB" + PIN 71: "WF0_XO_REQ" + PIN 72: "WF0_TOP_CLK" + PIN 73: "WF0_TOP_DATA" + PIN 74: "WF0_HB1" + PIN 75: "WF0_HB2" + PIN 76: "WF0_HB3" + PIN 77: "WF0_HB4" + PIN 78: "WF0_HB0" + PIN 79: "WF0_HB0_B" + PIN 80: "WF0_HB5" + PIN 81: "WF0_HB6" + PIN 82: "WF0_HB7" + PIN 83: "WF0_HB8" + PIN 84: "WF0_HB9" + PIN 85: "WF0_HB10" + PIN 86: "WF1_DIG_RESETB" + PIN 87: "WF1_CBA_RESETB" + PIN 88: "WF1_XO_REQ" + PIN 89: "WF1_TOP_CLK" + PIN 90: "WF1_TOP_DATA" + PIN 91: "WF1_HB1" + PIN 92: "WF1_HB2" + PIN 93: "WF1_HB3" + PIN 94: "WF1_HB4" + PIN 95: "WF1_HB0" + PIN 96: "WF1_HB0_B" + PIN 97: "WF1_HB5" + PIN 98: "WF1_HB6" + PIN 99: "WF1_HB7" + PIN 100: "WF1_HB8" + +There is no PIN 41 to PIN 65 above on mt7686b, you can only use those +pins on mt7986a. + +Valid values for function are: + "audio, "emmc", "eth", "i2c", "wifi", "led", "flash", "pcie", + "pwm", "spi", "uart", "watchdog" + +There is no "audio", "pcie" functions above on mt7986b, you can only +use those functions on mt7986a. + +Valid values for groups are: +additional data is put followingly with valid value allowing us to know which +applicable function and which relevant pins (in pin#) are able applied for that +group. + + Valid value function pins (in pin#) + ------------------------------------------------------------------------- + "watchdog" "watchdog" 0 + "wifi_led" "led" 1, 2 + "i2c" "i2c" 3, 4 + "uart1_0" "uart" 7, 8, 9, 10 + "pcie_clk" "pcie" 9 + "pcie_wake" "pcie" 10 + "spi1_0" "spi" 11, 12, 13, 14 + "pwm1_1" "pwm" 20, + "pwm0" "pwm" 21, + "pwm1_0" "pwm" 22, + "snfi" "flash" 23, 24, 25, 26, 27, 28 + "spi1_2" "spi" 29, 30, 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32 + "spi1_1" "spi" 23, 24, 25, 26 + "uart1_2" "uart" 29, 30, 31, 32 + "uart1_1" "uart" 23, 24, 25, 26 + "uart2_0" "uart" 29, 30, 31, 32 + "spi0" "spi" 33, 34, 35, 36 + "spi0_wp_hold" "spi" 37, 38 + "uart1_3_rx_tx" "uart" 35, 36 + "uart1_3_cts_rts" "uart" 37, 38 + "uart2_1" "uart" 33, 34, 35, 36 + "spi1_3" "spi" 33, 34, 35, 36 + "uart0" "uart" 39, 40 + "pcie_pereset" "pcie" 41 + "uart1" "uart" 42, 43, 44, 45 + "uart2" "uart" 46, 47, 48, 49 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, + 56, 57, 57, 59, 60, 61 + "pcm" "audio" 62, 63, 64, 65 + "i2s" "audio" 62, 63, 64, 65 + "switch_int" "eth" 66 + "mdc_mdio" "eth" 67 + +There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and "i2s" groups +above on mt7986b, you can only use those groups on mt7986a. + + Example: pio: pinctrl@10211000 { From patchwork Tue Aug 17 07:45:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86C48C43216 for ; Tue, 17 Aug 2021 07:46:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 679EA60FA0 for ; Tue, 17 Aug 2021 07:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239122AbhHQHrY (ORCPT ); Tue, 17 Aug 2021 03:47:24 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:49496 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238932AbhHQHrI (ORCPT ); Tue, 17 Aug 2021 03:47:08 -0400 X-UUID: 6a52e664a3cd4481ae5920f794536755-20210817 X-UUID: 6a52e664a3cd4481ae5920f794536755-20210817 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1263032662; Tue, 17 Aug 2021 15:46:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:24 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2,06/12] pinctrl: mediatek: add support for MT7986 SoC Date: Tue, 17 Aug 2021 15:45:51 +0800 Message-ID: <20210817074557.30953-7-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit includes pinctrl driver for Mediatek MT7986 The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by: Sam Shih --- v2: applied the comment suggested by reviewers: - for the pins not ballout, we can fill .name in struct mtk_pin_desc as NULL and return -ENOTSUPP in gpio/pinconf ops. --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1217 +++++++++++++++++++++ 3 files changed, 1225 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 7040a7a7bd5d..66db4ac5d169 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -119,6 +119,13 @@ config PINCTRL_MT7622 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT7986 + bool "Mediatek MT7986 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + config PINCTRL_MT8167 bool "Mediatek MT8167 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 1bb7f9c65bc2..1e3931d924e7 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c new file mode 100644 index 000000000000..808ae4e03eb2 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -0,0 +1,1217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7986 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) +#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number } + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +/** + * enum - Locking variants of the iocfg bases + * + * MT7986 have multiple bases to program pin configuration listed as the below: + * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, + * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, + * _i_based could be used to indicate what base the pin should be mapped into. + * + * Each iocfg register base control different group of pads on the SoC + * + * + * chip carrier + * + * A B C D E F G H + * +------------------------+ + * 8 | o o o o o o o o | + * 7 | o o o o o o o o | + * 6 | o o o o o o o o | + * 5 | o o o o o o o o | + * 4 | o o o o o o o o | + * 3 | o o o o o o o o | + * 2 | o o o o o o o o | + * 1 | o o o o o o o o | + * +------------------------+ + * + * inside Chip carrier + * + * A B C D E F G H + * +------------------------+ + * 8 | | + * 7 | TL TR | + * 6 | +---------+ | + * 5 | LT | | RT | + * 4 | | | | + * 3 | LB | | RB | + * 2 | +---------+ | + * 1 | | + * +------------------------+ + * + */ + +enum { + GPIO_BASE, + IOCFG_RT_BASE, + IOCFG_RB_BASE, + IOCFG_LT_BASE, + IOCFG_LB_BASE, + IOCFG_TR_BASE, + IOCFG_TL_BASE, +}; + +static const char *const mt7986_pinctrl_register_base_names[] = { + "gpio_base", "iocfg_rt_base", "iocfg_rb_base", "iocfg_lt_base", + "iocfg_lb_base", "iocfg_tr_base", "iocfg_tl_base", +}; + +static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = { + PIN_FIELD(0, 40, 0x300, 0x10, 0, 4), + PIN_FIELD(41, 65, 0x350, 0x10, 4, 4), + PIN_FIELD(66, 68, 0x380, 0x10, 8, 4), + PIN_FIELD(69, 100, 0x380, 0x10, 20, 4), +}; + +static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = { + PIN_FIELD(0, 40, 0x0, 0x10, 0, 1), + PIN_FIELD(41, 65, 0x10, 0x10, 9, 1), + PIN_FIELD(66, 68, 0x20, 0x10, 2, 1), + PIN_FIELD(69, 100, 0x20, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_di_range[] = { + PIN_FIELD(0, 40, 0x200, 0x10, 0, 1), + PIN_FIELD(41, 65, 0x210, 0x10, 9, 1), + PIN_FIELD(66, 68, 0x220, 0x10, 2, 1), + PIN_FIELD(69, 100, 0x220, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_do_range[] = { + PIN_FIELD(0, 40, 0x100, 0x10, 0, 1), + PIN_FIELD(41, 65, 0x110, 0x10, 9, 1), + PIN_FIELD(66, 68, 0x120, 0x10, 2, 1), + PIN_FIELD(69, 100, 0x120, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x30, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x30, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x40, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x40, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x40, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x40, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x40, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x40, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x30, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0xf0, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0xf0, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0xf0, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0xf0, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0xf0, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0xf0, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0xf0, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0xf0, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0xf0, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0xc0, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0xc0, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0xc0, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xf0, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xf0, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xf0, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xf0, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xf0, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0xc0, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0xc0, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0xc0, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x80, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x80, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x70, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = { + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x50, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = { + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x40, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x00, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x00, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x20, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x20, 0x10, 6, 3), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x20, 0x10, 24, 3), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x20, 0x10, 18, 3), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x00, 0x10, 2, 3), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x00, 0x10, 5, 3), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x00, 0x10, 8, 3), + PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x10, 0x10, 2, 3), + PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x10, 0x10, 5, 3), +}; + +static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x60, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x40, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x40, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x60, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x60, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x60, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x60, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x60, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x70, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x50, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x50, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x50, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x80, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x80, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x80, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x80, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x80, 0x10, 7, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x60, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x60, 0x10, 14, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x60, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x60, 0x10, 19, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x60, 0x10, 20, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1), + PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x80, 0x10, 19, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x80, 0x10, 22, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x80, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x80, 0x10, 26, 1), + PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), + PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x80, 0x10, 24, 1), + PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), + PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x60, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x60, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x60, 0x10, 10, 1), + PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1), + PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), +}; + +static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7986a_pins[] = { + MT7986_PIN(0, "SYS_WATCHDOG"), + MT7986_PIN(1, "WF2G_LED"), + MT7986_PIN(2, "WF5G_LED"), + MT7986_PIN(3, "I2C_SCL"), + MT7986_PIN(4, "I2C_SDA"), + MT7986_PIN(5, "GPIO_0"), + MT7986_PIN(6, "GPIO_1"), + MT7986_PIN(7, "GPIO_2"), + MT7986_PIN(8, "GPIO_3"), + MT7986_PIN(9, "GPIO_4"), + MT7986_PIN(10, "GPIO_5"), + MT7986_PIN(11, "GPIO_6"), + MT7986_PIN(12, "GPIO_7"), + MT7986_PIN(13, "GPIO_8"), + MT7986_PIN(14, "GPIO_9"), + MT7986_PIN(15, "GPIO_10"), + MT7986_PIN(16, "GPIO_11"), + MT7986_PIN(17, "GPIO_12"), + MT7986_PIN(18, "GPIO_13"), + MT7986_PIN(19, "GPIO_14"), + MT7986_PIN(20, "GPIO_15"), + MT7986_PIN(21, "PWM0"), + MT7986_PIN(22, "PWM1"), + MT7986_PIN(23, "SPI0_CLK"), + MT7986_PIN(24, "SPI0_MOSI"), + MT7986_PIN(25, "SPI0_MISO"), + MT7986_PIN(26, "SPI0_CS"), + MT7986_PIN(27, "SPI0_HOLD"), + MT7986_PIN(28, "SPI0_WP"), + MT7986_PIN(29, "SPI1_CLK"), + MT7986_PIN(30, "SPI1_MOSI"), + MT7986_PIN(31, "SPI1_MISO"), + MT7986_PIN(32, "SPI1_CS"), + MT7986_PIN(33, "SPI2_CLK"), + MT7986_PIN(34, "SPI2_MOSI"), + MT7986_PIN(35, "SPI2_MISO"), + MT7986_PIN(36, "SPI2_CS"), + MT7986_PIN(37, "SPI2_HOLD"), + MT7986_PIN(38, "SPI2_WP"), + MT7986_PIN(39, "UART0_RXD"), + MT7986_PIN(40, "UART0_TXD"), + MT7986_PIN(41, "PCIE_PERESET_N"), + MT7986_PIN(42, "UART1_RXD"), + MT7986_PIN(43, "UART1_TXD"), + MT7986_PIN(44, "UART1_CTS"), + MT7986_PIN(45, "UART1_RTS"), + MT7986_PIN(46, "UART2_RXD"), + MT7986_PIN(47, "UART2_TXD"), + MT7986_PIN(48, "UART2_CTS"), + MT7986_PIN(49, "UART2_RTS"), + MT7986_PIN(50, "EMMC_DATA_0"), + MT7986_PIN(51, "EMMC_DATA_1"), + MT7986_PIN(52, "EMMC_DATA_2"), + MT7986_PIN(53, "EMMC_DATA_3"), + MT7986_PIN(54, "EMMC_DATA_4"), + MT7986_PIN(55, "EMMC_DATA_5"), + MT7986_PIN(56, "EMMC_DATA_6"), + MT7986_PIN(57, "EMMC_DATA_7"), + MT7986_PIN(58, "EMMC_CMD"), + MT7986_PIN(59, "EMMC_CK"), + MT7986_PIN(60, "EMMC_DSL"), + MT7986_PIN(61, "EMMC_RSTB"), + MT7986_PIN(62, "PCM_DTX"), + MT7986_PIN(63, "PCM_DRX"), + MT7986_PIN(64, "PCM_CLK"), + MT7986_PIN(65, "PCM_FS"), + MT7986_PIN(66, "MT7531_INT"), + MT7986_PIN(67, "SMI_MDC"), + MT7986_PIN(68, "SMI_MDIO"), + MT7986_PIN(69, "WF0_DIG_RESETB"), + MT7986_PIN(70, "WF0_CBA_RESETB"), + MT7986_PIN(71, "WF0_XO_REQ"), + MT7986_PIN(72, "WF0_TOP_CLK"), + MT7986_PIN(73, "WF0_TOP_DATA"), + MT7986_PIN(74, "WF0_HB1"), + MT7986_PIN(75, "WF0_HB2"), + MT7986_PIN(76, "WF0_HB3"), + MT7986_PIN(77, "WF0_HB4"), + MT7986_PIN(78, "WF0_HB0"), + MT7986_PIN(79, "WF0_HB0_B"), + MT7986_PIN(80, "WF0_HB5"), + MT7986_PIN(81, "WF0_HB6"), + MT7986_PIN(82, "WF0_HB7"), + MT7986_PIN(83, "WF0_HB8"), + MT7986_PIN(84, "WF0_HB9"), + MT7986_PIN(85, "WF0_HB10"), + MT7986_PIN(86, "WF1_DIG_RESETB"), + MT7986_PIN(87, "WF1_CBA_RESETB"), + MT7986_PIN(88, "WF1_XO_REQ"), + MT7986_PIN(89, "WF1_TOP_CLK"), + MT7986_PIN(90, "WF1_TOP_DATA"), + MT7986_PIN(91, "WF1_HB1"), + MT7986_PIN(92, "WF1_HB2"), + MT7986_PIN(93, "WF1_HB3"), + MT7986_PIN(94, "WF1_HB4"), + MT7986_PIN(95, "WF1_HB0"), + MT7986_PIN(96, "WF1_HB0_B"), + MT7986_PIN(97, "WF1_HB5"), + MT7986_PIN(98, "WF1_HB6"), + MT7986_PIN(99, "WF1_HB7"), + MT7986_PIN(100, "WF1_HB8"), +}; + +static const struct mtk_pin_desc mt7986b_pins[] = { + MT7986_PIN(0, "SYS_WATCHDOG"), + MT7986_PIN(1, "WF2G_LED"), + MT7986_PIN(2, "WF5G_LED"), + MT7986_PIN(3, "I2C_SCL"), + MT7986_PIN(4, "I2C_SDA"), + MT7986_PIN(5, "GPIO_0"), + MT7986_PIN(6, "GPIO_1"), + MT7986_PIN(7, "GPIO_2"), + MT7986_PIN(8, "GPIO_3"), + MT7986_PIN(9, "GPIO_4"), + MT7986_PIN(10, "GPIO_5"), + MT7986_PIN(11, "GPIO_6"), + MT7986_PIN(12, "GPIO_7"), + MT7986_PIN(13, "GPIO_8"), + MT7986_PIN(14, "GPIO_9"), + MT7986_PIN(15, "GPIO_10"), + MT7986_PIN(16, "GPIO_11"), + MT7986_PIN(17, "GPIO_12"), + MT7986_PIN(18, "GPIO_13"), + MT7986_PIN(19, "GPIO_14"), + MT7986_PIN(20, "GPIO_15"), + MT7986_PIN(21, "PWM0"), + MT7986_PIN(22, "PWM1"), + MT7986_PIN(23, "SPI0_CLK"), + MT7986_PIN(24, "SPI0_MOSI"), + MT7986_PIN(25, "SPI0_MISO"), + MT7986_PIN(26, "SPI0_CS"), + MT7986_PIN(27, "SPI0_HOLD"), + MT7986_PIN(28, "SPI0_WP"), + MT7986_PIN(29, "SPI1_CLK"), + MT7986_PIN(30, "SPI1_MOSI"), + MT7986_PIN(31, "SPI1_MISO"), + MT7986_PIN(32, "SPI1_CS"), + MT7986_PIN(33, "SPI2_CLK"), + MT7986_PIN(34, "SPI2_MOSI"), + MT7986_PIN(35, "SPI2_MISO"), + MT7986_PIN(36, "SPI2_CS"), + MT7986_PIN(37, "SPI2_HOLD"), + MT7986_PIN(38, "SPI2_WP"), + MT7986_PIN(39, "UART0_RXD"), + MT7986_PIN(40, "UART0_TXD"), + MT7986_NOT_BALLOUT_PIN(41), + MT7986_NOT_BALLOUT_PIN(42), + MT7986_NOT_BALLOUT_PIN(43), + MT7986_NOT_BALLOUT_PIN(44), + MT7986_NOT_BALLOUT_PIN(45), + MT7986_NOT_BALLOUT_PIN(46), + MT7986_NOT_BALLOUT_PIN(47), + MT7986_NOT_BALLOUT_PIN(48), + MT7986_NOT_BALLOUT_PIN(49), + MT7986_NOT_BALLOUT_PIN(50), + MT7986_NOT_BALLOUT_PIN(51), + MT7986_NOT_BALLOUT_PIN(52), + MT7986_NOT_BALLOUT_PIN(53), + MT7986_NOT_BALLOUT_PIN(54), + MT7986_NOT_BALLOUT_PIN(55), + MT7986_NOT_BALLOUT_PIN(56), + MT7986_NOT_BALLOUT_PIN(57), + MT7986_NOT_BALLOUT_PIN(58), + MT7986_NOT_BALLOUT_PIN(59), + MT7986_NOT_BALLOUT_PIN(60), + MT7986_NOT_BALLOUT_PIN(61), + MT7986_NOT_BALLOUT_PIN(62), + MT7986_NOT_BALLOUT_PIN(63), + MT7986_NOT_BALLOUT_PIN(64), + MT7986_NOT_BALLOUT_PIN(65), + MT7986_PIN(66, "MT7531_INT"), + MT7986_PIN(67, "SMI_MDC"), + MT7986_PIN(68, "SMI_MDIO"), + MT7986_PIN(69, "WF0_DIG_RESETB"), + MT7986_PIN(70, "WF0_CBA_RESETB"), + MT7986_PIN(71, "WF0_XO_REQ"), + MT7986_PIN(72, "WF0_TOP_CLK"), + MT7986_PIN(73, "WF0_TOP_DATA"), + MT7986_PIN(74, "WF0_HB1"), + MT7986_PIN(75, "WF0_HB2"), + MT7986_PIN(76, "WF0_HB3"), + MT7986_PIN(77, "WF0_HB4"), + MT7986_PIN(78, "WF0_HB0"), + MT7986_PIN(79, "WF0_HB0_B"), + MT7986_PIN(80, "WF0_HB5"), + MT7986_PIN(81, "WF0_HB6"), + MT7986_PIN(82, "WF0_HB7"), + MT7986_PIN(83, "WF0_HB8"), + MT7986_PIN(84, "WF0_HB9"), + MT7986_PIN(85, "WF0_HB10"), + MT7986_PIN(86, "WF1_DIG_RESETB"), + MT7986_PIN(87, "WF1_CBA_RESETB"), + MT7986_PIN(88, "WF1_XO_REQ"), + MT7986_PIN(89, "WF1_TOP_CLK"), + MT7986_PIN(90, "WF1_TOP_DATA"), + MT7986_PIN(91, "WF1_HB1"), + MT7986_PIN(92, "WF1_HB2"), + MT7986_PIN(93, "WF1_HB3"), + MT7986_PIN(94, "WF1_HB4"), + MT7986_PIN(95, "WF1_HB0"), + MT7986_PIN(96, "WF1_HB0_B"), + MT7986_PIN(97, "WF1_HB5"), + MT7986_PIN(98, "WF1_HB6"), + MT7986_PIN(99, "WF1_HB7"), + MT7986_PIN(100, "WF1_HB8"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +static int mt7986_watchdog_pins[] = { 0, }; +static int mt7986_watchdog_funcs[] = { 1, }; + +static int mt7986_wifi_led_pins[] = { 1, 2, }; +static int mt7986_wifi_led_funcs[] = { 1, 1, }; + +static int mt7986_i2c_pins[] = { 3, 4, }; +static int mt7986_i2c_funcs[] = { 1, 1, }; + +static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; +static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; +static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_pwm1_1_pins[] = { 20, }; +static int mt7986_pwm1_1_funcs[] = { 2, }; + +static int mt7986_pwm0_pins[] = { 21, }; +static int mt7986_pwm0_funcs[] = { 1, }; + +static int mt7986_pwm1_0_pins[] = { 22, }; +static int mt7986_pwm1_0_funcs[] = { 1, }; + +static int mt7986_emmc_45_pins[] = { + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; +static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; +static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; + +static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; +static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; +static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; +static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; +static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; +static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; +static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; +static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; + +static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; +static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; + +static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; +static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; + +static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; +static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; + +static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; +static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; + +static int mt7986_uart0_pins[] = { 39, 40, }; +static int mt7986_uart0_funcs[] = { 1, 1, }; + +static int mt7986_pcie_reset_pins[] = { 41, }; +static int mt7986_pcie_reset_funcs[] = { 1, }; + +static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; +static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; +static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_emmc_51_pins[] = { + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; +static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; +static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; +static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; + +static int mt7986_switch_int_pins[] = { 66, }; +static int mt7986_switch_int_funcs[] = { 1, }; + +static int mt7986_mdc_mdio_pins[] = { 67, 68, }; +static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; + +static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; +static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; +static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static int mt7986_wf_dbdc_pins[] = { + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; +static int mt7986_wf_dbdc_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7986_pcie_clk_pins[] = { 9, }; +static int mt7986_pcie_clk_funcs[] = { 1, }; + +static int mt7986_pcie_wake_pins[] = { 10, }; +static int mt7986_pcie_wake_funcs[] = { 1, }; + +static const struct group_desc mt7986_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), + PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), + PINCTRL_PIN_GROUP("i2c", mt7986_i2c), + PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), + PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), + PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), + PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), + PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1), + PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0), + PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0), + PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45), + PINCTRL_PIN_GROUP("snfi", mt7986_snfi), + PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), + PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), + PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), + PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), + PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), + PINCTRL_PIN_GROUP("spi0", mt7986_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), + PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), + PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx), + PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts), + PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3), + PINCTRL_PIN_GROUP("uart0", mt7986_uart0), + PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int), + PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio), + PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset), + PINCTRL_PIN_GROUP("uart1", mt7986_uart1), + PINCTRL_PIN_GROUP("uart2", mt7986_uart2), + PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51), + PINCTRL_PIN_GROUP("pcm", mt7986_pcm), + PINCTRL_PIN_GROUP("i2s", mt7986_i2s), + PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g), + PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g), + PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ + +static const char *mt7986_audio_groups[] = { "pcm", "i2s" }; +static const char *mt7986_emmc_groups[] = { "emmc_45", "emmc_51", }; +static const char *mt7986_ethernet_groups[] = { "switch_int", "mdc_mdio", }; +static const char *mt7986_i2c_groups[] = { "i2c", }; +static const char *mt7986_led_groups[] = { "wifi_led", }; +static const char *mt7986_flash_groups[] = { "snfi", }; +static const char *mt7986_pcie_groups[] = { + "pcie_clk", "pcie_wake", "pcie_pereset" }; +static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; +static const char *mt7986_spi_groups[] = { + "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; + +static const char *mt7986_uart_groups[] = { + "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", + "uart2_0", "uart2_1", "uart0", "uart1", "uart2", +}; +static const char *mt7986_wdt_groups[] = { "watchdog", }; +static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", }; + +static const struct function_desc mt7986_functions[] = { + {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)}, + {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)}, + {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)}, + {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)}, + {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)}, + {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)}, + {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)}, + {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)}, + {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)}, + {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)}, + {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)}, + {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, +}; + +static const struct mtk_eint_hw mt7986a_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7986a_pins), + .db_cnt = 16, +}; + +static const struct mtk_eint_hw mt7986b_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7986b_pins), + .db_cnt = 16, +}; + +static struct mtk_pin_soc mt7986a_data = { + .reg_cal = mt7986_reg_cals, + .pins = mt7986a_pins, + .npins = ARRAY_SIZE(mt7986a_pins), + .grps = mt7986_groups, + .ngrps = ARRAY_SIZE(mt7986_groups), + .funcs = mt7986_functions, + .nfuncs = ARRAY_SIZE(mt7986_functions), + .eint_hw = &mt7986a_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static struct mtk_pin_soc mt7986b_data = { + .reg_cal = mt7986_reg_cals, + .pins = mt7986b_pins, + .npins = ARRAY_SIZE(mt7986b_pins), + .grps = mt7986_groups, + .ngrps = ARRAY_SIZE(mt7986_groups), + .funcs = mt7986_functions, + .nfuncs = ARRAY_SIZE(mt7986_functions), + .eint_hw = &mt7986b_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7986_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7986a_pinctrl_of_match[] = { + {.compatible = "mediatek,mt7986a-pinctrl",}, + {} +}; + +static const struct of_device_id mt7986b_pinctrl_of_match[] = { + {.compatible = "mediatek,mt7986b-pinctrl",}, + {} +}; + +static int mt7986a_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7986a_data); +} + +static int mt7986b_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7986b_data); +} + +static struct platform_driver mt7986a_pinctrl_driver = { + .driver = { + .name = "mt7986a-pinctrl", + .of_match_table = mt7986a_pinctrl_of_match, + }, + .probe = mt7986a_pinctrl_probe, +}; + +static struct platform_driver mt7986b_pinctrl_driver = { + .driver = { + .name = "mt7986b-pinctrl", + .of_match_table = mt7986b_pinctrl_of_match, + }, + .probe = mt7986b_pinctrl_probe, +}; + +static int __init mt7986a_pinctrl_init(void) +{ + return platform_driver_register(&mt7986a_pinctrl_driver); +} + +static int __init mt7986b_pinctrl_init(void) +{ + return platform_driver_register(&mt7986b_pinctrl_driver); +} + +arch_initcall(mt7986a_pinctrl_init); +arch_initcall(mt7986b_pinctrl_init); From patchwork Tue Aug 17 07:45:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC83EC43214 for ; Tue, 17 Aug 2021 07:46:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9343360FA0 for ; Tue, 17 Aug 2021 07:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234865AbhHQHr1 (ORCPT ); Tue, 17 Aug 2021 03:47:27 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:49608 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S238955AbhHQHrJ (ORCPT ); Tue, 17 Aug 2021 03:47:09 -0400 X-UUID: 64c792a303cd4805909b423755a85ad9-20210817 X-UUID: 64c792a303cd4805909b423755a85ad9-20210817 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1428143285; Tue, 17 Aug 2021 15:46:31 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:29 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2, 08/12] dt-bindings: rng: mediatek: add mt7986 to mtk rng binding Date: Tue, 17 Aug 2021 15:45:53 +0800 Message-ID: <20210817074557.30953-9-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add RNG binding for MT7986 SoC. Signed-off-by: Sam Shih --- v2: patch v1 has been applied --- Documentation/devicetree/bindings/rng/mtk-rng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml index 61888e07bda0..bb32491ee8ae 100644 --- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml @@ -21,6 +21,7 @@ properties: - enum: - mediatek,mt7622-rng - mediatek,mt7629-rng + - mediatek,mt7986-rng - mediatek,mt8365-rng - mediatek,mt8516-rng - const: mediatek,mt7623-rng From patchwork Tue Aug 17 07:45:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 498237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37E4EC25AE8 for ; Tue, 17 Aug 2021 07:46:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BDB060FA0 for ; Tue, 17 Aug 2021 07:46:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239160AbhHQHr2 (ORCPT ); Tue, 17 Aug 2021 03:47:28 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48454 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231500AbhHQHrM (ORCPT ); Tue, 17 Aug 2021 03:47:12 -0400 X-UUID: 70fb9f4f649a49bf93bf6b839e4a4a5d-20210817 X-UUID: 70fb9f4f649a49bf93bf6b839e4a4a5d-20210817 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1948333543; Tue, 17 Aug 2021 15:46:35 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 15:46:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 15:46:33 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [v2, 10/12] dt-bindings: watchdog: Add compatible for Mediatek MT7986 Date: Tue, 17 Aug 2021 15:45:55 +0800 Message-ID: <20210817074557.30953-11-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210817074557.30953-1-sam.shih@mediatek.com> References: <20210817074557.30953-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds dt-binding documentation of watchdog for Mediatek MT7986 SoC Platform. Signed-off-by: Sam Shih Acked-by: Rob Herring Reviewed-by: Guenter Roeck --- v2: added an Acked-by tag and a Reviewed-by tag --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 416d716403f6..a4e31ce96e0e 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,6 +13,7 @@ Required properties: "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 + "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986 "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192