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[209.51.188.17]) by mx.google.com with ESMTPS id 10si10099602ill.159.2021.08.21.13.01.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Aug 2021 13:01:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kPR+Jjsp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mHXBI-000287-Ii for patch@linaro.org; Sat, 21 Aug 2021 16:01:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mHX9x-00026t-F6 for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:05 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:33621) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mHX9u-0004SL-7w for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:05 -0400 Received: by mail-pf1-x42f.google.com with SMTP id w68so11712831pfd.0 for ; Sat, 21 Aug 2021 13:00:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F7ZS4B4B8gzp6eqM0t7V6IZHzjuH9VIN8nrlPVI9Ws0=; b=kPR+JjspKzn/KUK/PGcDC15mMzEeU5jGa4VcNMqDMnkEaMfVV+8wVLXyRUKIWRCVWR NhkUwZgxYVbT4uSgONJOCRpNU2lbxy9r4vQp+pyWWXLD7tM/og9s/oZOvnTQxz8z0klU Whx3wAXBeGYBQ9X8xS9WS0Gvq0/NOUi53OP0FsG2w+rGrzL8+Zv/WR+aZ7sxY3bMS9Pq LEuGkFSqQhFhF1sfSlF+JMGMJd3YpFxDR6zT1XFG2W8YO9ij5cEELMwIKRZgJE0oMuoX ts0zNjoXEDLWBD/9m9hWDLatci8eQX457hG3IjNf0aiF3M6dtDKcApCUkITLngb0UdA0 7DPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F7ZS4B4B8gzp6eqM0t7V6IZHzjuH9VIN8nrlPVI9Ws0=; b=rXccSiXYCrdfCaURJEiCGpS0kGs5NHXJC+DjGOuNKb9ArjQ06uixCj1JIoD/N2kbRg NYdcnL2uMLjGx2cRSi1RLcMrzF8+AtgLVBAWU7JBLp038T7BaRJ+YNTB7TuIkzmc0JzS 2ijVAy0TMUD4suXwtNwrTO3CCs5IyigJMXNMfhtm1+5fHjnJ/kvriTWU6mGLflY4+dJS N+17aVwQzs33ARDk3fOG37eYaa1dyFtCf8bgEckA2GLJMRl3QvqmKcEw1IFfkHS8tU6R Quq5UNVhTTRQ22T1yV6PaCrOmh7MTd88EwLRUD2nby/offc75y+8bzZtaR4kiUZ0QaMn y75g== X-Gm-Message-State: AOAM530JVJkmLmKP6q+amRViNSEykOyZMwZySWwTG35o7KDZJwRFdVEf Kt97SZRaKovyhkMKR1a1mmypGLYqQI7GdA== X-Received: by 2002:a05:6a00:2405:b0:3e1:9f65:9703 with SMTP id z5-20020a056a00240500b003e19f659703mr26215560pfh.6.1629576000702; Sat, 21 Aug 2021 13:00:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id h13sm12562257pgh.93.2021.08.21.13.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Aug 2021 13:00:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 1/8] target/arm: Take an exception if PSTATE.IL is set Date: Sat, 21 Aug 2021 12:59:51 -0700 Message-Id: <20210821195958.41312-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell In v8A, the PSTATE.IL bit is set for various kinds of illegal exception return or mode-change attempts. We already set PSTATE.IL (or its AArch32 equivalent CPSR.IL) in all those cases, but we weren't implementing the part of the behaviour where attempting to execute an instruction with PSTATE.IL takes an immediate exception with an appropriate syndrome value. Add a new TB flags bit tracking PSTATE.IL/CPSR.IL, and generate code to take an exception instead of whatever the instruction would have been. PSTATE.IL and CPSR.IL change only on exception entry, attempted exception exit, and various AArch32 mode changes via cpsr_write(). These places generally already rebuild the hflags, so the only place we need an extra rebuild_hflags call is in the illegal-return codepath of the AArch64 exception_return helper. Signed-off-by: Peter Maydell Message-Id: <20210817162118.24319-1-peter.maydell@linaro.org> Reviewed-by: Richard Henderson [rth: Added missing returns; set IL bit in syndrome] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/syndrome.h | 5 +++++ target/arm/translate.h | 2 ++ target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 ++++++++ target/arm/translate-a64.c | 11 +++++++++++ target/arm/translate.c | 21 +++++++++++++++++++++ 7 files changed, 49 insertions(+) -- 2.25.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9f0a5f84d5..be557bf5d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3441,6 +3441,7 @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) +FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 39a31260f2..54d135897b 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -270,4 +270,9 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) (cv << 24) | (cond << 20) | ti; } +static inline uint32_t syn_illegalstate(void) +{ + return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 241596c5bd..af1b6fa03c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -98,6 +98,8 @@ typedef struct DisasContext { bool hstr_active; /* True if memory operations require alignment */ bool align_mem; + /* True if PSTATE.IL is set */ + bool pstate_il; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 26f79f9141..19445b3c94 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1071,6 +1071,7 @@ illegal_return: if (!arm_singlestep_active(env)) { env->pstate &= ~PSTATE_SS; } + helper_rebuild_hflags_a64(env, cur_el); qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 155d8bf239..201ecf8c67 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13408,6 +13408,10 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } + if (env->uncached_cpsr & CPSR_IL) { + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -13502,6 +13506,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } } + if (env->pstate & PSTATE_IL) { + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); + } + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { /* * Set MTE_ACTIVE if any access may be Checked, and leave clear diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422e2ac0c9..230cc8d83b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14662,6 +14662,16 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) s->fp_access_checked = false; s->sve_access_checked = false; + if (s->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); + return; + } + if (dc_isar_feature(aa64_bti, s)) { if (s->base.num_insns == 1) { /* @@ -14780,6 +14790,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); + dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); diff --git a/target/arm/translate.c b/target/arm/translate.c index 80c282669f..5e0fc8a0a0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9045,6 +9045,16 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; } + if (s->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); + return; + } + if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used @@ -9313,6 +9323,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); + dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; @@ -9576,6 +9587,16 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->insn = insn; + if (dc->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(dc)); + return; + } + if (dc->eci) { /* * For M-profile continuable instructions, ECI/ICI handling From patchwork Sat Aug 21 19:59:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501023 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp825574jab; Sat, 21 Aug 2021 13:04:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzk5gys6ePSgKgWgMGdOe/DVp/NJoSGJHzAAbNe+VqMLedv6k83dk0OvlcQmiCiOsQLjJCI X-Received: by 2002:a05:6638:419e:: with SMTP id az30mr23803614jab.14.1629576248335; Sat, 21 Aug 2021 13:04:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576248; cv=none; d=google.com; s=arc-20160816; b=fgPYTwvx5wyOwzLFS0wpCMO04E8Nsf7+vm3867TsVsNHf3LKQmgZyGXG3LlyAHyTmN Q4CgAoPAgMjyI8z+kju4G+CtaRkOCNBNub3dbCJr4KZW6Ry9y/jXRwr2twtT1B9Mqvj6 QTuDmvbwbND+smXAgijDYhrtWdm0fPPvc2s07ZCYjs7pO5Z8O+nuLOQ7Q5Dh1z4U94GA B0u1AGomwYS0y1NYadeU8ZuCx2zz1QwVZwPc4qAmed5P9P+ahN/bP/QwW2K+5tDgS8mH oXTgz8plWKna39ZRNSXsDWZv65RHQJpYt7CIvLKw8flJ2OScvYglRwJZW0PfWLmGaLCF PS3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0gM1lJ5QbpFYG1IXZ0/xrE9q1D2a+icOd5fzVUyjtn4=; b=YQXIC1g4g3U8W3Jixj8yGRurrshwhEoWO2awVuH6NeQS3yJaxw4Y8Zuj5jFx7mkvAL KDwWPIj4COZMxF83s4/swDr3vCFOgXh1W1NsHomgfMgdgOP4zb4f8dUczUjRDta0mbq5 htcL2JmL4GfAfHtt80W0vPUbRP1L4TCo/nlWwDdyTv3T6HNlRwTFWqALNWMD0deZG/eq uSxivVPxH/n6cS45oTsbRniT/M5RhbQvrn/O4O2jVUL2M7zIx8+cw3JENValeT0eeDYl bAr8YwPIanzMHYmXRzBS3ipRdYPP+273okBittGhrq6AiBOtSfxiYSLAmf8U7W/YuDWm eDnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SnaO1ESL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k2si10740345ilu.143.2021.08.21.13.04.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Aug 2021 13:04:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SnaO1ESL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mHXDr-0006mr-Om for patch@linaro.org; Sat, 21 Aug 2021 16:04:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mHX9y-00027T-81 for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:06 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:38525) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mHX9u-0004T5-OP for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:05 -0400 Received: by mail-pg1-x534.google.com with SMTP id w8so12647740pgf.5 for ; Sat, 21 Aug 2021 13:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0gM1lJ5QbpFYG1IXZ0/xrE9q1D2a+icOd5fzVUyjtn4=; b=SnaO1ESLNbUnGpg0/rw50Kb4+kKiLQJd75sDaCgvx/efRaPmOWyJvmSJZs9+glVlx0 qNKA5+QNbWv1K/pbiCNp4UjZyPNVdLB4cUcMULah5BZfEo6tZ15aMkgIZozxMGOhRzWU bPzNCYEc7Ug2waa29W4axLKVnxGiWzorti3jGxM0u9WX2azZrcaMebzxKQPclpMYfD84 1F5IhWRXbVVpeVZ/G5HUwo6DFbaUgGrzEUBSgeqsHybhwhWdt9l8KSCVQpRPHqzMU757 Sa7FICcPcy5UOZkxfEsQi5iixbRQfJ6A8cIwA71/2TDm57LcDFAbz6PWz2yIxxZdXRqq 5z7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0gM1lJ5QbpFYG1IXZ0/xrE9q1D2a+icOd5fzVUyjtn4=; b=mNvYMyJsN4LCMtyhX3Y9rQsndJF4s2OgW3z6H0ziuDHRytPDW+vcMwVRqe3JaHdmdk yqoQVNJ22zOv0fMdLXmo9s/qDa8i/DL2VZ1y1+k1/+dM+vP+9w7P5R7fm1uHhlbgi+HI lXEuBpIq4MteyWiI9BNA+n6y3bqZT+zj/nB2LaCUmL7Utnzdsqieavt2DLMsvcdS0Ur/ q7ccxb84XeBzIriOp/G1EpBvVw5LiVxx2PYVRjJin1os9mnW6M4PPZNEEjF/RDxUMcdh g3FZZXH4AigotUA8ZzNsOgg8PFJ1Ukfe9kJcbv5UVBsUpdagPI8/qi8LqyD6TKp4VKaS YQGA== X-Gm-Message-State: AOAM530cxuhIIcSt0CuCbkfZsnCnq0KZ3o1grQa/o9VScR8M9rp/BuwR Lsrz44f2/RBob7EgeAMq1xBCXH9tlujs8w== X-Received: by 2002:a63:1f45:: with SMTP id q5mr16770305pgm.385.1629576001258; Sat, 21 Aug 2021 13:00:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id h13sm12562257pgh.93.2021.08.21.13.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Aug 2021 13:00:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/8] target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Date: Sat, 21 Aug 2021 12:59:52 -0700 Message-Id: <20210821195958.41312-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It is confusing to have different exits from translation for various conditions in separate functions. Merge disas_a64_insn into its only caller. Standardize on the "s" name for the DisasContext, as the code from disas_a64_insn had more instances. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 224 ++++++++++++++++++------------------- 1 file changed, 109 insertions(+), 115 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 230cc8d83b..333bc836b2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14649,113 +14649,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) return false; } -/* C3.1 A64 instruction index by encoding */ -static void disas_a64_insn(CPUARMState *env, DisasContext *s) -{ - uint32_t insn; - - s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); - s->insn = insn; - s->base.pc_next += 4; - - s->fp_access_checked = false; - s->sve_access_checked = false; - - if (s->pstate_il) { - /* - * Illegal execution state. This has priority over BTI - * exceptions, but comes after instruction abort exceptions. - */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); - return; - } - - if (dc_isar_feature(aa64_bti, s)) { - if (s->base.num_insns == 1) { - /* - * At the first insn of the TB, compute s->guarded_page. - * We delayed computing this until successfully reading - * the first insn of the TB, above. This (mostly) ensures - * that the softmmu tlb entry has been populated, and the - * page table GP bit is available. - * - * Note that we need to compute this even if btype == 0, - * because this value is used for BR instructions later - * where ENV is not available. - */ - s->guarded_page = is_guarded_page(env, s); - - /* First insn can have btype set to non-zero. */ - tcg_debug_assert(s->btype >= 0); - - /* - * Note that the Branch Target Exception has fairly high - * priority -- below debugging exceptions but above most - * everything else. This allows us to handle this now - * instead of waiting until the insn is otherwise decoded. - */ - if (s->btype != 0 - && s->guarded_page - && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype), - default_exception_el(s)); - return; - } - } else { - /* Not the first insn: btype must be 0. */ - tcg_debug_assert(s->btype == 0); - } - } - - switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ - unallocated_encoding(s); - break; - case 0x2: - if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { - unallocated_encoding(s); - } - break; - case 0x8: case 0x9: /* Data processing - immediate */ - disas_data_proc_imm(s, insn); - break; - case 0xa: case 0xb: /* Branch, exception generation and system insns */ - disas_b_exc_sys(s, insn); - break; - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; - case 0x5: - case 0xd: /* Data processing - register */ - disas_data_proc_reg(s, insn); - break; - case 0x7: - case 0xf: /* Data processing - SIMD and floating point */ - disas_data_proc_simd_fp(s, insn); - break; - default: - assert(FALSE); /* all 15 cases should be handled above */ - break; - } - - /* if we allocated any temporaries, free them here */ - free_tmp_a64(s); - - /* - * After execution of most insns, btype is reset to 0. - * Note that we set btype == -1 when the insn sets btype. - */ - if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { - reset_btype(s); - } -} - static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) { @@ -14857,10 +14750,11 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext *dc = container_of(dcbase, DisasContext, base); + DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t insn; - if (dc->ss_active && !dc->pstate_ss) { + if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either * a) we just took an exception to an EL which is being debugged @@ -14871,14 +14765,114 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(dc->base.num_insns == 1); - gen_swstep_exception(dc, 0, 0); - dc->base.is_jmp = DISAS_NORETURN; - } else { - disas_a64_insn(env, dc); + assert(s->base.num_insns == 1); + gen_swstep_exception(s, 0, 0); + s->base.is_jmp = DISAS_NORETURN; + return; } - translator_loop_temp_check(&dc->base); + s->pc_curr = s->base.pc_next; + insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); + s->insn = insn; + s->base.pc_next += 4; + + s->fp_access_checked = false; + s->sve_access_checked = false; + + if (s->pstate_il) { + /* + * Illegal execution state. This has priority over BTI + * exceptions, but comes after instruction abort exceptions. + */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); + return; + } + + if (dc_isar_feature(aa64_bti, s)) { + if (s->base.num_insns == 1) { + /* + * At the first insn of the TB, compute s->guarded_page. + * We delayed computing this until successfully reading + * the first insn of the TB, above. This (mostly) ensures + * that the softmmu tlb entry has been populated, and the + * page table GP bit is available. + * + * Note that we need to compute this even if btype == 0, + * because this value is used for BR instructions later + * where ENV is not available. + */ + s->guarded_page = is_guarded_page(env, s); + + /* First insn can have btype set to non-zero. */ + tcg_debug_assert(s->btype >= 0); + + /* + * Note that the Branch Target Exception has fairly high + * priority -- below debugging exceptions but above most + * everything else. This allows us to handle this now + * instead of waiting until the insn is otherwise decoded. + */ + if (s->btype != 0 + && s->guarded_page + && !btype_destination_ok(insn, s->bt, s->btype)) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_btitrap(s->btype), + default_exception_el(s)); + return; + } + } else { + /* Not the first insn: btype must be 0. */ + tcg_debug_assert(s->btype == 0); + } + } + + switch (extract32(insn, 25, 4)) { + case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + unallocated_encoding(s); + break; + case 0x2: + if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x8: case 0x9: /* Data processing - immediate */ + disas_data_proc_imm(s, insn); + break; + case 0xa: case 0xb: /* Branch, exception generation and system insns */ + disas_b_exc_sys(s, insn); + break; + case 0x4: + case 0x6: + case 0xc: + case 0xe: /* Loads and stores */ + disas_ldst(s, insn); + break; + case 0x5: + case 0xd: /* Data processing - register */ + disas_data_proc_reg(s, insn); + break; + case 0x7: + case 0xf: /* Data processing - SIMD and floating point */ + disas_data_proc_simd_fp(s, insn); + break; + default: + assert(FALSE); /* all 15 cases should be handled above */ + break; + } + + /* if we allocated any temporaries, free them here */ + free_tmp_a64(s); + + /* + * After execution of most insns, btype is reset to 0. + * Note that we set btype == -1 when the insn sets btype. + */ + if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { + reset_btype(s); + } + + translator_loop_temp_check(&s->base); } static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) From patchwork Sat Aug 21 19:59:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501022 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp824072jab; Sat, 21 Aug 2021 13:02:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8PlE89QkoPSYE6nEqYAfimC0uSa7KFS7u4bH7NmpLfrdM/Vz2PzzkrrVap1NBzWxvTAEP X-Received: by 2002:a92:cb4b:: with SMTP id f11mr18084585ilq.189.1629576121178; Sat, 21 Aug 2021 13:02:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576121; cv=none; d=google.com; s=arc-20160816; b=HPC2aYURAWmEemmhjW+KpBO3o9iUMsuLLsoFzp2oaumzWHOK6muxUUwt/pA35mn804 zxBz3bD0NnFJVeXGF8ODTnfm/W2xcCMp9H3YgYSpqEP1yucON3Puc97JCDLXRRjTfXoq 6lUZstrCnMHappOCm0Q+RKXIXszdaf6PHQji7Y9vm4UJNgCGJzn/eOiJpCkXwdKwwvAc FkwXyDEaSPJ3qkmVX2NVBeSMt9TPET0tg7tuj+Zne44olzyUWwkC105c00XjpC/rN2C/ a4rujFfJk9cz9XXKEu7knuM003na8WEAmhIY8hAwsn0L/6cgVvvTcRF/exEt2H6hpfDB w+jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S3Ic6iGbb2NTPoozAwoc6s7WItVnl35pmUzWVFyhl0M=; b=f72rjOumUP4ni3F0OcPDNOiC+m5rWmLxX7CW4D1vHrflgwRa06+D+knldLADGO98Zs P8E9n+lGKFMw+ZhGTNilALUi6rfzMpsRADf3h4EkN7Uzj0Ch8WcFi3tq6yYXp5T967pV BZWAoJMcL10lfZbM/d10TOr7OIPlJ2xxcYsKuOwyKge5DMOS0J7Mds+v1ZC2h57DRz/8 lwSOkuNBXuVZJbw7kS46y0PJAzO6xnNkbuLoxlQziiF0tiFyofd3JyGso0VK/rZfUzfM YeGGGR1jT1GWz7D/FbpOZ0JJooSy8Exy3smtXGFQAXh2FaxdufeKphdWwjBQkktHkl/+ QhLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v16q45jb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j10si10968204jat.46.2021.08.21.13.02.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Aug 2021 13:02:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v16q45jb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mHXBo-0003A2-K7 for patch@linaro.org; Sat, 21 Aug 2021 16:02:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mHX9y-00028E-U8 for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:06 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:36780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mHX9v-0004Te-4P for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:06 -0400 Received: by mail-pf1-x42f.google.com with SMTP id m26so11717912pff.3 for ; Sat, 21 Aug 2021 13:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S3Ic6iGbb2NTPoozAwoc6s7WItVnl35pmUzWVFyhl0M=; b=v16q45jbY0Bm/F9kON0YGyVoryrkJwCvBW2A/deLNRcp1d22BKL4IYCTzBd59Xn7zJ 0AaQXu87hv6aB67MJRVJNdf+kBpZtgsvMSvgMfPPuH6d6YPFYhfFtV0flPWgwFPDDV7x bBtiz8GWUCoL9f+xRTCPqe54KD5ln6LJn8JQBYTS8dIj30lJfoM2r3dB9mgn43WDgtmK Tl78iBelCV5fGKRwU5F76zie1xjwfEjqfCUxYu2lPXxpNabf6qt3wutqO1Z6lMmOf0sw /yPQ/87BXX8mM4vRM8Xjk0ENLTCGH2ezQVvK0Uog+dW8MnamJcFH2Al31pCl0KpNjShj bBbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S3Ic6iGbb2NTPoozAwoc6s7WItVnl35pmUzWVFyhl0M=; b=LDHWHgvW+fEg7OWRCJxNIcDlhZF/2s2xQqRdzeM9UF3YY83LnUzGvDnDm2U1N3uJZx EvzPBoysX0RaUUx+8MI1lY1cz3boMgwSmhAr5ez/xUwnYTtz+6yIG557X/Isueqp91DW sFhY9jzL3LH2xsQAE7ZH6hi5msxMUgvBHN3PqRbE6I5PHoxNEcg9DJm+UM41I0kOBnSI yqFmv5oAM5Of674WNTeLqXIP6qDMe2Q2I1fwN8guqoCSni6U7qe+CD0vbkd8HblMj0BK jChXkUTZqHMyUy01/BZcxPBeBF8Dh/srqm691ndWtYgllyasOsQ7umBG4YYKeDgLg+L7 1aXA== X-Gm-Message-State: AOAM533JH/Ff92+nMCLWuJGVw5kGG2xVHzWFhCXHBy3h+aSleCZcJ228 TtMX+STSo4Ksmd4M8H9IrMz0CFLTKUkPeg== X-Received: by 2002:a62:9288:0:b0:3e1:c44f:a1b7 with SMTP id o130-20020a629288000000b003e1c44fa1b7mr26538632pfd.63.1629576001839; Sat, 21 Aug 2021 13:00:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id h13sm12562257pgh.93.2021.08.21.13.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Aug 2021 13:00:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 3/8] linux-user/aarch64: Handle EC_PCALIGNMENT Date: Sat, 21 Aug 2021 12:59:53 -0700 Message-Id: <20210821195958.41312-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will shortly be raised for execution with a misaligned pc. Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 44 +++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 11e34cb100..6e03afb2bd 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -78,7 +78,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr, ec, fsc, si_code; + int trapnr, ec, fsc, si_sig, si_code; abi_long ret; for (;;) { @@ -112,28 +112,38 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ ec = syn_get_ec(env->exception.syndrome); - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc = extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_code = TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_sig = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_sig = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_sig = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MTESERR; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_code = TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_code = TARGET_SEGV_MTESERR; + case EC_PCALIGNMENT: + si_sig = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; break; default: g_assert_not_reached(); } - - force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress); + force_sig_fault(si_sig, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: From patchwork Sat Aug 21 19:59:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501024 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp825786jab; Sat, 21 Aug 2021 13:04:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/3a3JMNZB6IaacVzmVzQZftH9jWZapKsRE4jA8/dLrTPxEV2bUGwdQ5teBRHh6nnVj/7/ X-Received: by 2002:a05:6602:27ca:: with SMTP id l10mr21857964ios.16.1629576274525; Sat, 21 Aug 2021 13:04:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576274; cv=none; d=google.com; s=arc-20160816; b=ozromnHkUUI16su8zpLBS1D+tXTUIjV59OkISfDVcSqkX4xq+lTNPPjjDhH2J+Bpzy 7FCPlGMrrYv9iUuWbOgl+fr5p2wkH09JrtrQIDoMYc7jWWFcmbwihjAEonIDpsvuP/oT uDzLjrGKG5oXEwNDUGQdr7gpv+/M+BSVBPriS6yciiBseubi6/YYjq8f1OYhdlk66bxA K6vYSRbwlnKO1+gTldUHxJi9nBDRytxWW3biW4rrE0Qe1EtupQ5Cwsy8vWaUC1ocNRuD LhbrnX3eymNJRJrtFTseU/Ud7D8U/CUzQve8COf3yWeWSPWnuMzpGQSEqoUZCNp68fUR NNXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nW9fMChnRBXVS7c8vZgjblWrAXidwfTLKIZtt2ybyaE=; b=J7cCiSyxN2yKsf/Nu6wRiUeY9fNmNoUn+zHAJ9YewRYSJF8J1NFVEBJH8ZAJxsK+2S EQ8G0ktYIbysTCSodZ983gKc15B7iALGhg+qI/MxlImtSkwFt9YIVO7UpXPFQ0UogSs4 QtHEaUm6/mUhf1OX0EOqt9WEEgbSQmfPSPyee2cn2YRJ0bM0hMcJ3+YRb/4b+afNweXJ av71n11dST6BzvSIDhd1mwwFCnOk3kXgNEbqaQJE2yZvaBMVEFwwFeLPd1V0F6IQKKT4 l1S5UEXxHqAYclmJSNzBUr5mU7YL3NYoyxtMFt4uDXuYyL0XuE4Elm2cTV+BVcsldUQE gDYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="N/A6Bnyb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- Pulled out from the larger unaligned data patch set. For short-form FSC, pc misalignment is reported in the same way. --- linux-user/arm/cpu_loop.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index d4b4f0c71f..5731d3c937 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -24,6 +24,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -279,8 +280,8 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; - unsigned int n, insn; + int trapnr, si_signo, si_code; + unsigned int n, insn, ec, fsc; abi_ulong ret; for(;;) { @@ -422,9 +423,37 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* XXX: check env->error_code */ - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, - env->exception.vaddress); + /* + * For user-only we don't set TTBCR_EAE, so we always get + * short-form FSC, which then tells us to look at the FSR. + */ + ec = syn_get_ec(env->exception.syndrome); + assert(ec == EC_DATAABORT || ec == EC_INSNABORT); + fsc = extract32(env->exception.syndrome, 0, 6); + assert(fsc == 0x3f); + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: From patchwork Sat Aug 21 19:59:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501025 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp826960jab; Sat, 21 Aug 2021 13:06:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAt1TKyNZuc01dDdN7cynrQrZg24wS+QV7oh4XHoHw7CHQB2j9CmsO9w4IRoHremZT5FsR X-Received: by 2002:a05:6e02:1353:: with SMTP id k19mr18263592ilr.157.1629576390188; Sat, 21 Aug 2021 13:06:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576390; cv=none; d=google.com; s=arc-20160816; b=BjV22vTFH/l43lTID/aRR1zFsNOo08w210+DNBbZZLYcbZnhElOZI0xkOueDjh6SJO /jL7iWr58uE3vpIoPTJXXH/hxzWP8HDLCSpZyaap3lCYfvhDDDgN8PRq4hMkdLbLGA/z hLWXU7SFx/MFm+4le9M8cJUlcGJj1NWcI1d09xcD5vOMOyqFScHtSTkm1La62xKPyDJ0 9/aaRLZ9wI/jvwcp9BF4iBvbhLub//EEfuxUWqJlerQFYr9VG/3lMTJFLoCeGA2sEQEi 9K07fWfg7PLkhfd16dnIapc7JCCtEP4BCtrAYZaNaRTJN0EUk0QYJ2TwVl7tKCzC4TRt v0fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Hn7fpe16SCWF4h1OR7HYJ+ccPYtVq+eIAGolsqSBqQg=; b=GV2KYT1r6iuELh7Dfidng93WeqoOoJgyqQi5CeO0KEE44lxG0IqMgF8rp9GAGzntT9 6aOt3m2bjamBF6x9hDZPjT8rK2X0+fqCpKEI7DfrD+7ZZlNxkvlq3EpQPGMiadImz3c+ sS0JRBmzYb5N8bt1IQV4mbp2UalT5S2DDtlAKNiJq7lfgIs+wSV0zBHTccr6DpDEFqz8 VD34JaYUPNTPFAuae2nP46ahxhBHDtQLqZXCyS2R1zxLmuIpfyXdmKr/DGe87W4lbu8v YlEN6wxRak5PX3AGJ+cGeqNiT3BCBnplQ9Ka1o2MvpG35ZiE79oIskfgIK4GhB2sv71x 5GwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FPkA54iO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u4si8920683jak.106.2021.08.21.13.06.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Aug 2021 13:06:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FPkA54iO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mHXG9-00030a-MK for patch@linaro.org; Sat, 21 Aug 2021 16:06:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mHX9z-0002B5-Ty for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:07 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:40511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mHX9w-0004Va-I2 for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:07 -0400 Received: by mail-pf1-x433.google.com with SMTP id y190so11739249pfg.7 for ; Sat, 21 Aug 2021 13:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hn7fpe16SCWF4h1OR7HYJ+ccPYtVq+eIAGolsqSBqQg=; b=FPkA54iO9x5uIRs0eU6ZRiQrqcJBIYj4gLFIRCAqbF96eZDS4MOlnJQqrtbZlNVs6F YU8nraOK3x49ZTaV1DbJIt2CCFjWOKSazSFPAYYvbk5Yroh9VCboQSTwKiycn5P+BHEL 00kBPDaKye+51c197gCbSqqyeR7KdA3BxNkLjIW00rLGjKWAArvfrUiEHCOoa25aD+c6 +EzkLcgdtqHHeQzA/eJusxb+OwlCx0JKY+i1mWnccaybqrW7vX310/5BvUznKq6WGhYH vQ+Kj0xtGkmvtfQeCiKl18cy9MMHmED0hYGCX86QdtXPj/YFNepeNg4CzNwuJUhoFcNC CGPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hn7fpe16SCWF4h1OR7HYJ+ccPYtVq+eIAGolsqSBqQg=; b=rdq9YNuQQruoDGte/xJ2Kce7G/CPkLDNCz9oPaFfQ9RTLSWAtOc2HEdArkE1qQ8eVG 2CjnW5oL2sMFSLugjScK/Sqh4wslDpEKX00QK++c5ONp/aM6TeXUEkleK+Ea2LNKqS2M zMUYGDKWeICH2Ax4EbhheWfeusM44s+m0q9jOKb2wa2QPa1guKjAyFtxPT6rh5nXHsEt mRqcYqyOi/sKHuWbMNqdUNYVv+fMvYdxYUISJZxq9cOW46T3TL5CogJ4g9OzUkwZTD59 qPm3wGJ4xwM9MHzdApwJu7xfgxLsq+Svl1SYOp/NLErDMAYlXMB2xNvAyzvgmtOFpv7b jMQw== X-Gm-Message-State: AOAM530qCPDFDUpQrB+lsk4Jt4IAdiwspe5KaRTAxti7vN8A3qYTRCWI FTIalcBJQZHmp9YdsfpRYCRqF134IjEEpQ== X-Received: by 2002:a65:6398:: with SMTP id h24mr24869431pgv.367.1629576002913; Sat, 21 Aug 2021 13:00:02 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id h13sm12562257pgh.93.2021.08.21.13.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Aug 2021 13:00:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 5/8] target/arm: Take an exception if PC is misaligned Date: Sat, 21 Aug 2021 12:59:55 -0700 Message-Id: <20210821195958.41312-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/syndrome.h | 5 +++++ target/arm/tlb_helper.c | 24 +++++++++++++++++++++++ target/arm/translate-a64.c | 21 ++++++++++++++++++-- target/arm/translate.c | 39 +++++++++++++++++++++++++++++++------- 5 files changed, 81 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 248569b0cd..d629ee6859 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 54d135897b..e9d97fac6e 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -275,4 +275,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823e..25c422976e 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -123,6 +124,29 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + int target_el = exception_target_el(env); + + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { + /* + * To aarch64 and aarch32 el2, pc alignment has a + * special exception class. + */ + env->exception.vaddress = pc; + env->exception.fsr = 0; + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); + } else { + /* + * To aarch32 el1, pc alignment is like data alignment + * except with a prefetch abort. + */ + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; + arm_deliver_fault(env_archcpu(env), pc, MMU_INST_FETCH, + cpu_mmu_index(env, true), &fi); + } +} + #if !defined(CONFIG_USER_ONLY) /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 333bc836b2..39c2fb8c7e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14752,8 +14752,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint64_t pc = s->base.pc_next; uint32_t insn; + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14768,13 +14770,28 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; } - s->pc_curr = s->base.pc_next; + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + s->pc_curr = pc; insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); s->insn = insn; - s->base.pc_next += 4; + s->base.pc_next = pc + 4; s->fp_access_checked = false; s->sve_access_checked = false; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5e0fc8a0a0..dfeaa2321d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9452,7 +9452,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9464,7 +9464,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9498,17 +9502,38 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 4; + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next = pc + 4; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should only + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp = DISAS_NORETURN; + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { + dc->base.pc_next = pc + 4; + return; + } + + dc->pc_curr = pc; + insn = arm_ldl_code(env, pc, dc->sctlr_b); dc->insn = insn; - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; disas_arm_insn(dc, insn); arm_post_translate_insn(dc); @@ -9570,7 +9595,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next += 2; return; } From patchwork Sat Aug 21 19:59:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501027 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp827928jab; Sat, 21 Aug 2021 13:08:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjGkUggF437na3HzjW41o4lKiO/4rh9zOXBPVnyugPyj2X1Won13ECdtS4OQ7h1PW6y4xV X-Received: by 2002:a05:6638:2481:: with SMTP id x1mr23254179jat.69.1629576486496; Sat, 21 Aug 2021 13:08:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576486; cv=none; d=google.com; s=arc-20160816; b=WAfbf0jYfLIYRJ3nWyOF9uJt/i2JsqAeB7kmLASkidl5DZCOpCBnBj42fpKyGw7c03 hc8P3/1H+T62y61JOMCWf6xJhQ6nUjuMJnGeKjEkbAB/tiKg3WLlgyJ+FeGHF/+2QzOJ FByZkfvk6vovM8PQOyRi+HTSrbeqRsQS2zLN0MmkjTxPTyIZBnwrxlVa1lsTqWnP0z36 118cr1HIJM2h8sFhwZCOv59AvwAMSafBTW9JA5MeJ8/fBU5RHOAI8QT3HO6mWKkQ9TPy +4pYEHMEZYpnCEvVprMeUl5gc1dsD8pVg7OkwXVak17qu+1rsoVx7XkhgMxutYzsBL3e MRrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+ZAhinf24CQJmFBs0vLR+aQqqKuFbYYjrTVj6/rZMr0=; b=BK/YJzrJVBx4LwzKC+v6IACuv7O70yMStWvaA/bmUlo/8fa1cQGrr9ahRunNUo5OLs NeCVrY7ZYtmhaLmnaFPpU8pATsBFXIFlC3C79dhUAf2DycwigAtsVj5FEs6Dz0KSBmPr f6D2NL0TrgwYEJIMTPK3KZMr/5w9k2xAasiQHsCeDbqeknTmNPJgvVYMrZJib0derKbO 3/0ygLY6c9XXKFHmREcRX/9tWaX9NIcI5maXt0+zt+Xwz57wQOGfStgUHEWU81rp9qI0 wZt+NEM0Hm4KzJtuLn1uPttSevnRSnypBBblIl45Yw+ZPUi5vVzBuxDIPAE1bK712XC5 lzCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x8XzlXMq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j13si13397163iow.57.2021.08.21.13.08.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Aug 2021 13:08:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x8XzlXMq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mHXHh-0005vY-Vo for patch@linaro.org; Sat, 21 Aug 2021 16:08:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mHXA0-0002En-V3 for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:09 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:54208) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mHX9x-0004WM-CJ for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:08 -0400 Received: by mail-pj1-x1035.google.com with SMTP id j1so9427836pjv.3 for ; Sat, 21 Aug 2021 13:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ZAhinf24CQJmFBs0vLR+aQqqKuFbYYjrTVj6/rZMr0=; b=x8XzlXMqmNwEWr+RvHQwja3b0lcaWPiL2/HWJRE+q+Mv02ofI9U+RD1kU0CRrE/g2n YlZNlvt5UfgZDDTEo2O9eVIX7CwOTUr6qQjSLT+lxpPbrEEcT2CTgwbXR7jWcF0VJdmg FkeWjLd3niDydLoNQ+8ksEmI1XlO+cieLMJMs1WVdgvwXLi7ZpudUWYMUFfQNgnBxw/G moGbzvBV1PTBxHkkY7i6yya4TqoUcSh/roxkGARu9yjXV5MtHRlifMl6cEG5Aq7Qe7yD ZuoZj4GKHQh/PzlmD2qX7w7jtMiIQNS7V/pPt68RmzKMioRSc3X1Caa6z77MwM/0/ChN ipRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ZAhinf24CQJmFBs0vLR+aQqqKuFbYYjrTVj6/rZMr0=; b=FqRyUVzaoGAOYCqxPNKZ2w9XXcxSU7oP95W4XocFKrWDQgB/2nnsnN989cOWOmcJwP x5ThNVuruTg3z/kBpqeUzMbqx378GkFPh49RkS+twT4Q+ZpfCzg86xjuKBRy5a+xUnKi +h0Fo7F0o8SBwBA10oVk68/8+1DagJ3xsW6m47e2zpgvWgI74okfOh5IIXOj5ij9EJmM LVv8TFNpp7ecJ7azgsOpgp7AnXhXT0rTTOuNU5rmwzihzljS2V096hDsdriUSBw08h4t VHTgfcz7d4xvmz2yeaxSSARZJSEcZmdnV7rh6qxDk86bQpekFy8J4u7MZmRkLKWvlDRj xODg== X-Gm-Message-State: AOAM530kssCnuz0TCckLmsW93tUp0zUnM4qsrrwQz17lIZvGQCplXkif zuxlSWVsvHTt0h46MFKYNE5QY85i8HitCg== X-Received: by 2002:a17:902:8c90:b0:12f:699b:27 with SMTP id t16-20020a1709028c9000b0012f699b0027mr15372004plo.28.1629576003929; Sat, 21 Aug 2021 13:00:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id h13sm12562257pgh.93.2021.08.21.13.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Aug 2021 13:00:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 6/8] target/arm: Assert thumb pc is aligned Date: Sat, 21 Aug 2021 12:59:56 -0700 Message-Id: <20210821195958.41312-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Signed-off-by: Richard Henderson --- target/arm/gdbstub.c | 9 +++++++-- target/arm/machine.c | 9 +++++++++ target/arm/translate.c | 3 +++ 3 files changed, 19 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 826601b341..a54b42418b 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -76,8 +76,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n == 15) { tmp &= ~1; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 81e30de824..b5004a67e9 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -781,6 +781,15 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/translate.c b/target/arm/translate.c index dfeaa2321d..a93ea3c47c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9595,6 +9595,9 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) == 0); + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next += 2; return; From patchwork Sat Aug 21 19:59:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501026 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp827302jab; Sat, 21 Aug 2021 13:07:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwgUvEorxfxQ2AdimgQrm/pPnBu7CtdTxEVRjPSCFPDugmymbPWFcV9jUDXsB/Hsn3bVFx X-Received: by 2002:a5d:9355:: with SMTP id i21mr1231784ioo.12.1629576426368; Sat, 21 Aug 2021 13:07:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576426; cv=none; d=google.com; s=arc-20160816; b=n/PU1Zepq67o+Sbq/uwMwLlSnrBrQ6+onn+j/ZSpuL3Dk9bSNU5XOZtbdLXXUUWTte T4zIgN6iL21fXqYk06mxcsFsG0CGQoLZlpJFcrUw4PLuPx8qSGcDB9BAgjspHMQZ3rNF SVaGC3KnBULq7kn8PI7f6lwhNdbSPz6/2ykXDamz+8yewKb5f8X2EbnmClZ48jViVFaI LTDd8bcinkClMgtjE3WOdHSUP8wSxiecbWyy7Q6gPN4oI7c1Hgfo04OgH+TCCVkLJqOd 1UAQFYh7gZ74hhtZy19WaY3V3NSJXgBDGDfzZqdfcdupn4EUM3HPBgQndl2AAA65K4iW rI7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=jyjmx6dJlAZkeakh8uDBhf4OBANtwL2mG6Iow2I7JHtQjLRBMozJ4s0r88b6ijkCHW wJ+3JsO61b8rt7G8YOmLAQZI9Jejdfd5P7TSQ3XbA/G2ITFnbNmYIvML3Hns7QIBM56g L2n7umRQkOGQbCL3MkimtCknWkjB2iXV35otjijTCcljuRDc2LScblwDAf6srfi0BKwJ hrofQwSLMgebvzf/ZvHaybBGwo/6gdQ+9p/P0MQYBFpmZ3KOVboTFJhm+1yAEOcMPslL 2fOamFs+L5di34zYPAqve4oc+SbOL1gTy8Q5z28B3+1VCBHbzpeHGfy/jNi+CoPTFp9Z WswA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CWy0u4It; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q7si11387952ilu.111.2021.08.21.13.07.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Aug 2021 13:07:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CWy0u4It; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mHXGj-0003bD-TA for patch@linaro.org; Sat, 21 Aug 2021 16:07:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mHXA2-0002HD-2G for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:10 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:40512) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mHX9y-0004X7-6l for qemu-devel@nongnu.org; Sat, 21 Aug 2021 16:00:09 -0400 Received: by mail-pf1-x434.google.com with SMTP id y190so11739311pfg.7 for ; Sat, 21 Aug 2021 13:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=CWy0u4ItQ1fMEI83X7OMtn0drKtEV8/2zb7hqU3BgWpKtZovNZU80UGL0Sne0i54uf BxT1K8kfL4Zlo9fcSACd1py78BetXDy/ZKjh5G+JK9hSQ3sR3/g8Pe2+WQtGANFOSWxf XsXlchc15t9nMOjw2HlFFpPPs7ZWUUVsYhJfoAQiIjFjVqVsO/vParXY6gbg/opafsch a5rQOnWUmIMUXE5kE2OC8N1pyWNsTnKUjiGbUC+pU1UcUGQfjqWD30D0h2whwtq8KALc ffMiaoXPvAhPbosmv292M1cfjxFBMuL4BNMLxRjnzfTeHFcucXS9+Z9mA6fobJ4iED2R R09A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=i3uIK1XomERr1hCInq68PAhbZxQ4v+TBt0m+JaK3yWdvocRb5tsszY/mmT9psnkCNZ zXHF6Shn+kNY4a1Kr9cW5enAlLCZtXc8Aez6hGN0XOtkjaHNIqZXpDJ77jgU/vld7/mX oDpnd25Z7+49d/G7sYQy+Jou/zR8lf5JjRwEuxlfWp56BW4dVDd0te2Hc76OzSXLWQjw 03YiY/qDeFa9oVhBRBJ+rRAsx4ZBa3bwT4K73of0Yjvt7IbBnMxho9gq7gyawzsWSRik Facxy9Z9vSPnP0GCODYnVOWLafVOtif80sBG0B9etrpkxb9mw1n4FjGpi48XHVdPFJWE Zx7A== X-Gm-Message-State: AOAM532aCa5EHsGQcJfyKCi/zP6kXJNY/12hs34tUepSQYSnSxcIuR4z yzof78mw9ogU/G/JEZiGmILh/uECi94hnA== X-Received: by 2002:a65:670f:: with SMTP id u15mr24513059pgf.205.1629576004541; Sat, 21 Aug 2021 13:00:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id h13sm12562257pgh.93.2021.08.21.13.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Aug 2021 13:00:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 7/8] target/arm: Suppress bp for exceptions with more priority Date: Sat, 21 Aug 2021 12:59:57 -0700 Message-Id: <20210821195958.41312-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both single-step and pc alignment faults have priority over breakpoint exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.25.1 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..32f3caec23 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + target_ulong pc; int n; /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc = is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; From patchwork Sat Aug 21 19:59:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 501028 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp829114jab; Sat, 21 Aug 2021 13:10:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOPtwllwz13P5ZlyMwD6pjnyspMGah7dAkDbRhsJUYvD0uSeUNx10uzE2pfEAGQ3LoZqQ2 X-Received: by 2002:a92:d0b:: with SMTP id 11mr19025978iln.244.1629576602361; Sat, 21 Aug 2021 13:10:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629576602; cv=none; d=google.com; s=arc-20160816; b=UCwiG1vP58JoLjsbXlLp/AccrgNrctUqXh+f/GQf8rnUNQqIvImP16E9rXsoNFPKhD X4BMVR2Uj0quASMJ0T2JwN6aHY/K2L+kxqe+k/CiyPW9r55J52Q+eIGuzIAf5vg8KaYq vE9z+WlcYj8Xnds60WofC0FuMIq+AgXGnSsoKAIOKgOFatBqdHPvtzaTqrnOzBWqV88V Z2dog51QCfgXMcdCMU0tP7c71Si6xocyZLscFMOMM3m1FrEgwtU6wMcbNQ9ddw7pCcqS Bs3dslLusRgarUFebTEGZtwXtK0TASqu7PlAISmteaDXASyBydV00FaubBeGbYaczRfz 8riA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y0WTE2RfE+PmoTGLshyvWonUTc3RdZZ7/tjZ5VZamls=; b=gIkBVEoISP4zhzTdjkkYa/fxzgy4uVmxT37eYHMWUkRythQhvxnkqrOTI5DM6uVw2G PRRyMh7D5T8x2p1xcHvfnp4WOhwsKTm90gN33I2RqdKbdbaMlNnUdcMej4eyty3PbvQ2 QxmqoW68C3X+892Mbu0/AzasTpG5SK+koUGGA+fZT8U7RjtdN9PPBzBLkPD3NvNW51th Lr58TeyaXo4v4Wdl0F9R9lbNBXhnuHoQkXVevMtonQp0XSLAiytkPNZnR0VPET/Glg5Z 3bDNq8BCuPkvS7jMI2STV8+b9AWKM54UusbcAc/0EBd7Ot+nS2dYuhHxA9vRwZe/Et9r DiXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PWp2PQBw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sat, 21 Aug 2021 13:00:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 8/8] tests/tcg: Add arm and aarch64 pc alignment tests Date: Sat, 21 Aug 2021 12:59:58 -0700 Message-Id: <20210821195958.41312-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210821195958.41312-1-richard.henderson@linaro.org> References: <20210821195958.41312-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +-- tests/tcg/arm/Makefile.target | 4 +++ 4 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c new file mode 100644 index 0000000000..6b9277f919 --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + abort(); +} diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 0000000000..3c9c8cc97b --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2c05c90d17..1d967901bd 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# Float-convert Tests -AARCH64_TESTS=fcvt +# Base architecture tests +AARCH64_TESTS=fcvt pcalign-a64 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce..f509d823d4 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# PC alignment test +ARM_TESTS += pcalign-a32 +pcalign-a32: CFLAGS+=-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) # Semihosting smoke test for linux-user