From patchwork Thu Aug 26 09:15:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 503019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D888C4320E for ; Thu, 26 Aug 2021 09:16:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 114A7610CE for ; Thu, 26 Aug 2021 09:16:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240893AbhHZJRJ (ORCPT ); Thu, 26 Aug 2021 05:17:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240918AbhHZJRI (ORCPT ); Thu, 26 Aug 2021 05:17:08 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C0FFC06179A; Thu, 26 Aug 2021 02:16:20 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id om1-20020a17090b3a8100b0017941c44ce4so6148504pjb.3; Thu, 26 Aug 2021 02:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T16hPym+Gbg5qTCFIPoHdSKLfvoWtFjTf0ClBNpU9Uc=; b=UmiQHF33ws4tudVoG3QYkrvG1XBp7SxdYUF3zGbFI2I+S3QNAaXggAhXAIn6Z/jkgf mPN5oi691+Mi9nW7XbX14ec9JOoOgflcB3kAgpEjwT5DOYyhae3Ls+hZF+HPas1m/kD5 FzjwQmpvvbD6apX/ojokWDsQfpvqWiisD48cjOreQdU5Ow+9DMI3oNZ6sPfPnX8EvZUR SCb86ZrsTiUB1bo2L8p7vC/54wTg+g3TFvafZi5WclAIzxcrCHHGScXQO2sZmxEYo7HQ E4Wog0zdYoZnxcLZ3cHDKMlLfwhxYaVwvKnb0pACX08w0tgZEGnXtF1XFDkiW5CNg1Dh YWrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T16hPym+Gbg5qTCFIPoHdSKLfvoWtFjTf0ClBNpU9Uc=; b=rxz7VAdRVpzGv++BKunf/McdThdPkchucRRWvuJk9zkkz18iJYKJhhl5phmgIQBNXj YinkTtKaXnI1IgWlzBRYsYGppICGFZX4KIjkNY7IY8RBO6gbVNmpvaON34Us/vHIfEGD S9vQPPwvuK3Bmk1JFTyOABcNTR0spjpQoMZy8Qn4CYzrhn551kB60VgZlJjdcaq7oaK6 EsrT1GZqnl4jCYsDh0xJNiegeFoOoHjBsinbFTok6PaMthPBQyWrOF3vmfr3cCwTLZrS nelS3QdGHi27xy3qaDyAw1ovDyQoRAYM0xNxy1PgKyDEpPFQ1+XWK5pEy5Ztd5FlRrbU gSjA== X-Gm-Message-State: AOAM53104MZ1R98JHAnyt6rESsRFjCHU+p/xkIrM1z1/d09jS+G21Jmq k5A29jQLTqpOk/clLZr4lAE= X-Google-Smtp-Source: ABdhPJwNJ4aVRcvzmYacli+y2TCes91mC51Q6wES6lTFJL1+aHwKpm+yH9s3aFwKuWFBntrn38Lrfw== X-Received: by 2002:a17:903:2302:b0:133:f033:6eb4 with SMTP id d2-20020a170903230200b00133f0336eb4mr2754985plh.34.1629969379306; Thu, 26 Aug 2021 02:16:19 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j20sm2777569pgb.2.2021.08.26.02.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 02:16:18 -0700 (PDT) From: Chunyan Zhang To: Mark Brown Cc: linux-spi@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , Luting Guo , LKML Subject: [PATCH V3 1/4] spi: sprd: Fix the wrong WDG_LOAD_VAL Date: Thu, 26 Aug 2021 17:15:46 +0800 Message-Id: <20210826091549.2138125-2-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210826091549.2138125-1-zhang.lyra@gmail.com> References: <20210826091549.2138125-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chunyan Zhang Use 50ms as default timeout value and the time clock is 32768HZ. The original value of WDG_LOAD_VAL is not correct, so this patch fixes it. Fixes: ac1775012058 ("spi: sprd: Add the support of restarting the system") Signed-off-by: Chunyan Zhang --- drivers/spi/spi-sprd-adi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-sprd-adi.c b/drivers/spi/spi-sprd-adi.c index 07f11b17bf20..d392dc6db927 100644 --- a/drivers/spi/spi-sprd-adi.c +++ b/drivers/spi/spi-sprd-adi.c @@ -103,7 +103,7 @@ #define HWRST_STATUS_WATCHDOG 0xf0 /* Use default timeout 50 ms that converts to watchdog values */ -#define WDG_LOAD_VAL ((50 * 1000) / 32768) +#define WDG_LOAD_VAL ((50 * 32768) / 1000) #define WDG_LOAD_MASK GENMASK(15, 0) #define WDG_UNLOCK_KEY 0xe551 From patchwork Thu Aug 26 09:15:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 503018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7C2C4320E for ; Thu, 26 Aug 2021 09:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9275610A3 for ; Thu, 26 Aug 2021 09:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241019AbhHZJRT (ORCPT ); Thu, 26 Aug 2021 05:17:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241016AbhHZJRO (ORCPT ); Thu, 26 Aug 2021 05:17:14 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54123C0617A8; Thu, 26 Aug 2021 02:16:27 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id z24-20020a17090acb1800b0018e87a24300so1949568pjt.0; Thu, 26 Aug 2021 02:16:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L3k81M1U8IPFSz98hjzAzxK/MacZrQJoEq89TXnAhpU=; b=nL3j1OKocvOFpouDzx/sgrajh3gvc+583g/kg/hV4LF4OxNxXHwef59efhudULAfUp 3b+0ZlveJNZtcG6GXaddd+5quMbS84RCyk9KBIkrc7dRxonld+WRPpqfQ3Mu4DkN3TeA c3litQMHg3e+30zuLv3rFZ+nEHNLjO90n0NFwen7lDSjr3CgxS9YKb95Hj/dvsjak/9V Ky3TsjBCXR/WzBF+IgJO3AC6SvfYoXALsDtTnJ6RJU/E/zOO/rW601jmPQpiejCu9YgR 0/AhSW+iEvuXC2zdh0GbsymB45wuzviv5/faFBuodV5yiU8q6JUlwKMWjD9ctU8Nrsyw HBJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L3k81M1U8IPFSz98hjzAzxK/MacZrQJoEq89TXnAhpU=; b=WiVibrUxCDJjcBlk4Ufm/oPcb4GbW9v2i9dBqe27U9DItURZildf5bgdJ68N8BEb9h ouar6yOCNzs6kYTBJsaAg65RpK7VPMZltd+hVZQuNprPsWOQ43zqjV6WVuaEVsrnaQF4 p5NLGblcLz7RwDW8+Mb5a8JdFO8qyx7yMUL76vK7yxFHLqIVpGN8YuQnV/8hxqmanHHp J7U427b3IRC1mLxYoehFU5YIpGoVtyvpXav6+9NvqKvYaa63hs4G9xBkfe+Kae05vX0o tKH3yMRwP43cfrN4fe3BxDJZM/FWK1O1tTkje72bBA046P8qd7dxgMOZeVPyEaCdJ7yS xcmw== X-Gm-Message-State: AOAM531oPW1Oz06Vvu1PFG3SGmmMPOzx2fPkdlUWpG1SVb45sH2+hZg9 aTRhihIHVf/Pi49jlLiDwofx+jhL/Yw= X-Google-Smtp-Source: ABdhPJzEc1OjEcm3ev5ych4oDsTQNWyOv6H1KlqiBq+Yf7weQoDYQ6nOSvh6Vqgz+KfCXvdo77/jzQ== X-Received: by 2002:a17:902:7d90:b0:134:d977:22de with SMTP id a16-20020a1709027d9000b00134d97722demr2834377plm.30.1629969386840; Thu, 26 Aug 2021 02:16:26 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j20sm2777569pgb.2.2021.08.26.02.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 02:16:26 -0700 (PDT) From: Chunyan Zhang To: Mark Brown Cc: linux-spi@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , Luting Guo , LKML Subject: [PATCH V3 3/4] dt-bindings: spi: Convert sprd ADI bindings to yaml Date: Thu, 26 Aug 2021 17:15:48 +0800 Message-Id: <20210826091549.2138125-4-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210826091549.2138125-1-zhang.lyra@gmail.com> References: <20210826091549.2138125-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chunyan Zhang Convert spi-sprd-adi.txt to yaml. Signed-off-by: Chunyan Zhang Reviewed-by: Rob Herring --- .../devicetree/bindings/spi/spi-sprd-adi.txt | 63 ----------- .../devicetree/bindings/spi/sprd,spi-adi.yaml | 102 ++++++++++++++++++ 2 files changed, 102 insertions(+), 63 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/spi-sprd-adi.txt create mode 100644 Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml diff --git a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt deleted file mode 100644 index 2567c829e2dc..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt +++ /dev/null @@ -1,63 +0,0 @@ -Spreadtrum ADI controller - -ADI is the abbreviation of Anolog-Digital interface, which is used to access -analog chip (such as PMIC) from digital chip. ADI controller follows the SPI -framework for its hardware implementation is alike to SPI bus and its timing -is compatile to SPI timing. - -ADI controller has 50 channels including 2 software read/write channels and -48 hardware channels to access analog chip. For 2 software read/write channels, -users should set ADI registers to access analog chip. For hardware channels, -we can configure them to allow other hardware components to use it independently, -which means we can just link one analog chip address to one hardware channel, -then users can access the mapped analog chip address by this hardware channel -triggered by hardware components instead of ADI software channels. - -Thus we introduce one property named "sprd,hw-channels" to configure hardware -channels, the first value specifies the hardware channel id which is used to -transfer data triggered by hardware automatically, and the second value specifies -the analog chip address where user want to access by hardware components. - -Since we have multi-subsystems will use unique ADI to access analog chip, when -one system is reading/writing data by ADI software channels, that should be under -one hardware spinlock protection to prevent other systems from reading/writing -data by ADI software channels at the same time, or two parallel routine of setting -ADI registers will make ADI controller registers chaos to lead incorrect results. -Then we need one hardware spinlock to synchronize between the multiple subsystems. - -The new version ADI controller supplies multiple master channels for different -subsystem accessing, that means no need to add hardware spinlock to synchronize, -thus change the hardware spinlock support to be optional to keep backward -compatibility. - -Required properties: -- compatible: Should be "sprd,sc9860-adi". -- reg: Offset and length of ADI-SPI controller register space. -- #address-cells: Number of cells required to define a chip select address - on the ADI-SPI bus. Should be set to 1. -- #size-cells: Size of cells required to define a chip select address size - on the ADI-SPI bus. Should be set to 0. - -Optional properties: -- hwlocks: Reference to a phandle of a hwlock provider node. -- hwlock-names: Reference to hwlock name strings defined in the same order - as the hwlocks, should be "adi". -- sprd,hw-channels: This is an array of channel values up to 49 channels. - The first value specifies the hardware channel id which is used to - transfer data triggered by hardware automatically, and the second - value specifies the analog chip address where user want to access - by hardware components. - -SPI slave nodes must be children of the SPI controller node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - adi_bus: spi@40030000 { - compatible = "sprd,sc9860-adi"; - reg = <0 0x40030000 0 0x10000>; - hwlocks = <&hwlock1 0>; - hwlock-names = "adi"; - #address-cells = <1>; - #size-cells = <0>; - sprd,hw-channels = <30 0x8c20>; - }; diff --git a/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml b/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml new file mode 100644 index 000000000000..3e399d31168b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/sprd,spi-adi.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Spreadtrum ADI controller + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +description: | + ADI is the abbreviation of Anolog-Digital interface, which is used to access + analog chip (such as PMIC) from digital chip. ADI controller follows the SPI + framework for its hardware implementation is alike to SPI bus and its timing + is compatile to SPI timing. + + ADI controller has 50 channels including 2 software read/write channels and + 48 hardware channels to access analog chip. For 2 software read/write channels, + users should set ADI registers to access analog chip. For hardware channels, + we can configure them to allow other hardware components to use it independently, + which means we can just link one analog chip address to one hardware channel, + then users can access the mapped analog chip address by this hardware channel + triggered by hardware components instead of ADI software channels. + + Thus we introduce one property named "sprd,hw-channels" to configure hardware + channels, the first value specifies the hardware channel id which is used to + transfer data triggered by hardware automatically, and the second value specifies + the analog chip address where user want to access by hardware components. + + Since we have multi-subsystems will use unique ADI to access analog chip, when + one system is reading/writing data by ADI software channels, that should be under + one hardware spinlock protection to prevent other systems from reading/writing + data by ADI software channels at the same time, or two parallel routine of setting + ADI registers will make ADI controller registers chaos to lead incorrect results. + Then we need one hardware spinlock to synchronize between the multiple subsystems. + + The new version ADI controller supplies multiple master channels for different + subsystem accessing, that means no need to add hardware spinlock to synchronize, + thus change the hardware spinlock support to be optional to keep backward + compatibility. + +allOf: + - $ref: /spi/spi-controller.yaml# + +properties: + compatible: + enum: + - sprd,sc9860-adi + + reg: + maxItems: 1 + + hwlocks: + maxItems: 1 + + hwlock-names: + const: adi + + sprd,hw-channels: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: A list of hardware channels + minItems: 1 + maxItems: 48 + items: + items: + - description: The hardware channel id which is used to transfer data + triggered by hardware automatically, channel id 0-1 are for software + use, 2-49 are hardware channels. + minimum: 2 + maximum: 49 + - description: The analog chip address where user want to access by + hardware components. + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + aon { + #address-cells = <2>; + #size-cells = <2>; + + adi_bus: spi@40030000 { + compatible = "sprd,sc9860-adi"; + reg = <0 0x40030000 0 0x10000>; + hwlocks = <&hwlock1 0>; + hwlock-names = "adi"; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <30 0x8c20>; + }; + }; +...