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Wed, 25 Aug 2021 18:10:05 -0700 Received: from elite-desk-aura.lan (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2242.12 via Frontend Transport; Wed, 25 Aug 2021 20:10:03 -0500 From: Aurabindo Pillai To: CC: , , , , Subject: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Date: Wed, 25 Aug 2021 21:09:59 -0400 Message-ID: <20210826011002.425361-1-aurabindo.pillai@amd.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5210b775-15b1-4f17-7ab0-08d9682e3e7a X-MS-TrafficTypeDiagnostic: DM5PR1201MB0091: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sauyYXS8xgQ1CR6glS2eucLmr7bJvtHB0X+Xsy0SiCjvxCCeTtfe8QpIml+e/2AevLKupf457rMge1h+pf1UfWD2rWSoZ7S1JVsoPrtBMWOVHd3+rYBrjlnj6Eho16R8ckHFs4RoyOQnBZWujE06lZSeuJ4+P1a+swVcxhlvDt8/2e3DKVE5LwKgbK1+sSEEEboaDbfwljk5WHRo4gKeOdbOIth+1BZI0slzAfdIx6IrxW60JurWEiLMvHtTPgQ9KvuDu0GrZ+VGCFbQbdd8Gw7cJrXbIDbU5kHsG+sBPPuLTlOsUzyeNTPfHVEBzloHrrwlZgHaQs8ssPrLTsatkyaPUU3SsxbgmjH7qkvr7VZ0JK82TUcAIbVmtrqVHPPNwCfELjXcEF9xQGk7y7mfdXbswKnblMkffy2o3dglZIq6ZznZhvmeOUi/RZXQarYu6L4w4S6uE8f0ko12HxoPX74V9lpKuLpIo8kefL5RDTd7Vm7njQtppDRFNXFH5ZeFU+sRO/Psy1IuRN0QXXEvvFXONk2IC1QbFT0HomyEoJLqSCyZTWV1PsjRCEA8Kntj4afgs0fiXpNI1npqqhaVj01FHyk6K/8LuOohxJUu99i31nNcZvQaVYbP7V6FdZUm/6YzQw0cg6K6W1iCQoDOL/1M+7GW34j4DoAEA8TrLFaaO1QnoXBEho/T8acfuXeitTRCGlcBYCEHIpVUX8yKzjK95VMZ4wGW76Pw5WgKhQiI7PYT2dfi7IDe/7eOZjqvtGNtzDJojYP1ugVTLGiSDQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(376002)(136003)(396003)(346002)(39860400002)(46966006)(36840700001)(426003)(1076003)(54906003)(26005)(81166007)(4744005)(2616005)(86362001)(316002)(4326008)(8936002)(44832011)(2906002)(5660300002)(36860700001)(70586007)(336012)(70206006)(186003)(83380400001)(8676002)(6916009)(6666004)(82310400003)(82740400003)(36756003)(478600001)(47076005)(356005)(117716001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2021 01:10:07.2846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5210b775-15b1-4f17-7ab0-08d9682e3e7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0091 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org [Why & How] The DCN3 SoC parameter num_states was calculated but not saved into the object. Signed-off-by: Aurabindo Pillai Cc: stable@vger.kernel.org --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index 1333f0541f1b..43ac6f42dd80 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } + dcn3_0_soc.num_states = num_states; for (i = 0; i < dcn3_0_soc.num_states; i++) { dcn3_0_soc.clock_limits[i].state = i; dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; From patchwork Thu Aug 26 01:10:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurabindo Pillai X-Patchwork-Id: 503766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F02AC4320E for ; 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Wed, 25 Aug 2021 20:10:05 -0500 From: Aurabindo Pillai To: CC: , , , , "Jerry (Fangzhi) Zuo" , Subject: [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Date: Wed, 25 Aug 2021 21:10:00 -0400 Message-ID: <20210826011002.425361-2-aurabindo.pillai@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210826011002.425361-1-aurabindo.pillai@amd.com> References: <20210826011002.425361-1-aurabindo.pillai@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4b5ee877-601c-4bc7-a060-08d9682e3f28 X-MS-TrafficTypeDiagnostic: DM5PR12MB1691: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k7rUjZaFBEoRY/EAtJsinAB7WqerQvWUajVQEAgbo59Dsfz1qJKhFua+2TiQEwBqvbfgJP8enKdEi9XBE+hd9y0Gwm7pN+weDhWH8WvCPJ8toVsPoSUcMf3Ikdkg8So4fkgc1/LrWHREF6LTEJauZGn2cJF2mxw2tLEM2JPYrC7Hzn6Oes2NtK/p7Q4g9BqHk97SZ1UgrSMgJiPW24+ukhZdZG8kiOR2Q4WVXIPrOYoaO5iCm3KZdGf3PAn47+jndFs2WDjKRIcXZOorAAemGZzu+5J+rnFAKXGPiYWVsfa7L1bxco8ECrp+zn6c2A/ZR1CdKo3CUylI0cGpY7XgM+atcT2pR1x5Vk1EsyHyQjtefGH9d3Q8nN2EMMyQeKnKcsMlXda2LXrHczDnl2aoVNgMgWX2Lbd9GzG1sr0rSFBfR0TYBvFXsZLHFZbbx0EkAgll3T6rTqIwH2KJmMOgLuOCgwLY5EOkOTOvX4mmG2OcN+XKziZ3DnVdYjSb9fWAMpgRtZLNFK4j2ljLfyrE6ILl+uPgKHb6BYAMKipfA+SyBIBmiZSb3ljBLqu0k2Kq95QQx18fnKQ3NJq72zS7u78mnf5vRb3d4Crha0M8jvidWasEQbW9VGgEmucixeUbYoQSlUC2kBzQegXDn68Ua/hS52RoGQMBm3nY8+NcS+IYo4jUvFToswjm+3od7OmqWBU63vGeFSkP5suleUswvdNEH0n7I5wkaCorLFwL0UGKDKqRxYqLO2SceqJVgm17LKhNlweatSRqWue3pyMR3w== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(39860400002)(136003)(346002)(396003)(376002)(46966006)(36840700001)(70206006)(26005)(36756003)(82740400003)(6666004)(1076003)(70586007)(47076005)(2616005)(8936002)(6916009)(44832011)(82310400003)(36860700001)(81166007)(8676002)(356005)(83380400001)(426003)(186003)(336012)(4326008)(2906002)(86362001)(316002)(54906003)(5660300002)(478600001)(117716001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2021 01:10:08.4169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b5ee877-601c-4bc7-a060-08d9682e3f28 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1691 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: "Jerry (Fangzhi) Zuo" [Why] Drop hardcoded dispclk, dppclk, phyclk [How] Read the corresponding values from clock table entries already populated. Signed-off-by: Jerry (Fangzhi) Zuo Signed-off-by: Aurabindo Pillai Cc: stable@vger.kernel.org --- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 41 ++++++++++++++----- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index 43ac6f42dd80..3d2443328345 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -2398,16 +2398,37 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; if (bw_params->clk_table.entries[0].memclk_mhz) { + int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; + + for (i = 0; i < MAX_NUM_DPM_LVL; i++) { + if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) + max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; + if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; + if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; + if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) + max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; + } + + if (!max_dcfclk_mhz) + max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; + if (!max_dispclk_mhz) + max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; + if (!max_dppclk_mhz) + max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; + if (!max_phyclk_mhz) + max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; - if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array - dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz; + dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; num_dcfclk_sta_targets++; - } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates for (i = 0; i < num_dcfclk_sta_targets; i++) { - if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) { - dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz; + if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { + dcfclk_sta_targets[i] = max_dcfclk_mhz; break; } } @@ -2447,7 +2468,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { - if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) { + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } else { @@ -2462,7 +2483,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params } while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && - optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) { + optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } @@ -2475,9 +2496,9 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; /* Fill all states with max values of all other clocks */ - dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz; - dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz; - dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz; + dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; + dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; + dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */