From patchwork Tue May 23 14:23:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100376 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp1898356obb; Tue, 23 May 2017 07:25:04 -0700 (PDT) X-Received: by 10.98.34.22 with SMTP id i22mr32698412pfi.103.1495549504694; Tue, 23 May 2017 07:25:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495549504; cv=none; d=google.com; s=arc-20160816; b=hycosOi8PaqABtjySlG2G1wC7q2kuMAdUR7ZCdv7ic1mKb5RITSfUysTLjIQkLDj9j fS8R6SD0Eu0RbVwu0X6VZidJ9EWmGfc8+sFciPgGgcFlwRGvJKxT4sAl9FvbjgDgeS5e 7bJ6SQ/kWSLj6fHxjePbIHZYMhaVz4s7DgkmMfdT7GvSU6z2VbpgBg8lZFKO2ecKU4A1 Br22lYUAt4g6nU6d4WpGp0rAOoIJe+Ao705swbKfC5L/524d1ben7RVy+TKdmTZBA3pk MIfGsrrUaJKV7FpwarR8PZinCvwIdAEURGBJNNvEdCN/sL6Sk9HolEXrH+rvU/ih2fZ3 sa7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=OmiBUa+HVg33No2UUgR98hp+y7+Jf9Oo7VujSFJnIRo=; b=S/AXYhMUMqq1pC4q7TmG9DeXcFuhZivcVWMfC43TzAn8aEoOIG+WZ72XTJcYFLTsyR M7due489ahBQLLaC120YQ0NeFACIiepWjZbNiYP7KgAEO3dRbs6bTpNwR126NOORELnn vhHaLbP4Chi6bYZZsImSGLuiBdoierXCC0hnQ7IYlSJLPr3i6ujs7ocHzXa/O1o/y8Sq YVvkR4olNOfjHytpYxiTf482usUEXgRNhNuSdKAaxRs8S88TNNlmdpSmhVeSnmcgVhKs 3i8AfIX5/S7TFbXzM6hP8PenCj534+8sCzaFSOdGtTNPWpzepVxTp/gDx8AmDLEvlkpi SmTA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 7si20707328pll.337.2017.05.23.07.25.04; Tue, 23 May 2017 07:25:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764233AbdEWOYl (ORCPT + 25 others); Tue, 23 May 2017 10:24:41 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6448 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762191AbdEWOYe (ORCPT ); Tue, 23 May 2017 10:24:34 -0400 Received: from 172.30.72.55 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOE00902; Tue, 23 May 2017 22:24:25 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Tue, 23 May 2017 22:24:15 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v5 1/2] PCI/portdrv: add support for different MSI interrupts for PCIe port services Date: Tue, 23 May 2017 15:23:58 +0100 Message-ID: <1495549439-10372-2-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495549439-10372-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495549439-10372-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.59244619.024D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: be99c95b7adfa2dfea9835f74bfd24f8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently PCIe port services are assigned with different interrutps only if MSI-x are supported by calling pcie_port_enable_msix(). If a root port supports MSI instead of MSI-x currently we fall back to use a single shared interrupt for all the services. This patch renames and extends pcie_port_enable_msix() to use MSI in case MSI-x allocation fails. Signed-off-by: Gabriele Paoloni Reviewed-by: Christoph Hellwig --- drivers/pci/pcie/portdrv.h | 8 +++++--- drivers/pci/pcie/portdrv_core.c | 38 ++++++++++++++++++++------------------ 2 files changed, 25 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 587aef3..1993e2c 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -13,10 +13,12 @@ #define PCIE_PORT_DEVICE_MAXSERVICES 5 /* - * According to the PCI Express Base Specification 2.0, the indices of - * the MSI-X table entries used by port services must not exceed 31 + * According to the PCI Express Base Specification REV. 3.1 and according + * to the PCI Local Bus Specification REV. 3.0 respectively, the indices of + * the MSI-X table entries or the max number of MSI vectors used by port + * services must not exceed 31 */ -#define PCIE_PORT_MAX_MSIX_ENTRIES 32 +#define PCIE_PORT_MAX_MSI_ENTRIES 32 #define get_descriptor_id(type, service) (((type - 4) << 8) | service) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index cea504f..07d8e01 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -44,14 +44,15 @@ static void release_pcie_device(struct device *dev) } /** - * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port + * pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode + * for given port * @dev: PCI Express port to handle * @irqs: Array of interrupt vectors to populate * @mask: Bitmask of port capabilities returned by get_port_device_capability() * * Return value: 0 on success, error code on failure */ -static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) +static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) { int nr_entries, entry, nvec = 0; @@ -61,8 +62,8 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * equal to the number of entries this port actually uses, we'll happily * go through without any tricks. */ - nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES, - PCI_IRQ_MSIX); + nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES, + PCI_IRQ_MSIX | PCI_IRQ_MSI); if (nr_entries < 0) return nr_entries; @@ -77,7 +78,9 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * Number field in the PCI Express Capabilities register", where * according to Section 7.8.2 of the specification "For MSI-X, * the value in this field indicates which MSI-X Table entry is - * used to generate the interrupt message." + * used to generate the interrupt message." and "For MSI, the + * value in this field indicates the offset between the base + * Message Data and the interrupt message that is generated." */ pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16); entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; @@ -100,7 +103,9 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * MSI/MSI-X vectors assigned to the port is going to be used * for AER, where "For MSI-X, the value in this register * indicates which MSI-X Table entry is used to generate the - * interrupt message." + * interrupt message." and "For MSI, the value + * in this field indicates the offset between the base Message + * Data and the interrupt message that is generated." */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32); @@ -124,7 +129,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) /* Now allocate the MSI-X vectors for real */ nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec, - PCI_IRQ_MSIX); + PCI_IRQ_MSIX | PCI_IRQ_MSI); if (nr_entries < 0) return nr_entries; } @@ -146,26 +151,23 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) */ static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask) { - unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI; int ret, i; for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) irqs[i] = -1; /* - * If MSI cannot be used for PCIe PME or hotplug, we have to use - * INTx or other interrupts, e.g. system shared interrupt. + * Make sure MSI can be used for PCIe PME or hotplug. otherwise we have + * to use INTx or other interrupts, e.g. system shared interrupt. */ - if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) || - ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) { - flags &= ~PCI_IRQ_MSI; - } else { - /* Try to use MSI-X if supported */ - if (!pcie_port_enable_msix(dev, irqs, mask)) + if (!((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) && + !((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) + /* Try to use MSI-X or MSI if supported */ + if (!pcie_port_enable_irq_vec(dev, irqs, mask)) return 0; - } - ret = pci_alloc_irq_vectors(dev, 1, 1, flags); + /* fall back to legacy IRQ */ + ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); if (ret < 0) return -ENODEV; From patchwork Tue May 23 14:23:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100377 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp1898362obb; Tue, 23 May 2017 07:25:05 -0700 (PDT) X-Received: by 10.98.103.87 with SMTP id b84mr33025214pfc.235.1495549505194; Tue, 23 May 2017 07:25:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495549505; cv=none; d=google.com; s=arc-20160816; b=tOX2tqFBmlYSIec8l9K9R5mZytOueIL3scFu4q8PPcfKmTv2Qzv4ort1nEPsUFnBAS /wjmaRD0aH6bjMmEZoz5FETRmIgouFHu9BIfpiOVXa/+3ELXItnFw8Qokq4SIs1blrJ0 LPx9v6OTHOtxSYRVglEHyHBGQD3x8O8CpkqUw9Ks4BAT3ZNRB2P7lhVr+s3rGQsIOrZb bj1y3ssswru6DhYysuHWoTEFNrIfGUhgD9UrwmLg0Dz0mQf1oh/1AthzsOdF5AZ91VFT q+y0pSW/CkfGQB+rSYd7Tm3QQJAibCX6ueUaa2CPcjWsFM45iI/6SRcbvhCwSCvt+pcb myDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; 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[209.132.180.67]) by mx.google.com with ESMTP id 7si20707328pll.337.2017.05.23.07.25.04; Tue, 23 May 2017 07:25:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965358AbdEWOYo (ORCPT + 25 others); Tue, 23 May 2017 10:24:44 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6449 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762279AbdEWOYf (ORCPT ); Tue, 23 May 2017 10:24:35 -0400 Received: from 172.30.72.55 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOE00903; Tue, 23 May 2017 22:24:25 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Tue, 23 May 2017 22:24:19 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v5 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Tue, 23 May 2017 15:23:59 +0100 Message-ID: <1495549439-10372-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495549439-10372-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495549439-10372-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.59244619.03B7, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7a5d69a707038fced6c25efec7d04873 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni Reviewed-by: Christoph Hellwig --- drivers/pci/pcie/portdrv_core.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.7.4 diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 07d8e01..8e6320e 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -118,6 +118,31 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the