From patchwork Sun Aug 29 19:36:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 463CAC4320E for ; Sun, 29 Aug 2021 19:36:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 26E7560F44 for ; Sun, 29 Aug 2021 19:36:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234080AbhH2ThV (ORCPT ); Sun, 29 Aug 2021 15:37:21 -0400 Received: from m-r2.th.seeweb.it ([5.144.164.171]:41439 "EHLO m-r2.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233841AbhH2ThU (ORCPT ); Sun, 29 Aug 2021 15:37:20 -0400 Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 2E7E93E83D; Sun, 29 Aug 2021 21:36:26 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v2 3/9] clk: qcom: gcc-msm8994: Fix up SPI QUP clocks Date: Sun, 29 Aug 2021 21:36:10 +0200 Message-Id: <20210829193617.4105-3-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix up SPI QUP freq tables to account for the fact that not every QUP can run at the same set of frequencies. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 118 +++++++++++++++++++++++++++++---- 1 file changed, 105 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 8e9a8ebadf73..78c06104854e 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -169,7 +169,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { }, }; -static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = { +static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { F(960000, P_XO, 10, 1, 2), F(4800000, P_XO, 4, 0, 0), F(9600000, P_XO, 2, 0, 0), @@ -187,7 +187,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -209,12 +209,25 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(42860000, P_GPLL0, 14, 0, 0), + F(46150000, P_GPLL0, 13, 0, 0), + { } +}; + static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .cmd_rcgr = 0x06cc, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -236,12 +249,25 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(42860000, P_GPLL0, 14, 0, 0), + F(44440000, P_GPLL0, 13.5, 0, 0), + { } +}; + static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .cmd_rcgr = 0x074c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -268,7 +294,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -290,12 +316,25 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(40000000, P_GPLL0, 15, 0, 0), + F(42860000, P_GPLL0, 14, 0, 0), + { } +}; + static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .cmd_rcgr = 0x084c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -317,12 +356,25 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(27906976, P_GPLL0, 1, 2, 43), + F(41380000, P_GPLL0, 15, 0, 0), + F(42860000, P_GPLL0, 14, 0, 0), + { } +}; + static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .cmd_rcgr = 0x08cc, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -447,12 +499,25 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(42860000, P_GPLL0, 14, 0, 0), + F(44440000, P_GPLL0, 13.5, 0, 0), + { } +}; + static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .cmd_rcgr = 0x098c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -479,7 +544,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -488,6 +553,19 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(42860000, P_GPLL0, 14, 0, 0), + F(48000000, P_GPLL0, 12.5, 0, 0), + { } +}; + static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .cmd_rcgr = 0x0aa0, .hid_width = 5, @@ -506,7 +584,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -533,7 +611,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -560,7 +638,8 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */ + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, @@ -582,12 +661,25 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { }, }; +static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 12.5, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(44440000, P_GPLL0, 13.5, 0, 0), + F(48000000, P_GPLL0, 12.5, 0, 0), + { } +}; + static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .cmd_rcgr = 0x0c0c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0_map, - .freq_tbl = ftbl_blspqup_spi_apps_clk_src, + .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", .parent_data = gcc_xo_gpll0, From patchwork Sun Aug 29 19:36:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2FA9C4320E for ; Sun, 29 Aug 2021 19:36:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CADBD60C3E for ; Sun, 29 Aug 2021 19:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230459AbhH2ThX (ORCPT ); Sun, 29 Aug 2021 15:37:23 -0400 Received: from m-r2.th.seeweb.it ([5.144.164.171]:32909 "EHLO m-r2.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234527AbhH2ThW (ORCPT ); Sun, 29 Aug 2021 15:37:22 -0400 Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 672FD3E857; Sun, 29 Aug 2021 21:36:27 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH RESEND v2 4/9] clk: qcom: gcc-msm8994: Add missing NoC clocks Date: Sun, 29 Aug 2021 21:36:11 +0200 Message-Id: <20210829193617.4105-4-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add necessary NoC clocks to provide frequency sources for relevant branch clocks. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 101 ++++++++++++++++--- include/dt-bindings/clock/qcom,gcc-msm8994.h | 3 + 2 files changed, 92 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 78c06104854e..629ab6ab455f 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -106,6 +106,42 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { { .hw = &gpll4.clkr.hw }, }; +static struct clk_rcg2 system_noc_clk_src = { + .cmd_rcgr = 0x0120, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 config_noc_clk_src = { + .cmd_rcgr = 0x0150, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "config_noc_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 periph_noc_clk_src = { + .cmd_rcgr = 0x0190, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "periph_noc_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + static struct freq_tbl ftbl_ufs_axi_clk_src[] = { F(50000000, P_GPLL0, 12, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), @@ -1089,6 +1125,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1372,6 +1410,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1699,6 +1739,8 @@ static struct clk_branch gcc_lpass_q6_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_lpass_q6_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1711,6 +1753,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1738,6 +1782,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1750,6 +1797,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_mstr_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1779,6 +1829,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_slv_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1806,6 +1859,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1818,6 +1874,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_mstr_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1846,6 +1905,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_slv_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1873,6 +1935,8 @@ static struct clk_branch gcc_pdm_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1900,10 +1964,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1916,10 +1979,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1947,10 +2009,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1978,10 +2039,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2039,6 +2099,8 @@ static struct clk_branch gcc_tsif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2066,6 +2128,8 @@ static struct clk_branch gcc_ufs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2109,6 +2173,8 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_0_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2122,6 +2188,8 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_1_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2150,6 +2218,8 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_0_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2163,6 +2233,8 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_1_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2254,6 +2326,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hs_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2331,6 +2405,9 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL4_EARLY] = &gpll4_early.clkr, [GPLL4] = &gpll4.clkr, + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 507b8d6effd2..219d5441c0fa 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -148,6 +148,9 @@ #define GCC_USB30_SLEEP_CLK 138 #define GCC_USB_HS_AHB_CLK 139 #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 +#define CONFIG_NOC_CLK_SRC 141 +#define PERIPH_NOC_CLK_SRC 142 +#define SYSTEM_NOC_CLK_SRC 143 /* GDSCs */ #define PCIE_GDSC 0 From patchwork Sun Aug 29 19:36:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37922C4320E for ; Sun, 29 Aug 2021 19:36:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FD4D60F25 for ; Sun, 29 Aug 2021 19:36:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235946AbhH2Th0 (ORCPT ); Sun, 29 Aug 2021 15:37:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235902AbhH2ThY (ORCPT ); Sun, 29 Aug 2021 15:37:24 -0400 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [IPv6:2001:4b7a:2000:18::168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90C91C06175F for ; Sun, 29 Aug 2021 12:36:31 -0700 (PDT) Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 2B09A3E81B; Sun, 29 Aug 2021 21:36:29 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH RESEND v2 5/9] clk: qcom: gcc-msm8994: Add missing clocks Date: Sun, 29 Aug 2021 21:36:12 +0200 Message-Id: <20210829193617.4105-5-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This should be the last "add missing clocks" commit, as to my knowledge there are no more clocks registered within gcc. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 134 +++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8994.h | 9 ++ 2 files changed, 143 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 629ab6ab455f..98b2fd429629 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -2319,6 +2319,19 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { }, }; +static struct clk_branch gcc_usb3_phy_pipe_clk = { + .halt_reg = 0x140c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x140c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb_hs_ahb_clk = { .halt_reg = 0x0488, .clkr = { @@ -2360,6 +2373,118 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { }, }; +static struct clk_branch gpll0_out_mmsscc = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_mmsscc", + .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpll0_out_msscc = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_msscc", + .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch pcie_0_phy_ldo = { + .halt_reg = 0x1e00, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E00, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pcie_0_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch pcie_1_phy_ldo = { + .halt_reg = 0x1e04, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E04, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pcie_1_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ufs_phy_ldo = { + .halt_reg = 0x1e0c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E0C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "ufs_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch usb_ss_phy_ldo = { + .halt_reg = 0x1e08, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E08, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "usb_ss_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x0e04, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x0e04, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x0d04, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_gdsc = { .gdscr = 0x1e18, .pd = { @@ -2542,9 +2667,18 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, + [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, + [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, + [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, + [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, + [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, }; static struct gdsc *gcc_msm8994_gdscs[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 219d5441c0fa..dcb49817dcec 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -151,6 +151,15 @@ #define CONFIG_NOC_CLK_SRC 141 #define PERIPH_NOC_CLK_SRC 142 #define SYSTEM_NOC_CLK_SRC 143 +#define GPLL0_OUT_MMSSCC 144 +#define GPLL0_OUT_MSSCC 145 +#define PCIE_0_PHY_LDO 146 +#define PCIE_1_PHY_LDO 147 +#define UFS_PHY_LDO 148 +#define USB_SS_PHY_LDO 149 +#define GCC_BOOT_ROM_AHB_CLK 150 +#define GCC_PRNG_AHB_CLK 151 +#define GCC_USB3_PHY_PIPE_CLK 152 /* GDSCs */ #define PCIE_GDSC 0 From patchwork Sun Aug 29 19:36:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCFE8C432BE for ; Sun, 29 Aug 2021 19:36:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF06860ED8 for ; Sun, 29 Aug 2021 19:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236011AbhH2The (ORCPT ); Sun, 29 Aug 2021 15:37:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235920AbhH2ThZ (ORCPT ); Sun, 29 Aug 2021 15:37:25 -0400 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [IPv6:2001:4b7a:2000:18::168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA979C061756 for ; Sun, 29 Aug 2021 12:36:32 -0700 (PDT) Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id A6A3F3E83D; Sun, 29 Aug 2021 21:36:30 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v2 6/9] clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE Date: Sun, 29 Aug 2021 21:36:13 +0200 Message-Id: <20210829193617.4105-6-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This GDSC is not present on msm8994. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 98b2fd429629..2ed206ecb60d 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -2485,14 +2485,6 @@ static struct clk_branch gcc_prng_ahb_clk = { }, }; -static struct gdsc pcie_gdsc = { - .gdscr = 0x1e18, - .pd = { - .name = "pcie", - }, - .pwrsts = PWRSTS_OFF_ON, -}; - static struct gdsc pcie_0_gdsc = { .gdscr = 0x1ac4, .pd = { @@ -2682,7 +2674,8 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { }; static struct gdsc *gcc_msm8994_gdscs[] = { - [PCIE_GDSC] = &pcie_gdsc, + /* This GDSC does not exist, but ABI has to remain intact */ + [PCIE_GDSC] = NULL, [PCIE_0_GDSC] = &pcie_0_gdsc, [PCIE_1_GDSC] = &pcie_1_gdsc, [USB30_GDSC] = &usb30_gdsc, From patchwork Sun Aug 29 19:36:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A5EDC43216 for ; Sun, 29 Aug 2021 19:36:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83AA060C3E for ; Sun, 29 Aug 2021 19:36:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233976AbhH2Thc (ORCPT ); Sun, 29 Aug 2021 15:37:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235972AbhH2Th2 (ORCPT ); Sun, 29 Aug 2021 15:37:28 -0400 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B21AC061575 for ; Sun, 29 Aug 2021 12:36:35 -0700 (PDT) Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 435F83E81B; Sun, 29 Aug 2021 21:36:33 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v2 8/9] clk: qcom: gcc-msm8994: Add proper msm8992 support Date: Sun, 29 Aug 2021 21:36:15 +0200 Message-Id: <20210829193617.4105-8-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8992 is a cut-down version of MSM8994, featuring largely the same hardware. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 73 +++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 7545e973fd0d..72038e4c04df 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -218,6 +219,17 @@ static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { { } }; +static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0, 12, 1, 2), + F(50000000, P_GPLL0, 12, 0, 0), + { } +}; + static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .cmd_rcgr = 0x064c, .mnd_width = 8, @@ -974,6 +986,18 @@ static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { { } }; +static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 15, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(50000000, P_GPLL0, 12, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(172000000, P_GPLL4, 2, 0, 0), + F(344000000, P_GPLL4, 1, 0, 0), + { } +}; + static struct clk_rcg2 sdcc1_apps_clk_src = { .cmd_rcgr = 0x04d0, .mnd_width = 8, @@ -2710,13 +2734,60 @@ static const struct qcom_cc_desc gcc_msm8994_desc = { }; static const struct of_device_id gcc_msm8994_match_table[] = { - { .compatible = "qcom,gcc-msm8994" }, + { .compatible = "qcom,gcc-msm8992" }, + { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */ {} }; MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); static int gcc_msm8994_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; + + if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) { + /* MSM8992 features less clocks and some have different freq tables */ + gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL; + gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL; + gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL; + + sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992; + blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; + + /* + * Some 8992 boards might *possibly* use + * PCIe1 clocks and controller, but it's not + * standard and they should be disabled otherwise. + */ + gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL; + gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL; + gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL; + gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; + gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; + } + return qcom_cc_probe(pdev, &gcc_msm8994_desc); }