From patchwork Sun Aug 29 19:36:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B5B7C4320E for ; Sun, 29 Aug 2021 19:36:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D6F260F45 for ; Sun, 29 Aug 2021 19:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231956AbhH2ThS (ORCPT ); Sun, 29 Aug 2021 15:37:18 -0400 Received: from m-r2.th.seeweb.it ([5.144.164.171]:34517 "EHLO m-r2.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230459AbhH2ThS (ORCPT ); Sun, 29 Aug 2021 15:37:18 -0400 Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 8A9DC3E81B; Sun, 29 Aug 2021 21:36:22 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Rob Herring , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Date: Sun, 29 Aug 2021 21:36:08 +0200 Message-Id: <20210829193617.4105-1-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the MSM8994 GCC driver. Signed-off-by: Konrad Dybcio Acked-by: Rob Herring --- No changes since the original v2, only added Rob's A-b .../bindings/clock/qcom,gcc-msm8994.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml new file mode 100644 index 000000000000..b44a844d894c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8994 + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8994 and MSM8992. + + See also: + - dt-bindings/clock/qcom,gcc-msm8994.h + +maintainers: + - Stephen Boyd + - Taniya Das + +properties: + compatible: + enum: + - qcom,gcc-msm8992 + - qcom,gcc-msm8994 + + clocks: + items: + - description: XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8994"; + reg = <0x300000 0x90000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, <&sleep_clk>; + clock-names = "xo", "sleep"; + }; +... From patchwork Sun Aug 29 19:36:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7673DC43214 for ; Sun, 29 Aug 2021 19:36:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F9C560C3E for ; Sun, 29 Aug 2021 19:36:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231511AbhH2Th1 (ORCPT ); Sun, 29 Aug 2021 15:37:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233976AbhH2ThW (ORCPT ); Sun, 29 Aug 2021 15:37:22 -0400 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1075CC061575 for ; Sun, 29 Aug 2021 12:36:30 -0700 (PDT) Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 672FD3E857; Sun, 29 Aug 2021 21:36:27 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH RESEND v2 4/9] clk: qcom: gcc-msm8994: Add missing NoC clocks Date: Sun, 29 Aug 2021 21:36:11 +0200 Message-Id: <20210829193617.4105-4-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add necessary NoC clocks to provide frequency sources for relevant branch clocks. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 101 ++++++++++++++++--- include/dt-bindings/clock/qcom,gcc-msm8994.h | 3 + 2 files changed, 92 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 78c06104854e..629ab6ab455f 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -106,6 +106,42 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { { .hw = &gpll4.clkr.hw }, }; +static struct clk_rcg2 system_noc_clk_src = { + .cmd_rcgr = 0x0120, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 config_noc_clk_src = { + .cmd_rcgr = 0x0150, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "config_noc_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 periph_noc_clk_src = { + .cmd_rcgr = 0x0190, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "periph_noc_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), + .ops = &clk_rcg2_ops, + }, +}; + static struct freq_tbl ftbl_ufs_axi_clk_src[] = { F(50000000, P_GPLL0, 12, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), @@ -1089,6 +1125,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1372,6 +1410,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1699,6 +1739,8 @@ static struct clk_branch gcc_lpass_q6_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_lpass_q6_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1711,6 +1753,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1738,6 +1782,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1750,6 +1797,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_mstr_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1779,6 +1829,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_slv_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1806,6 +1859,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1818,6 +1874,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_mstr_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1846,6 +1905,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_slv_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1873,6 +1935,8 @@ static struct clk_branch gcc_pdm_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1900,10 +1964,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1916,10 +1979,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1947,10 +2009,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1978,10 +2039,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", - }, + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2039,6 +2099,8 @@ static struct clk_branch gcc_tsif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2066,6 +2128,8 @@ static struct clk_branch gcc_ufs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2109,6 +2173,8 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_0_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2122,6 +2188,8 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_1_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2150,6 +2218,8 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_0_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2163,6 +2233,8 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_1_clk", + .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2254,6 +2326,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hs_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -2331,6 +2405,9 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL4_EARLY] = &gpll4_early.clkr, [GPLL4] = &gpll4.clkr, + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 507b8d6effd2..219d5441c0fa 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -148,6 +148,9 @@ #define GCC_USB30_SLEEP_CLK 138 #define GCC_USB_HS_AHB_CLK 139 #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 +#define CONFIG_NOC_CLK_SRC 141 +#define PERIPH_NOC_CLK_SRC 142 +#define SYSTEM_NOC_CLK_SRC 143 /* GDSCs */ #define PCIE_GDSC 0 From patchwork Sun Aug 29 19:36:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FCBBC43216 for ; Sun, 29 Aug 2021 19:36:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6648D60C3E for ; Sun, 29 Aug 2021 19:36:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235942AbhH2Th0 (ORCPT ); Sun, 29 Aug 2021 15:37:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235868AbhH2ThY (ORCPT ); Sun, 29 Aug 2021 15:37:24 -0400 Received: from relay05.th.seeweb.it (relay05.th.seeweb.it [IPv6:2001:4b7a:2000:18::166]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 787BDC061575; Sun, 29 Aug 2021 12:36:31 -0700 (PDT) Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 2B09A3E81B; Sun, 29 Aug 2021 21:36:29 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH RESEND v2 5/9] clk: qcom: gcc-msm8994: Add missing clocks Date: Sun, 29 Aug 2021 21:36:12 +0200 Message-Id: <20210829193617.4105-5-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This should be the last "add missing clocks" commit, as to my knowledge there are no more clocks registered within gcc. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 134 +++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8994.h | 9 ++ 2 files changed, 143 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 629ab6ab455f..98b2fd429629 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -2319,6 +2319,19 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { }, }; +static struct clk_branch gcc_usb3_phy_pipe_clk = { + .halt_reg = 0x140c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x140c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb_hs_ahb_clk = { .halt_reg = 0x0488, .clkr = { @@ -2360,6 +2373,118 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { }, }; +static struct clk_branch gpll0_out_mmsscc = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_mmsscc", + .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpll0_out_msscc = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_msscc", + .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch pcie_0_phy_ldo = { + .halt_reg = 0x1e00, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E00, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pcie_0_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch pcie_1_phy_ldo = { + .halt_reg = 0x1e04, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E04, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pcie_1_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ufs_phy_ldo = { + .halt_reg = 0x1e0c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E0C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "ufs_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch usb_ss_phy_ldo = { + .halt_reg = 0x1e08, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1E08, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "usb_ss_phy_ldo", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x0e04, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x0e04, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x0d04, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1484, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_gdsc = { .gdscr = 0x1e18, .pd = { @@ -2542,9 +2667,18 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, + [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, + [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, + [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, + [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, + [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, }; static struct gdsc *gcc_msm8994_gdscs[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 219d5441c0fa..dcb49817dcec 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -151,6 +151,15 @@ #define CONFIG_NOC_CLK_SRC 141 #define PERIPH_NOC_CLK_SRC 142 #define SYSTEM_NOC_CLK_SRC 143 +#define GPLL0_OUT_MMSSCC 144 +#define GPLL0_OUT_MSSCC 145 +#define PCIE_0_PHY_LDO 146 +#define PCIE_1_PHY_LDO 147 +#define UFS_PHY_LDO 148 +#define USB_SS_PHY_LDO 149 +#define GCC_BOOT_ROM_AHB_CLK 150 +#define GCC_PRNG_AHB_CLK 151 +#define GCC_USB3_PHY_PIPE_CLK 152 /* GDSCs */ #define PCIE_GDSC 0 From patchwork Sun Aug 29 19:36:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FC6FC4320A for ; Sun, 29 Aug 2021 19:36:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A59E60F25 for ; Sun, 29 Aug 2021 19:36:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236017AbhH2Thb (ORCPT ); Sun, 29 Aug 2021 15:37:31 -0400 Received: from relay06.th.seeweb.it ([5.144.164.167]:55317 "EHLO relay06.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235930AbhH2Th0 (ORCPT ); Sun, 29 Aug 2021 15:37:26 -0400 Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id EDD553E850; Sun, 29 Aug 2021 21:36:31 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH RESEND v2 7/9] clk: qcom: gcc-msm8994: Add modem reset Date: Sun, 29 Aug 2021 21:36:14 +0200 Message-Id: <20210829193617.4105-7-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This will be required to support the modem. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-msm8994.c | 1 + include/dt-bindings/clock/qcom,gcc-msm8994.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 2ed206ecb60d..7545e973fd0d 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -2685,6 +2685,7 @@ static struct gdsc *gcc_msm8994_gdscs[] = { static const struct qcom_reset_map gcc_msm8994_resets[] = { [USB3_PHY_RESET] = { 0x1400 }, [USB3PHY_PHY_RESET] = { 0x1404 }, + [MSS_RESET] = { 0x1680 }, [PCIE_PHY_0_RESET] = { 0x1b18 }, [PCIE_PHY_1_RESET] = { 0x1b98 }, [QUSB2_PHY_RESET] = { 0x04b8 }, diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index dcb49817dcec..f6836f430bb5 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -174,5 +174,6 @@ #define PCIE_PHY_0_RESET 2 #define PCIE_PHY_1_RESET 3 #define QUSB2_PHY_RESET 4 +#define MSS_RESET 5 #endif From patchwork Sun Aug 29 19:36:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 504440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51E50C43214 for ; Sun, 29 Aug 2021 19:36:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 399F660F45 for ; Sun, 29 Aug 2021 19:36:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235977AbhH2The (ORCPT ); Sun, 29 Aug 2021 15:37:34 -0400 Received: from relay05.th.seeweb.it ([5.144.164.166]:44937 "EHLO relay05.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235976AbhH2Th3 (ORCPT ); Sun, 29 Aug 2021 15:37:29 -0400 Received: from localhost.localdomain (83.6.166.149.neoplus.adsl.tpnet.pl [83.6.166.149]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 8976C3E859; Sun, 29 Aug 2021 21:36:34 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Date: Sun, 29 Aug 2021 21:36:16 +0200 Message-Id: <20210829193617.4105-9-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210829193617.4105-1-konrad.dybcio@somainline.org> References: <20210829193617.4105-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some devices come with a different SDCC clock configuration, account for that. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index b44a844d894c..4ba2f72d3cad 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -49,6 +49,10 @@ properties: description: Protected clock specifier list as per common clock binding. + qcom,sdcc2-clk-src-40mhz: + description: SDCC2_APPS clock source runs at 40MHz. + type: boolean + required: - compatible - reg diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 72038e4c04df..55c0fd069640 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -1012,6 +1012,19 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { }, }; +static struct freq_tbl ftbl_sdcc2_40mhz_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 15, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(40000000, P_GPLL0, 15, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(80000000, P_GPLL0, 7.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(200000000, P_GPLL0, 3, 0, 0), + { } +}; + static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { F(144000, P_XO, 16, 3, 25), F(400000, P_XO, 12, 1, 4), @@ -2788,6 +2801,9 @@ static int gcc_msm8994_probe(struct platform_device *pdev) gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; } + if (of_find_property(dev->of_node, "qcom,sdcc2-clk-src-40mhz", NULL)) + sdcc2_apps_clk_src.freq_tbl = ftbl_sdcc2_40mhz_apps_clk_src; + return qcom_cc_probe(pdev, &gcc_msm8994_desc); }