From patchwork Fri Oct 12 14:42:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148770 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819271lji; Fri, 12 Oct 2018 07:42:40 -0700 (PDT) X-Google-Smtp-Source: ACcGV62e3i1DYGJBv2veX5ibRQf3ehplZSgwTlFiGjTBHwsSVKWFXjUKofvIifSHeZ9a7rztGJ15 X-Received: by 2002:a19:1147:: with SMTP id g68-v6mr4125996lfi.22.1539355360681; Fri, 12 Oct 2018 07:42:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355360; cv=none; d=google.com; s=arc-20160816; b=Gls5TVhJAbP9R9AEn9nvsmxE2sMCPcTBAGFX0Mb/ikQa3kaUsKgp2BDttcLZ/Cvcm+ 7mOfa1Fs5n7gQdECsKbISRANVPVSJ+rxqECTvj4r5kjir700fTmomTuuXdw+Ln50dIg6 xLv6Vt4xWTFkenQp/9+EHFdumJomllZAVhhxk6ZE9h/en/WlPKq6q5xlyC3YgWDJUich k/B7jYsig4If2PAneOlvvEGKlcpLkjmnoxVzDeJMs2oaGEeEkYn913OyedIWyGde0Uiv okchcFl4yErCFVDlmb0CdTgZC1JtRMesH1B6cgwMu3J8txhq3O/Mr3Wp2nUp0WZ8TCvU +Gig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=tlEhyYUCyTMXDXN6Dfk2vDOyKXMM5OHd4tq4KG9hpTg=; b=U4+PyRfjHGIV6omU9NXlZ3TqWTIQj6y1xKvIJFlFrDNCKOaE50bbCmLT5nmMZ8Mniq OyIsoL0y+UiIfN2W+EpZ1op67GI8PBFJw5ZeZSkDmJbrDfNSjuvbWB6qt+PnzTpxhMaS 9dYaQvy3qr1bInXpiWsgoBFXRmGsOQ00ROZXQ+UjYdfB0+rjGgKBH/UkMWGk27cEukbY wGtajJiWm1kJ7yqMq/O5QkbhlbJjS0Yyp6AFHyio1wO+l6WtHp75XErUSDNQheAoq8VR vS3Rt9C98lGXEjD2FAW0mDtLflh7N5Omp5/Th2ghWik4CwJNrRDuQvM8zY170Rs4SNDh AYXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id z64-v6si1338485ljb.146.2018.10.12.07.42.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeF-0000No-GA; Fri, 12 Oct 2018 15:42:39 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 01/10] target/arm: Improve debug logging of AArch32 exception return Date: Fri, 12 Oct 2018 15:42:26 +0100 Message-Id: <20181012144235.19646-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 For AArch32, exception return happens through certain kinds of CPSR write. We don't currently have any CPU_LOG_INT logging of these events (unlike AArch64, where we log in the ERET instruction). Add some suitable logging. This will log exception returns like this: Exception return from AArch32 hyp to usr PC 0x80100374 paralleling the existing logging in the exception_return helper for AArch64 exception returns: Exception return from AArch64 EL2 to AArch64 EL0 PC 0x8003045c Exception return from AArch64 EL2 to AArch32 EL0 PC 0x8003045c (Note that an AArch32 exception return can only be AArch32->AArch32, never to AArch64.) Signed-off-by: Peter Maydell --- target/arm/internals.h | 18 ++++++++++++++++++ target/arm/helper.c | 10 ++++++++++ target/arm/translate.c | 7 +------ 3 files changed, 29 insertions(+), 6 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index a4fc709bcc7..abe4d73b59c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -840,4 +840,22 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env) } } +/** + * aarch32_mode_name(): Return name of the AArch32 CPU mode + * @psr: Program Status Register indicating CPU mode + * + * Returns, for debug logging purposes, a printable representation + * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by + * the low bits of the specified PSR. + */ +static inline const char *aarch32_mode_name(uint32_t psr) +{ + static const char * const cpu_mode_names[16] = { + "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", + "???", "???", "hyp", "und", "???", "???", "???", "sys" + }; + + return cpu_mode_names[psr & 0xf]; +} + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index e3368e7edc5..0fa5ac0450f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6205,7 +6205,17 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, mask |= CPSR_IL; val |= CPSR_IL; } + qemu_log_mask(LOG_GUEST_ERROR, + "Illegal AArch32 mode switch attempt from %s to %s\n", + aarch32_mode_name(env->uncached_cpsr), + aarch32_mode_name(val)); } else { + qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", + write_type == CPSRWriteExceptionReturn ? + "Exception return from AArch32" : + "AArch32 mode switch from", + aarch32_mode_name(env->uncached_cpsr), + aarch32_mode_name(val), env->regs[15]); switch_mode(env, val & CPSR_M); } } diff --git a/target/arm/translate.c b/target/arm/translate.c index 1b4bacb522b..7c7d920e331 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13092,11 +13092,6 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) translator_loop(ops, &dc.base, cpu, tb); } -static const char *cpu_mode_names[16] = { - "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", - "???", "???", "hyp", "und", "???", "???", "???", "sys" -}; - void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -13162,7 +13157,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, psr & CPSR_V ? 'V' : '-', psr & CPSR_T ? 'T' : 'A', ns_status, - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); } if (flags & CPU_DUMP_FPU) { From patchwork Fri Oct 12 14:42:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148771 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819276lji; Fri, 12 Oct 2018 07:42:41 -0700 (PDT) X-Google-Smtp-Source: ACcGV632LSH3IXTGnMPw6P2ujgaKMA7LVqMFC/CQ0cB1DspDoRvHOx1O/cVdIZjekkM+6kZfrpxC X-Received: by 2002:adf:e70f:: with SMTP id c15-v6mr5945299wrm.165.1539355361046; Fri, 12 Oct 2018 07:42:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355361; cv=none; d=google.com; s=arc-20160816; b=Xcb7W214mVjFz3eMNvoLBSEDv/oROjt9yawppUEBFHukNTAAOGiass+vGWhT3jcGj3 5sNVXcYbyQsx0wW2dIKXu2EZ8fQR/qcTQf+azDIDx8k1FbbOtUTVHm3JfdRC9qM4MkoZ oc+0N3/hr3+60ep/sM9yjifl/nqX00qxkPQ6yKvwn6x/Zgz4t+G/FUE5jHKZlFeZk5Or 4HnsQqKjLnbGXFKODEOVZnrki7lprPS7AUfVqYCOvUrM5eurK+cIr9ODTR8bKOAi+Buq uNIxSL4ymE70TXxCCwp0gQKWA61Y8ThTjClBP3cn7FZ8RFUCSgs5XCuaiEAhBYsWhcbG MQXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=5NELGqkVegsuFLiL+w9oa4KbdKG/pxd6jjvzB2xcjf8=; b=urCTW7OnA0cxK8FL3n5oDyXaJ+3a7PHrR2oE6zDNuwibUaaIKj8KiQtcCfiSq4DTmn SutLIZpTXRNic+k/0KBt/SzWGnrbUBqC8zQcJZrjJT9fZlW3Lo8/i/Hjn1eO7kLLs6aC MjpOGFT7A/JaXAhJekl3Kcz0gZAJ/nzPNOAPE2gvrGaIcgACMbTMDPzfYAPmdNc/QhuD WRqbF35oiXJEECcqbCL+bVxe+o2IQJLd/shwT0dzKzYeBwxSgzskkrW4TwUcBcq2Zfwh ABqw243q8iv/Rdk+25qTYs6xzUA0f02YU7/QN0XaP/gs3+ALpQqm/DChpS91mzGvMCrR i02w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j13-v6si1157947wmh.61.2018.10.12.07.42.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeG-0000O3-FA; Fri, 12 Oct 2018 15:42:40 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 02/10] target/arm: Make switch_mode() file-local Date: Fri, 12 Oct 2018 15:42:27 +0100 Message-Id: <20181012144235.19646-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The switch_mode() function is defined in target/arm/helper.c and used only in that file and nowhere else, so we can make it file-local rather than global. Signed-off-by: Peter Maydell --- target/arm/internals.h | 1 - target/arm/helper.c | 6 ++++-- 2 files changed, 4 insertions(+), 3 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index abe4d73b59c..d4b1973efa1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -145,7 +145,6 @@ static inline int bank_number(int mode) g_assert_not_reached(); } -void switch_mode(CPUARMState *, int); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0fa5ac0450f..0253a971099 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -56,6 +56,8 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, V8M_SAttributes *sattrs); #endif +static void switch_mode(CPUARMState *env, int mode); + static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -6313,7 +6315,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return 0; } -void switch_mode(CPUARMState *env, int mode) +static void switch_mode(CPUARMState *env, int mode) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -6335,7 +6337,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) #else -void switch_mode(CPUARMState *env, int mode) +static void switch_mode(CPUARMState *env, int mode) { int old_mode; int i; From patchwork Fri Oct 12 14:42:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148772 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819291lji; Fri, 12 Oct 2018 07:42:42 -0700 (PDT) X-Google-Smtp-Source: ACcGV60csgFeW+9NSgcI0Bmtwa1xDrY8uo72awUTwXa3XTeycJgBwZPZXO6RRFwzqXL4miUnWawB X-Received: by 2002:adf:9c0a:: with SMTP id f10-v6mr5794274wrc.93.1539355361994; Fri, 12 Oct 2018 07:42:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355361; cv=none; d=google.com; s=arc-20160816; b=H3evswQ2Q01wCtcjUvmcvwWA8PTpKYwsq/1uQrjIO1T2yyvmqoXmifWm0Uv15tMu06 22Ubu2IQuLyd/3Ez/o/PRR54kVVWgl7v5cmiV8e06DRi5mU98stAheVQe+0Xn4Uj04Eb AtbB9bT98EtMVE8gX6EzY6KcPY/XQ5be2e5UCxAvr7kVtkuq8OyX5Ab6ub0AyAzx2cXY GEOLxc/DX1s5pqm2Q1YsmJnQA1TN5+a/nh/f6bJPNIGHMKB1ZAPMDynYM7fsZ2SmkKwW j5itFqvdv3Pg7OZ2SpB1zpAXLXcgbkGAcZhd+fynaH33MBXo5vNwFMUqjCr6OXOZrwWs K7uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=UEAf8biAmwcJHLotS/pBLVi9BNB2NcVIiigaL73Q284=; b=N9aoNRib7SoyfSjdxIWbAkqsCpT91GOrvi0/CCHCmnb6dpfkdCGFtAjSt9o6y+zy6d 6fyScCEXP3a4Kaq5BaHXZ9MRSjoNwGCHQ4b+8QzwjlCxmDX2TKCYodG1N5GPfS7G3ss4 HJFmQaI7JMj8e1NxgIfax2ySFORHs+GPlvtYLsBjqVcBNqgvJqFTQiJm6Wv6FRTThHMn r9efJLmnohmL/g9/odr1H8Z5bLoGWTX8e2C3ncRpW0oa13LQrDez/Ugrbk8OyXtlf7Av 1mdl8EgC9FLugtkG68iTrDFkvZrNx5sop+1R5hmsDuTT0SVaiBYdOuicSzKzpzZvVuZM g8Cw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id x75-v6si1376826wmf.14.2018.10.12.07.42.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeH-0000OI-F1; Fri, 12 Oct 2018 15:42:41 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 03/10] target/arm: Implement HCR.FB Date: Fri, 12 Oct 2018 15:42:28 +0100 Message-Id: <20181012144235.19646-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The HCR.FB virtualization configuration register bit requests that TLB maintenance, branch predictor invalidate-all and icache invalidate-all operations performed in NS EL1 should be upgraded from "local CPU only to "broadcast within Inner Shareable domain". For QEMU we NOP the branch predictor and icache operations, so we only need to upgrade the TLB invalidates: AArch32 TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVAL, TLBIMVAAL AArch64 TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1, TLBI VALE1, TLBI VAALE1 Signed-off-by: Peter Maydell --- target/arm/helper.c | 191 +++++++++++++++++++++++++++----------------- 1 file changed, 116 insertions(+), 75 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 0253a971099..cbec6844a44 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -554,42 +554,6 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } -static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate all (TLBIALL) */ - ARMCPU *cpu = arm_env_get_cpu(env); - - tlb_flush(CPU(cpu)); -} - -static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu = arm_env_get_cpu(env); - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); -} - -static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu = arm_env_get_cpu(env); - - tlb_flush(CPU(cpu)); -} - -static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu = arm_env_get_cpu(env); - - tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); -} - /* IS variants of TLB operations must affect all cores */ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -623,6 +587,73 @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } +/* + * Non-IS variants of TLB operations are upgraded to + * IS versions if we are at NS EL1 and HCR_EL2.FB is set to + * force broadcast of these operations. + */ +static bool tlb_force_broadcast(CPUARMState *env) +{ + return (env->cp15.hcr_el2 & HCR_FB) && + arm_current_el(env) == 1 && arm_is_secure_below_el3(env); +} + +static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate all (TLBIALL) */ + ARMCPU *cpu = arm_env_get_cpu(env); + + if (tlb_force_broadcast(env)) { + tlbiall_is_write(env, NULL, value); + return; + } + + tlb_flush(CPU(cpu)); +} + +static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ + ARMCPU *cpu = arm_env_get_cpu(env); + + if (tlb_force_broadcast(env)) { + tlbimva_is_write(env, NULL, value); + return; + } + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); +} + +static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by ASID (TLBIASID) */ + ARMCPU *cpu = arm_env_get_cpu(env); + + if (tlb_force_broadcast(env)) { + tlbiasid_is_write(env, NULL, value); + return; + } + + tlb_flush(CPU(cpu)); +} + +static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ + ARMCPU *cpu = arm_env_get_cpu(env); + + if (tlb_force_broadcast(env)) { + tlbimvaa_is_write(env, NULL, value); + return; + } + + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); +} + static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3082,22 +3113,6 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, * Page D4-1736 (DDI0487A.b) */ -static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs = ENV_GET_CPU(env); - - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } -} - static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3115,6 +3130,27 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs = ENV_GET_CPU(env); + + if (tlb_force_broadcast(env)) { + tlbi_aa64_vmalle1_write(env, NULL, value); + return; + } + + if (arm_is_secure_below_el3(env)) { + tlb_flush_by_mmuidx(cs, + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); + } else { + tlb_flush_by_mmuidx(cs, + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); + } +} + static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3204,29 +3240,6 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); } -static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by VA, EL1&0 (AArch64 version). - * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, - * since we don't support flush-for-specific-ASID-only or - * flush-last-level-only. - */ - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); - uint64_t pageaddr = sextract64(value << 12, 0, 56); - - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } -} - static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3274,6 +3287,34 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by VA, EL1&0 (AArch64 version). + * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); + uint64_t pageaddr = sextract64(value << 12, 0, 56); + + if (tlb_force_broadcast(env)) { + tlbi_aa64_vae1is_write(env, NULL, value); + return; + } + + if (arm_is_secure_below_el3(env)) { + tlb_flush_page_by_mmuidx(cs, pageaddr, + ARMMMUIdxBit_S1SE1 | + ARMMMUIdxBit_S1SE0); + } else { + tlb_flush_page_by_mmuidx(cs, pageaddr, + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); + } +} + static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { From patchwork Fri Oct 12 14:42:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148773 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819310lji; Fri, 12 Oct 2018 07:42:43 -0700 (PDT) X-Google-Smtp-Source: ACcGV61UoSy8YPK89ivSZQO2MTwJG0cgf/Tr3vVTM97S4KV6zQi8F5A8QQmfOCO1OvwL3O63eDeM X-Received: by 2002:adf:cf0b:: with SMTP id o11-v6mr5576018wrj.272.1539355362987; Fri, 12 Oct 2018 07:42:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355362; cv=none; d=google.com; s=arc-20160816; b=uV87ys/9dfhHrjr3nnjb57BAqC+fngSimgNjOq2w2oCAytGyZXLCy25YINJfLZaXCo TlK4JHu0yIrMPaatnzqyz0spPSyUl83ivnNUBFAyRj8lYRWvm+W5IN2q1JYy1I+OlNuG ySFTW625ixjG/HxNsDhaTTG4oINQs97iUT7tXilN/ICw2WqR1nb/OYGfVDSZ9J+GAx7b XSYRPPXMM3W3meGugVWhGw1cfygJk0ACI3X2ijO0iFIylc7qlRZP4if0QgCgvhvinJjF 2bYUNJeOauwVB1SrcP5TThZYq0GjEu4GnWwkM39k/3EhS4lYwbJbXy2WVThwMCYI29Nn CzCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=iObEMsr/13XQ1GLf3oHj58Lpoh8cCzm072IM9EYM930=; b=Ph3U0Ou6wpPiA1qVG+YDYMbXFS3+r10MXsmOJMDRiwkBIFiCFB5qcliQ2G5+CKyt3w Dxg30IOuoJAtjusUqhv9HvySTYaSZc7W3u1502wG6L8KSp5m++kOSNnEJBmYYHh0Vm9w 6rfqIgNkBZRa1wErdE8VzKScm+i5q+gYzDk7Yo8Z/2271xfAQgIvM4DzLUQLvf2vFlc5 320ZjT2dHtP4vt/MougUIn3QWBYtt0KSisG8PN3p1OyMtwdDvjp/BLBihAsrvmCY3c4g brz5cXTbUj/OdSn9ty+sykeu2uPu434fwA6crSS/jFavH+4RLoCiAuhqgUcsVsTr3fZ1 7PxQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id z70-v6si1410790wmd.43.2018.10.12.07.42.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeI-0000Oa-Di; Fri, 12 Oct 2018 15:42:42 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 04/10] target/arm: Implement HCR.DC Date: Fri, 12 Oct 2018 15:42:29 +0100 Message-Id: <20181012144235.19646-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The HCR.DC virtualization configuration register bit has the following effects: * SCTLR.M behaves as if it is 0 for all purposes except direct reads of the bit * HCR.VM behaves as if it is 1 for all purposes except direct reads of the bit * the memory type produced by the first stage of the EL1&EL0 translation regime is Normal Non-Shareable, Inner Write-Back Read-Allocate Write-Allocate, Outer Write-Back Read-Allocate Write-Allocate. Implement this behaviour. Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index cbec6844a44..84b40031b6f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2300,13 +2300,15 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * * The Non-secure TTBCR.EAE bit is set to 1 * * The implementation includes EL2, and the value of HCR.VM is 1 * + * (Note that HCR.DC makes HCR.VM behave as if it is 1.) + * * ATS1Hx always uses the 64bit format (not supported yet). */ format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); if (arm_feature(env, ARM_FEATURE_EL2)) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { - format64 |= env->cp15.hcr_el2 & HCR_VM; + format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |= arm_current_el(env) == 2; } @@ -8711,7 +8713,8 @@ static inline bool regime_translation_disabled(CPUARMState *env, } if (mmu_idx == ARMMMUIdx_S2NS) { - return (env->cp15.hcr_el2 & HCR_VM) == 0; + /* HCR.DC means HCR.VM behaves as 1 */ + return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; } if (env->cp15.hcr_el2 & HCR_TGE) { @@ -8721,6 +8724,12 @@ static inline bool regime_translation_disabled(CPUARMState *env, } } + if ((env->cp15.hcr_el2 & HCR_DC) && + (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) { + /* HCR.DC means SCTLR_EL1.M behaves as 0 */ + return true; + } + return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } @@ -10701,6 +10710,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* Combine the S1 and S2 cache attributes, if needed */ if (!ret && cacheattrs != NULL) { + if (env->cp15.hcr_el2 & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + */ + cacheattrs->attrs = 0xff; + cacheattrs->shareability = 0; + } *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); } From patchwork Fri Oct 12 14:42:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148774 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819374lji; Fri, 12 Oct 2018 07:42:46 -0700 (PDT) X-Google-Smtp-Source: ACcGV61TMXKyPf0X07y3W/3oMIejal4tn/ybL06myLbG6qVP3IWTSXy5x7twOsJbtn2NkOtCsYYd X-Received: by 2002:adf:9206:: with SMTP id 6-v6mr5693866wrj.275.1539355366003; Fri, 12 Oct 2018 07:42:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355365; cv=none; d=google.com; s=arc-20160816; b=Hh2clG8DdmXJ7xvCRUSMfzlgnyMkR0Wbsky7K+Y+y/+iZ4PJzyhwhULsy7aCHVzQfL uH+PR9O5oxL2DCD+9a+hhLTc1C15HZwBn3hfV9/aaTI9EeDkYY4QNuLwLxrCoY9Nh078 Lb7PiwmKeOxKnr7D3j/ZGoqlYvNS1ref6Ud5Or20MNsioLrNEyShzt83p6cKbI6KAVBz /xjQgAQuWzxy5yFQZGJA40VMtwaH+HxkQJefjHPT8ALg3ukhqAzUfvz01H+S8WK9tdUd OMX1XILuiMTST7w/IGlK/W2LTr8AbOhF3Nw7pKPyikuLMHoEKdxsguv5i16CkoLvLJz+ XawA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=JZH/Kjnru7jKz33s+DuzqVq7dopxuu2ZiwaPLzptua8=; b=PKgdT8NffeyW8NzGsq7LWELse76+1lngv1ORcPIwrGC3UqujvjyI3QX1NYoELdtbBJ B6fIas0GTiuT6YF/C3tl3JjBLwmLWoK5dV94xuVByw2+5Et+r4fzk1dW+blTzILjZD1S G5PK1MsdLi6WTpMPdtMceysbww67lNZLGqoSFCdyPZAQSdBmYlJH7w8bqv18F7Vn+dQ9 ceFwpiNXDcGjZZIM4sTS95cgSNSzOPwDx6VEvDIqdBZner8s2CuoJsjIDxCZNqsBBEJp azoaaarLAZG0LQnKuHyRUqiYtvjnPzG5RABH70i+xLejm2FrwmhWchR+T9tSKHHpS43u J3gw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id i2-v6si1290938wrb.392.2018.10.12.07.42.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeL-0000Ow-II; Fri, 12 Oct 2018 15:42:45 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 05/10] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set Date: Fri, 12 Oct 2018 15:42:30 +0100 Message-Id: <20181012144235.19646-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The A/I/F bits in ISR_EL1 should track the virtual interrupt status, not the physical interrupt status, if the associated HCR_EL2.AMO/IMO/FMO bit is set. Implement this, rather than always showing the physical interrupt status. We don't currently implement anything to do with external aborts, so this applies only to the I and F bits (though it ought to be possible for the outer guest to present a virtual external abort to the inner guest, even if QEMU doesn't emulate physical external aborts, so there is missing functionality in this area). Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 84b40031b6f..65e431e03b3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1328,12 +1328,26 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) CPUState *cs = ENV_GET_CPU(env); uint64_t ret = 0; - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - ret |= CPSR_I; + if (arm_hcr_el2_imo(env)) { + if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { + ret |= CPSR_I; + } + } else { + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + ret |= CPSR_I; + } } - if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { - ret |= CPSR_F; + + if (arm_hcr_el2_fmo(env)) { + if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { + ret |= CPSR_F; + } + } else { + if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { + ret |= CPSR_F; + } } + /* External aborts are not possible in QEMU so A bit is always clear */ return ret; } From patchwork Fri Oct 12 14:42:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148775 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819386lji; Fri, 12 Oct 2018 07:42:47 -0700 (PDT) X-Google-Smtp-Source: ACcGV60/8tM7hLCgX0DolVPeGgpPehObi4zpscN0xZtYn+CvfkVc+Wnes/JCjycZT5l/hNPBF1Nv X-Received: by 2002:a1c:924d:: with SMTP id u74-v6mr5833237wmd.105.1539355366978; Fri, 12 Oct 2018 07:42:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355366; cv=none; d=google.com; s=arc-20160816; b=aX5w2FDyo+7cHr52g9aiARvOkcUFfaT/idj7BPmE3firm45x8gKfCa9l0PN+AdSmig TXR+hDqQkYIUDecuwyNEIZKkH0Ea1j5f7yo+PTCaE6N9ztCvPdNuUjkEYunsZhfpKqh5 nGKAn1sLdEeto/Z+ldZ7QoeU5oF3gFjZKFrVkPMwO+eQb+RpJWlZxm04guEG6fcjwoik /mbjOqMRTJaRPzZpcUlgSEA0ZTuSzbmqrmdjHMaZRoELzsSKTBALXKTLa1GJrhpLytrF /gTHr9EVjsmyppwmtieZwlyeXkLdaUrCFpei75Sq/nI5X6jSLwKxBLqCvVsFsmOBFclb Rfqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=Gfp+9hvT9xbFDfxH3lmrAmrqulo71kbP2rq88HKrnZg=; b=lgM54qZnuy0k9YpTneShmGsdRBTlduye6eLktfaPmhLJJdiqBTPjg+2aMjuLOh5f5a WmcdziTR/yLE0hlvjrFLZ3EehSF4neR8uXooT4lzahjFbXyYQX/3Ah1CbPioLrpXgBDv AGiXi4v4aXceVNIEfGQWcmXIj1qHX2Sg5BPTl+08VkeSxR066zaGbRQoLwbzV9HNoSGr YLlpYA38lp6+pTrhF34Wygs5UBuxOuG6p1dQGvuRexRoKg3jaAw3enFOpBahwmsifr5S 7cw1T4nvmR7FPi5AY6uk+gmFaQ3BNdzMRQL87ivAVrAIwCz3SO6ppTvMZUkioG4QdsNN VQGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id t18-v6si1183625wro.85.2018.10.12.07.42.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeM-0000PB-HJ; Fri, 12 Oct 2018 15:42:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 06/10] target/arm: Implement HCR.VI and VF Date: Fri, 12 Oct 2018 15:42:31 +0100 Message-Id: <20181012144235.19646-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 The HCR_EL2 VI and VF bits are supposed to track whether there is a pending virtual IRQ or virtual FIQ. For QEMU we store the pending VIRQ/VFIQ status in cs->interrupt_request, so this means: * if the register is read we must get these bit values from cs->interrupt_request * if the register is written then we must write the bit values back into cs->interrupt_request Signed-off-by: Peter Maydell --- target/arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 4 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 65e431e03b3..78d05fe1e57 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3928,6 +3928,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = ENV_GET_CPU(env); uint64_t valid_mask = HCR_MASK; if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -3946,6 +3947,28 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &= valid_mask; + /* + * VI and VF are kept in cs->interrupt_request. Modifying that + * requires that we have the iothread lock, which is done by + * marking the reginfo structs as ARM_CP_IO. + * Note that if a write to HCR pends a VIRQ or VFIQ it is never + * possible for it to be taken immediately, because VIRQ and + * VFIQ are masked unless running at EL0 or EL1, and HCR + * can only be written at EL2. + */ + g_assert(qemu_mutex_iothread_locked()); + if (value & HCR_VI) { + cs->interrupt_request |= CPU_INTERRUPT_VIRQ; + } else { + cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + } + if (value & HCR_VF) { + cs->interrupt_request |= CPU_INTERRUPT_VFIQ; + } else { + cs->interrupt_request &= ~CPU_INTERRUPT_VFIQ; + } + value &= ~(HCR_VI | HCR_VF); + /* These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups @@ -3973,16 +3996,32 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } +static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* The VI and VF bits live in cs->interrupt_request */ + uint64_t ret = env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF); + CPUState *cs = ENV_GET_CPU(env); + + if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { + ret |= HCR_VI; + } + if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { + ret |= HCR_VF; + } + return ret; +} + static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write }, + .writefn = hcr_write, .readfn = hcr_read }, { .name = "HCR", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_writelow }, + .writefn = hcr_writelow, .readfn = hcr_read }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, @@ -4219,7 +4258,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { static const ARMCPRegInfo el2_v8_cp_reginfo[] = { { .name = "HCR2", .state = ARM_CP_STATE_AA32, - .type = ARM_CP_ALIAS, + .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, .access = PL2_RW, .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), From patchwork Fri Oct 12 14:42:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148776 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819399lji; Fri, 12 Oct 2018 07:42:48 -0700 (PDT) X-Google-Smtp-Source: ACcGV60YEfFyaqP7OA8AtUmGo/5L2aC9WqPMQ6MbhiCPxo3Xv7yCUlZ0Ub5POptzvyeNoWO3kucg X-Received: by 2002:adf:e348:: with SMTP id n8-v6mr5349576wrj.158.1539355367970; Fri, 12 Oct 2018 07:42:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355367; cv=none; d=google.com; s=arc-20160816; b=euzfdkrKMXyvSs0V/GEcYmF99VsKt6+NT/bsZRQJUfqN5e216FvndPBGEGr6XgSDTF bX+Hz/z4q2G3EDmTqqFhqEpSeYSDhwYtBPfvr0Yfpg9PZvDERrkJB6aOkUEx/uP3ZeuJ fYEGWl8SHgksEeNV4LOuBw8V/5PoE1IabuHymMxbd8EBEDd6N3ICCq5kC0P3zU0HHgd9 B7vC/Eg2jSF6dzdEne/RHnJL79N1/Ani9LR5In5vs4HrdpEyUWZUkfn1q4qvDMxlMKSV iEOruGwiwxy6po3eXYVm4KjMQ8Ud/EW27gzQuI5yOkJX107cLQMHLjUvQIymBojSWu0d qaWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=qNj/af0mtDZaV7h55GKVgJxjNnCohQEo/odm7w6QZ4I=; b=aKBSm8LX8Z85wG950llMyGy9Afr1hQ0NwMAxv8LeCJOGKW5+x1Tdv5g8BU/M8QEiv/ b+ZKo4i1XPIhdyVl+zYDl7JayP/NNb8DrLo4nxo0yeSY5iN3unlMle4naWAGDVufDlSx ZxaPXMbXatBTifF0j3mQ4pZHj/Ij+PmMnBNPWUb1FECkKkRdOhG7qaxyUD3LWsJh49iq e8ot9ofv3FRL0cQvGY2r2Hfx5GGPvLLhTjgTDwuxEqQ01yd3LvRb6RElsi5ekI0u3xDA mJQ/0Yylpx7CN3h8q3FghX4jyIo4LXo4YUpN0JHZNJjwzr7ctPAWa8iVSEg37pg9gE3i HXqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c3-v6si1227558wrw.86.2018.10.12.07.42.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeN-0000PR-Gp; Fri, 12 Oct 2018 15:42:47 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 07/10] target/arm: Implement HCR.PTW Date: Fri, 12 Oct 2018 15:42:32 +0100 Message-Id: <20181012144235.19646-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 If the HCR_EL2 PTW virtualizaiton configuration register bit is set, then this means that a stage 2 Permission fault must be generated if a stage 1 translation table access is made to an address that is mapped as Device memory in stage 2. Implement this. Signed-off-by: Peter Maydell --- target/arm/helper.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 78d05fe1e57..b5752d52dd1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9134,9 +9134,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; + ARMCacheAttrs cacheattrs = {}; + ARMCacheAttrs *pcacheattrs = NULL; + + if (env->cp15.hcr_el2 & HCR_PTW) { + /* + * PTW means we must fault if this S1 walk touches S2 Device + * memory; otherwise we don't care about the attributes and can + * save the S2 translation the effort of computing them. + */ + pcacheattrs = &cacheattrs; + } ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, fi, NULL); + &txattrs, &s2prot, &s2size, fi, pcacheattrs); if (ret) { assert(fi->type != ARMFault_None); fi->s2addr = addr; @@ -9144,6 +9155,14 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s1ptw = true; return ~0; } + if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { + /* Access was to Device memory: generate Permission fault */ + fi->type = ARMFault_Permission; + fi->s2addr = addr; + fi->stage2 = true; + fi->s1ptw = true; + return ~0; + } addr = s2pa; } return addr; From patchwork Fri Oct 12 14:42:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148777 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819415lji; Fri, 12 Oct 2018 07:42:48 -0700 (PDT) X-Google-Smtp-Source: ACcGV600AA1VuKWBIh5L8BavcIqLIcuSiSDcQpOr69YMCa4J5CAqW7XvRBVBRnAcZGiDMcvC5BWw X-Received: by 2002:adf:f14a:: with SMTP id y10-v6mr5430935wro.29.1539355368925; Fri, 12 Oct 2018 07:42:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355368; cv=none; d=google.com; s=arc-20160816; b=vYDIUdIZSRMtRLldGTYB5a1LFtTRU5jsh1SO84v1stxF+zoUw3N4gX+eO1zTa4xCbj cqPG2xWJLZD6NFjHp2fnSwOJiuloTLDi0TUJNst8jDAvwjw6Ip9r8heMM+uMTb9O+mwe v3Iwu61pVrKavlDg8LM4yl9iH6+p8tkv5XpPG1QD6Tma60+ZnW5FHGY/YVydVAqLFlGW xewuRhyD8K6ZRqTsbWftq/DPvVKquCB6SoeARk/oAzbC2LfLJqsL6O+whwj+DXjaBZXy 5g3ppPKaoRnkvMturnOTLVZa5GA1YnM3J6ksTr90FOKQyc0XBjxHAMsBAnZx7SIgeTsh KdbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=H+vkl/qzeenehwtysQ8Hz+5KAKjqPVse5tygDQbTdDI=; b=Uj5LeacqokIFavcpx0VSVEzfpLaCkVZAKu0vdSSoy9ShuLegarFAkxeBS76/rbXq2G BGo71dgSWBruWr5xXrVBilwjL0l4rhlBjOtowr0GRz5lZY+T8jaOtd1w9FtPc3jc7c+o WFw/ki2AZ+TMio5BeRGnrt8IxoOBf0yLgPxEGdHuVIyuBnTY3vZlE59mjwuzlnYd+oeA YYQ4kqY8U+KLRkJDr1UTBLPlr3NcopcTs54fnegVc0c50pU2c6hmdPorFDEve6j3ddg7 GquvDXQSPkfthP5mzfXptIC8OFD36elwx+C5Y2sGOVNgwS2OxGUl23ALbc48hafv0qr1 aL/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j1-v6si1276559wrg.455.2018.10.12.07.42.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeO-0000Pg-EI; Fri, 12 Oct 2018 15:42:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 08/10] target/arm: New utility function to extract EC from syndrome Date: Fri, 12 Oct 2018 15:42:33 +0100 Message-Id: <20181012144235.19646-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 Create and use a utility function to extract the EC field from a syndrome, rather than open-coding the shift. Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 +- target/arm/op_helper.c | 2 +- 4 files changed, 9 insertions(+), 4 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index d4b1973efa1..516f9454e9b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -278,6 +278,11 @@ enum arm_exception_class { #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + /* Utility functions for constructing various kinds of syndrome value. * Note that in general we follow the AArch64 syndrome values; in a * few cases the value in HSR for exceptions taken to AArch32 Hyp diff --git a/target/arm/helper.c b/target/arm/helper.c index b5752d52dd1..0b89804961b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8333,7 +8333,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) uint32_t moe; /* If this is a debug exception we must update the DBGDSCR.MOE bits */ - switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { + switch (syn_get_ec(env->exception.syndrome)) { case EC_BREAKPOINT: case EC_BREAKPOINT_SAME_EL: moe = 1; @@ -8669,7 +8669,7 @@ void arm_cpu_do_interrupt(CPUState *cs) if (qemu_loglevel_mask(CPU_LOG_INT) && !excp_is_internal(cs->exception_index)) { qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", - env->exception.syndrome >> ARM_EL_EC_SHIFT, + syn_get_ec(env->exception.syndrome), env->exception.syndrome); } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e0b82462838..ce33cbc65a6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -920,7 +920,7 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) { - int hsr_ec = debug_exit->hsr >> ARM_EL_EC_SHIFT; + int hsr_ec = syn_get_ec(debug_exit->hsr); ARMCPU *cpu = ARM_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = &cpu->env; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index fb15a13e6c9..b1e65f43d38 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -42,7 +42,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, * (see DDI0478C.a D1.10.4) */ target_el = 2; - if (syndrome >> ARM_EL_EC_SHIFT == EC_ADVSIMDFPACCESSTRAP) { + if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { syndrome = syn_uncategorized(); } } From patchwork Fri Oct 12 14:42:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148778 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819426lji; Fri, 12 Oct 2018 07:42:49 -0700 (PDT) X-Google-Smtp-Source: ACcGV61oNV2bK5RiFTsZo38/j/kth/ONmKxrPvtZ9G9GeNBOTcRMAcKEbZ9zLUtKlfWUVumv06vD X-Received: by 2002:a5d:45c7:: with SMTP id b7-v6mr5552202wrs.73.1539355369848; Fri, 12 Oct 2018 07:42:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355369; cv=none; d=google.com; s=arc-20160816; b=QdRwWLqVKdsg3adC2s0hE0R+VIzfO1wnKIULtFRFdXU+/lEDNhY7DML2LATwAkjkpm B1thvcHW3UIR8fB3Q+f8oDmIMv7jjpy2fy/FQSP9btP6zcnkIWlan3SXYQ0jqY+U5Kne hEMKpq+CLfe0J31UEj+ERBJ0U/pnWdm3ojJpq7+3IQr67nCf85581ly+9klP6x4ClL4a ctOCjD8MHtZABluLBTWifvWphLyDbDmROPfhHezgcr/zR56K7C7d0qoA3eWEJuC6CbAg WrPw+RQ00gjfzEg/DLmyTg+3xp4UwLDn5x0MVbNWXbVqpGoNxobpu41cEVWnxktgWoxZ H1vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=pZ928PqtXoHiTiJza6pAV6Kf8NA0Snr65ZtehZeM3+M=; b=cdeaKzHyiuxCxss8TRd0KbZaRUpoKoJ3dHsSNqjgOrXf6LmfB+Jmm+Q1s/lbtCCpiB d2LguI1lGGi+qiTBhJCOFwn4DbQE6QdWl9p/IhHTGJ/w9bdzSHBmSvBWKXGv0VI70Qvp R9lJRo61lb9CJ6oQnhl6R9obFlNUzM0eYV2X5vha/4Xa70huwvhKVd4PyXJJsz/8NoJv xhLR8mUMMrAgztx6sdR96eT8ZN8cDcujvOMp9zoZdR7F61LtjiEX8PF9vL0xEBbVUGxs OCmAI4RPlX1xSGkj5L9Rvuebsp4eyN5USpkGLLIWU1Wgz50yxwa/FDzTHGADv+l2yD3r 9qow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id e202-v6si1374941wma.179.2018.10.12.07.42.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeP-0000Pv-Cb; Fri, 12 Oct 2018 15:42:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 09/10] target/arm: Get IL bit correct for v7 syndrome values Date: Fri, 12 Oct 2018 15:42:34 +0100 Message-Id: <20181012144235.19646-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 For the v7 version of the Arm architecture, the IL bit in syndrome register values where the field is not valid was defined to be UNK/SBZP. In v8 this is RES1, which is what QEMU currently implements. Handle the desired v7 behaviour by squashing the IL bit for the affected cases: * EC == EC_UNCATEGORIZED * prefetch aborts * data aborts where ISV is 0 (The fourth case listed in the v8 Arm ARM DDI 0487C.a in section G7.2.70, "illegal state exception", can't happen on a v7 CPU.) This deals with a corner case noted in a comment. Signed-off-by: Peter Maydell --- target/arm/internals.h | 7 ++----- target/arm/helper.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 5 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index 516f9454e9b..cd8bc1ec3d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -286,11 +286,8 @@ static inline uint32_t syn_get_ec(uint32_t syn) /* Utility functions for constructing various kinds of syndrome value. * Note that in general we follow the AArch64 syndrome values; in a * few cases the value in HSR for exceptions taken to AArch32 Hyp - * mode differs slightly, so if we ever implemented Hyp mode then the - * syndrome value would need some massaging on exception entry. - * (One example of this is that AArch64 defaults to IL bit set for - * exceptions which don't specifically indicate information about the - * trapping instruction, whereas AArch32 defaults to IL bit clear.) + * mode differs slightly, and we fix this up when populating HSR in + * arm_cpu_do_interrupt_aarch32_hyp(). */ static inline uint32_t syn_uncategorized(void) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b89804961b..0b659171b07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8299,6 +8299,20 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) } if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { + + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* + * QEMU syndrome values are v8-style. v7 has the IL bit + * UNK/SBZP for "field not valid" cases, where v8 uses RES1. + * If this is a v7 CPU, squash the IL bit in those cases. + */ + if (cs->exception_index == EXCP_PREFETCH_ABORT || + (cs->exception_index == EXCP_DATA_ABORT && + !(env->exception.syndrome & ARM_EL_ISV)) || + syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { + env->exception.syndrome &= ~ARM_EL_IL; + } + } env->cp15.esr_el[2] = env->exception.syndrome; } From patchwork Fri Oct 12 14:42:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 148779 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp819443lji; Fri, 12 Oct 2018 07:42:50 -0700 (PDT) X-Google-Smtp-Source: ACcGV63zTAnhDJJolkM9aJdI2LKowEJ/qxuYc/Js/uQvfstp3IMC0qy36SLFgtvHJ1S/G0CVjxn7 X-Received: by 2002:adf:8103:: with SMTP id 3-v6mr5424165wrm.106.1539355370804; Fri, 12 Oct 2018 07:42:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539355370; cv=none; d=google.com; s=arc-20160816; b=abYphch3ASyxfPFpzu+0PF58kSTKx+mjRhQ2gDXLKTWrqQ+icc9OaLnRCrwb4tUx1T ZFIrIHDVuZM2rGJjuTDJ6ctk7LHgEN+H8yqc6iCU9eNdL4GGqMJpvU4NlKW/JTwISN5b WPpY6P1wl/pbcFKsbCUi8wEIwMWs84lvtR7JqGoYH6RCBDszuolVPEomWB7GjEluezHD N2zaYJdT6caUYf0zPILNapJynnFFxCB33nIWNxuKF/oH9UYyUBZIlnwV3fIR0PjnT0hU 2TrwCdYb1fuv0EJVpTwLgE9h/jvR+/WUoIbLLsHvvnNWyDzVtkpqlcaxGs+exAE6ephR +Hqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=iou+UBXP+eQFdyool2gb/5TStsa+qgoBYA3ItGGn5wY=; b=Qu27+JXJMGqEM8HKYGsLwc104m1zQ2ymaWow+7L2cbg9w9BCw21PKd8CJ5//pxmEwG nEqjRfOMzj90JvwgBxAEmC41ASb9lEMmISZZCjjz871P3ytbpmZDeQwPjSBCZ/pZl7Mn pxg9VNxP3UhlZFPRfh/ajr5jWbqfVo2yvrWz8FKJb+nLWmrHBfxV6tBwnSAcQgH5Rq0J FrRhKVi/kgjIplqpOscAB6TUroMLMW88lozSVzjY9UxV03FzL6+zBVgKHM6lotu8ktWI Y32oFMDFK26AHEJ3Ox5aKvyJWXE5ECnIwqq1ZPc4H9zBnG/2UIsvNafuuppDwm+jETM+ O3Rw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id d17-v6si1225769wrs.188.2018.10.12.07.42.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Oct 2018 07:42:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeQ-0000QD-BJ; Fri, 12 Oct 2018 15:42:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 10/10] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode Date: Fri, 12 Oct 2018 15:42:35 +0100 Message-Id: <20181012144235.19646-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 For traps of FP/SIMD instructions to AArch32 Hyp mode, the syndrome provided in HSR has more information than is reported to AArch64. Specifically, there are extra fields TA and coproc which indicate whether the trapped instruction was FP or SIMD. Add this extra information to the syndromes we construct, and mask it out when taking the exception to AArch64. Signed-off-by: Peter Maydell --- target/arm/internals.h | 14 +++++++++++++- target/arm/helper.c | 9 +++++++++ target/arm/translate.c | 8 ++++---- 3 files changed, 26 insertions(+), 5 deletions(-) -- 2.19.0 Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index cd8bc1ec3d4..960dfb3c06a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -288,6 +288,9 @@ static inline uint32_t syn_get_ec(uint32_t syn) * few cases the value in HSR for exceptions taken to AArch32 Hyp * mode differs slightly, and we fix this up when populating HSR in * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra coproc + * and TA fields, and mask them out when taking the exception to AArch64. */ static inline uint32_t syn_uncategorized(void) { @@ -387,9 +390,18 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) { + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20); + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 SIMD trap: TA == 1 coproc == 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); } static inline uint32_t syn_sve_access_trap(void) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b659171b07..43afdd082e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8540,6 +8540,15 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) case EXCP_HVC: case EXCP_HYP_TRAP: case EXCP_SMC: + if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) { + /* + * QEMU internal FP/SIMD syndromes from AArch32 include the + * TA and coproc fields which are only exposed if the exception + * is taken to AArch32 Hyp mode. Mask them out to get a valid + * AArch64 format syndrome. + */ + env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); + } env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c7d920e331..d71597796f5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4948,7 +4948,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) */ if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -5727,7 +5727,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) */ if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -7840,7 +7840,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } if (!s->vfp_enabled) { @@ -7926,7 +7926,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } if (!s->vfp_enabled) {