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+ struct caam_jr_qp *qp = NULL; + + PMD_INIT_FUNC_TRACE(); + CAAM_JR_DEBUG("dev =%p, queue =%d", dev, qp_id); + + internals = dev->data->dev_private; + if (qp_id >= internals->max_nb_queue_pairs) { + CAAM_JR_ERR("Max supported qpid %d", + internals->max_nb_queue_pairs); + return -EINVAL; + } + + qp = &internals->qps[qp_id]; + qp->ring = NULL; + dev->data->queue_pairs[qp_id] = NULL; + + return 0; +} + +/* Setup a queue pair */ +static int +caam_jr_queue_pair_setup( + struct rte_cryptodev *dev, uint16_t qp_id, + __rte_unused const struct rte_cryptodev_qp_conf *qp_conf, + __rte_unused int socket_id, + __rte_unused struct rte_mempool *session_pool) +{ + struct sec_job_ring_t *internals; + struct caam_jr_qp *qp = NULL; + + PMD_INIT_FUNC_TRACE(); + CAAM_JR_DEBUG("dev =%p, queue =%d, conf =%p", dev, qp_id, qp_conf); + + internals = dev->data->dev_private; + if (qp_id >= internals->max_nb_queue_pairs) { + CAAM_JR_ERR("Max supported qpid %d", + internals->max_nb_queue_pairs); + return -EINVAL; + } + + qp = &internals->qps[qp_id]; + qp->ring = internals; + dev->data->queue_pairs[qp_id] = qp; + + return 0; +} + +/* Return the number of allocated queue pairs */ +static uint32_t +caam_jr_queue_pair_count(struct rte_cryptodev *dev) +{ + PMD_INIT_FUNC_TRACE(); + + return dev->data->nb_queue_pairs; +} static int caam_jr_dev_configure(struct rte_cryptodev *dev, @@ -178,6 +239,9 @@ static struct rte_cryptodev_ops caam_jr_ops = { .dev_stop = caam_jr_dev_stop, .dev_close = caam_jr_dev_close, .dev_infos_get = caam_jr_dev_infos_get, + .queue_pair_setup = caam_jr_queue_pair_setup, + .queue_pair_release = caam_jr_queue_pair_release, + .queue_pair_count = caam_jr_queue_pair_count, }; From patchwork Fri Oct 12 14:40:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gagandeep Singh X-Patchwork-Id: 148781 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp820220lji; Fri, 12 Oct 2018 07:43:39 -0700 (PDT) X-Google-Smtp-Source: ACcGV60mrIQaaYU9+fJSY1XrdTpL9lrzGz3804Ks34/CfHxl2LiVlyJwHifMgs/OahvyatFN+xU8 X-Received: by 2002:adf:9f0f:: with SMTP id l15-v6mr5630674wrf.206.1539355419232; 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HE1PR04MB1530; 6:/5LdAP/1gWQziHeB3Bs4Ktz9FCDPBqNLFNJ6PW+XBMSG5JnJ6Ug3p1ceaFRqYhBqOowrZ9jpqvbi71wact5TTO0ANXAfkFIhIK4XkQ1pz+LPDcADyPm3809eRNfq6hMfYrrkK2RZTHSGFL0KTOEg+ef4e7EG3xVcYtSqtjauGtrpIg4jn1U/FNXBYJ3HhWYyFVracNE4btb9o3ekhl7WEDgfqgtTQIXEgkKggWG5dpgv0fbAi11wVXyXhZkA+1VOH1pv98bHlAB8vUa/VfsZRt6QDoBbINLFErwB8uhrlnfzeE3NSWjha9tz8IgERlVr0f+dd4OK50CsEgzR1nKT87vd2N3goOm4xcCqJe8KmpxBPtUJ6bFAS90TQYolAPbXUWe6NwXGA4safw7UR04kP7h8YBhdyfTbtWiXCiE0Xmr7VsBbUjmW3mD6lNRezRaoQXUqohhrVD89qzO17Pe09Q==; 5:R5DDvufc99W+YB+jBdKgUtYlVmrxPdLXkXZ01L5yk/+wMyR+MXVKE7JRtbVw+lcIJWoBMttL9eCYG3LA4O7uJp49jtDcvIe0szPOdwKGjJWb2kpqV/nXthfqex9QolxoEVadr9KyHimN1R+IBve8+OrX1fDB3eNO+IzXeAe+TU4=; 7:EEet7jXrWsOzwrEfXIj01tk0CGVKNCEXTulZtf5ziOIMTmIcFifNbc6WjJ3rH0nD04/VI90bGuP7ET5QqhcDbqigWTFN8ZOxJEdMIVGhhgKlSdfbxZcYZ29v2kZVYJ0QOwgtVI42+dKf4h6rH/Cp8c0ifI1oIGMdXDSHTEQgXZNJwEFGALPWY7985Irg4eeKR+sQuZ0NgGidcAs1sW9RpkZn5KESUvNdIfkukubzNnNSSbuRmrFB7xJyo08GfJSR SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2018 14:41:53.6001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26d03462-7955-410d-b9f6-08d63050daed X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR04MB1530 Subject: [dpdk-dev] [PATCH v2 12/14] crypto/caam_jr: add statistics ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal This patch adds the following statistics operations: - stats_get - stats_reset Signed-off-by: Gagandeep Singh Signed-off-by: Hemant Agrawal --- drivers/crypto/caam_jr/caam_jr.c | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) -- 2.17.1 diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c index a4118cd11..beb54d5da 100644 --- a/drivers/crypto/caam_jr/caam_jr.c +++ b/drivers/crypto/caam_jr/caam_jr.c @@ -104,6 +104,58 @@ caam_jr_alloc_ctx(struct caam_jr_session *ses) return ctx; } +static +void caam_jr_stats_get(struct rte_cryptodev *dev, + struct rte_cryptodev_stats *stats) +{ + struct caam_jr_qp **qp = (struct caam_jr_qp **) + dev->data->queue_pairs; + int i; + + PMD_INIT_FUNC_TRACE(); + if (stats == NULL) { + CAAM_JR_ERR("Invalid stats ptr NULL"); + return; + } + for (i = 0; i < dev->data->nb_queue_pairs; i++) { + if (qp[i] == NULL) { + CAAM_JR_WARN("Uninitialised queue pair"); + continue; + } + + stats->enqueued_count += qp[i]->tx_pkts; + stats->dequeued_count += qp[i]->rx_pkts; + stats->enqueue_err_count += qp[i]->tx_errs; + stats->dequeue_err_count += qp[i]->rx_errs; + CAAM_JR_INFO("extra stats:\n\tRX Poll ERR = %" PRIu64 + "\n\tTX Ring Full = %" PRIu64, + qp[i]->rx_poll_err, + qp[i]->tx_ring_full); + } +} + +static +void caam_jr_stats_reset(struct rte_cryptodev *dev) +{ + int i; + struct caam_jr_qp **qp = (struct caam_jr_qp **) + (dev->data->queue_pairs); + + PMD_INIT_FUNC_TRACE(); + for (i = 0; i < dev->data->nb_queue_pairs; i++) { + if (qp[i] == NULL) { + CAAM_JR_WARN("Uninitialised queue pair"); + continue; + } + qp[i]->rx_pkts = 0; + qp[i]->rx_errs = 0; + qp[i]->rx_poll_err = 0; + qp[i]->tx_pkts = 0; + qp[i]->tx_errs = 0; + qp[i]->tx_ring_full = 0; + } +} + static inline int is_cipher_only(struct caam_jr_session *ses) { @@ -1716,6 +1768,8 @@ static struct rte_cryptodev_ops caam_jr_ops = { .dev_stop = caam_jr_dev_stop, .dev_close = caam_jr_dev_close, .dev_infos_get = caam_jr_dev_infos_get, + .stats_get = caam_jr_stats_get, + .stats_reset = caam_jr_stats_reset, .queue_pair_setup = caam_jr_queue_pair_setup, .queue_pair_release = caam_jr_queue_pair_release, .queue_pair_count = caam_jr_queue_pair_count, From patchwork Fri Oct 12 14:40:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gagandeep Singh X-Patchwork-Id: 148782 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp820377lji; Fri, 12 Oct 2018 07:43:51 -0700 (PDT) X-Google-Smtp-Source: ACcGV62aJnsiKdMVbBnpEr6nqywMaoduOY9gQWRj6Oer49k5PiJ4k6dZDwS9q6zgpMf/c8u1fP5x X-Received: by 2002:adf:e886:: with SMTP id d6-v6mr5863872wrm.7.1539355430952; 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HE1PR04MB1530; 6:OhBFA++osu2uaik1vaXqiE0Qryi5MjDvY7xdAWa+s2xmqsa3f8SvoGmRWDUwYjFsyleaRnPkaL6+F5YZDEIoCeOUxKqaFlw72At3tzTHYdzFrvcGCatjpCmMyvq7KnVN8BZ69Ty/fzEemfr1Dl9DUavohjp109ZrxNUz4XTmkdZLoiN3vKp2wHH88Ag8ko2ofb8UAPCWTuG4a6Hlo2V0jy9YXXLcEV28jmOZb8QzN9EdnfYrtAL51dUKyuCtMGIeHz5c4fFY3CcT18bW5bAYAZgEUKoB/CPH/VEq9MVkIU0ID8b2kQobvEmwMU/2of8eJOOwOp2ebfZaHG4LLsv7UDUby96MIcRSorubzbx1F+QchpYsME3Tu2s8tHHcrWZK7Gt40jDmg8gsWXxeB9fekr6X4qce8YpK0VPKJhg07n1USuY26YezxthKRKNfTtGdQcMgjrugfe0pPgWigOJO4Q==; 5:otzSGBzGVQSv4vS8PBr8HiZtxzelXIM3O3oCMUzQk9c+/RXFczX813MiFk6Jnt+9ezJS6TLP2+BdY8F+6mh5n98d2W1rKtRXnEbCjm4sC12B0x24qJtQW8/hO0+JDJGtMS9HRf2WgEQxxPhJZGCs5xVJCGB7klSbfWmn8CBDnCw=; 7:nukMBuyFolE3wn8CZRwkuA9fQ6yjrCZjd20Zybd2IQT6P8O2GEdCsoQWLfYP0IArTIXOMFITvr5IschK61p5mM874fkAYLAkupikeQfUg0OXXr0Ht/J9kFCBjaERvRO0et2//i7CqysPXPJdMJjxjQbVEf6VTWXe5Y5NnscNMIMQDcT8bsbjdPNM/ic8ezhJBrbeRhCPId6M5v00BvqVo6yUgwSpPfqMjFHHLUQDeYM8J+flXJW2HiE9ZEZHYDdO SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2018 14:41:55.2408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac15e7e6-2de6-494f-d9fe-08d63050dbcd X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR04MB1530 Subject: [dpdk-dev] [PATCH v2 13/14] crypto/caam_jr: add security offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal This patch provides the support for protocol offload to the hardware. following security operations are added: - session_create - session_destroy - capabilities_get Signed-off-by: Hemant Agrawal --- drivers/crypto/caam_jr/caam_jr.c | 360 ++++++++++++++++++++++++++- drivers/crypto/caam_jr/caam_jr_pvt.h | 5 + 2 files changed, 354 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c index beb54d5da..e3002d6fb 100644 --- a/drivers/crypto/caam_jr/caam_jr.c +++ b/drivers/crypto/caam_jr/caam_jr.c @@ -27,7 +27,6 @@ /* RTA header files */ #include #include -#include #include #define CAAM_JR_DBG 0 @@ -186,7 +185,15 @@ is_auth_cipher(struct caam_jr_session *ses) { PMD_INIT_FUNC_TRACE(); return ((ses->cipher_alg != RTE_CRYPTO_CIPHER_NULL) && - (ses->auth_alg != RTE_CRYPTO_AUTH_NULL)); + (ses->auth_alg != RTE_CRYPTO_AUTH_NULL) && + (ses->proto_alg != RTE_SECURITY_PROTOCOL_IPSEC)); +} + +static inline int +is_proto_ipsec(struct caam_jr_session *ses) +{ + PMD_INIT_FUNC_TRACE(); + return (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC); } static inline int @@ -212,27 +219,39 @@ caam_auth_alg(struct caam_jr_session *ses, struct alginfo *alginfo_a) ses->digest_length = 0; break; case RTE_CRYPTO_AUTH_MD5_HMAC: - alginfo_a->algtype = OP_ALG_ALGSEL_MD5; + alginfo_a->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_HMAC_MD5_96 : OP_ALG_ALGSEL_MD5; alginfo_a->algmode = OP_ALG_AAI_HMAC; break; case RTE_CRYPTO_AUTH_SHA1_HMAC: - alginfo_a->algtype = OP_ALG_ALGSEL_SHA1; + alginfo_a->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_HMAC_SHA1_96 : OP_ALG_ALGSEL_SHA1; alginfo_a->algmode = OP_ALG_AAI_HMAC; break; case RTE_CRYPTO_AUTH_SHA224_HMAC: - alginfo_a->algtype = OP_ALG_ALGSEL_SHA224; + alginfo_a->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_HMAC_SHA1_160 : OP_ALG_ALGSEL_SHA224; alginfo_a->algmode = OP_ALG_AAI_HMAC; break; case RTE_CRYPTO_AUTH_SHA256_HMAC: - alginfo_a->algtype = OP_ALG_ALGSEL_SHA256; + alginfo_a->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_HMAC_SHA2_256_128 : OP_ALG_ALGSEL_SHA256; alginfo_a->algmode = OP_ALG_AAI_HMAC; break; case RTE_CRYPTO_AUTH_SHA384_HMAC: - alginfo_a->algtype = OP_ALG_ALGSEL_SHA384; + alginfo_a->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_HMAC_SHA2_384_192 : OP_ALG_ALGSEL_SHA384; alginfo_a->algmode = OP_ALG_AAI_HMAC; break; case RTE_CRYPTO_AUTH_SHA512_HMAC: - alginfo_a->algtype = OP_ALG_ALGSEL_SHA512; + alginfo_a->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_HMAC_SHA2_512_256 : OP_ALG_ALGSEL_SHA512; alginfo_a->algmode = OP_ALG_AAI_HMAC; break; default: @@ -248,15 +267,21 @@ caam_cipher_alg(struct caam_jr_session *ses, struct alginfo *alginfo_c) case RTE_CRYPTO_CIPHER_NULL: break; case RTE_CRYPTO_CIPHER_AES_CBC: - alginfo_c->algtype = OP_ALG_ALGSEL_AES; + alginfo_c->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_AES_CBC : OP_ALG_ALGSEL_AES; alginfo_c->algmode = OP_ALG_AAI_CBC; break; case RTE_CRYPTO_CIPHER_3DES_CBC: - alginfo_c->algtype = OP_ALG_ALGSEL_3DES; + alginfo_c->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_3DES : OP_ALG_ALGSEL_3DES; alginfo_c->algmode = OP_ALG_AAI_CBC; break; case RTE_CRYPTO_CIPHER_AES_CTR: - alginfo_c->algtype = OP_ALG_ALGSEL_AES; + alginfo_c->algtype = + (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ? + OP_PCL_IPSEC_AES_CTR : OP_ALG_ALGSEL_AES; alginfo_c->algmode = OP_ALG_AAI_CTR; break; default: @@ -420,6 +445,22 @@ caam_jr_prep_cdb(struct caam_jr_session *ses) cdb->sh_desc[0] = 0; cdb->sh_desc[1] = 0; cdb->sh_desc[2] = 0; + if (is_proto_ipsec(ses)) { + if (ses->dir == DIR_ENC) { + shared_desc_len = cnstr_shdsc_ipsec_new_encap( + cdb->sh_desc, + true, swap, SHR_SERIAL, + &ses->encap_pdb, + (uint8_t *)&ses->ip4_hdr, + &alginfo_c, &alginfo_a); + } else if (ses->dir == DIR_DEC) { + shared_desc_len = cnstr_shdsc_ipsec_new_decap( + cdb->sh_desc, + true, swap, SHR_SERIAL, + &ses->decap_pdb, + &alginfo_c, &alginfo_a); + } + } else { /* Auth_only_len is set as 0 here and it will be * overwritten in fd for each packet. */ @@ -427,6 +468,7 @@ caam_jr_prep_cdb(struct caam_jr_session *ses) true, swap, &alginfo_c, &alginfo_a, ses->iv.length, 0, ses->digest_length, ses->dir); + } } if (shared_desc_len < 0) { @@ -1281,6 +1323,50 @@ build_cipher_auth(struct rte_crypto_op *op, struct caam_jr_session *ses) return ctx; } + +static inline struct caam_jr_op_ctx * +build_proto(struct rte_crypto_op *op, struct caam_jr_session *ses) +{ + struct rte_crypto_sym_op *sym = op->sym; + struct caam_jr_op_ctx *ctx = NULL; + phys_addr_t src_start_addr, dst_start_addr; + struct sec_cdb *cdb; + uint64_t sdesc_offset; + struct sec_job_descriptor_t *jobdescr; + + PMD_INIT_FUNC_TRACE(); + ctx = caam_jr_alloc_ctx(ses); + if (!ctx) + return NULL; + ctx->op = op; + + src_start_addr = rte_pktmbuf_iova(sym->m_src); + if (sym->m_dst) + dst_start_addr = rte_pktmbuf_iova(sym->m_dst); + else + dst_start_addr = src_start_addr; + + cdb = ses->cdb; + sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb); + + jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc; + + SEC_JD_INIT(jobdescr); + SEC_JD_SET_SD(jobdescr, + (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset, + cdb->sh_hdr.hi.field.idlen); + + /* output */ + SEC_JD_SET_OUT_PTR(jobdescr, (uint64_t)dst_start_addr, 0, + sym->m_src->buf_len - sym->m_src->data_off); + /* input */ + SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)src_start_addr, 0, + sym->m_src->pkt_len); + sym->m_src->packet_type &= ~RTE_PTYPE_L4_MASK; + + return ctx; +} + static int caam_jr_enqueue_op(struct rte_crypto_op *op, struct caam_jr_qp *qp) { @@ -1296,6 +1382,11 @@ caam_jr_enqueue_op(struct rte_crypto_op *op, struct caam_jr_qp *qp) get_sym_session_private_data(op->sym->session, cryptodev_driver_id); break; + case RTE_CRYPTO_OP_SECURITY_SESSION: + ses = (struct caam_jr_session *) + get_sec_session_private_data( + op->sym->sec_session); + break; default: CAAM_JR_DP_ERR("sessionless crypto op not supported"); qp->tx_errs++; @@ -1317,6 +1408,8 @@ caam_jr_enqueue_op(struct rte_crypto_op *op, struct caam_jr_qp *qp) ctx = build_auth_only(op, ses); else if (is_cipher_only(ses)) ctx = build_cipher_only(op, ses); + else if (is_proto_ipsec(ses)) + ctx = build_proto(op, ses); } else { if (is_auth_cipher(ses)) ctx = build_cipher_auth_sg(op, ses); @@ -1687,6 +1780,228 @@ caam_jr_sym_session_clear(struct rte_cryptodev *dev, } } +static int +caam_jr_set_ipsec_session(__rte_unused struct rte_cryptodev *dev, + struct rte_security_session_conf *conf, + void *sess) +{ + struct sec_job_ring_t *internals = dev->data->dev_private; + struct rte_security_ipsec_xform *ipsec_xform = &conf->ipsec; + struct rte_crypto_auth_xform *auth_xform; + struct rte_crypto_cipher_xform *cipher_xform; + struct caam_jr_session *session = (struct caam_jr_session *)sess; + + PMD_INIT_FUNC_TRACE(); + + if (ipsec_xform->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) { + cipher_xform = &conf->crypto_xform->cipher; + auth_xform = &conf->crypto_xform->next->auth; + } else { + auth_xform = &conf->crypto_xform->auth; + cipher_xform = &conf->crypto_xform->next->cipher; + } + session->proto_alg = conf->protocol; + session->cipher_key.data = rte_zmalloc(NULL, + cipher_xform->key.length, + RTE_CACHE_LINE_SIZE); + if (session->cipher_key.data == NULL && + cipher_xform->key.length > 0) { + CAAM_JR_ERR("No Memory for cipher key\n"); + return -ENOMEM; + } + + session->cipher_key.length = cipher_xform->key.length; + session->auth_key.data = rte_zmalloc(NULL, + auth_xform->key.length, + RTE_CACHE_LINE_SIZE); + if (session->auth_key.data == NULL && + auth_xform->key.length > 0) { + CAAM_JR_ERR("No Memory for auth key\n"); + rte_free(session->cipher_key.data); + return -ENOMEM; + } + session->auth_key.length = auth_xform->key.length; + memcpy(session->cipher_key.data, cipher_xform->key.data, + cipher_xform->key.length); + memcpy(session->auth_key.data, auth_xform->key.data, + auth_xform->key.length); + + switch (auth_xform->algo) { + case RTE_CRYPTO_AUTH_SHA1_HMAC: + session->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC; + break; + case RTE_CRYPTO_AUTH_MD5_HMAC: + session->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC; + break; + case RTE_CRYPTO_AUTH_SHA256_HMAC: + session->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC; + break; + case RTE_CRYPTO_AUTH_SHA384_HMAC: + session->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC; + break; + case RTE_CRYPTO_AUTH_SHA512_HMAC: + session->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC; + break; + case RTE_CRYPTO_AUTH_AES_CMAC: + session->auth_alg = RTE_CRYPTO_AUTH_AES_CMAC; + break; + case RTE_CRYPTO_AUTH_NULL: + session->auth_alg = RTE_CRYPTO_AUTH_NULL; + break; + case RTE_CRYPTO_AUTH_SHA224_HMAC: + case RTE_CRYPTO_AUTH_AES_XCBC_MAC: + case RTE_CRYPTO_AUTH_SNOW3G_UIA2: + case RTE_CRYPTO_AUTH_SHA1: + case RTE_CRYPTO_AUTH_SHA256: + case RTE_CRYPTO_AUTH_SHA512: + case RTE_CRYPTO_AUTH_SHA224: + case RTE_CRYPTO_AUTH_SHA384: + case RTE_CRYPTO_AUTH_MD5: + case RTE_CRYPTO_AUTH_AES_GMAC: + case RTE_CRYPTO_AUTH_KASUMI_F9: + case RTE_CRYPTO_AUTH_AES_CBC_MAC: + case RTE_CRYPTO_AUTH_ZUC_EIA3: + CAAM_JR_ERR("Crypto: Unsupported auth alg %u\n", + auth_xform->algo); + goto out; + default: + CAAM_JR_ERR("Crypto: Undefined Auth specified %u\n", + auth_xform->algo); + goto out; + } + + switch (cipher_xform->algo) { + case RTE_CRYPTO_CIPHER_AES_CBC: + session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC; + break; + case RTE_CRYPTO_CIPHER_3DES_CBC: + session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC; + break; + case RTE_CRYPTO_CIPHER_AES_CTR: + session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CTR; + break; + case RTE_CRYPTO_CIPHER_NULL: + case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: + case RTE_CRYPTO_CIPHER_3DES_ECB: + case RTE_CRYPTO_CIPHER_AES_ECB: + case RTE_CRYPTO_CIPHER_KASUMI_F8: + CAAM_JR_ERR("Crypto: Unsupported Cipher alg %u\n", + cipher_xform->algo); + goto out; + default: + CAAM_JR_ERR("Crypto: Undefined Cipher specified %u\n", + cipher_xform->algo); + goto out; + } + + if (ipsec_xform->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) { + memset(&session->encap_pdb, 0, sizeof(struct ipsec_encap_pdb) + + sizeof(session->ip4_hdr)); + session->ip4_hdr.ip_v = IPVERSION; + session->ip4_hdr.ip_hl = 5; + session->ip4_hdr.ip_len = rte_cpu_to_be_16( + sizeof(session->ip4_hdr)); + session->ip4_hdr.ip_tos = ipsec_xform->tunnel.ipv4.dscp; + session->ip4_hdr.ip_id = 0; + session->ip4_hdr.ip_off = 0; + session->ip4_hdr.ip_ttl = ipsec_xform->tunnel.ipv4.ttl; + session->ip4_hdr.ip_p = (ipsec_xform->proto == + RTE_SECURITY_IPSEC_SA_PROTO_ESP) ? IPPROTO_ESP + : IPPROTO_AH; + session->ip4_hdr.ip_sum = 0; + session->ip4_hdr.ip_src = ipsec_xform->tunnel.ipv4.src_ip; + session->ip4_hdr.ip_dst = ipsec_xform->tunnel.ipv4.dst_ip; + session->ip4_hdr.ip_sum = calc_chksum((uint16_t *) + (void *)&session->ip4_hdr, + sizeof(struct ip)); + + session->encap_pdb.options = + (IPVERSION << PDBNH_ESP_ENCAP_SHIFT) | + PDBOPTS_ESP_OIHI_PDB_INL | + PDBOPTS_ESP_IVSRC | + PDBHMO_ESP_ENCAP_DTTL; + session->encap_pdb.spi = ipsec_xform->spi; + session->encap_pdb.ip_hdr_len = sizeof(struct ip); + + session->dir = DIR_ENC; + } else if (ipsec_xform->direction == + RTE_SECURITY_IPSEC_SA_DIR_INGRESS) { + memset(&session->decap_pdb, 0, sizeof(struct ipsec_decap_pdb)); + session->decap_pdb.options = sizeof(struct ip) << 16; + session->dir = DIR_DEC; + } else + goto out; + session->ctx_pool = internals->ctx_pool; + + return 0; +out: + rte_free(session->auth_key.data); + rte_free(session->cipher_key.data); + memset(session, 0, sizeof(struct caam_jr_session)); + return -1; +} + +static int +caam_jr_security_session_create(void *dev, + struct rte_security_session_conf *conf, + struct rte_security_session *sess, + struct rte_mempool *mempool) +{ + void *sess_private_data; + struct rte_cryptodev *cdev = (struct rte_cryptodev *)dev; + int ret; + + PMD_INIT_FUNC_TRACE(); + if (rte_mempool_get(mempool, &sess_private_data)) { + CAAM_JR_ERR("Couldn't get object from session mempool"); + return -ENOMEM; + } + + switch (conf->protocol) { + case RTE_SECURITY_PROTOCOL_IPSEC: + ret = caam_jr_set_ipsec_session(cdev, conf, + sess_private_data); + break; + case RTE_SECURITY_PROTOCOL_MACSEC: + return -ENOTSUP; + default: + return -EINVAL; + } + if (ret != 0) { + CAAM_JR_ERR("failed to configure session parameters"); + /* Return session to mempool */ + rte_mempool_put(mempool, sess_private_data); + return ret; + } + + set_sec_session_private_data(sess, sess_private_data); + + return ret; +} + +/* Clear the memory of session so it doesn't leave key material behind */ +static int +caam_jr_security_session_destroy(void *dev __rte_unused, + struct rte_security_session *sess) +{ + PMD_INIT_FUNC_TRACE(); + void *sess_priv = get_sec_session_private_data(sess); + + struct caam_jr_session *s = (struct caam_jr_session *)sess_priv; + + if (sess_priv) { + struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv); + + rte_free(s->cipher_key.data); + rte_free(s->auth_key.data); + memset(sess, 0, sizeof(struct caam_jr_session)); + set_sec_session_private_data(sess, NULL); + rte_mempool_put(sess_mp, sess_priv); + } + return 0; +} + + static int caam_jr_dev_configure(struct rte_cryptodev *dev, struct rte_cryptodev_config *config __rte_unused) @@ -1778,6 +2093,14 @@ static struct rte_cryptodev_ops caam_jr_ops = { .sym_session_clear = caam_jr_sym_session_clear }; +static struct rte_security_ops caam_jr_security_ops = { + .session_create = caam_jr_security_session_create, + .session_update = NULL, + .session_stats_get = NULL, + .session_destroy = caam_jr_security_session_destroy, + .set_pkt_metadata = NULL, + .capabilities_get = caam_jr_get_security_capabilities +}; /* @brief Flush job rings of any processed descs. * The processed descs are silently dropped, @@ -1997,6 +2320,7 @@ caam_jr_dev_init(const char *name, struct rte_cryptodev_pmd_init_params *init_params) { struct rte_cryptodev *dev; + struct rte_security_ctx *security_instance; struct uio_job_ring *job_ring; char str[RTE_CRYPTODEV_NAME_MAX_LEN]; @@ -2066,6 +2390,20 @@ caam_jr_dev_init(const char *name, return 0; } + /*TODO free it during teardown*/ + security_instance = rte_malloc("caam_jr", + sizeof(struct rte_security_ctx), 0); + if (security_instance == NULL) { + CAAM_JR_ERR("memory allocation failed\n"); + //todo error handling. + goto cleanup2; + } + + security_instance->device = (void *)dev; + security_instance->ops = &caam_jr_security_ops; + security_instance->sess_cnt = 0; + dev->security_ctx = security_instance; + RTE_LOG(INFO, PMD, "%s cryptodev init\n", dev->data->name); return 0; diff --git a/drivers/crypto/caam_jr/caam_jr_pvt.h b/drivers/crypto/caam_jr/caam_jr_pvt.h index 58fd257fc..9f1adabc7 100644 --- a/drivers/crypto/caam_jr/caam_jr_pvt.h +++ b/drivers/crypto/caam_jr/caam_jr_pvt.h @@ -5,6 +5,8 @@ #ifndef CAAM_JR_PVT_H #define CAAM_JR_PVT_H +#include + /* NXP CAAM JR PMD device name */ #define CAAM_JR_ALG_UNSUPPORT (-1) @@ -110,6 +112,7 @@ struct caam_jr_session { enum rte_crypto_cipher_algorithm cipher_alg; /* Cipher Algorithm*/ enum rte_crypto_auth_algorithm auth_alg; /* Authentication Algorithm*/ enum rte_crypto_aead_algorithm aead_alg; /* AEAD Algorithm*/ + enum rte_security_session_protocol proto_alg; /* Security Algorithm*/ union { struct { uint8_t *data; /* pointer to key data */ @@ -132,7 +135,9 @@ struct caam_jr_session { } iv; /* Initialisation vector parameters */ uint16_t auth_only_len; /* Length of data for Auth only */ uint32_t digest_length; + struct ipsec_encap_pdb encap_pdb; struct ip ip4_hdr; + struct ipsec_decap_pdb decap_pdb; struct caam_jr_qp *qp; struct sec_cdb *cdb; /* cmd block associated with qp */ struct rte_mempool *ctx_pool; /* session mempool for caam_jr_op_ctx */ From patchwork Fri Oct 12 14:40:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gagandeep Singh X-Patchwork-Id: 148783 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp820466lji; Fri, 12 Oct 2018 07:43:57 -0700 (PDT) X-Google-Smtp-Source: ACcGV60zrVorwxuAMhi5lMo6m4r4JfuZRYSYra4yoTcxUUpSh2+YjZEMfDemBSpKvuFYva/gcbK6 X-Received: by 2002:adf:91a4:: with SMTP id 33-v6mr5560036wri.37.1539355437124; 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HE1PR04MB1530; 6:H0YK/zKSsneZq9B8v7hPEcJCrZOK1jeElZgpjP06BHvjrcX7O6DuCCHhs3pcU0+BtWwWLdz1vdaLMTrD5JP7XRN1tKd7dlJ7sfaA7m+p4jUa80PvqJaEgg/11vKw4hSIGGaOgSDyhE57hhqjWjJo+Jhvb0tlfCbyJFeGjq+RFBnORfUaLD1eQf5RNDKPgdtCN26DKSPOtMEnPiLwho56uItCby+zHvQ0/zhhyZ07x+QVSvjYtL6ux1lqMogOkX3Ea6Iw+ecr03T5WifEThdVNRsVvifwDHwoaOr2Ssq5pk1NxFxRW9+q6qnAaWiw5g+nXBHOYswhAwl/gF9ZrxFX08yJyk7moxlb5DDwUnYIToZsDkLRFYVFb6SCC+0yu1hh3WMWVWERERUPEZf0hH6iq0vGabp4vxT1Z9Y+wXXkBbAbXBBD01K4qnEOtT5Xh4qpC+uvTlJQsdBPZiMWPXgnkA==; 5:422jIn4pL2Je+m0e+4epwZqWc4CHUvUkNyRml6k7WfJTnW81xi4jJOQHRQTnz+CtLmx59KN9pZIIXGivPtxWHmp5rXEC46Y6bahqVmikf87/QGjDrqOJD9jD9Sfyun5F9SdNawiJUVkO89QEmRnNSJGhJVChMEiA73poIEizPr8=; 7:wuVFUJWePrWND6UVj55Nk9+xk+XBAhFEiIB2Zm7dvGYdx0mQhLu+rEegwDD/lGsODfJFeq6/uqTaltUzyffjk1s8kK74P22IRvxnlNFneE3ik6IMqHKJu+yoXbeBneJZYgNY7UwGBdCyh8/m/U+IlDYi40EGCgaPhzmBLfCGdGnOK7gsxRB2GfuFqtI2+aKW3i6lxsvBFY74sBD4Kx9lg8MA37PhhI8ewK5K3ZbuxXTLZp/gjbQeFXU+hFejLjTR SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2018 14:41:56.7409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42c077c6-e4ac-4595-beca-08d63050dcb2 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR04MB1530 Subject: [dpdk-dev] [PATCH v2 14/14] doc: add caam jr cryptodev details X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal add caam jr driver details, supported features and algorithms in the document. release note and MAINTAINERS are also updated. Signed-off-by: Hemant Agrawal --- MAINTAINERS | 7 + doc/guides/cryptodevs/caam_jr.rst | 150 +++++++++++++++++++++ doc/guides/cryptodevs/features/caam_jr.ini | 46 +++++++ doc/guides/cryptodevs/index.rst | 1 + doc/guides/rel_notes/release_18_11.rst | 5 + 5 files changed, 209 insertions(+) create mode 100644 doc/guides/cryptodevs/caam_jr.rst create mode 100644 doc/guides/cryptodevs/features/caam_jr.ini -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index b5294cbea..f50c6cae0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -850,6 +850,13 @@ F: drivers/crypto/null/ F: doc/guides/cryptodevs/null.rst F: doc/guides/cryptodevs/features/null.ini +NXP CAAM JR +M: Gagandeep Singh +M: Hemant Agrawal +F: drivers/crypto/caam_jr/ +F: doc/guides/cryptodevs/caam_jr.rst +F: doc/guides/cryptodevs/features/caam_jr.ini + NXP DPAA_SEC M: Akhil Goyal M: Hemant Agrawal diff --git a/doc/guides/cryptodevs/caam_jr.rst b/doc/guides/cryptodevs/caam_jr.rst new file mode 100644 index 000000000..e87ff0915 --- /dev/null +++ b/doc/guides/cryptodevs/caam_jr.rst @@ -0,0 +1,150 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright 2018 NXP + + +NXP CAAM JOB RING (caam_jr) +=========================== + +The caam_jr PMD provides poll mode crypto driver support for NXP SEC 4.x+ (CAAM) +hardware accelerator. More information is available at: + +`NXP Cryptographic Acceleration Technology `_. + +Architecture +------------ + +SEC is the SOC's security engine, which serves as NXP's latest cryptographic +acceleration and offloading hardware. It combines functions previously +implemented in separate modules to create a modular and scalable acceleration +and assurance engine. It also implements block encryption algorithms, stream +cipher algorithms, hashing algorithms, public key algorithms, run-time +integrity checking, and a hardware random number generator. SEC performs +higher-level cryptographic operations than previous NXP cryptographic +accelerators. This provides significant improvement to system level performance. + +SEC HW accelerator above 4.x+ version are also known as CAAM. + +caam_jr PMD is one of DPAA drivers which uses uio interface to interact with +Linux kernel for configure and destroy the device instance (ring). + + +Implementation +-------------- + +SEC provides platform assurance by working with SecMon, which is a companion +logic block that tracks the security state of the SOC. SEC is programmed by +means of descriptors (not to be confused with frame descriptors (FDs)) that +indicate the operations to be performed and link to the message and +associated data. SEC incorporates two DMA engines to fetch the descriptors, +read the message data, and write the results of the operations. The DMA +engine provides a scatter/gather capability so that SEC can read and write +data scattered in memory. SEC may be configured by means of software for +dynamic changes in byte ordering. The default configuration for this version +of SEC is little-endian mode. + +Note that one physical Job Ring represent one caam_jr device. + +Features +-------- + +The CAAM_JR PMD has support for: + +Cipher algorithms: + +* ``RTE_CRYPTO_CIPHER_3DES_CBC`` +* ``RTE_CRYPTO_CIPHER_AES128_CBC`` +* ``RTE_CRYPTO_CIPHER_AES192_CBC`` +* ``RTE_CRYPTO_CIPHER_AES256_CBC`` +* ``RTE_CRYPTO_CIPHER_AES128_CTR`` +* ``RTE_CRYPTO_CIPHER_AES192_CTR`` +* ``RTE_CRYPTO_CIPHER_AES256_CTR`` + +Hash algorithms: + +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` +* ``RTE_CRYPTO_AUTH_MD5_HMAC`` + +AEAD algorithms: + +* ``RTE_CRYPTO_AEAD_AES_GCM`` + +Supported DPAA SoCs +-------------------- + +* LS1046A/LS1026A +* LS1043A/LS1023A +* LS1028A +* LS1012A + +Limitations +----------- + +* Hash followed by Cipher mode is not supported +* Only supports the session-oriented API implementation (session-less APIs are not supported). + +Prerequisites +------------- + +caam_jr driver has following dependencies are not part of DPDK and must be installed separately: + +* **NXP Linux SDK** + + NXP Linux software development kit (SDK) includes support for the family + of QorIQ® ARM-Architecture-based system on chip (SoC) processors + and corresponding boards. + + It includes the Linux board support packages (BSPs) for NXP SoCs, + a fully operational tool chain, kernel and board specific modules. + + SDK and related information can be obtained from: `NXP QorIQ SDK `_. + +Currently supported by DPDK: + +* NXP SDK **18.09+**. +* Supported architectures: **arm64 LE**. + +* Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup the basic DPDK environment. + +Pre-Installation Configuration +------------------------------ + +Config File Options +~~~~~~~~~~~~~~~~~~~ + +The following options can be modified in the ``config`` file +to enable caam_jr PMD. + +Please note that enabling debugging options may affect system performance. + +* ``CONFIG_RTE_LIBRTE_PMD_CAAM_JR`` (default ``n``) + By default it is only enabled in common_linuxapp config. + Toggle compilation of the ``librte_pmd_caam_jr`` driver. + +* ``CONFIG_RTE_LIBRTE_PMD_CAAM_JR_BE`` (default ``n``) + By default it is disabled. + It can be used when the underlying hardware supports the CAAM in BE mode. + e.g. LS1043A, LS1046A supports CAAM in BE mode. + BE mode is enabled by default in defconfig-arm64-dpaa-linuxapp-gcc. + +Installations +------------- +To compile the caam_jr PMD for Linux arm64 gcc target, run the +following ``make`` command: + +.. code-block:: console + + cd + make config T=arm64-armv8a-linuxapp-gcc install + +Enabling logs +------------- + +For enabling logs, use the following EAL parameter: + +.. code-block:: console + + ./your_crypto_application --log-level=pmd.crypto.caam, diff --git a/doc/guides/cryptodevs/features/caam_jr.ini b/doc/guides/cryptodevs/features/caam_jr.ini new file mode 100644 index 000000000..68f8d8195 --- /dev/null +++ b/doc/guides/cryptodevs/features/caam_jr.ini @@ -0,0 +1,46 @@ +; +; Supported features of the 'caam_jr' crypto driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Symmetric crypto = Y +Sym operation chaining = Y +HW Accelerated = Y +Protocol offload = Y +In Place SGL = Y +OOP SGL In SGL Out = Y +OOP SGL In LB Out = Y +OOP LB In SGL Out = Y +OOP LB In LB Out = Y + +; +; Supported crypto algorithms of the 'dpaa2_sec' crypto driver. +; +[Cipher] +AES CBC (128) = Y +AES CBC (192) = Y +AES CBC (256) = Y +AES CTR (128) = Y +AES CTR (192) = Y +AES CTR (256) = Y +3DES CBC = Y + +; +; Supported authentication algorithms of the 'dpaa2_sec' crypto driver. +; +[Auth] +MD5 HMAC = Y +SHA1 HMAC = Y +SHA224 HMAC = Y +SHA256 HMAC = Y +SHA384 HMAC = Y +SHA512 HMAC = Y + +; +; Supported AEAD algorithms of the 'dpaa2_sec' crypto driver. +; +[AEAD] +AES GCM (128) = Y +AES GCM (192) = Y +AES GCM (256) = Y diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst index bd1588537..83610e64f 100644 --- a/doc/guides/cryptodevs/index.rst +++ b/doc/guides/cryptodevs/index.rst @@ -13,6 +13,7 @@ Crypto Device Drivers aesni_mb aesni_gcm armv8 + caam_jr ccp dpaa2_sec dpaa_sec diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst index 56bc435ed..fba349a48 100644 --- a/doc/guides/rel_notes/release_18_11.rst +++ b/doc/guides/rel_notes/release_18_11.rst @@ -174,6 +174,11 @@ New Features The AESNI MB PMD has been updated with additional support for AES-GCM algorithm support. +* **Added NXP CAAM JR PMD.** + + Added the new caam job ring driver for NXP platforms. See the + "NXP CAAM JOB RING (caam_jr)" document for more details on this new driver. + API Changes -----------