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CAT:NONE; SFS:(4636009)(396003)(136003)(376002)(39860400002)(346002)(46966006)(36840700001)(110136005)(54906003)(6666004)(82310400003)(36860700001)(36906005)(83380400001)(70206006)(2616005)(4326008)(86362001)(478600001)(5660300002)(356005)(8676002)(82740400003)(316002)(26005)(8936002)(7696005)(186003)(336012)(70586007)(36756003)(1076003)(7636003)(2906002)(426003)(47076005)(107886003)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 05:29:04.1350 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8b15ff4-6a22-484f-4fa4-08d96c403f21 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1373 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Laxman Dewangan Add support to save and restore the pincontrol HW register for GPIO mode configurations. This helps in changing the pin configure only during suspend and restore in resume. Signed-off-by: Laxman Dewangan Signed-off-by: pshete Reported-by: kernel test robot --- drivers/pinctrl/pinmux.c | 24 ++++++++++++++++++++++++ drivers/pinctrl/pinmux.h | 18 ++++++++++++++++++ include/linux/pinctrl/pinmux.h | 9 +++++++++ 3 files changed, 51 insertions(+) diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 6cdbd9ccf2f0..66fc0ca22623 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -317,6 +317,30 @@ int pinmux_gpio_direction(struct pinctrl_dev *pctldev, return ret; } +int pinmux_gpio_save_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + const struct pinmux_ops *ops = pctldev->desc->pmxops; + + if (ops->gpio_save_config) + return ops->gpio_save_config(pctldev, range, pin); + + return 0; +} + +int pinmux_gpio_restore_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + const struct pinmux_ops *ops = pctldev->desc->pmxops; + + if (ops->gpio_restore_config) + return ops->gpio_restore_config(pctldev, range, pin); + + return 0; +} + static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, const char *function) { diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 78c3a31be882..425c31a0115b 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -31,6 +31,12 @@ int pinmux_map_to_setting(const struct pinctrl_map *map, void pinmux_free_setting(const struct pinctrl_setting *setting); int pinmux_enable_setting(const struct pinctrl_setting *setting); void pinmux_disable_setting(const struct pinctrl_setting *setting); +int pinmux_gpio_save_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin); +int pinmux_gpio_restore_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin); #else @@ -89,6 +95,18 @@ static inline void pinmux_disable_setting(const struct pinctrl_setting *setting) { } +int pinmux_gpio_save_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + return 0; +} +int pinmux_gpio_restore_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + return 0; +} #endif #if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS) diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index 9a647fa5c8f1..cca87586d8c1 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -53,6 +53,8 @@ struct pinctrl_dev; * depending on whether the GPIO is configured as input or output, * a direction selector function may be implemented as a backing * to the GPIO controllers that need pin muxing. + * @gpio_save_config: Save the GPIo configurations. + * @gpio_restore_config: Restore GPIO configurations. * @strict: do not allow simultaneous use of the same pin for GPIO and another * function. Check both gpio_owner and mux_owner strictly before approving * the pin request. @@ -79,6 +81,13 @@ struct pinmux_ops { struct pinctrl_gpio_range *range, unsigned offset, bool input); + int (*gpio_save_config) (struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset); + int (*gpio_restore_config) (struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset); + bool strict; }; From patchwork Tue Aug 31 05:28:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 505313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7EE0C432BE for ; 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CAT:NONE; SFS:(4636009)(39860400002)(136003)(396003)(376002)(346002)(36840700001)(46966006)(4326008)(1076003)(7636003)(6666004)(36756003)(356005)(70206006)(26005)(86362001)(36860700001)(47076005)(5660300002)(70586007)(110136005)(478600001)(336012)(426003)(36906005)(2906002)(83380400001)(316002)(8936002)(82310400003)(2616005)(82740400003)(8676002)(7696005)(54906003)(186003)(107886003)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 05:29:11.9382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ae77144-d30a-4c28-6bef-08d96c4043d3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5476 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Laxman Dewangan Implement the pinmux register save and restore for the GPIO configuration of pins. This helps in changing the pins configuration for suspend state only. Signed-off-by: Laxman Dewangan Signed-off-by: pshete --- drivers/pinctrl/tegra/pinctrl-tegra.c | 66 +++++++++++++++++++++++++++ drivers/pinctrl/tegra/pinctrl-tegra.h | 1 + 2 files changed, 67 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 195cfe557511..7f947c952e09 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -275,6 +275,66 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, return 0; } +static int tegra_pinctrl_gpio_save_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tegra_pingroup *g; + unsigned group, num_pins; + const unsigned *pins; + int ret; + + for (group = 0; group < pmx->soc->ngroups; ++group) { + ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins); + if (ret < 0 || num_pins != 1) + continue; + if (offset == pins[0]) + break; + } + + if (group == pmx->soc->ngroups) { + dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset); + return -EINVAL; + } + + g = &pmx->soc->groups[group]; + if (g->mux_reg >= 0) + pmx->gpio_conf[offset] = pmx_readl(pmx, g->mux_bank, g->mux_reg); + + return 0; +} + +static int tegra_pinctrl_gpio_restore_config(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tegra_pingroup *g; + unsigned group, num_pins; + const unsigned *pins; + int ret; + + for (group = 0; group < pmx->soc->ngroups; ++group) { + ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins); + if (ret < 0 || num_pins != 1) + continue; + if (offset == pins[0]) + break; + } + + if (group == pmx->soc->ngroups) { + dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset); + return -EINVAL; + } + + g = &pmx->soc->groups[group]; + if (g->mux_reg >= 0) + pmx_writel(pmx, pmx->gpio_conf[offset], g->mux_bank, g->mux_reg); + + return 0; +} + static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) @@ -326,6 +386,8 @@ static const struct pinmux_ops tegra_pinmux_ops = { .set_mux = tegra_pinctrl_set_mux, .gpio_request_enable = tegra_pinctrl_gpio_request_enable, .gpio_disable_free = tegra_pinctrl_gpio_disable_free, + .gpio_save_config = tegra_pinctrl_gpio_save_config, + .gpio_restore_config = tegra_pinctrl_gpio_restore_config, }; static int tegra_pinconf_reg(struct tegra_pmx *pmx, @@ -826,6 +888,10 @@ int tegra_pinctrl_probe(struct platform_device *pdev, if (!pmx->backup_regs) return -ENOMEM; + pmx->gpio_conf = devm_kzalloc(&pdev->dev, backup_regs_size, GFP_KERNEL); + if (!pmx->gpio_conf) + return -ENOMEM; + for (i = 0; i < pmx->nbanks; i++) { pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); if (IS_ERR(pmx->regs[i])) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index fcad7f74c5a2..c08c676bfa03 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -18,6 +18,7 @@ struct tegra_pmx { int nbanks; void __iomem **regs; u32 *backup_regs; + u32 *gpio_conf; }; enum tegra_pinconf_param {