From patchwork Mon Oct 15 18:40:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 148882 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4134700lji; Mon, 15 Oct 2018 11:41:02 -0700 (PDT) X-Google-Smtp-Source: ACcGV633RArXKj8AXxPr+5LzxMtTckbpsSk/LtTRtqAQ+x6ZAhG7JeJ+YQiXVP7RB1iAuNPuUDX5 X-Received: by 2002:a17:902:4e:: with SMTP id 72-v6mr17996975pla.204.1539628862165; Mon, 15 Oct 2018 11:41:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539628862; cv=none; d=google.com; s=arc-20160816; b=cTMMaG5VJrMHyGAzBHRr34h068ABl0uUR1/D3Lu/650vyxUinu5xYu/joe+JGI0aEe n1stE8LOHGoTqpjqdPwOj8E8JR4f40jgGs3mdpGbt/AjGUzgLkF9QtIpnhwtQlpmKkEm NVjr2he85jEb3waP8YxA0DRzGgYwbTmqD+JwGJlegKdo37p42t6WhaffYyPE3FQkCQqQ q7L5EhlcfJCXJyxYsceIs6HIad151Z9QyDa+D9xsa6wuuJiEq3i3bxN6Om1nWq4Kwhfi eMEmRuhfTEQUBbZOWmWgYfAgVEz5x8fGCnStgB6sDrMftLE1BTMF38+nWh23RQj89Lmu K1gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=uwoVlZjkMzpETniD2CtZPXgGTNMJgtgkij4h1+Ma+X8=; b=LLWVcs3XhbSP9deQQQxj9JiYB5ZvqmPT9tMQoAKOYrVbiOb9Vs+znyAxttrEoIr3+I a3BwH7PjofXxirVw8BRHaSvFTb6rSMPK+MTi1suzNLza0HAtVZED4pkqbgwy4FU97ECm YZIN1BLK1gs6ZnIcBNT3Wc80JASdBMp+JithK7gV5DwgmYPuEngWXENBAkHGGkOb6Lue EKXD9+0TVTnpJ5G9rUMcNxjDj4++KNvLMIyQtSFfIH+W7xazqACUFP+lphrG7B3xFpzo aNLOIWuYGAXaDpF97SM5mFoQmHWT7nQsbHEJK0+hTUEhyTNAVLpToK8xV5Z6yPIDfT09 Y+jA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HVn5v1NH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k22-v6si11338945pgh.340.2018.10.15.11.41.01; Mon, 15 Oct 2018 11:41:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HVn5v1NH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727005AbeJPC11 (ORCPT + 32 others); Mon, 15 Oct 2018 22:27:27 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40131 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726976AbeJPC10 (ORCPT ); Mon, 15 Oct 2018 22:27:26 -0400 Received: by mail-pf1-f194.google.com with SMTP id g21-v6so3124694pfi.7 for ; Mon, 15 Oct 2018 11:40:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=uwoVlZjkMzpETniD2CtZPXgGTNMJgtgkij4h1+Ma+X8=; b=HVn5v1NHy29J8BnXbSnm1jhy6KVoaDQfHNjamo8YGjAEAAF7FMvvhbgjact3SPQnoK ZlmZDBXi+AhReHDFJKV/TMws3lzorRWXMJuR0SK/KCflul6Ejz8kms2n0Wqjeru8TPb+ /+qD3MgqwiQ//JzDN3+Y7QXGCtEhi1eHzFrcE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=uwoVlZjkMzpETniD2CtZPXgGTNMJgtgkij4h1+Ma+X8=; b=AcK+VUhKg9wgGV71KR/tWfQrWpw/VduBp+ImX4avdXc1I59TOLJhnACgoU6VHoFqKq w1jKeMhqjOPNp7d/uTY3+lJyHon/T5Js3FPGNZcpTRVrFqTVm/XulfTmhfH1OjcGlLZ1 WcOWwc2NPQYV6tOvH1cuUULtJ/CjKlcb8qC9+RQy51BRf85C/k21uATI3CVv3jsIPhYd 9t7fGl5QaThFCXJI9c36mnu35j5QAXZyjU8W04tcQyiSXvtrd2FI17ClFF441CLw80VB QUQIdg70H6mgGDJZvCpveW454zozkNfQZ1cZ3vXOYXFcFHraM7rUeVfPWJXZy3XASy6M uqAg== X-Gm-Message-State: ABuFfogq18NlJXIWPJyd844R0Lc5Tm5WIk9UCj2ybdi5bvyfNHPkTV/U nDxjK2LKXkB277senG6d58XNpb7ozGk= X-Received: by 2002:a63:f05:: with SMTP id e5-v6mr16366947pgl.84.1539628858987; Mon, 15 Oct 2018 11:40:58 -0700 (PDT) Received: from localhost ([49.248.168.189]) by smtp.gmail.com with ESMTPSA id a16-v6sm13915296pfi.49.2018.10.15.11.40.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Oct 2018 11:40:57 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, Zhang Rui , Daniel Lezcano Subject: [PATCH v1 2/4] drivers: thermal: tsens: Add generic support for TSENS v1 IP Date: Tue, 16 Oct 2018 00:10:41 +0530 Message-Id: <164bf2c5352cee95a783d6f17f401e59f587c5bc.1539627762.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4 of the TSENS IP, functionality for which is encapsulated inside qcom,tsens-v1 compatible. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/Makefile | 2 +- drivers/thermal/qcom/tsens-v1.c | 196 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 2 +- 4 files changed, 201 insertions(+), 2 deletions(-) create mode 100644 drivers/thermal/qcom/tsens-v1.c -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index a821929ede0b..60269ee90c43 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o +qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o tsens-v1.o diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c new file mode 100644 index 000000000000..297bcac3b94e --- /dev/null +++ b/drivers/thermal/qcom/tsens-v1.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include "tsens.h" + +/* eeprom layout data for qcs404 (v1) */ +#define BASE0_MASK 0x000007f8 +#define BASE1_MASK 0x0007f800 +#define BASE0_SHIFT 3 +#define BASE1_SHIFT 11 + +#define S0_P1_MASK 0x0000003f +#define S1_P1_MASK 0x0003f000 +#define S2_P1_MASK 0x3f000000 +#define S3_P1_MASK 0x000003f0 +#define S4_P1_MASK 0x003f0000 +#define S5_P1_MASK 0x0000003f +#define S6_P1_MASK 0x0003f000 +#define S7_P1_MASK 0x3f000000 +#define S8_P1_MASK 0x000003f0 +#define S9_P1_MASK 0x003f0000 + +#define S0_P2_MASK 0x00000fc0 +#define S1_P2_MASK 0x00fc0000 +#define S2_P2_MASK_1_0 0xc0000000 +#define S2_P2_MASK_5_2 0x0000000f +#define S3_P2_MASK 0x0000fc00 +#define S4_P2_MASK 0x0fc00000 +#define S5_P2_MASK 0x00000fc0 +#define S6_P2_MASK 0x00fc0000 +#define S7_P2_MASK_1_0 0xc0000000 +#define S7_P2_MASK_5_2 0x0000000f +#define S8_P2_MASK 0x0000fc00 +#define S9_P2_MASK 0x0fc00000 + +#define S0_P1_SHIFT 0 +#define S0_P2_SHIFT 6 +#define S1_P1_SHIFT 12 +#define S1_P2_SHIFT 18 +#define S2_P1_SHIFT 24 +#define S2_P2_SHIFT_1_0 30 + +#define S2_P2_SHIFT_5_2 0 +#define S3_P1_SHIFT 4 +#define S3_P2_SHIFT 10 +#define S4_P1_SHIFT 16 +#define S4_P2_SHIFT 22 + +#define S5_P1_SHIFT 0 +#define S5_P2_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S6_P2_SHIFT 18 +#define S7_P1_SHIFT 24 +#define S7_P2_SHIFT_1_0 30 + +#define S7_P2_SHIFT_5_2 0 +#define S8_P1_SHIFT 4 +#define S8_P2_SHIFT 10 +#define S9_P1_SHIFT 16 +#define S9_P2_SHIFT 22 + +#define CAL_SEL_MASK 7 +#define CAL_SEL_SHIFT 0 + +static int calibrate_v1(struct tsens_device *tmdev) +{ + u32 base0 = 0, base1 = 0; + u32 p1[tmdev->num_sensors], p2[tmdev->num_sensors]; + u32 mode = 0, lsb = 0, msb = 0; + u32 *qfprom_cdata; + int i; + + qfprom_cdata = (u32 *)qfprom_read(tmdev->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; + dev_dbg(tmdev->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; + msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; + p2[2] = msb << 2 | lsb; + p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; + msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; + p2[7] = msb << 2 | lsb; + p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; + for (i = 0; i < tmdev->num_sensors; i++) + p2[i] = ((base1 + p2[i]) << 2); + /* Fall through */ + case ONE_PT_CALIB2: + base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; + p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; + p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; + for (i = 0; i < tmdev->num_sensors; i++) + p1[i] = (((base0) + p1[i]) << 2); + break; + default: + for (i = 0; i < tmdev->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope(tmdev, p1, p2, mode); + + return 0; +} + +#define STATUS_OFFSET 0x44 +#define LAST_TEMP_MASK 0x3ff +#define STATUS_VALID_BIT BIT(14) + +static int get_temp_tsens_v1(struct tsens_device *tmdev, int id, int *temp) +{ + struct tsens_sensor *s = &tmdev->sensor[id]; + u32 code; + unsigned int status_reg; + u32 last_temp = 0, last_temp2 = 0, last_temp3 = 0; + int ret; + + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + last_temp = code & LAST_TEMP_MASK; + if (code & STATUS_VALID_BIT) + goto done; + + /* Try a second time */ + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + if (code & STATUS_VALID_BIT) { + last_temp = code & LAST_TEMP_MASK; + goto done; + } else { + last_temp2 = code & LAST_TEMP_MASK; + } + + /* Try a third/last time */ + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + if (code & STATUS_VALID_BIT) { + last_temp = code & LAST_TEMP_MASK; + goto done; + } else { + last_temp3 = code & LAST_TEMP_MASK; + } + + if (last_temp == last_temp2) + last_temp = last_temp2; + else if (last_temp2 == last_temp3) + last_temp = last_temp3; +done: + /* Convert temperature from deciCelsius to milliCelsius */ + *temp = sign_extend32(last_temp, fls(LAST_TEMP_MASK) - 1) * 100; + + return 0; +} + +static const struct tsens_ops ops_generic_v1 = { + .init = init_common, + .calibrate = calibrate_v1, + .get_temp = get_temp_tsens_v1, +}; + +const struct tsens_data data_tsens_v1 = { + .ops = &ops_generic_v1, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index f1ec9bbe4717..d0cc0c09894a 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -63,6 +63,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,tsens-v1", + .data = &data_tsens_v1, }, { .compatible = "qcom,tsens-v2", .data = &data_tsens_v2, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 7b7feee5dc46..7060c22ea611 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -92,7 +92,7 @@ int init_common(struct tsens_device *); int get_temp_common(struct tsens_device *, int, int *); /* TSENS v1 targets */ -extern const struct tsens_data data_8916, data_8974, data_8960; +extern const struct tsens_data data_8916, data_8974, data_8960, data_tsens_v1; /* TSENS v2 targets */ extern const struct tsens_data data_8996, data_tsens_v2; From patchwork Mon Oct 15 18:40:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 148883 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4134747lji; Mon, 15 Oct 2018 11:41:05 -0700 (PDT) X-Google-Smtp-Source: ACcGV60YQPKqhIj6+u99/Hx0tnLsshL6ZIB85T+QWB86aXqBk528Puziq/AVbz3GaJdCMWxBdHpa X-Received: by 2002:a17:902:124:: with SMTP id 33-v6mr18509001plb.205.1539628865844; Mon, 15 Oct 2018 11:41:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539628865; cv=none; d=google.com; s=arc-20160816; b=1LClgXES69PNdTbJ4zCL3kQVwHHl3RiUr8K5IdpvnjETMt0oHbmn4cQDU5IYq9CNhX 6nD1ZPpvWQ3RMAsXDl6gBGbc+0ZSJnNOwE+XlQ7dDxN9twdy1UtPTft4wnkbnIF89PlY MhnNAtbt68Ci3+S0oSkBmUp17dY+odSMcFiDXQRMs8AWl3H11DVoRE9Ywl7l4yHS5voI TZ28sznQMYXqusvod3AmAETCZYqdJlj/AzL7OzhEIVrbN1cE2vtfBsZPUhVNaZlyjlBz 2g9eQLK4lFMTnNGEHaCgJJFiVM1n7b46BnwfP0PmTmpXaGxTBelDM3Y/tXnEox7mk6MN GiBA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id v32-v6si11672316pgk.16.2018.10.15.11.41.05; Mon, 15 Oct 2018 11:41:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ayjNbFIM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727027AbeJPC1a (ORCPT + 32 others); Mon, 15 Oct 2018 22:27:30 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:39293 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbeJPC1a (ORCPT ); Mon, 15 Oct 2018 22:27:30 -0400 Received: by mail-pl1-f195.google.com with SMTP id e67-v6so741071plb.6 for ; Mon, 15 Oct 2018 11:41:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ogGQSy3dAWO6K9za/agsvOo3IJdF2oHNe8AuFMdfokI=; b=ayjNbFIMWUbEYOOTbf9xYFPjVipvqTvsLCX66z9P7KANNUtZ/j36x9xGvQ9pBtxNg8 4te2B+0UbjF7VnKVrxeABrCAQfmivkd53ojOu9+cWsqhFGc3GoZ5Z5nMmSSMD70HBd82 hBMwcZ74R6snIts9YiEHEJgERwfxZ+t94iuGE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ogGQSy3dAWO6K9za/agsvOo3IJdF2oHNe8AuFMdfokI=; b=WRp00/QIQJkl7QVH8TdeUe8WTx6qAPU3CoJVL05oYrnTAw9XJS9T7CS5OkjgPXvINo BGGvEWD8QqFV3taIiVeVk5AE8i9Wqw7uHP+HJJoyq2dOnrWFHyDRmIryc9x4IUxPI8sm KkfLuwB4aGmxL/gxe0UcrI9zi2dPfEU2fE3NjJYJJO40e0oEl2QmD2JA3eRo/Tj/c6I/ UFNWiFYE/fFmlSdBp4XdyK2GTOeoasqcVmpRD1hL3HGnoC6h1jPZ5U85Aw4lQlPUiCOU 7kdGa5DMoXnH8fiQ/nrFndBN017f2PBbxLahNoLdc62y/m0stDasD5mP75OmmV9ZKCe6 NoTg== X-Gm-Message-State: ABuFfojQjn4I7hYhPQN2d3CcuXoy0PLYyNo6AAFGLcugpgWWxPfnDQG3 tVJuzS5TXx/v6FE2bQZ5ZpGenDgRr7A= X-Received: by 2002:a17:902:263:: with SMTP id 90-v6mr18103770plc.190.1539628862759; Mon, 15 Oct 2018 11:41:02 -0700 (PDT) Received: from localhost ([49.248.168.189]) by smtp.gmail.com with ESMTPSA id l26-v6sm19276104pfg.161.2018.10.15.11.41.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Oct 2018 11:41:02 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, David Brown , Rob Herring , Mark Rutland Subject: [PATCH v1 3/4] arm64: dts: qcom: qcs404: Add tsens controller Date: Tue, 16 Oct 2018 00:10:42 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. The calibration data is stored in an eeprom (qfprom) that is accessed through the nvmem framework. We add the qfprom node to allow the tsens sensors to be calibrated correctly. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index e1e2ba9cbfcd..dfd65c53cf5f 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -273,6 +273,26 @@ status = "okay"; }; + qfprom: qfprom@a4000 { + compatible = "qcom,qfprom"; + reg = <0xa4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0x1f8 0x14>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + apcs_glb: mailbox@b011000 { compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0xb011000 0x1000>;