From patchwork Wed Sep 1 08:32:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BF96C4320E for ; Wed, 1 Sep 2021 08:32:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C1E460FED for ; Wed, 1 Sep 2021 08:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243271AbhIAIdY (ORCPT ); Wed, 1 Sep 2021 04:33:24 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:42960 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243272AbhIAIdX (ORCPT ); Wed, 1 Sep 2021 04:33:23 -0400 X-UUID: c190e405213d4c6f9366e724de2c4a97-20210901 X-UUID: c190e405213d4c6f9366e724de2c4a97-20210901 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 302919122; Wed, 01 Sep 2021 16:32:22 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:21 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:20 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 02/15] media: mtk-vcodec: Align vcodec wake up interrupt interface Date: Wed, 1 Sep 2021 16:32:02 +0800 Message-ID: <20210901083215.25984-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Vdec and venc can use the same function to wake up interrupt event. Reviewed-by: Tzung-Bi Shih Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 9 +-------- drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 8 ++++++++ drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c | 8 -------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index 983e0f2831af..8db9cdc66043 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -31,13 +31,6 @@ module_param(mtk_v4l2_dbg_level, int, 0644); module_param(mtk_vcodec_dbg, bool, 0644); -/* Wake up context wait_queue */ -static void wake_up_ctx(struct mtk_vcodec_ctx *ctx) -{ - ctx->int_cond = 1; - wake_up_interruptible(&ctx->queue); -} - static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) { struct mtk_vcodec_dev *dev = priv; @@ -69,7 +62,7 @@ static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) writel((readl(vdec_misc_addr) & ~VDEC_IRQ_CLR), dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG); - wake_up_ctx(ctx); + wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED); mtk_v4l2_debug(3, "mtk_vcodec_dec_irq_handler :wake up ctx %d, dec_done_status=%x", diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h index d4f840a7bbcb..3b1e5e3a450e 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -472,4 +472,12 @@ static inline struct mtk_vcodec_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl) return container_of(ctrl->handler, struct mtk_vcodec_ctx, ctrl_hdl); } +/* Wake up context wait_queue */ +static inline void wake_up_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason) +{ + ctx->int_cond = 1; + ctx->int_type = reason; + wake_up_interruptible(&ctx->queue); +} + #endif /* _MTK_VCODEC_DRV_H_ */ diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c index 4167e865b23f..2828df77020c 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c @@ -73,14 +73,6 @@ static const struct mtk_video_fmt mtk_video_formats_capture_mt8183[] = { }, }; -/* Wake up context wait_queue */ -static void wake_up_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason) -{ - ctx->int_cond = 1; - ctx->int_type = reason; - wake_up_interruptible(&ctx->queue); -} - static void clean_irq_status(unsigned int irq_status, void __iomem *addr) { if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE) From patchwork Wed Sep 1 08:32:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C376EC00143 for ; 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Wed, 1 Sep 2021 16:32:21 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 03/15] media: mtk-vcodec: Refactor vcodec pm interface Date: Wed, 1 Sep 2021 16:32:03 +0800 Message-ID: <20210901083215.25984-4-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Using the needed param for pm init/release function and remove unused param mtkdev in 'struct mtk_vcodec_pm'. Reviewed-by: Tzung-Bi Shih Signed-off-by: Yunfei Dong --- .../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 ++--- .../platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 22 ++++++++----------- .../platform/mtk-vcodec/mtk_vcodec_dec_pm.h | 5 +++-- .../platform/mtk-vcodec/mtk_vcodec_drv.h | 1 - .../platform/mtk-vcodec/mtk_vcodec_enc_pm.c | 1 - 5 files changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index 8db9cdc66043..dd749d41c75a 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -249,7 +249,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) if (IS_ERR(dev->fw_handler)) return PTR_ERR(dev->fw_handler); - ret = mtk_vcodec_init_dec_pm(dev); + ret = mtk_vcodec_init_dec_pm(dev->plat_dev, &dev->pm); if (ret < 0) { dev_err(&pdev->dev, "Failed to get mt vcodec clock source"); goto err_dec_pm; @@ -379,7 +379,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) err_dec_alloc: v4l2_device_unregister(&dev->v4l2_dev); err_res: - mtk_vcodec_release_dec_pm(dev); + mtk_vcodec_release_dec_pm(&dev->pm); err_dec_pm: mtk_vcodec_fw_release(dev->fw_handler); return ret; @@ -422,7 +422,7 @@ static int mtk_vcodec_dec_remove(struct platform_device *pdev) video_unregister_device(dev->vfd_dec); v4l2_device_unregister(&dev->v4l2_dev); - mtk_vcodec_release_dec_pm(dev); + mtk_vcodec_release_dec_pm(&dev->pm); mtk_vcodec_fw_release(dev->fw_handler); return 0; } diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c index 6038db96f71c..20bd157a855c 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c @@ -13,18 +13,15 @@ #include "mtk_vcodec_dec_pm.h" #include "mtk_vcodec_util.h" -int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev) +int mtk_vcodec_init_dec_pm(struct platform_device *pdev, + struct mtk_vcodec_pm *pm) { struct device_node *node; - struct platform_device *pdev; - struct mtk_vcodec_pm *pm; + struct platform_device *larb_pdev; struct mtk_vcodec_clk *dec_clk; struct mtk_vcodec_clk_info *clk_info; int i = 0, ret = 0; - pdev = mtkdev->plat_dev; - pm = &mtkdev->pm; - pm->mtkdev = mtkdev; dec_clk = &pm->vdec_clk; node = of_parse_phandle(pdev->dev.of_node, "mediatek,larb", 0); if (!node) { @@ -32,13 +29,12 @@ int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev) return -1; } - pdev = of_find_device_by_node(node); + larb_pdev = of_find_device_by_node(node); of_node_put(node); - if (WARN_ON(!pdev)) { + if (WARN_ON(!larb_pdev)) { return -1; } - pm->larbvdec = &pdev->dev; - pdev = mtkdev->plat_dev; + pm->larbvdec = &larb_pdev->dev; pm->dev = &pdev->dev; dec_clk->clk_num = @@ -82,10 +78,10 @@ int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev) return ret; } -void mtk_vcodec_release_dec_pm(struct mtk_vcodec_dev *dev) +void mtk_vcodec_release_dec_pm(struct mtk_vcodec_pm *pm) { - pm_runtime_disable(dev->pm.dev); - put_device(dev->pm.larbvdec); + pm_runtime_disable(pm->dev); + put_device(pm->larbvdec); } int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h index 280aeaefdb65..a3df6aef6cb9 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h @@ -9,8 +9,9 @@ #include "mtk_vcodec_drv.h" -int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *dev); -void mtk_vcodec_release_dec_pm(struct mtk_vcodec_dev *dev); +int mtk_vcodec_init_dec_pm(struct platform_device *pdev, + struct mtk_vcodec_pm *pm); +void mtk_vcodec_release_dec_pm(struct mtk_vcodec_pm *pm); int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm); void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h index 3b1e5e3a450e..973b0b3649c6 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -195,7 +195,6 @@ struct mtk_vcodec_pm { struct mtk_vcodec_clk venc_clk; struct device *larbvenc; struct device *dev; - struct mtk_vcodec_dev *mtkdev; }; /** diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c index 1b2e4930ed27..0c8c8f86788c 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c @@ -26,7 +26,6 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev) pdev = mtkdev->plat_dev; pm = &mtkdev->pm; memset(pm, 0, sizeof(struct mtk_vcodec_pm)); - pm->mtkdev = mtkdev; pm->dev = &pdev->dev; dev = &pdev->dev; enc_clk = &pm->venc_clk; From patchwork Wed Sep 1 08:32:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46D44C43216 for ; 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Wed, 1 Sep 2021 16:32:25 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:24 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 05/15] dt-bindings: media: mtk-vcodec: Separate video encoder and decoder dt-bindings Date: Wed, 1 Sep 2021 16:32:05 +0800 Message-ID: <20210901083215.25984-6-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Decoder will use component framework to manage hardware, it is big difference with encoder. Reviewed-by: Rob Herring Signed-off-by: Yunfei Dong --- .../media/mediatek,vcodec-decoder.yaml | 175 +++++++++++++++++ .../media/mediatek,vcodec-encoder.yaml | 185 ++++++++++++++++++ .../bindings/media/mediatek-vcodec.txt | 130 ------------ 3 files changed, 360 insertions(+), 130 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml delete mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml new file mode 100644 index 000000000000..b6b97110024d --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-encoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Video Decode Accelerator With Component + +maintainers: + - Yunfei Dong + +description: |+ + Mediatek Video Decode is the video decode hardware present in Mediatek + SoCs which supports high resolution decoding functionalities. + +properties: + compatible: + enum: + - mediatek,mt8173-vcodec-dec + - mediatek,mt8183-vcodec-dec + + reg: + maxItems: 12 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 8 + + clock-names: + items: + - const: vcodecpll + - const: univpll_d2 + - const: clk_cci400_sel + - const: vdec_sel + - const: vdecpll + - const: vencpll + - const: venc_lt_sel + - const: vdec_bus_clk_src + + assigned-clocks: true + + assigned-clock-parents: true + + assigned-clock-rates: true + + power-domains: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + mediatek,larb: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: | + Must contain the local arbiters in the current Socs. + + mediatek,vpu: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Describes point to vpu. + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Describes point to scp. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + - assigned-clocks + - assigned-clock-parents + +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8183-vcodec-dec + + then: + required: + - mediatek,scp + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8173-vcodec-dec + + then: + required: + - mediatek,vpu + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + vcodec_dec: vcodec@16000000 { + compatible = "mediatek,mt8173-vcodec-dec"; + reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/ + <0 0x16020000 0 0x1000>, /*VDEC_MISC*/ + <0 0x16021000 0 0x800>, /*VDEC_LD*/ + <0 0x16021800 0 0x800>, /*VDEC_TOP*/ + <0 0x16022000 0 0x1000>, /*VDEC_CM*/ + <0 0x16023000 0 0x1000>, /*VDEC_AD*/ + <0 0x16024000 0 0x1000>, /*VDEC_AV*/ + <0 0x16025000 0 0x1000>, /*VDEC_PP*/ + <0 0x16026800 0 0x800>, /*VP8_VD*/ + <0 0x16027000 0 0x800>, /*VP6_VD*/ + <0 0x16027800 0 0x800>, /*VP8_VL*/ + <0 0x16028400 0 0x400>; /*VP9_VD*/ + interrupts = ; + mediatek,larb = <&larb1>; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; + mediatek,vpu = <&vpu>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vcodecpll", + "univpll_d2", + "clk_cci400_sel", + "vdec_sel", + "vdecpll", + "vencpll", + "venc_lt_sel", + "vdec_bus_clk_src"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_VCODECPLL>; + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml new file mode 100644 index 000000000000..6f28394e8ce3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-encoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Video Encode Accelerator With Component + +maintainers: + - Yunfei Dong + +description: |+ + Mediatek Video Encode is the video encode hardware present in Mediatek + SoCs which supports high resolution encoding functionalities. + +properties: + compatible: + enum: + - mediatek,mt8173-vcodec-enc-vp8 + - mediatek,mt8173-vcodec-enc + - mediatek,mt8183-vcodec-enc + - mediatek,mt8192-vcodec-enc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + assigned-clocks: true + + assigned-clock-parents: true + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + mediatek,larb: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: | + Must contain the local arbiters in the current Socs. + + mediatek,vpu: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Describes point to vpu. + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Describes point to scp. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + - assigned-clocks + - assigned-clock-parents + +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8183-vcodec-enc + - mediatek,mt8192-vcodec-enc + + then: + required: + - mediatek,scp + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8173-vcodec-enc-vp8 + - mediatek,mt8173-vcodec-enc + + then: + required: + - mediatek,vpu + + - if: + properties: + compatible: + enum: + - mediatek,mt8173-vcodec-enc + - mediatek,mt8192-vcodec-enc + - mediatek,mt8173-vcodec-enc + + then: + properties: + clock: + items: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: venc_sel + else: # for vp8 hw decoder + properties: + clock: + items: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: venc_lt_sel + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + vcodec_enc_avc: vcodec@18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>; + interrupts = ; + iommus = <&iommu M4U_PORT_VENC_RCPU>, + <&iommu M4U_PORT_VENC_REC>, + <&iommu M4U_PORT_VENC_BSDMA>, + <&iommu M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_PORT_VENC_NBM_WDMA>; + mediatek,larb = <&larb3>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + }; + + vcodec_enc_vp8: vcodec@19002000 { + compatible = "mediatek,mt8173-vcodec-enc-vp8"; + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = ; + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,larb = <&larb5>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt deleted file mode 100644 index c44a6e6943af..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ /dev/null @@ -1,130 +0,0 @@ -Mediatek Video Codec - -Mediatek Video Codec is the video codec hw present in Mediatek SoCs which -supports high resolution encoding and decoding functionalities. - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder. - "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder. - "mediatek,mt8183-vcodec-enc" for MT8183 encoder. - "mediatek,mt8173-vcodec-dec" for MT8173 decoder. - "mediatek,mt8192-vcodec-enc" for MT8192 encoder. - "mediatek,mt8183-vcodec-dec" for MT8183 decoder. -- reg : Physical base address of the video codec registers and length of - memory mapped region. -- interrupts : interrupt number to the cpu. -- mediatek,larb : must contain the local arbiters in the current Socs. -- clocks : list of clock specifiers, corresponding to entries in - the clock-names property. -- clock-names: avc encoder must contain "venc_sel", vp8 encoder must - contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2", - "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", - "vdec_bus_clk_src". -- iommus : should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml - for details. -- dma-ranges : describes the dma address range space that the codec hw access. -One of the two following nodes: -- mediatek,vpu : the node of the video processor unit, if using VPU. -- mediatek,scp : the node of the SCP unit, if using SCP. - - -Example: - -vcodec_dec: vcodec@16000000 { - compatible = "mediatek,mt8173-vcodec-dec"; - reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/ - <0 0x16020000 0 0x1000>, /*VDEC_MISC*/ - <0 0x16021000 0 0x800>, /*VDEC_LD*/ - <0 0x16021800 0 0x800>, /*VDEC_TOP*/ - <0 0x16022000 0 0x1000>, /*VDEC_CM*/ - <0 0x16023000 0 0x1000>, /*VDEC_AD*/ - <0 0x16024000 0 0x1000>, /*VDEC_AV*/ - <0 0x16025000 0 0x1000>, /*VDEC_PP*/ - <0 0x16026800 0 0x800>, /*VP8_VD*/ - <0 0x16027000 0 0x800>, /*VP6_VD*/ - <0 0x16027800 0 0x800>, /*VP8_VL*/ - <0 0x16028400 0 0x400>; /*VP9_VD*/ - interrupts = ; - mediatek,larb = <&larb1>; - iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, - <&iommu M4U_PORT_HW_VDEC_PP_EXT>, - <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, - <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; - mediatek,vpu = <&vpu>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&topckgen CLK_TOP_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>, - <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; - clock-names = "vcodecpll", - "univpll_d2", - "clk_cci400_sel", - "vdec_sel", - "vdecpll", - "vencpll", - "venc_lt_sel", - "vdec_bus_clk_src"; - assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_VCODECPLL>; - assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; - }; - -vcodec_enc_avc: vcodec@18002000 { - compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>; - interrupts = ; - iommus = <&iommu M4U_PORT_VENC_RCPU>, - <&iommu M4U_PORT_VENC_REC>, - <&iommu M4U_PORT_VENC_BSDMA>, - <&iommu M4U_PORT_VENC_SV_COMV>, - <&iommu M4U_PORT_VENC_RD_COMV>, - <&iommu M4U_PORT_VENC_CUR_LUMA>, - <&iommu M4U_PORT_VENC_CUR_CHROMA>, - <&iommu M4U_PORT_VENC_REF_LUMA>, - <&iommu M4U_PORT_VENC_REF_CHROMA>, - <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>; - mediatek,larb = <&larb3>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENC_SEL>; - clock-names = "venc_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; - }; - -vcodec_enc_vp8: vcodec@19002000 { - compatible = "mediatek,mt8173-vcodec-enc-vp8"; - reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = ; - iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,larb = <&larb5>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; - }; From patchwork Wed Sep 1 08:32:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FBA3C43216 for ; Wed, 1 Sep 2021 08:32:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 360C761057 for ; Wed, 1 Sep 2021 08:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243368AbhIAIdg (ORCPT ); Wed, 1 Sep 2021 04:33:36 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51146 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243331AbhIAIdc (ORCPT ); Wed, 1 Sep 2021 04:33:32 -0400 X-UUID: fd8a5d0d514141d3b8f760861d104421-20210901 X-UUID: fd8a5d0d514141d3b8f760861d104421-20210901 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 188293874; Wed, 01 Sep 2021 16:32:33 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:31 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:30 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 09/15] media: mtk-vcodec: Generalize power and clock on/off interfaces Date: Wed, 1 Sep 2021 16:32:09 +0800 Message-ID: <20210901083215.25984-10-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Generalizes power and clock on/off interfaces to support different hardware. Signed-off-by: Yunfei Dong --- .../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 +- .../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +- .../platform/mtk-vcodec/mtk_vcodec_dec_hw.h | 4 + .../platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 76 ++++++++++++++-- .../platform/mtk-vcodec/mtk_vcodec_dec_pm.h | 8 +- .../platform/mtk-vcodec/mtk_vcodec_drv.h | 2 + .../platform/mtk-vcodec/mtk_vcodec_util.c | 87 ++++++++++++++++--- .../platform/mtk-vcodec/mtk_vcodec_util.h | 8 +- .../media/platform/mtk-vcodec/vdec_drv_if.c | 21 ++--- 9 files changed, 174 insertions(+), 40 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index f096ad1c01ac..109f7de126a1 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -126,7 +126,7 @@ static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) void __iomem *vdec_misc_addr = dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG; - ctx = mtk_vcodec_get_curr_ctx(dev); + ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE); /* check if HW active or not */ cg_status = readl(dev->reg_base[0]); @@ -286,7 +286,7 @@ static int fops_vcodec_open(struct file *file) mtk_vcodec_dec_set_default_params(ctx); if (v4l2_fh_is_singular(&ctx->fh)) { - ret = mtk_vcodec_dec_pw_on(&dev->pm); + ret = mtk_vcodec_dec_pw_on(dev, MTK_VDEC_LAT0); if (ret < 0) goto err_load_fw; /* @@ -347,7 +347,7 @@ static int fops_vcodec_release(struct file *file) mtk_vcodec_dec_release(ctx); if (v4l2_fh_is_singular(&ctx->fh)) - mtk_vcodec_dec_pw_off(&dev->pm); + mtk_vcodec_dec_pw_off(dev, MTK_VDEC_LAT0); v4l2_fh_del(&ctx->fh); v4l2_fh_exit(&ctx->fh); v4l2_ctrl_handler_free(&ctx->ctrl_hdl); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c index 7a31afd294ba..714df68ffb19 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.c @@ -68,7 +68,7 @@ static irqreturn_t mtk_vdec_comp_irq_handler(int irq, void *priv) void __iomem *vdec_misc_addr = dev->reg_base[VDEC_COMP_MISC] + VDEC_IRQ_CFG_REG; - ctx = mtk_vcodec_get_curr_ctx(dev->master_dev); + ctx = mtk_vcodec_get_curr_ctx(dev->master_dev, dev->comp_idx); /* check if HW active or not */ cg_status = readl(dev->reg_base[VDEC_COMP_SYS]); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h index 8d6e818a3474..0a4c2e6f5df2 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_hw.h @@ -32,6 +32,8 @@ enum mtk_comp_hw_reg_idx { * @master_dev: master device * @reg_base: Mapped address of MTK Vcodec registers. * + * @curr_ctx: The context that is waiting for codec hardware + * * @dec_irq: decoder irq resource * @pm: power management control * @comp_idx: component index @@ -41,6 +43,8 @@ struct mtk_vdec_comp_dev { struct mtk_vcodec_dev *master_dev; void __iomem *reg_base[VDEC_COMP_MAX]; + struct mtk_vcodec_ctx *curr_ctx; + int dec_irq; struct mtk_vcodec_pm pm; int comp_idx; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c index 20bd157a855c..183d4c4e36f0 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c @@ -5,11 +5,13 @@ */ #include +#include #include #include #include #include +#include "mtk_vcodec_dec_hw.h" #include "mtk_vcodec_dec_pm.h" #include "mtk_vcodec_util.h" @@ -84,10 +86,23 @@ void mtk_vcodec_release_dec_pm(struct mtk_vcodec_pm *pm) put_device(pm->larbvdec); } -int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) +int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int comp_idx) { + struct mtk_vdec_comp_dev *comp_dev; + struct mtk_vcodec_pm *pm; int ret; + if (vdec_dev->vdec_pdata->is_comp_supported) { + comp_dev = mtk_vcodec_get_hw_dev(vdec_dev, comp_idx); + if (!comp_dev) { + mtk_v4l2_err("Failed to get hw dev\n"); + return -EINVAL; + } + pm = &comp_dev->pm; + } else { + pm = &vdec_dev->pm; + } + ret = pm_runtime_resume_and_get(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_resume_and_get fail %d", ret); @@ -95,20 +110,49 @@ int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) return ret; } -void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm) +void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int comp_idx) { + struct mtk_vdec_comp_dev *comp_dev; + struct mtk_vcodec_pm *pm; int ret; + if (vdec_dev->vdec_pdata->is_comp_supported) { + comp_dev = mtk_vcodec_get_hw_dev(vdec_dev, comp_idx); + if (!comp_dev) { + mtk_v4l2_err("Failed to get hw dev\n"); + return; + } + pm = &comp_dev->pm; + } else { + pm = &vdec_dev->pm; + } + ret = pm_runtime_put_sync(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); } -void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) +void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int comp_idx) { - struct mtk_vcodec_clk *dec_clk = &pm->vdec_clk; - int ret, i = 0; + struct mtk_vdec_comp_dev *comp_dev; + struct mtk_vcodec_pm *pm; + struct mtk_vcodec_clk *dec_clk; + int ret, i; + + if (vdec_dev->vdec_pdata->is_comp_supported) { + comp_dev = mtk_vcodec_get_hw_dev(vdec_dev, comp_idx); + if (!comp_dev) { + mtk_v4l2_err("Failed to get hw dev\n"); + return; + } + pm = &comp_dev->pm; + enable_irq(comp_dev->dec_irq); + } else { + pm = &vdec_dev->pm; + enable_irq(vdec_dev->dec_irq); + } + dec_clk = &pm->vdec_clk; for (i = 0; i < dec_clk->clk_num; i++) { ret = clk_prepare_enable(dec_clk->clk_info[i].vcodec_clk); if (ret) { @@ -130,11 +174,27 @@ void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); } -void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm) +void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int comp_idx) { - struct mtk_vcodec_clk *dec_clk = &pm->vdec_clk; - int i = 0; + struct mtk_vdec_comp_dev *comp_dev; + struct mtk_vcodec_pm *pm; + struct mtk_vcodec_clk *dec_clk; + int i; + if (vdec_dev->vdec_pdata->is_comp_supported) { + comp_dev = mtk_vcodec_get_hw_dev(vdec_dev, comp_idx); + if (!comp_dev) { + mtk_v4l2_err("Failed to get hw dev\n"); + return; + } + pm = &comp_dev->pm; + disable_irq(comp_dev->dec_irq); + } else { + pm = &vdec_dev->pm; + disable_irq(vdec_dev->dec_irq); + } + + dec_clk = &pm->vdec_clk; mtk_smi_larb_put(pm->larbvdec); for (i = dec_clk->clk_num - 1; i >= 0; i--) clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h index a3df6aef6cb9..698750572b57 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.h @@ -13,9 +13,9 @@ int mtk_vcodec_init_dec_pm(struct platform_device *pdev, struct mtk_vcodec_pm *pm); void mtk_vcodec_release_dec_pm(struct mtk_vcodec_pm *pm); -int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm); -void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm); -void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm); -void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm); +int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int comp_idx); +void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int comp_idx); +void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int comp_idx); +void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int comp_idx); #endif /* _MTK_VCODEC_DEC_PM_H_ */ diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h index 4ad0566e715d..a8242389ad24 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -284,6 +284,7 @@ struct vdec_pic_info { * @decoded_frame_cnt: number of decoded frames * @lock: protect variables accessed by V4L2 threads and worker thread such as * mtk_video_dec_buf. + * @hw_id: hardware index used to identify different hardware. * * @msg_queue: msg queue used to store lat buffer information. */ @@ -328,6 +329,7 @@ struct mtk_vcodec_ctx { int decoded_frame_cnt; struct mutex lock; + int hw_id; struct vdec_msg_queue msg_queue; }; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.c index ac5973b6735f..511b75e49fe7 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.c @@ -6,7 +6,10 @@ */ #include +#include +#include +#include "mtk_vcodec_dec_hw.h" #include "mtk_vcodec_drv.h" #include "mtk_vcodec_util.h" @@ -81,25 +84,87 @@ void mtk_vcodec_mem_free(struct mtk_vcodec_ctx *data, } EXPORT_SYMBOL(mtk_vcodec_mem_free); -void mtk_vcodec_set_curr_ctx(struct mtk_vcodec_dev *dev, - struct mtk_vcodec_ctx *ctx) +void *mtk_vcodec_get_hw_dev(struct mtk_vcodec_dev *dev, int comp_idx) { - unsigned long flags; + struct platform_device *hw_pdev; + struct device_node *node; + struct mtk_vdec_comp_dev *master_dev; + + if (comp_idx >= MTK_VDEC_HW_MAX || comp_idx < 0) { + mtk_v4l2_err("Comp idx is out of range:%d", comp_idx); + return NULL; + } + + if (dev->comp_dev[comp_idx]) + return dev->comp_dev[comp_idx]; + + node = dev->component_node[comp_idx]; + if (!node) { + mtk_v4l2_err("Get lat node fail:%d", comp_idx); + return NULL; + } + + hw_pdev = of_find_device_by_node(node); + of_node_put(node); + + if (WARN_ON(!hw_pdev)) { + mtk_v4l2_err("Get hw id(%d) node fail", comp_idx); + return NULL; + } + + master_dev = platform_get_drvdata(hw_pdev); + if (!master_dev) { + mtk_v4l2_err("Get hw id(%d) pdev fail", comp_idx); + return NULL; + } - spin_lock_irqsave(&dev->irqlock, flags); - dev->curr_ctx = ctx; - spin_unlock_irqrestore(&dev->irqlock, flags); + dev->comp_dev[master_dev->comp_idx] = master_dev; + return master_dev; +} +EXPORT_SYMBOL(mtk_vcodec_get_hw_dev); + +void mtk_vcodec_set_curr_ctx(struct mtk_vcodec_dev *vdec_dev, + struct mtk_vcodec_ctx *ctx, int comp_idx) +{ + unsigned long flags; + struct mtk_vdec_comp_dev *comp_dev; + + spin_lock_irqsave(&vdec_dev->irqlock, flags); + if (vdec_dev->vdec_pdata->is_comp_supported) { + comp_dev = mtk_vcodec_get_hw_dev(vdec_dev, comp_idx); + if (!comp_dev) { + mtk_v4l2_err("Failed to get hw dev"); + spin_unlock_irqrestore(&vdec_dev->irqlock, flags); + return; + } + comp_dev->curr_ctx = ctx; + } else { + vdec_dev->curr_ctx = ctx; + } + spin_unlock_irqrestore(&vdec_dev->irqlock, flags); } EXPORT_SYMBOL(mtk_vcodec_set_curr_ctx); -struct mtk_vcodec_ctx *mtk_vcodec_get_curr_ctx(struct mtk_vcodec_dev *dev) +struct mtk_vcodec_ctx *mtk_vcodec_get_curr_ctx(struct mtk_vcodec_dev *vdec_dev, + unsigned int comp_idx) { unsigned long flags; struct mtk_vcodec_ctx *ctx; - - spin_lock_irqsave(&dev->irqlock, flags); - ctx = dev->curr_ctx; - spin_unlock_irqrestore(&dev->irqlock, flags); + struct mtk_vdec_comp_dev *comp_dev; + + spin_lock_irqsave(&vdec_dev->irqlock, flags); + if (vdec_dev->vdec_pdata->is_comp_supported) { + comp_dev = mtk_vcodec_get_hw_dev(vdec_dev, comp_idx); + if (!comp_dev) { + mtk_v4l2_err("Failed to get hw dev"); + spin_unlock_irqrestore(&vdec_dev->irqlock, flags); + return NULL; + } + ctx = comp_dev->curr_ctx; + } else { + ctx = vdec_dev->curr_ctx; + } + spin_unlock_irqrestore(&vdec_dev->irqlock, flags); return ctx; } EXPORT_SYMBOL(mtk_vcodec_get_curr_ctx); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h index b999d7b84ed1..4cb0fc60c94f 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h @@ -79,8 +79,10 @@ int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem); void mtk_vcodec_mem_free(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem); -void mtk_vcodec_set_curr_ctx(struct mtk_vcodec_dev *dev, - struct mtk_vcodec_ctx *ctx); -struct mtk_vcodec_ctx *mtk_vcodec_get_curr_ctx(struct mtk_vcodec_dev *dev); +void mtk_vcodec_set_curr_ctx(struct mtk_vcodec_dev *vdec_dev, + struct mtk_vcodec_ctx *ctx, int comp_idx); +struct mtk_vcodec_ctx *mtk_vcodec_get_curr_ctx(struct mtk_vcodec_dev *vdec_dev, + unsigned int comp_idx); +void *mtk_vcodec_get_hw_dev(struct mtk_vcodec_dev *dev, int comp_idx); #endif /* _MTK_VCODEC_UTIL_H_ */ diff --git a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c b/drivers/media/platform/mtk-vcodec/vdec_drv_if.c index 42008243ceac..05a5b240e906 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec_drv_if.c @@ -24,21 +24,24 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc) break; case V4L2_PIX_FMT_H264: ctx->dec_if = &vdec_h264_if; + ctx->hw_id = MTK_VDEC_CORE; break; case V4L2_PIX_FMT_VP8: ctx->dec_if = &vdec_vp8_if; + ctx->hw_id = MTK_VDEC_CORE; break; case V4L2_PIX_FMT_VP9: ctx->dec_if = &vdec_vp9_if; + ctx->hw_id = MTK_VDEC_CORE; break; default: return -EINVAL; } mtk_vdec_lock(ctx); - mtk_vcodec_dec_clock_on(&ctx->dev->pm); + mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); ret = ctx->dec_if->init(ctx); - mtk_vcodec_dec_clock_off(&ctx->dev->pm); + mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); mtk_vdec_unlock(ctx); return ret; @@ -69,13 +72,11 @@ int vdec_if_decode(struct mtk_vcodec_ctx *ctx, struct mtk_vcodec_mem *bs, mtk_vdec_lock(ctx); - mtk_vcodec_set_curr_ctx(ctx->dev, ctx); - mtk_vcodec_dec_clock_on(&ctx->dev->pm); - enable_irq(ctx->dev->dec_irq); + mtk_vcodec_set_curr_ctx(ctx->dev, ctx, ctx->hw_id); + mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); ret = ctx->dec_if->decode(ctx->drv_handle, bs, fb, res_chg); - disable_irq(ctx->dev->dec_irq); - mtk_vcodec_dec_clock_off(&ctx->dev->pm); - mtk_vcodec_set_curr_ctx(ctx->dev, NULL); + mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); + mtk_vcodec_set_curr_ctx(ctx->dev, NULL, ctx->hw_id); mtk_vdec_unlock(ctx); @@ -103,9 +104,9 @@ void vdec_if_deinit(struct mtk_vcodec_ctx *ctx) return; mtk_vdec_lock(ctx); - mtk_vcodec_dec_clock_on(&ctx->dev->pm); + mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); ctx->dec_if->deinit(ctx->drv_handle); - mtk_vcodec_dec_clock_off(&ctx->dev->pm); + mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); mtk_vdec_unlock(ctx); ctx->drv_handle = NULL; From patchwork Wed Sep 1 08:32:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C26DFC4320A for ; Wed, 1 Sep 2021 08:33:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD4566108B for ; Wed, 1 Sep 2021 08:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243371AbhIAId4 (ORCPT ); Wed, 1 Sep 2021 04:33:56 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:43370 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243305AbhIAIdg (ORCPT ); Wed, 1 Sep 2021 04:33:36 -0400 X-UUID: 145919c5bf884c09bb44cf065c520b1d-20210901 X-UUID: 145919c5bf884c09bb44cf065c520b1d-20210901 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1015915197; Wed, 01 Sep 2021 16:32:34 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:33 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:32 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 10/15] media: mtk-vcodec: Add new interface to lock different hardware Date: Wed, 1 Sep 2021 16:32:10 +0800 Message-ID: <20210901083215.25984-11-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For add new hardware, not only need to lock lat hardware, also need to lock core hardware in case of different instance start to decoder at the same time. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 4 ++-- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 +++--- drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c index 2b334a8a81c6..130ecef2e766 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -105,12 +105,12 @@ static int vidioc_decoder_cmd(struct file *file, void *priv, void mtk_vdec_unlock(struct mtk_vcodec_ctx *ctx) { - mutex_unlock(&ctx->dev->dec_mutex); + mutex_unlock(&ctx->dev->dec_mutex[ctx->hw_id]); } void mtk_vdec_lock(struct mtk_vcodec_ctx *ctx) { - mutex_lock(&ctx->dev->dec_mutex); + mutex_lock(&ctx->dev->dec_mutex[ctx->hw_id]); } void mtk_vcodec_dec_release(struct mtk_vcodec_ctx *ctx) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index 109f7de126a1..e448cb238c7f 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -373,7 +373,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) struct video_device *vfd_dec; phandle rproc_phandle; enum mtk_vcodec_fw_type fw_type; - int ret; + int i, ret; dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); if (!dev) @@ -405,8 +405,8 @@ static int mtk_vcodec_probe(struct platform_device *pdev) goto err_dec_pm; } - mutex_init(&dev->dec_mutex); - mutex_init(&dev->dev_mutex); + for (i = 0; i < MTK_VDEC_HW_MAX; i++) + mutex_init(&dev->dec_mutex[i]); spin_lock_init(&dev->irqlock); snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s", diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h index a8242389ad24..f1e63acaec76 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h @@ -496,7 +496,7 @@ struct mtk_vcodec_dev { int dec_irq; int enc_irq; - struct mutex dec_mutex; + struct mutex dec_mutex[MTK_VDEC_HW_MAX]; struct mutex enc_mutex; struct mtk_vcodec_pm pm; From patchwork Wed Sep 1 08:32:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A892C432BE for ; Wed, 1 Sep 2021 08:35:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 52A1760FED for ; Wed, 1 Sep 2021 08:35:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243294AbhIAIgI (ORCPT ); Wed, 1 Sep 2021 04:36:08 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51564 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243331AbhIAIdo (ORCPT ); Wed, 1 Sep 2021 04:33:44 -0400 X-UUID: 8f4dd9e0392e42e1beecd9c5552a8eba-20210901 X-UUID: 8f4dd9e0392e42e1beecd9c5552a8eba-20210901 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 210389898; Wed, 01 Sep 2021 16:32:43 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:35 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:34 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 12/15] media: mtk-vcodec: Support 34bits dma address for vdec Date: Wed, 1 Sep 2021 16:32:12 +0800 Message-ID: <20210901083215.25984-13-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use the dma_set_mask_and_coherent helper to set vdec DMA bit mask to support 34bits iova space(16GB) that the mt8192 iommu HW support. Whole the iova range separate to 0~4G/4G~8G/8G~12G/12G~16G, regarding which iova range VDEC actually locate, it depends on the dma-ranges property of vdec dtsi node. Signed-off-by: Yunfei Dong --- drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c index 002352fcf8de..1a8d9308327d 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c @@ -417,6 +417,9 @@ static int mtk_vcodec_probe(struct platform_device *pdev) } } + if (of_get_property(pdev->dev.of_node, "dma-ranges", NULL)) + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34)); + for (i = 0; i < MTK_VDEC_HW_MAX; i++) mutex_init(&dev->dec_mutex[i]); spin_lock_init(&dev->irqlock); From patchwork Wed Sep 1 08:32:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59F2CC432BE for ; Wed, 1 Sep 2021 08:32:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4257961054 for ; Wed, 1 Sep 2021 08:32:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243450AbhIAIds (ORCPT ); Wed, 1 Sep 2021 04:33:48 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51350 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243389AbhIAIdi (ORCPT ); Wed, 1 Sep 2021 04:33:38 -0400 X-UUID: 9daa3dcc3cbc4119988739c24aeed941-20210901 X-UUID: 9daa3dcc3cbc4119988739c24aeed941-20210901 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1311144393; Wed, 01 Sep 2021 16:32:38 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:37 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:36 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v6, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192 Date: Wed, 1 Sep 2021 16:32:13 +0800 Message-ID: <20210901083215.25984-14-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds decoder dt-bindings for mt8192. Signed-off-by: Yunfei Dong --- v6: add decoder block diagram for Laurent's comments. This patch depends on "Mediatek MT8192 clock support"[1]. The definition of decoder clocks are in mt8192-clk.h, and this patch already in clk tree[1]. [1]https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/?h=clk-next&id=f35f1a23e0e12e3173e9e9dedbc150d139027189 --- .../media/mediatek,vcodec-comp-decoder.yaml | 192 ++++++++++++++++++ 1 file changed, 192 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml new file mode 100644 index 000000000000..2184cf7ef9e3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Video Decode Accelerator With Component + +maintainers: + - Yunfei Dong + +description: |+ + Mediatek Video Decode is the video decode hardware present in Mediatek + SoCs which supports high resolution decoding functionalities. Required + master and component node. + + About the Decoder Hardware Block Diagram, please check below: + + +---------------------------------+------------------------------------+ + | | | + | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | + | || | || | + +------------||-------------------+---------------------||-------------+ + || lat thread | core thread || + -------------||-----------------------------------------||---------------- + || || + \/ <----------------HW index-------------->\/ + +------------------------------------------------------+ + | enable/disable | + | clk power irq iommu port | + | (lat/lat soc/core0/core1) | + +------------------------------------------------------+ + + As above, mean in master device, mean in component device. + The information of each hardware will be stored in each component device. There + are two thread in master device: lat and core. Enable/disable the lat clk/power/irq + when lat hardware need to work through hardware index, core is the same. + + Normally the smi common may not the same for each hardware, can't combine all + hardware in one node, or leading to iommu fault when access dram data. + +properties: + compatible: + - enum: + - mediatek,mt8192-vcodec-dec # for lat hardware + - mediatek,mtk-vcodec-lat # for core hardware + - mediatek,mtk-vcodec-core + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 5 + + clock-names: + items: + - const: vdec-sel + - const: vdec-soc-vdec + - const: vdec-soc-lat + - const: vdec-vdec + - const: vdec-top + + power-domains: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Describes point to scp. + +required: + - compatible + - reg + - iommus + - dma-ranges + +allOf: + - if: #master node + properties: + compatible: + contains: + enum: + - mediatek,mt8192-vcodec-dec # for lat hardware + + then: + required: + - mediatek,scp + + - if: #component node + properties: + compatible: + contains: + enum: + - mediatek,mtk-vcodec-lat # for core hardware + - mediatek,mtk-vcodec-core + + then: + required: + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - power-domains + + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + vcodec_dec: vcodec_dec@16000000 { + compatible = "mediatek,mt8192-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + mediatek,scp = <&scp>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + + vcodec_lat: vcodec_lat@0x16010000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ + interrupts = ; + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", + "vdec-vdec", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec_core@0x16025000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", + "vdec-vdec", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; From patchwork Wed Sep 1 08:32:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 505253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB089C432BE for ; Wed, 1 Sep 2021 08:35:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AAAF60FED for ; Wed, 1 Sep 2021 08:35:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243408AbhIAIgM (ORCPT ); Wed, 1 Sep 2021 04:36:12 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:43528 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S243398AbhIAIdl (ORCPT ); Wed, 1 Sep 2021 04:33:41 -0400 X-UUID: 996d24e720264c239cf27fc30e2695cc-20210901 X-UUID: 996d24e720264c239cf27fc30e2695cc-20210901 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2109408028; Wed, 01 Sep 2021 16:32:42 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:40 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkcas07.mediatek.inc (172.21.101.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 1 Sep 2021 16:32:39 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 1 Sep 2021 16:32:38 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , "Tzung-Bi Shih" , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Laurent Pinchart CC: Daniel Vetter , dri-devel , Hsin-Yi Wang , "Fritz Koenig" , Irui Wang , , , , , , , Subject: [PATCH v6, 15/15] media: mtk-vcodec: Use codec type to separate different hardware Date: Wed, 1 Sep 2021 16:32:15 +0800 Message-ID: <20210901083215.25984-16-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com> References: <20210901083215.25984-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are just one core thread, in order to separeate different hardware, using codec type to separeate it in scp driver. Signed-off-by: Yunfei Dong --- .../media/platform/mtk-vcodec/vdec_ipi_msg.h | 12 ++++--- .../media/platform/mtk-vcodec/vdec_vpu_if.c | 34 ++++++++++++++++--- .../media/platform/mtk-vcodec/vdec_vpu_if.h | 4 +++ 3 files changed, 41 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h b/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h index 9d8079c4f976..c488f0c40190 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h +++ b/drivers/media/platform/mtk-vcodec/vdec_ipi_msg.h @@ -35,6 +35,8 @@ enum vdec_ipi_msgid { * @msg_id : vdec_ipi_msgid * @vpu_inst_addr : VPU decoder instance address. Used if ABI version < 2. * @inst_id : instance ID. Used if the ABI version >= 2. + * @codec_type : Codec fourcc + * @reserved : reserved param */ struct vdec_ap_ipi_cmd { uint32_t msg_id; @@ -42,6 +44,8 @@ struct vdec_ap_ipi_cmd { uint32_t vpu_inst_addr; uint32_t inst_id; }; + uint32_t codec_type; + uint32_t reserved; }; /** @@ -59,12 +63,12 @@ struct vdec_vpu_ipi_ack { /** * struct vdec_ap_ipi_init - for AP_IPIMSG_DEC_INIT * @msg_id : AP_IPIMSG_DEC_INIT - * @reserved : Reserved field + * @codec_type : Codec fourcc * @ap_inst_addr : AP video decoder instance address */ struct vdec_ap_ipi_init { uint32_t msg_id; - uint32_t reserved; + uint32_t codec_type; uint64_t ap_inst_addr; }; @@ -77,7 +81,7 @@ struct vdec_ap_ipi_init { * H264 decoder [0]:buf_sz [1]:nal_start * VP8 decoder [0]:width/height * VP9 decoder [0]:profile, [1][2] width/height - * @reserved : Reserved field + * @codec_type : Codec fourcc */ struct vdec_ap_ipi_dec_start { uint32_t msg_id; @@ -86,7 +90,7 @@ struct vdec_ap_ipi_dec_start { uint32_t inst_id; }; uint32_t data[3]; - uint32_t reserved; + uint32_t codec_type; }; /** diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c index bfd8e87dceff..c84fac52fe26 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.c @@ -100,18 +100,29 @@ static void vpu_dec_ipi_handler(void *data, unsigned int len, void *priv) static int vcodec_vpu_send_msg(struct vdec_vpu_inst *vpu, void *msg, int len) { - int err; + int err, id, msgid; - mtk_vcodec_debug(vpu, "id=%X", *(uint32_t *)msg); + msgid = *(uint32_t *)msg; + mtk_vcodec_debug(vpu, "id=%X", msgid); vpu->failure = 0; vpu->signaled = 0; - err = mtk_vcodec_fw_ipi_send(vpu->ctx->dev->fw_handler, vpu->id, msg, + if (vpu->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_LAT_SINGLE_CORE) { + if (msgid == AP_IPIMSG_DEC_CORE || + msgid == AP_IPIMSG_DEC_CORE_END) + id = vpu->core_id; + else + id = vpu->id; + } else { + id = vpu->id; + } + + err = mtk_vcodec_fw_ipi_send(vpu->ctx->dev->fw_handler, id, msg, len, 2000); if (err) { mtk_vcodec_err(vpu, "send fail vpu_id=%d msg_id=%X status=%d", - vpu->id, *(uint32_t *)msg, err); + id, msgid, err); return err; } @@ -131,6 +142,7 @@ static int vcodec_send_ap_ipi(struct vdec_vpu_inst *vpu, unsigned int msg_id) msg.vpu_inst_addr = vpu->inst_addr; else msg.inst_id = vpu->inst_id; + msg.codec_type = vpu->codec_type; err = vcodec_vpu_send_msg(vpu, &msg, sizeof(msg)); mtk_vcodec_debug(vpu, "- id=%X ret=%d", msg_id, err); @@ -149,14 +161,25 @@ int vpu_dec_init(struct vdec_vpu_inst *vpu) err = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler, vpu->id, vpu->handler, "vdec", NULL); - if (err != 0) { + if (err) { mtk_vcodec_err(vpu, "vpu_ipi_register fail status=%d", err); return err; } + if (vpu->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_LAT_SINGLE_CORE) { + err = mtk_vcodec_fw_ipi_register(vpu->ctx->dev->fw_handler, + vpu->core_id, vpu->handler, + "vdec", NULL); + if (err) { + mtk_vcodec_err(vpu, "vpu_ipi_register core fail status=%d", err); + return err; + } + } + memset(&msg, 0, sizeof(msg)); msg.msg_id = AP_IPIMSG_DEC_INIT; msg.ap_inst_addr = (unsigned long)vpu; + msg.codec_type = vpu->codec_type; mtk_vcodec_debug(vpu, "vdec_inst=%p", vpu); @@ -187,6 +210,7 @@ int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len) for (i = 0; i < len; i++) msg.data[i] = data[i]; + msg.codec_type = vpu->codec_type; err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg)); mtk_vcodec_debug(vpu, "- ret=%d", err); diff --git a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h index ae24b75d1649..802660770a87 100644 --- a/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h +++ b/drivers/media/platform/mtk-vcodec/vdec_vpu_if.h @@ -14,6 +14,7 @@ struct mtk_vcodec_ctx; /** * struct vdec_vpu_inst - VPU instance for video codec * @id : ipi msg id for each decoder + * @core_id : core id used to separate different hardware * @vsi : driver structure allocated by VPU side and shared to AP side * for control and info share * @failure : VPU execution result status, 0: success, others: fail @@ -26,9 +27,11 @@ struct mtk_vcodec_ctx; * @dev : platform device of VPU * @wq : wait queue to wait VPU message ack * @handler : ipi handler for each decoder + * @codec_type : used codec type to separate different codecs */ struct vdec_vpu_inst { int id; + int core_id; void *vsi; int32_t failure; uint32_t inst_addr; @@ -38,6 +41,7 @@ struct vdec_vpu_inst { struct mtk_vcodec_ctx *ctx; wait_queue_head_t wq; mtk_vcodec_ipi_handler handler; + unsigned int codec_type; }; /**