From patchwork Wed Sep 1 05:39:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 505265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1E85C43214 for ; Wed, 1 Sep 2021 05:39:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D21A1610FD for ; Wed, 1 Sep 2021 05:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242062AbhIAFkx (ORCPT ); Wed, 1 Sep 2021 01:40:53 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:43051 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242046AbhIAFkw (ORCPT ); Wed, 1 Sep 2021 01:40:52 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 1A5585804EC; Wed, 1 Sep 2021 01:39:56 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 01 Sep 2021 01:39:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=xNxl1EEs8ZC8t hhUYggA/mA77asD+KQkI79V0Cgwm9k=; b=rb6ZY5b0GyM3AmHeW555IzXGQeEyJ tRwWIupsqdj/FJgzo9vawl1Wr0IepLnC4bjsCjPQE39TA9uwHWBvDvQHHyINpNF/ jrEGH5/OS3zQFPNOFA+UB1AaNgqrGltfdS1zQmOXQ3fDk34BXJdM5Ea8JEY0aSo7 YmsK5wTYwbeARfCyzqaAFi+VpILz3hI6k/SSW2eQeJlOva2fOrGCxeza+qj7VKQ5 Ol2s0fDH0n4urAcBp1Gk38wup+E2lkHibuZQMbBGpQW4RXiMQt+8Z+IRS3PHHROQ RnRAQrhUyC/YSpWRk92rer2xEegST8gJar9zsuNAIHHS4MXwbh8gKsbGA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=xNxl1EEs8ZC8thhUYggA/mA77asD+KQkI79V0Cgwm9k=; b=RI1dDRfS jDayyk9cWjw/fbRuwpz7Ux4OPsClzrV8SZXOeVoxBOr7ar0RrcaLyya86NMThEVx L1V7LVmlog9t8uKvGFa4wPuksx109mDdFiiAu/Yc/zaRA5CmVRrsYtU9JEwOBwov zXMOxpzgxmFE8aoZlIZwkDQoVG+Vss/slVyRe+0RNm1fi83jIBYb17aFTsxsb7tE BPH9Bqm18bFk/a7ORV0UF4I5wD6G/jD3omQWRfEIyID8cmY7mszfAjoGFv4lVxQ2 mY7Q+3toYCDBvV5FeypJQ+4l0cicsT1YPxZ1nXGBw3IXXLijILsvECU5N+hrd+fB SqSHMIVyES8M4A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddruddvvddgleejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 1 Sep 2021 01:39:55 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 1/7] dt-bindings: rtc: sun6i: Add H616 and R329 compatibles Date: Wed, 1 Sep 2021 00:39:45 -0500 Message-Id: <20210901053951.60952-2-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For these new SoCs, start requiring a complete list of input clocks. For H616, this means bus, hosc, and pll-32k. For R329, this means ahb, bus, and hosc; and optionally ext-osc32k. I'm not sure how to best represent this in the binding... Signed-off-by: Samuel Holland --- .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 55 +++++++++++++++++-- include/dt-bindings/clock/sun50i-rtc.h | 12 ++++ 2 files changed, 61 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/sun50i-rtc.h diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index beeb90e55727..3e085db1294f 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,8 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - const: allwinner,sun50i-h616-rtc + - const: allwinner,sun50i-r329-rtc reg: maxItems: 1 @@ -37,7 +39,24 @@ properties: - description: RTC Alarm 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + - anyOf: + - const: ahb + description: AHB parent for SPI bus clock + - const: bus + description: AHB/APB bus clock for register access + - const: ext-osc32k + description: External 32768 Hz oscillator input + - const: hosc + description: 24 MHz oscillator input + - const: pll-32k + description: 32 kHz clock divided from a PLL clock-output-names: minItems: 1 @@ -85,6 +104,9 @@ allOf: enum: - allwinner,sun8i-h3-rtc - allwinner,sun50i-h5-rtc + - allwinner,sun50i-h6-rtc + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc then: properties: @@ -96,13 +118,35 @@ allOf: properties: compatible: contains: - const: allwinner,sun50i-h6-rtc + enum: + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc then: + clocks: + minItems: 3 # bus, hosc, and (pll-32k [H616] or ahb [R329]) + + clock-names: + minItems: 3 + + required: + - clock-names + + else: + required: + - clock-output-names + + - if: + properties: clock-names + + then: + required: + - clocks # hosc is required + + else: properties: - clock-output-names: - minItems: 3 - maxItems: 3 + clocks: + maxItems: 1 # only ext-osc32k is allowed - if: properties: @@ -127,7 +171,6 @@ required: - compatible - reg - interrupts - - clock-output-names additionalProperties: false diff --git a/include/dt-bindings/clock/sun50i-rtc.h b/include/dt-bindings/clock/sun50i-rtc.h new file mode 100644 index 000000000000..d45e3ff4e105 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-rtc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#define CLK_RTC_SPI 8 + +#endif /* _DT_BINDINGS_CLK_SUN50I_RTC_CCU_H_ */ From patchwork Wed Sep 1 05:39:46 2021 Content-Type: text/plain; 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Wed, 1 Sep 2021 01:39:56 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 2/7] clk: sunxi-ng: div: Add macro using CLK_HW_INIT_FW_NAME Date: Wed, 1 Sep 2021 00:39:46 -0500 Message-Id: <20210901053951.60952-3-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To use the external clock references from the device tree, instead of hardcoded global names, parents should be referenced with .fw_name. Add a variant of the SUNXI_CCU_M_WITH_GATE initializer which does this. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu_div.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 6682fde6043c..4f8c78a4665b 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -166,6 +166,20 @@ struct ccu_div { SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ _mshift, _mwidth, 0, _flags) +#define SUNXI_CCU_M_FW_WITH_GATE(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, _flags) \ + struct ccu_div _struct = { \ + .enable = _gate, \ + .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_FW_NAME(_name, \ + _parent, \ + &ccu_div_ops, \ + _flags), \ + }, \ + } + static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Wed Sep 1 05:39:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 505262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA4AC432BE for ; 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Wed, 1 Sep 2021 01:39:58 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 4/7] clk: sunxi-ng: mux: Allow muxes to have keys Date: Wed, 1 Sep 2021 00:39:48 -0500 Message-Id: <20210901053951.60952-5-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The muxes in the RTC can only be updated when setting a key field to a specific value. Add a feature flag to denote muxes with this property. Since so far the key value is always the same, it does not need to be provided separately for each mux. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu_common.h | 1 + drivers/clk/sunxi-ng/ccu_mux.c | 7 +++++++ drivers/clk/sunxi-ng/ccu_mux.h | 14 ++++++++++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h index 98a1834b58bb..fbf16c6b896d 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -17,6 +17,7 @@ #define CCU_FEATURE_LOCK_REG BIT(5) #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) +#define CCU_FEATURE_KEY_FIELD BIT(8) /* MMC timing mode switch bit */ #define CCU_MMC_NEW_TIMING_MODE BIT(30) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 785803cd7e51..fb93cea3a502 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -12,6 +12,8 @@ #include "ccu_gate.h" #include "ccu_mux.h" +#define CCU_MUX_KEY_VALUE 0x16aa0000 + static u16 ccu_mux_get_prediv(struct ccu_common *common, struct ccu_mux_internal *cm, int parent_index) @@ -188,6 +190,11 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); + + /* The key field always reads as zero. */ + if (common->features & CCU_FEATURE_KEY_FIELD) + reg |= CCU_MUX_KEY_VALUE; + reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift); writel(reg | (index << cm->shift), common->base + common->reg); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index 5aa5a6f49bd8..6ca15e43f9c8 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -87,6 +87,20 @@ struct ccu_mux { } \ } +#define SUNXI_CCU_MUX_HW_WITH_KEY(_struct, _name, _parents, _reg, \ + _shift, _width, _flags) \ + struct ccu_mux _struct = { \ + .mux = _SUNXI_CCU_MUX(_shift, _width), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_KEY_FIELD, \ + .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \ + _parents, \ + &ccu_mux_ops, \ + _flags), \ + } \ + } + static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) { struct ccu_common *common = hw_to_ccu_common(hw); From patchwork Wed Sep 1 05:39:51 2021 Content-Type: text/plain; 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Wed, 1 Sep 2021 01:39:59 -0400 (EDT) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [RFC PATCH 7/7] [DO NOT MERGE] clk: sunxi-ng: Add support for T5 Date: Wed, 1 Sep 2021 00:39:51 -0500 Message-Id: <20210901053951.60952-8-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210901053951.60952-1-samuel@sholland.org> References: <20210901053951.60952-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The T5 RTC is similar to the H616 RTC (no rtc-32k mux, pll-32k as the second fanout input), except that it adds the ext-osc32k input. It also isn't a "sun50i" SoC, so it creates a bit of a naming problem... Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/sun50i-rtc-ccu.c | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c index 9603dc0d3d7b..fe6b21a24193 100644 --- a/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c +++ b/drivers/clk/sunxi-ng/sun50i-rtc-ccu.c @@ -227,6 +227,15 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "rtc-32k-fanout", static SUNXI_CCU_M_FW_WITH_GATE(rtc_spi_clk, "rtc-spi", "ahb", 0x310, 0, 5, BIT(31), 0); +static struct ccu_common *sun8i_t5_rtc_ccu_clks[] = { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &osc24M_32k_clk.common, + &osc32k_fanout_clk.common, +}; + static struct ccu_common *sun50i_h6_rtc_ccu_clks[] = { &iosc_clk, &iosc_32k_clk, @@ -256,6 +265,21 @@ static struct ccu_common *sun50i_r329_rtc_ccu_clks[] = { &rtc_spi_clk.common, }; +static struct clk_hw_onecell_data sun8i_t5_rtc_ccu_hw_clks = { + .num = CLK_NUMBER, + .hws = { + [CLK_OSC32K] = &osc32k_clk.common.hw, + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, + [CLK_IOSC] = &iosc_clk.hw, + + [CLK_IOSC_32K] = &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, + [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, + [CLK_RTC_32K] = &rtc_32k_fixed_clk.hw, + [CLK_RTC_SPI] = NULL, + }, +}; + static struct clk_hw_onecell_data sun50i_h6_rtc_ccu_hw_clks = { .num = CLK_NUMBER, .hws = { @@ -301,6 +325,13 @@ static struct clk_hw_onecell_data sun50i_r329_rtc_ccu_hw_clks = { }, }; +static const struct sunxi_ccu_desc sun8i_t5_rtc_ccu_desc = { + .ccu_clks = sun8i_t5_rtc_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_t5_rtc_ccu_clks), + + .hw_clks = &sun8i_t5_rtc_ccu_hw_clks, +}; + static const struct sunxi_ccu_desc sun50i_h6_rtc_ccu_desc = { .ccu_clks = sun50i_h6_rtc_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_rtc_ccu_clks), @@ -350,6 +381,15 @@ static void __init sunxi_rtc_ccu_init(struct device_node *node, of_sunxi_ccu_probe(node, reg, desc); } +static void __init sun8i_t5_rtc_ccu_setup(struct device_node *node) +{ + have_iosc_calib = 1; + + sunxi_rtc_ccu_init(node, &sun8i_t5_rtc_ccu_desc); +} +CLK_OF_DECLARE_DRIVER(sun8i_t5_rtc_ccu, "allwinner,sun8i-t5-rtc", + sun8i_t5_rtc_ccu_setup); + static void __init sun50i_h6_rtc_ccu_setup(struct device_node *node) { struct clk_init_data *init;