From patchwork Thu Oct 18 13:20:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149133 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972727lji; Thu, 18 Oct 2018 06:23:27 -0700 (PDT) X-Google-Smtp-Source: ACcGV61PLOFFLZJ956IpREbMSOhzWpXasxtRkFb2wS5kLcx0u+/9DtqeR9X1A8QJzkxPhb2tnPDo X-Received: by 2002:a81:5505:: with SMTP id j5-v6mr18615086ywb.186.1539869007203; Thu, 18 Oct 2018 06:23:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869007; cv=none; d=google.com; s=arc-20160816; b=x023YcuCTUl0XSUJT9i6aKSW6995ZEKEMUs+pqtbf1rheFPqC7frKyFN0QniGksKJm c2q/7DOvSVtlaWrymelwQBt71GRdfBuWgK1yNxhCJSZt7O/xZGuGLL2cNFrJK8/ZA2ZQ MYAabgw9GDdqzF4xXjS4aI92B7C51g+ZXxjdPL4FVsztiU3rZ8+n7Z+ETqcary6THiWb MehYp5JW76bMvNjvYLDYSuHWynF3FglI/CYjj3sNsfoWvJESH6WinJjxFjDsCmjPb7zT CfOZ8Om57TpIlW1FIBeqyNfSxA4gdLlpcBOop9hxEnAnF7iRJ/cHqnKhd2//PXyj8uWE mX2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=AVecml907P9D1LRLe9cU7gvsl/BMESRS6InQQRsscFM=; b=N2hk37beGxmHjNllPVSnTjmwrCelYfmDysGcjnkWzewdFxsmSyjEVPofAbpNclZLPQ jKSacBM0J7VbP5WNxT/EvKCrrb5WmRQUljzcQKDWIPfgDrJo9/ydZlyjyiCtyy/6SQZP f+LEI4KfRubKe4dj4vf+fqh+BwunSWTtc8fqw7Yd4HcXvpUzB7DkTAv8MoiUztp7XFlu Bjomva2Z6e86ni0yXPOEKEworYbfcKX1658I0qqT1TKNh2tWWV6KtJt9bxo11vHWB1lR FeZ7y9EdUkf5dYGB9U0EPJPjx1N4f3mYP8XJPtnTC1ymUL6H7AwgSoUIPHzs1RNBWJHf Tt8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s9-v6si7863283ybg.344.2018.10.18.06.23.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Er-0002zF-3j; Thu, 18 Oct 2018 13:21:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ep-0002yw-5V for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:19 +0000 X-Inumbo-ID: e5390d4e-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e5390d4e-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:43 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E08081596; Thu, 18 Oct 2018 06:21:17 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2423A3F59C; Thu, 18 Oct 2018 06:21:17 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:48 +0100 Message-Id: <20181018132109.31192-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 01/22] xen/arm: traps: Constify show_registers parameters X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" show_registers helpers are not meant to modify any parameters. So constify them. Signed-off-by: Julien Grall --- xen/arch/arm/traps.c | 14 +++++++------- xen/include/asm-arm/processor.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 51d2e42c77..9eec51ea90 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -787,8 +787,8 @@ static const char *mode_string(uint32_t cpsr) return mode_strings[mode] ? : "Unknown"; } -static void show_registers_32(struct cpu_user_regs *regs, - struct reg_ctxt *ctxt, +static void show_registers_32(const struct cpu_user_regs *regs, + const struct reg_ctxt *ctxt, int guest_mode, const struct vcpu *v) { @@ -864,8 +864,8 @@ static void show_registers_32(struct cpu_user_regs *regs, } #ifdef CONFIG_ARM_64 -static void show_registers_64(struct cpu_user_regs *regs, - struct reg_ctxt *ctxt, +static void show_registers_64(const struct cpu_user_regs *regs, + const struct reg_ctxt *ctxt, int guest_mode, const struct vcpu *v) { @@ -925,8 +925,8 @@ static void show_registers_64(struct cpu_user_regs *regs, } #endif -static void _show_registers(struct cpu_user_regs *regs, - struct reg_ctxt *ctxt, +static void _show_registers(const struct cpu_user_regs *regs, + const struct reg_ctxt *ctxt, int guest_mode, const struct vcpu *v) { @@ -981,7 +981,7 @@ static void _show_registers(struct cpu_user_regs *regs, printk("\n"); } -void show_registers(struct cpu_user_regs *regs) +void show_registers(const struct cpu_user_regs *regs) { struct reg_ctxt ctxt; ctxt.sctlr_el1 = READ_SYSREG(SCTLR_EL1); diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 8016cf306f..efa33b4665 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -794,7 +794,7 @@ void init_traps(void); void panic_PAR(uint64_t par); void show_execution_state(struct cpu_user_regs *regs); -void show_registers(struct cpu_user_regs *regs); +void show_registers(const struct cpu_user_regs *regs); //#define dump_execution_state() run_in_exception_handler(show_execution_state) #define dump_execution_state() WARN() From patchwork Thu Oct 18 13:20:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149136 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972794lji; Thu, 18 Oct 2018 06:23:31 -0700 (PDT) X-Google-Smtp-Source: ACcGV607VC5EuUWnkPFFUvWDKJnpaehFY6keWmgdqciztCvx7JDVcoDo45xpz9/Dxzr0SIePjyQg X-Received: by 2002:a81:52ca:: with SMTP id g193-v6mr12039783ywb.41.1539869011015; Thu, 18 Oct 2018 06:23:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869011; cv=none; d=google.com; s=arc-20160816; b=VqXxmb+xPYmVXz1DqoWlWkjc4Wz/bLdMFI9TcEfte4p+99bXn/yUek2pKFSvvEW4+x XF9TSpnxTI/qTk73r/spcCFQIQKnc2jh4KnVxkdEz31AR7LS1wkRKbKjNOXyjJtIl1Pf SvqXrfpia2Mrb3EiooAyHrIUIVcTzduHlGajcWLtvU/heZprEnC3E1qnFIXBCh3LDGXb hsaKja/M/M+3tsEi6XT21JEFVU0kfFh/SSKa6g6KD64kk6AFIYhthwj9fkCtCGsYFBiQ ck67CdosepPSq5gAYffSwazTeb1voLTga/+reZsYgQuDxu+IdYL55fdEPwyGApV80ITy /kFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=GmpCrz1NRqqaOKZ2LP/ufmdxxJf9BqUBncNHVyHFNBM=; b=MSDEryVtCO3+Ox0qao2EPWyI0W6nEAKf3DSGYNvKQwfbbsOAxr5z2R5nlYCvoRVYZr 7OGVdXSmlS4aXTMVQnzjZ2r+GVQpzAWG31zrAFsd4tSICWr6Ul0bQ87JB8DMeE8yjnqv rC/2UN7oLSW5kbkBanBWQuaUo3fKaMIdy7g42XBoPcmse39oZ8VfZBeoSvHv6ctu8tnD VuJg0CtQ+8JlpyrL/4E0OQiX9K82IpBaHrxpN9QDUlR6NT4jcsfBkuiRd0mbJvpTpKOD TZz6o8lSzMpID/zStU4YHoyL7kdIlOL9cw2+O/o5eUA+xYbIza3Kh0WlLIJv4slt0ZO2 v04w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f127-v6si8130109ywh.326.2018.10.18.06.23.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Er-0002zL-DV; Thu, 18 Oct 2018 13:21:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Eq-0002z4-CC for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:20 +0000 X-Inumbo-ID: e5b88ebb-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e5b88ebb-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:44 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E551B15BE; Thu, 18 Oct 2018 06:21:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2963B3F59C; Thu, 18 Oct 2018 06:21:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:49 +0100 Message-Id: <20181018132109.31192-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 02/22] xen/arm: regs: Convert guest_mode to a static inline helper X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the same time, switch the parameter guest_mode from int to bool Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/traps.c | 6 +++--- xen/include/asm-arm/regs.h | 22 ++++++++++++---------- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9eec51ea90..1b0b27434f 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -789,7 +789,7 @@ static const char *mode_string(uint32_t cpsr) static void show_registers_32(const struct cpu_user_regs *regs, const struct reg_ctxt *ctxt, - int guest_mode, + bool guest_mode, const struct vcpu *v) { @@ -866,7 +866,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, #ifdef CONFIG_ARM_64 static void show_registers_64(const struct cpu_user_regs *regs, const struct reg_ctxt *ctxt, - int guest_mode, + bool guest_mode, const struct vcpu *v) { @@ -927,7 +927,7 @@ static void show_registers_64(const struct cpu_user_regs *regs, static void _show_registers(const struct cpu_user_regs *regs, const struct reg_ctxt *ctxt, - int guest_mode, + bool guest_mode, const struct vcpu *v) { print_xen_info(); diff --git a/xen/include/asm-arm/regs.h b/xen/include/asm-arm/regs.h index 2440edb29a..ddc6eba9ce 100644 --- a/xen/include/asm-arm/regs.h +++ b/xen/include/asm-arm/regs.h @@ -5,8 +5,10 @@ #ifndef __ASSEMBLY__ +#include #include #include +#include #include #define psr_mode(psr,m) (((psr) & PSR_MODE_MASK) == m) @@ -37,16 +39,16 @@ (psr_mode((r)->cpsr,PSR_MODE_EL0t) || usr_mode(r)) #endif -#define guest_mode(r) \ -({ \ - unsigned long diff = (char *)guest_cpu_user_regs() - (char *)(r); \ - /* Frame pointer must point into current CPU stack. */ \ - ASSERT(diff < STACK_SIZE); \ - /* If not a guest frame, it must be a hypervisor frame. */ \ - ASSERT((diff == 0) || hyp_mode(r)); \ - /* Return TRUE if it's a guest frame. */ \ - (diff == 0); \ -}) +static inline bool guest_mode(const struct cpu_user_regs *r) +{ + unsigned long diff = (char *)guest_cpu_user_regs() - (char *)(r); + /* Frame pointer must point into current CPU stack. */ + ASSERT(diff < STACK_SIZE); + /* If not a guest frame, it must be a hypervisor frame. */ + ASSERT((diff == 0) || hyp_mode(r)); + /* Return TRUE if it's a guest frame. */ + return (diff == 0); +} #define return_reg(v) ((v)->arch.cpu_info->guest_cpu_user_regs.r0) From patchwork Thu Oct 18 13:20:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149137 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972796lji; Thu, 18 Oct 2018 06:23:31 -0700 (PDT) X-Google-Smtp-Source: ACcGV63+sRIrWXJBb24N/2WsKl6ksCI9ZNbm+ZMXz3WXUkKVs012AOSmxaIgPf8UffFQZO+S76WY X-Received: by 2002:a25:ed10:: with SMTP id k16-v6mr5842376ybh.501.1539869011140; Thu, 18 Oct 2018 06:23:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869011; cv=none; d=google.com; s=arc-20160816; b=kw/KX3ywY95+ItYI/WWtn96Z+3MjTWVLHM2CA3w8MzrjL3VPRt6daqELrbGa2cW1cL M4WbfG29gRhal1TOIDO1/4iNrRW8L4dTmtDIfG+47hOr0Id17dUl4Cb1sRNvmJSjWXSm pdHNiQNqlx3zR657d3oMIYdTqNOFzPT5gSUX5aC6/9kZ0LK+/1f8yyDfe0rTGoL9ILPb fLke5T/jnSgC43hy+dt0DGQ1PBhtQKh13wNPjamXlbzVyMX3SewSTUf5xK77JtJBNzci Fn+qCO+rDG6qoqxK6ZAYV7/IF9dhCnzPnr+jobdfET1iubCP1Lt6Bg+PiAy2wS1oLe47 urIA== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id i8-v6si7548473ybk.356.2018.10.18.06.23.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Es-0002zb-Nr; Thu, 18 Oct 2018 13:21:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Er-0002zO-Ix for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:21 +0000 X-Inumbo-ID: e6651b72-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e6651b72-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:45 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1985D341; Thu, 18 Oct 2018 06:21:20 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2E84C3F59C; Thu, 18 Oct 2018 06:21:19 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:50 +0100 Message-Id: <20181018132109.31192-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 03/22] xen/arm: Remove __init from prototype X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In Xen, it is common to add __init to the declaration and not the prototype. Remove the few __init on some prototypes which allows to avoid the inclusion of init.h in headers. With these changes, init.h is now required to be included on some c files. Also, add __init where it was missing in declaration. Signed-off-by: Julien Grall --- xen/arch/arm/acpi/lib.c | 1 + xen/arch/arm/bootfdt.c | 2 +- xen/arch/arm/cpuerrata.c | 1 + xen/arch/arm/device.c | 1 + xen/arch/arm/psci.c | 1 + xen/include/asm-arm/acpi.h | 7 +++---- xen/include/asm-arm/alternative.h | 3 +-- xen/include/asm-arm/device.h | 10 ++++------ xen/include/asm-arm/platform.h | 7 +++---- xen/include/asm-arm/setup.h | 6 +++--- xen/include/xen/device_tree.h | 5 ++--- 11 files changed, 21 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/acpi/lib.c b/xen/arch/arm/acpi/lib.c index ada5298a38..4fc6e17322 100644 --- a/xen/arch/arm/acpi/lib.c +++ b/xen/arch/arm/acpi/lib.c @@ -22,6 +22,7 @@ */ #include +#include #include char *__acpi_map_table(paddr_t phys, unsigned long size) diff --git a/xen/arch/arm/bootfdt.c b/xen/arch/arm/bootfdt.c index 8eba42c7b9..44af11c0fd 100644 --- a/xen/arch/arm/bootfdt.c +++ b/xen/arch/arm/bootfdt.c @@ -349,7 +349,7 @@ size_t __init boot_fdt_info(const void *fdt, paddr_t paddr) return fdt_totalsize(fdt); } -const char *boot_fdt_cmdline(const void *fdt) +const __init char *boot_fdt_cmdline(const void *fdt) { int node; const struct fdt_property *prop; diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 97a118293b..adf88e7bdc 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -1,5 +1,6 @@ #include #include +#include #include #include #include diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c index a0072c1563..70cd6c1a19 100644 --- a/xen/arch/arm/device.c +++ b/xen/arch/arm/device.c @@ -19,6 +19,7 @@ #include #include +#include #include extern const struct device_desc _sdevice[], _edevice[]; diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index a93121f43b..d23cb8e76e 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -19,6 +19,7 @@ #include +#include #include #include #include diff --git a/xen/include/asm-arm/acpi.h b/xen/include/asm-arm/acpi.h index c183b6bb6e..feec4fb0ac 100644 --- a/xen/include/asm-arm/acpi.h +++ b/xen/include/asm-arm/acpi.h @@ -23,7 +23,6 @@ #ifndef _ASM_ARM_ACPI_H #define _ASM_ARM_ACPI_H -#include #include #include @@ -43,9 +42,9 @@ typedef enum { TBL_MMAX, } EFI_MEM_RES; -bool __init acpi_psci_present(void); -bool __init acpi_psci_hvc_present(void); -void __init acpi_smp_init_cpus(void); +bool acpi_psci_present(void); +bool acpi_psci_hvc_present(void); +void acpi_smp_init_cpus(void); /* * This function returns the offset of a given ACPI/EFI table in the allocated diff --git a/xen/include/asm-arm/alternative.h b/xen/include/asm-arm/alternative.h index 9b4b02811b..dedb6dd001 100644 --- a/xen/include/asm-arm/alternative.h +++ b/xen/include/asm-arm/alternative.h @@ -7,7 +7,6 @@ #ifndef __ASSEMBLY__ -#include #include #include @@ -28,7 +27,7 @@ typedef void (*alternative_cb_t)(const struct alt_instr *alt, const uint32_t *origptr, uint32_t *updptr, int nr_inst); -void __init apply_alternatives_all(void); +void apply_alternatives_all(void); int apply_alternatives(const struct alt_instr *start, const struct alt_instr *end); #define ALTINSTR_ENTRY(feature, cb) \ diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h index 6734ae8efd..63a0f3631d 100644 --- a/xen/include/asm-arm/device.h +++ b/xen/include/asm-arm/device.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_DEVICE_H #define __ASM_ARM_DEVICE_H -#include - enum device_type { DEV_DT, @@ -68,8 +66,8 @@ struct acpi_device_desc { * * Return 0 on success. */ -int __init acpi_device_init(enum device_class class, - const void *data, int class_type); +int acpi_device_init(enum device_class class, + const void *data, int class_type); /** * device_init - Initialize a device @@ -79,8 +77,8 @@ int __init acpi_device_init(enum device_class class, * * Return 0 on success. */ -int __init device_init(struct dt_device_node *dev, enum device_class class, - const void *data); +int device_init(struct dt_device_node *dev, enum device_class class, + const void *data); /** * device_get_type - Get the type of the device diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h index 2591d7bb03..bf9258156c 100644 --- a/xen/include/asm-arm/platform.h +++ b/xen/include/asm-arm/platform.h @@ -1,7 +1,6 @@ #ifndef __ASM_ARM_PLATFORM_H #define __ASM_ARM_PLATFORM_H -#include #include #include #include @@ -46,9 +45,9 @@ struct platform_desc { */ #define PLATFORM_QUIRK_GIC_64K_STRIDE (1 << 0) -void __init platform_init(void); -int __init platform_init_time(void); -int __init platform_specific_mapping(struct domain *d); +void platform_init(void); +int platform_init_time(void); +int platform_specific_mapping(struct domain *d); #ifdef CONFIG_ARM_32 int platform_smp_init(void); int platform_cpu_up(int cpu); diff --git a/xen/include/asm-arm/setup.h b/xen/include/asm-arm/setup.h index 0cc3330807..5f41ba0cba 100644 --- a/xen/include/asm-arm/setup.h +++ b/xen/include/asm-arm/setup.h @@ -74,14 +74,14 @@ void discard_initial_modules(void); void dt_unreserved_regions(paddr_t s, paddr_t e, void (*cb)(paddr_t, paddr_t), int first); -size_t __init boot_fdt_info(const void *fdt, paddr_t paddr); -const char __init *boot_fdt_cmdline(const void *fdt); +size_t boot_fdt_info(const void *fdt, paddr_t paddr); +const char *boot_fdt_cmdline(const void *fdt); struct bootmodule *add_boot_module(bootmodule_kind kind, paddr_t start, paddr_t size, const char *cmdline); struct bootmodule *boot_module_find_by_kind(bootmodule_kind kind); -const char * __init boot_module_kind_as_string(bootmodule_kind kind); +const char *boot_module_kind_as_string(bootmodule_kind kind); #endif /* diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 91fa0b6f61..7408a6c48c 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -169,7 +168,7 @@ int device_tree_for_each_node(const void *fdt, * Create a hierarchical device tree for the host DTB to be able * to retrieve parents. */ -void __init dt_unflatten_host_device_tree(void); +void dt_unflatten_host_device_tree(void); /** * IRQ translation callback @@ -204,7 +203,7 @@ extern const struct dt_device_node *dt_interrupt_controller; * * If found, return the interrupt controller device node. */ -struct dt_device_node * __init +struct dt_device_node * dt_find_interrupt_controller(const struct dt_device_match *matches); #define dt_prop_cmp(s1, s2) strcmp((s1), (s2)) From patchwork Thu Oct 18 13:20:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149134 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972765lji; 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[192.237.175.120]) by mx.google.com with ESMTPS id v11-v6si8077613ywe.217.2018.10.18.06.23.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Eu-0002zv-5c; Thu, 18 Oct 2018 13:21:24 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Es-0002za-QE for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:22 +0000 X-Inumbo-ID: e70561a2-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e70561a2-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:46 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E9721596; Thu, 18 Oct 2018 06:21:21 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 56BA93F59C; Thu, 18 Oct 2018 06:21:20 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:51 +0100 Message-Id: <20181018132109.31192-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 04/22] xen/arm: bugs: Move do_bug_frame to traps.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" do_bug_frame is only necessary when trapping. This allows to remove processor.h include. However, time.h was missing an include resulting to compilation error if processor.h is removed from bug.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/arm32/traps.c | 1 + xen/include/asm-arm/bug.h | 4 ---- xen/include/asm-arm/time.h | 2 ++ xen/include/asm-arm/traps.h | 2 ++ 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm32/traps.c b/xen/arch/arm/arm32/traps.c index 4f27543dec..76f714a168 100644 --- a/xen/arch/arm/arm32/traps.c +++ b/xen/arch/arm/arm32/traps.c @@ -22,6 +22,7 @@ #include #include +#include void do_trap_reset(struct cpu_user_regs *regs) { diff --git a/xen/include/asm-arm/bug.h b/xen/include/asm-arm/bug.h index 4704e2d858..36c803357c 100644 --- a/xen/include/asm-arm/bug.h +++ b/xen/include/asm-arm/bug.h @@ -1,8 +1,6 @@ #ifndef __ARM_BUG_H__ #define __ARM_BUG_H__ -#include - #if defined(CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) @@ -77,8 +75,6 @@ extern const struct bug_frame __start_bug_frames[], __stop_bug_frames_1[], __stop_bug_frames_2[]; -int do_bug_frame(struct cpu_user_regs *regs, vaddr_t pc); - #endif /* __ARM_BUG_H__ */ /* * Local variables: diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index 19a4515e72..ea88e76304 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -1,6 +1,8 @@ #ifndef __ARM_TIME_H__ #define __ARM_TIME_H__ +#include + #define DT_MATCH_TIMER \ DT_MATCH_COMPATIBLE("arm,armv7-timer"), \ DT_MATCH_COMPATIBLE("arm,armv8-timer") diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 70b52d1d16..059aa370c3 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -43,6 +43,8 @@ void do_cp(struct cpu_user_regs *regs, const union hsr hsr); void do_trap_smc(struct cpu_user_regs *regs, const union hsr hsr); void do_trap_hvc_smccc(struct cpu_user_regs *regs); +int do_bug_frame(struct cpu_user_regs *regs, vaddr_t pc); + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: From patchwork Thu Oct 18 13:20:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149142 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972885lji; Thu, 18 Oct 2018 06:23:37 -0700 (PDT) X-Google-Smtp-Source: ACcGV613JkyWMmCz1D2C5/oA2U+qYuMIr2atBClz3ESfH3MVIIsszFU0sWxv0lLa+VpMT/KmjzyH X-Received: by 2002:a25:f805:: with SMTP id u5-v6mr17946365ybd.193.1539869016892; Thu, 18 Oct 2018 06:23:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869016; cv=none; d=google.com; s=arc-20160816; b=d9TWc/vq3x+9HbouCq3DXQN6I7KPHUdz7k1bUzTjGGqgmgyGcwGB+4DVcrGZ00Eb6C 0RkN7S7Nx1kOULtrF1rCnW+fZW829Kat66M4bYiRCfP64/Co+nO2ATbksDVTsFZnMfT7 tUHbCSlT/ELNlVjEUAiTvLtuIt5rZQiVS+vBzK/HN2Jl6GIjUZ0dewZO6K1LV3y/VbY+ wyGCiiPguFmHFT1q4fKUioVG5sJ+xHe3u0Dv5Nj17OkAjFKqIRZxlirA4UCwwxOIMiRs t8SG2P85TBiNUW3NqYZRrWQlyJ5SdzarYmzI1lg5cr+gjXqBCwMdAUA+RJgqEHkNJhMW zcpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=J7GecMl6EpjxsRsEmYWm/rdS2JExqENfd7HV38z+UGQ=; b=gJRcj+EK68bdz/WkjqZjdzO5cWz/vnE3p/5+F0RYA+EWvgICC652rLeFLsnNQF3f45 xWalUI9exUVisdmA0GUngmfVDW0t9q0or0tfG+SvntoB1E6Nhk9B8CrhQTSAUMyE6COb JJG0/IZ4XfDcWjpN4QtGerlns19OoqQjn9dog5W5685P+tqzfzBgk80oenwlG2K1+1tY z1Af9m9JdcJayBvOfaS5Bx9IZdyU43G1wS6GFeEMOP2wAffi3xE9kMtZZNL/hOhudRHr /9yuMXfjNuGTTj+Od1y1LV6TkMXr/alOicVHSaBxO8R/3jHGnetLezwsDInvtFafqVKU wCEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s11-v6si8299994ywb.297.2018.10.18.06.23.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ex-000315-8A; Thu, 18 Oct 2018 13:21:27 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ev-000309-8K for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:25 +0000 X-Inumbo-ID: 517c1e6c-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 517c1e6c-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:36 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 483F6341; Thu, 18 Oct 2018 06:21:22 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5BF4B3F59C; Thu, 18 Oct 2018 06:21:21 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:52 +0100 Message-Id: <20181018132109.31192-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 05/22] xen/arm: Consolidate CPU identification in cpufeature.{c, h} X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, CPU Identification is spread accross cpu.c, cpufeature.c, processor.h, cpufeature.h. It would be better to keep everything together in a single place. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/Makefile | 1 - xen/arch/arm/cpu.c | 68 -------------------- xen/arch/arm/cpufeature.c | 42 ++++++++++++ xen/arch/arm/vcpreg.c | 1 + xen/include/asm-arm/cpufeature.h | 134 ++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/processor.h | 135 --------------------------------------- 6 files changed, 177 insertions(+), 204 deletions(-) delete mode 100644 xen/arch/arm/cpu.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 37fa8268b3..6d91ba7c46 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -6,7 +6,6 @@ subdir-$(CONFIG_ACPI) += acpi obj-$(CONFIG_HAS_ALTERNATIVE) += alternative.o obj-y += bootfdt.init.o -obj-y += cpu.o obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o diff --git a/xen/arch/arm/cpu.c b/xen/arch/arm/cpu.c deleted file mode 100644 index 9595f1d63a..0000000000 --- a/xen/arch/arm/cpu.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include - -void identify_cpu(struct cpuinfo_arm *c) -{ - c->midr.bits = READ_SYSREG32(MIDR_EL1); - c->mpidr.bits = READ_SYSREG(MPIDR_EL1); - -#ifdef CONFIG_ARM_64 - c->pfr64.bits[0] = READ_SYSREG64(ID_AA64PFR0_EL1); - c->pfr64.bits[1] = READ_SYSREG64(ID_AA64PFR1_EL1); - - c->dbg64.bits[0] = READ_SYSREG64(ID_AA64DFR0_EL1); - c->dbg64.bits[1] = READ_SYSREG64(ID_AA64DFR1_EL1); - - c->aux64.bits[0] = READ_SYSREG64(ID_AA64AFR0_EL1); - c->aux64.bits[1] = READ_SYSREG64(ID_AA64AFR1_EL1); - - c->mm64.bits[0] = READ_SYSREG64(ID_AA64MMFR0_EL1); - c->mm64.bits[1] = READ_SYSREG64(ID_AA64MMFR1_EL1); - - c->isa64.bits[0] = READ_SYSREG64(ID_AA64ISAR0_EL1); - c->isa64.bits[1] = READ_SYSREG64(ID_AA64ISAR1_EL1); -#endif - - c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); - c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); - - c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); - - c->aux32.bits[0] = READ_SYSREG32(ID_AFR0_EL1); - - c->mm32.bits[0] = READ_SYSREG32(ID_MMFR0_EL1); - c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); - c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); - c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); - - c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); - c->isa32.bits[1] = READ_SYSREG32(ID_ISAR1_EL1); - c->isa32.bits[2] = READ_SYSREG32(ID_ISAR2_EL1); - c->isa32.bits[3] = READ_SYSREG32(ID_ISAR3_EL1); - c->isa32.bits[4] = READ_SYSREG32(ID_ISAR4_EL1); - c->isa32.bits[5] = READ_SYSREG32(ID_ISAR5_EL1); -} - -/* - * Local variables: - * mode: C - * c-file-style: "BSD" - * c-basic-offset: 4 - * indent-tabs-mode: nil - * End: - */ diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 3aaff4c0e6..44126dbf07 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -97,6 +97,48 @@ int enable_nonboot_cpu_caps(const struct arm_cpu_capabilities *caps) return rc; } +void identify_cpu(struct cpuinfo_arm *c) +{ + c->midr.bits = READ_SYSREG32(MIDR_EL1); + c->mpidr.bits = READ_SYSREG(MPIDR_EL1); + +#ifdef CONFIG_ARM_64 + c->pfr64.bits[0] = READ_SYSREG64(ID_AA64PFR0_EL1); + c->pfr64.bits[1] = READ_SYSREG64(ID_AA64PFR1_EL1); + + c->dbg64.bits[0] = READ_SYSREG64(ID_AA64DFR0_EL1); + c->dbg64.bits[1] = READ_SYSREG64(ID_AA64DFR1_EL1); + + c->aux64.bits[0] = READ_SYSREG64(ID_AA64AFR0_EL1); + c->aux64.bits[1] = READ_SYSREG64(ID_AA64AFR1_EL1); + + c->mm64.bits[0] = READ_SYSREG64(ID_AA64MMFR0_EL1); + c->mm64.bits[1] = READ_SYSREG64(ID_AA64MMFR1_EL1); + + c->isa64.bits[0] = READ_SYSREG64(ID_AA64ISAR0_EL1); + c->isa64.bits[1] = READ_SYSREG64(ID_AA64ISAR1_EL1); +#endif + + c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); + c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); + + c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); + + c->aux32.bits[0] = READ_SYSREG32(ID_AFR0_EL1); + + c->mm32.bits[0] = READ_SYSREG32(ID_MMFR0_EL1); + c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); + c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); + c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); + + c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); + c->isa32.bits[1] = READ_SYSREG32(ID_ISAR1_EL1); + c->isa32.bits[2] = READ_SYSREG32(ID_ISAR2_EL1); + c->isa32.bits[3] = READ_SYSREG32(ID_ISAR3_EL1); + c->isa32.bits[4] = READ_SYSREG32(ID_ISAR4_EL1); + c->isa32.bits[5] = READ_SYSREG32(ID_ISAR5_EL1); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index b04d996fd3..7b783e4bcc 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -18,6 +18,7 @@ #include +#include #include #include #include diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 2d82264427..17de928467 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -104,6 +104,140 @@ void update_cpu_capabilities(const struct arm_cpu_capabilities *caps, void enable_cpu_capabilities(const struct arm_cpu_capabilities *caps); int enable_nonboot_cpu_caps(const struct arm_cpu_capabilities *caps); +/* + * capabilities of CPUs + */ +struct cpuinfo_arm { + union { + uint32_t bits; + struct { + unsigned long revision:4; + unsigned long part_number:12; + unsigned long architecture:4; + unsigned long variant:4; + unsigned long implementer:8; + }; + } midr; + union { + register_t bits; + struct { + unsigned long aff0:8; + unsigned long aff1:8; + unsigned long aff2:8; + unsigned long mt:1; /* Multi-thread, iff MP == 1 */ + unsigned long __res0:5; + unsigned long up:1; /* UP system, iff MP == 1 */ + unsigned long mp:1; /* MP extensions */ + +#ifdef CONFIG_ARM_64 + unsigned long aff3:8; + unsigned long __res1:24; +#endif + }; + } mpidr; + +#ifdef CONFIG_ARM_64 + /* 64-bit CPUID registers. */ + union { + uint64_t bits[2]; + struct { + unsigned long el0:4; + unsigned long el1:4; + unsigned long el2:4; + unsigned long el3:4; + unsigned long fp:4; /* Floating Point */ + unsigned long simd:4; /* Advanced SIMD */ + unsigned long gic:4; /* GIC support */ + unsigned long __res0:28; + unsigned long csv2:4; + unsigned long __res1:4; + }; + } pfr64; + + struct { + uint64_t bits[2]; + } dbg64; + + struct { + uint64_t bits[2]; + } aux64; + + union { + uint64_t bits[2]; + struct { + unsigned long pa_range:4; + unsigned long asid_bits:4; + unsigned long bigend:4; + unsigned long secure_ns:4; + unsigned long bigend_el0:4; + unsigned long tgranule_16K:4; + unsigned long tgranule_64K:4; + unsigned long tgranule_4K:4; + unsigned long __res0:32; + + unsigned long hafdbs:4; + unsigned long vmid_bits:4; + unsigned long vh:4; + unsigned long hpds:4; + unsigned long lo:4; + unsigned long pan:4; + unsigned long __res1:8; + unsigned long __res2:32; + }; + } mm64; + + struct { + uint64_t bits[2]; + } isa64; + +#endif + + /* + * 32-bit CPUID registers. On ARMv8 these describe the properties + * when running in 32-bit mode. + */ + union { + uint32_t bits[2]; + struct { + unsigned long arm:4; + unsigned long thumb:4; + unsigned long jazelle:4; + unsigned long thumbee:4; + unsigned long __res0:16; + + unsigned long progmodel:4; + unsigned long security:4; + unsigned long mprofile:4; + unsigned long virt:4; + unsigned long gentimer:4; + unsigned long __res1:12; + }; + } pfr32; + + struct { + uint32_t bits[1]; + } dbg32; + + struct { + uint32_t bits[1]; + } aux32; + + struct { + uint32_t bits[4]; + } mm32; + + struct { + uint32_t bits[6]; + } isa32; +}; + +extern struct cpuinfo_arm boot_cpu_data; + +extern void identify_cpu(struct cpuinfo_arm *); + +extern struct cpuinfo_arm cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] + #endif /* __ASSEMBLY__ */ #endif diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index efa33b4665..f7a2e9a3ad 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -350,141 +350,6 @@ #ifndef __ASSEMBLY__ -struct cpuinfo_arm { - union { - uint32_t bits; - struct { - unsigned long revision:4; - unsigned long part_number:12; - unsigned long architecture:4; - unsigned long variant:4; - unsigned long implementer:8; - }; - } midr; - union { - register_t bits; - struct { - unsigned long aff0:8; - unsigned long aff1:8; - unsigned long aff2:8; - unsigned long mt:1; /* Multi-thread, iff MP == 1 */ - unsigned long __res0:5; - unsigned long up:1; /* UP system, iff MP == 1 */ - unsigned long mp:1; /* MP extensions */ - -#ifdef CONFIG_ARM_64 - unsigned long aff3:8; - unsigned long __res1:24; -#endif - }; - } mpidr; - -#ifdef CONFIG_ARM_64 - /* 64-bit CPUID registers. */ - union { - uint64_t bits[2]; - struct { - unsigned long el0:4; - unsigned long el1:4; - unsigned long el2:4; - unsigned long el3:4; - unsigned long fp:4; /* Floating Point */ - unsigned long simd:4; /* Advanced SIMD */ - unsigned long gic:4; /* GIC support */ - unsigned long __res0:28; - unsigned long csv2:4; - unsigned long __res1:4; - }; - } pfr64; - - struct { - uint64_t bits[2]; - } dbg64; - - struct { - uint64_t bits[2]; - } aux64; - - union { - uint64_t bits[2]; - struct { - unsigned long pa_range:4; - unsigned long asid_bits:4; - unsigned long bigend:4; - unsigned long secure_ns:4; - unsigned long bigend_el0:4; - unsigned long tgranule_16K:4; - unsigned long tgranule_64K:4; - unsigned long tgranule_4K:4; - unsigned long __res0:32; - - unsigned long hafdbs:4; - unsigned long vmid_bits:4; - unsigned long vh:4; - unsigned long hpds:4; - unsigned long lo:4; - unsigned long pan:4; - unsigned long __res1:8; - unsigned long __res2:32; - }; - } mm64; - - struct { - uint64_t bits[2]; - } isa64; - -#endif - - /* - * 32-bit CPUID registers. On ARMv8 these describe the properties - * when running in 32-bit mode. - */ - union { - uint32_t bits[2]; - struct { - unsigned long arm:4; - unsigned long thumb:4; - unsigned long jazelle:4; - unsigned long thumbee:4; - unsigned long __res0:16; - - unsigned long progmodel:4; - unsigned long security:4; - unsigned long mprofile:4; - unsigned long virt:4; - unsigned long gentimer:4; - unsigned long __res1:12; - }; - } pfr32; - - struct { - uint32_t bits[1]; - } dbg32; - - struct { - uint32_t bits[1]; - } aux32; - - struct { - uint32_t bits[4]; - } mm32; - - struct { - uint32_t bits[6]; - } isa32; -}; - -/* - * capabilities of CPUs - */ - -extern struct cpuinfo_arm boot_cpu_data; - -extern void identify_cpu(struct cpuinfo_arm *); - -extern struct cpuinfo_arm cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] - extern register_t __cpu_logical_map[]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] From patchwork Thu Oct 18 13:20:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149141 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972864lji; Thu, 18 Oct 2018 06:23:35 -0700 (PDT) X-Google-Smtp-Source: ACcGV61er61dtqJ8OgqaElgiSBx8pwd0ij00KQ9KhBWNv+x/2FGyuuVMf5HZnjXZ/kv+gFR/3z1M X-Received: by 2002:a5b:f43:: with SMTP id y3-v6mr18065128ybr.296.1539869015535; Thu, 18 Oct 2018 06:23:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869015; cv=none; d=google.com; s=arc-20160816; b=QaGe8JSwSstEpmUw69HqWW7uyzxFtabZf9py39KoDBkf1tM+WuWCst3qtzdajzB9We Iz16ZsirmUBfMltegS2jwK0Y+HHpVUNSNXWYyQMaL1XTPBg70d9CF3c6vpXQ8/Z4zf0Y haV8GGD2XWcFHKc660h6sjH/C8nzWIwarK5XXzkZLfH8hfJIUnv81AZvag1PD4MT0qfZ DMjl8m65+H07RWR7FKb9JJVl/tQWspYuohrMN0FCY0MdxV/jFgbNghiDC78gKix/ioIy aiH0bqf68sQYmjy4S9VVqnhx2G8iCIIhtpbDyT7XX0UsU5mJg9SAv/XHwfOVYklFdxsE 6U/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=4UsijaZbarhr18Naq7ZGusmT+8Ou4/RphY/NeO6bZKo=; b=vuqBHGcz/1pSYz3s7xRdTVdbCMpmFm1H5r/cI+unLME8KAvSnqcQcYI5AqK4EHxo+A BDarnbEWFHqxSLy9yzdKlquqjYRQqZgmdt5Q1p0p4TadBUEXu0bjaCISMYz907THsE1K yzZGwSbcm0/ivGIaUAge8QYPoFa9kxit7v+aquxQ2QPBaV/Q8pNfF5cbT1GMkzYxMfVz O5v6v/WQP+bYVZ+kg+vemN7eawx8ElLkvLAfufy3dFD0CkFHN5SeE1pnJUJM8KzSq6e0 E0X1ZqEiYfTO3ik8y7XHVWBgaH1KVTdw29EZJzsniEBfd66HlguMUXSsO7m284jXB4G8 jOeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s63-v6si1797673ybb.355.2018.10.18.06.23.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ev-00030h-Rk; Thu, 18 Oct 2018 13:21:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ev-000308-1W for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:25 +0000 X-Inumbo-ID: e85dd7a8-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e85dd7a8-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D73515BE; Thu, 18 Oct 2018 06:21:23 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8587D3F59C; Thu, 18 Oct 2018 06:21:22 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:53 +0100 Message-Id: <20181018132109.31192-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 06/22] xen/arm: Move VABORT_GEN_BY_GUEST to traps.h and turned into inline X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The macro VABORT_GEN_BY_GUEST is only used by the trap code. So move it to trap.h. While moving the code, convert is to a static inline to allow typecheck. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/processor.h | 10 ---------- xen/include/asm-arm/traps.h | 10 ++++++++++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index f7a2e9a3ad..5b6bd0c38c 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -683,16 +683,6 @@ void do_trap_guest_serror(struct cpu_user_regs *regs); register_t get_default_hcr_flags(void); -/* Functions for pending virtual abort checking window. */ -void abort_guest_exit_start(void); -void abort_guest_exit_end(void); - -#define VABORT_GEN_BY_GUEST(r) \ -( \ - ( (unsigned long)abort_guest_exit_start == (r)->pc ) || \ - ( (unsigned long)abort_guest_exit_end == (r)->pc ) \ -) - /* * Synchronize SError unless the feature is selected. * This is relying on the SErrors are currently unmasked. diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 059aa370c3..c12e9e4082 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -45,6 +45,16 @@ void do_trap_hvc_smccc(struct cpu_user_regs *regs); int do_bug_frame(struct cpu_user_regs *regs, vaddr_t pc); +/* Functions for pending virtual abort checking window. */ +void abort_guest_exit_start(void); +void abort_guest_exit_end(void); + +static inline bool VABORT_GEN_BY_GUEST(const struct cpu_user_regs *regs) +{ + return ((unsigned long)abort_guest_exit_start == regs->pc) || + (unsigned long)abort_guest_exit_end == regs->pc; +} + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: From patchwork Thu Oct 18 13:20:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149130 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972606lji; Thu, 18 Oct 2018 06:23:21 -0700 (PDT) X-Google-Smtp-Source: ACcGV63sdbHU+Nau34Y14JmDWQ3o6HvL6RpI2/X7xN/J5nrYhE+qBM9kzEFPMAXUNqyJqKrT+Ls7 X-Received: by 2002:a0d:c283:: with SMTP id e125-v6mr18360514ywd.11.1539869001498; Thu, 18 Oct 2018 06:23:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869001; cv=none; d=google.com; s=arc-20160816; b=mKjRGrvXFrbcxhVuZOiVFmb4S3AllR8yFPG5jGV19zGU+tkmCR4420U7Ftm63ybWg4 tQIjESebCa71FjNPK7ma889XNfrVheak3k+QHBmNysXVVPR24EZQTDPFgUA0YTqLtxUp 78HJBJd05dw4K4pkxgjQe17y/HKGOALFFJOlTB4DQD7EBU++LzpDHF5MHWcgXkRFqgPX K2REZjw2+dJtwP+MgLLJ1sZXJWEqpbOCaWT46uFYhvp4CKY5VSteJkvugWUv/m/0LCdd JLFYpH5xhQ+WCiIQvAUMWNqpgLln5M+i2y6qY0mO8QIT6FXfc0hqWYCZkcedTvz7uXGO eLmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=S41j0Zk700HXnfxOB0jAW+zsMNOBmxC9GjMYzDi590c=; b=mCLE+sRHcsmBXIkFfA+ZtrtPcPw/iebMd+dis5yNNzo5OjRqJ5Ey6/ctrvi7oSRc0e h9r5/Aqw5lTfP0ybmfs734LUfoVJYf3wNkoFTqZapXqFtSlkBSMChRXUdjCyQXdbdC3a 1D67xb5u6iFgN1J1ioeXmQaexeVFsmWNDtnckMA9PrH7QJpwcdV5KilA2hghywQul2LF 7uIP9Pwpqb4eURBNN1kVtETEoSJfTgghTHvNAJehWyvdHATfNmN6C8QyWiHxLuBUoasJ JGsBGHOWIc2R6lTaVG8A296Ecm820GU/jQPeE/PYWQMJDJl5NKFBCY7m582hZR/5zuGG d0mg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id y7-v6si7788006ywf.184.2018.10.18.06.23.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ev-00030O-Gt; Thu, 18 Oct 2018 13:21:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ev-000307-0f for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:25 +0000 X-Inumbo-ID: e8d7d44a-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e8d7d44a-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:49 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 526C7341; Thu, 18 Oct 2018 06:21:24 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8AA2F3F59C; Thu, 18 Oct 2018 06:21:23 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:54 +0100 Message-Id: <20181018132109.31192-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 07/22] xen/arm: gic-3: Remove unused includes X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/gic-v3.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 2952335d05..8ff4e0f08e 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -23,7 +23,6 @@ #include #include -#include #include #include #include @@ -33,18 +32,14 @@ #include #include #include -#include #include #include -#include -#include #include #include #include #include #include #include -#include /* Global state */ static struct { From patchwork Thu Oct 18 13:20:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149132 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972707lji; Thu, 18 Oct 2018 06:23:26 -0700 (PDT) X-Google-Smtp-Source: ACcGV63DeJGw0HNQLUD1VxsaX3bq3BrcuYDVeLT4xzpt7KZ9yw8ibbSIjAtAnVId8JOZDsxD6K49 X-Received: by 2002:a0d:f002:: with SMTP id z2-v6mr19007465ywe.185.1539869006575; Thu, 18 Oct 2018 06:23:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869006; cv=none; d=google.com; s=arc-20160816; b=YyEqMFyfE5S0Cbvc3JZiXqVmDXqueSyd4npKYXuPmXp22kKcKCw5L7pPYg+TgUJ8QX WcpkATaBBzoFf/emM3oodKKQtDFp+ylJoxeV+OLF8mglldrjUqPltzWmsFqVWaTY7tbp EO402jkWmi560ql4YNkUWE7t3fcv5rMZSo3dXB1M5x53x2H3k7xoFy5plyTD1VzkM7+r DfVOUiaMrn/NytKjvis/agvF3x15xAFsjZyA3ecwiqTnd9NcfcdfEuYm34yotl26eCY+ OThSc4pjt96uqUui0fGHyUxJ0GEQNnanbPTBkdQ1nsuLSR5QcHSuryTQH1bbCo8bx2oF VwkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=/l0FC8uPAOIWEaPlgo7qVvIabc+OHKlxvjtmmECKzSE=; b=mj2P0UTMlf6VZGeR6+KXhTNeWz9n3wGhCjmXxA1acLeijKAEtSOV+RrW7LogZomHzb V0L0A+3F3EkoF/WyHPzjyV1pW4nooc6dB78SXYEhGUIW0G4908GfSnerLNBK1kiYfINI 1bZZIYERFal2ZJBhvm+4EiunxTS+jAgnHKoaScXh0nJAX6wuKqzDVxtVA7D9wS83B712 DdTaovNlnVC12NQIyqU//RBoc1PzGmvIJLteqipYnLBW68WRwlGV9YWi9Zp3AxTwB/2S mV8xc/w/9ZGk8NxPw2d4G1JH6aE9OOKULjhicU8af2nCgFfx8Bhc/zPbQmySzWWMho8Z jw2A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d28-v6si8049346yba.278.2018.10.18.06.23.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ey-00032l-MO; Thu, 18 Oct 2018 13:21:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ex-000312-91 for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:27 +0000 X-Inumbo-ID: e979cf01-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e979cf01-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:50 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 573221596; Thu, 18 Oct 2018 06:21:25 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8F5CB3F59C; Thu, 18 Oct 2018 06:21:24 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:55 +0100 Message-Id: <20181018132109.31192-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 08/22] xen/arm: gic-v3: Re-order includes in alphabetical order X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Andrii Anisov Reviewed-by: Andrii Anisov<andrii_anisov@epam.com>
--- xen/arch/arm/gic-v3.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 8ff4e0f08e..a7ce94789c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -21,25 +21,27 @@ * GNU General Public License for more details. */ -#include +#include +#include +#include +#include #include -#include -#include #include +#include +#include +#include +#include #include -#include -#include -#include #include -#include -#include + #include -#include + +#include #include #include #include #include -#include +#include /* Global state */ static struct { From patchwork Thu Oct 18 13:20:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149144 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1973090lji; Thu, 18 Oct 2018 06:23:46 -0700 (PDT) X-Google-Smtp-Source: ACcGV60e5nXQm08WDeQhowmawBmzd+4WkIc2nbHjkG1nH01hmWa5qYg6jrpmZ1KSgtj+1LVcC2gD X-Received: by 2002:a81:5f86:: with SMTP id t128-v6mr18955166ywb.84.1539869026184; Thu, 18 Oct 2018 06:23:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869026; cv=none; d=google.com; s=arc-20160816; b=jvg+Y6cUIHBMLWFoXkMH7BY6njJIYdwlUVj2f55r2ZOKwJ33rjIruZLdIbW2VvrdXm rQUvvMo0lGu4Rx2bq0QRvSgm/gpIkZO3rqN6kn8RVObIjl/a/fXwsG9RW5Nl6/vgOdvG XvD3kyQorT8oDwF7Eso4VdLaY0w13CqRTnLH/zq/l7MHG1lK7acYc0dGr1rTWj7MYSsY EIb04wymym5PXQZvAg769TkRjuHX3r1RsUGfQUzAld2epXGj/nZ3tTFsJNxa4hR7kIqq ggTaqndFmmOBDFlf8MERli8sry/CAMgEvx9rhZfwcMVxAIcvMMV82KN548WE6o41guxw vTGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Rgq5lqmbyQsdnfmU2w0JU74WFL2pBVD7pkKV67zy/Cg=; b=H4I/+TRjvFHeG+kyI6QwEGbqLYWTJeosqOXL4SFp6p1xlh2ady1a635oz5Eb8XSA1M vexE1AF7Z5o2oLNFEZKYJpAnF6d/8Oqgs7jKlD6Daquvtz1J/rz/zEk8Ty0eHlg34sQH C4H7GrLb0UBu67MPsbI1EFoTBLlOiDZ39APQfXybCoNOebuzB2CDfVripPJOxmHnT/xY egf+BXR+EALv9i8lmoQ0xin2xaSxWIb18gQu6W+VVOE2xm5m3MvvsNuKIcsiwB+Qln8D ZLubmOhwRQNz7OWBj7qFJjuBTI4TOWMwb/v223V/GX6TKHy6Vz3hT6MvsPhf2qeK9omu Zp/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id k8-v6si5858429ybh.260.2018.10.18.06.23.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F0-00034E-3p; Thu, 18 Oct 2018 13:21:30 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ey-00032b-8c for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:28 +0000 X-Inumbo-ID: 53e78037-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 53e78037-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:39 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 805F4341; Thu, 18 Oct 2018 06:21:26 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 947B33F59C; Thu, 18 Oct 2018 06:21:25 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:56 +0100 Message-Id: <20181018132109.31192-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 09/22] xen/arm: Move HSR defines in a new header hsr.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The HSR defines are pretty much self-contained and not necessary to be included everywhere in Xen. So move them in a new header hsr.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/arm64/traps.c | 1 + xen/arch/arm/traps.c | 1 + xen/include/asm-arm/arm64/hsr.h | 122 ++++++++++++++++++++ xen/include/asm-arm/arm64/sysregs.h | 109 ------------------ xen/include/asm-arm/hsr.h | 217 ++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/mmio.h | 2 + xen/include/asm-arm/processor.h | 199 --------------------------------- xen/include/asm-arm/traps.h | 1 + 8 files changed, 344 insertions(+), 308 deletions(-) create mode 100644 xen/include/asm-arm/arm64/hsr.h create mode 100644 xen/include/asm-arm/hsr.h diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c index e5240190e6..babfc1d884 100644 --- a/xen/arch/arm/arm64/traps.c +++ b/xen/arch/arm/arm64/traps.c @@ -18,6 +18,7 @@ #include +#include #include #include diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1b0b27434f..0dd664cc08 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hsr.h new file mode 100644 index 0000000000..ca931dd2fe --- /dev/null +++ b/xen/include/asm-arm/arm64/hsr.h @@ -0,0 +1,122 @@ +#ifndef __ASM_ARM_ARM64_HSR_H +#define __ASM_ARM_ARM64_HSR_H + +/* AArch 64 System Register Encodings */ +#define __HSR_SYSREG_c0 0 +#define __HSR_SYSREG_c1 1 +#define __HSR_SYSREG_c2 2 +#define __HSR_SYSREG_c3 3 +#define __HSR_SYSREG_c4 4 +#define __HSR_SYSREG_c5 5 +#define __HSR_SYSREG_c6 6 +#define __HSR_SYSREG_c7 7 +#define __HSR_SYSREG_c8 8 +#define __HSR_SYSREG_c9 9 +#define __HSR_SYSREG_c10 10 +#define __HSR_SYSREG_c11 11 +#define __HSR_SYSREG_c12 12 +#define __HSR_SYSREG_c13 13 +#define __HSR_SYSREG_c14 14 +#define __HSR_SYSREG_c15 15 + +#define __HSR_SYSREG_0 0 +#define __HSR_SYSREG_1 1 +#define __HSR_SYSREG_2 2 +#define __HSR_SYSREG_3 3 +#define __HSR_SYSREG_4 4 +#define __HSR_SYSREG_5 5 +#define __HSR_SYSREG_6 6 +#define __HSR_SYSREG_7 7 + +/* These are used to decode traps with HSR.EC==HSR_EC_SYSREG */ +#define HSR_SYSREG(op0,op1,crn,crm,op2) \ + (((__HSR_SYSREG_##op0) << HSR_SYSREG_OP0_SHIFT) | \ + ((__HSR_SYSREG_##op1) << HSR_SYSREG_OP1_SHIFT) | \ + ((__HSR_SYSREG_##crn) << HSR_SYSREG_CRN_SHIFT) | \ + ((__HSR_SYSREG_##crm) << HSR_SYSREG_CRM_SHIFT) | \ + ((__HSR_SYSREG_##op2) << HSR_SYSREG_OP2_SHIFT)) + +#define HSR_SYSREG_DCISW HSR_SYSREG(1,0,c7,c6,2) +#define HSR_SYSREG_DCCSW HSR_SYSREG(1,0,c7,c10,2) +#define HSR_SYSREG_DCCISW HSR_SYSREG(1,0,c7,c14,2) + +#define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2) +#define HSR_SYSREG_MDRAR_EL1 HSR_SYSREG(2,0,c1,c0,0) +#define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4) +#define HSR_SYSREG_OSLSR_EL1 HSR_SYSREG(2,0,c1,c1,4) +#define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) +#define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) +#define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) + +#define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) +#define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) +#define HSR_SYSREG_DBGWVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,6) +#define HSR_SYSREG_DBGWCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,7) + +#define HSR_SYSREG_DBG_CASES(REG) case HSR_SYSREG_##REG##n_EL1(0): \ + case HSR_SYSREG_##REG##n_EL1(1): \ + case HSR_SYSREG_##REG##n_EL1(2): \ + case HSR_SYSREG_##REG##n_EL1(3): \ + case HSR_SYSREG_##REG##n_EL1(4): \ + case HSR_SYSREG_##REG##n_EL1(5): \ + case HSR_SYSREG_##REG##n_EL1(6): \ + case HSR_SYSREG_##REG##n_EL1(7): \ + case HSR_SYSREG_##REG##n_EL1(8): \ + case HSR_SYSREG_##REG##n_EL1(9): \ + case HSR_SYSREG_##REG##n_EL1(10): \ + case HSR_SYSREG_##REG##n_EL1(11): \ + case HSR_SYSREG_##REG##n_EL1(12): \ + case HSR_SYSREG_##REG##n_EL1(13): \ + case HSR_SYSREG_##REG##n_EL1(14): \ + case HSR_SYSREG_##REG##n_EL1(15) + +#define HSR_SYSREG_SCTLR_EL1 HSR_SYSREG(3,0,c1, c0,0) +#define HSR_SYSREG_ACTLR_EL1 HSR_SYSREG(3,0,c1, c0,1) +#define HSR_SYSREG_TTBR0_EL1 HSR_SYSREG(3,0,c2, c0,0) +#define HSR_SYSREG_TTBR1_EL1 HSR_SYSREG(3,0,c2, c0,1) +#define HSR_SYSREG_TCR_EL1 HSR_SYSREG(3,0,c2, c0,2) +#define HSR_SYSREG_AFSR0_EL1 HSR_SYSREG(3,0,c5, c1,0) +#define HSR_SYSREG_AFSR1_EL1 HSR_SYSREG(3,0,c5, c1,1) +#define HSR_SYSREG_ESR_EL1 HSR_SYSREG(3,0,c5, c2,0) +#define HSR_SYSREG_FAR_EL1 HSR_SYSREG(3,0,c6, c0,0) +#define HSR_SYSREG_PMINTENSET_EL1 HSR_SYSREG(3,0,c9,c14,1) +#define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2) +#define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0) +#define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0) +#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5) +#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6) +#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) +#define HSR_SYSREG_ICC_SRE_EL1 HSR_SYSREG(3,0,c12,c12,5) +#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1) + +#define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0) +#define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1) +#define HSR_SYSREG_PMCNTENCLR_EL0 HSR_SYSREG(3,3,c9,c12,2) +#define HSR_SYSREG_PMOVSCLR_EL0 HSR_SYSREG(3,3,c9,c12,3) +#define HSR_SYSREG_PMSWINC_EL0 HSR_SYSREG(3,3,c9,c12,4) +#define HSR_SYSREG_PMSELR_EL0 HSR_SYSREG(3,3,c9,c12,5) +#define HSR_SYSREG_PMCEID0_EL0 HSR_SYSREG(3,3,c9,c12,6) +#define HSR_SYSREG_PMCEID1_EL0 HSR_SYSREG(3,3,c9,c12,7) + +#define HSR_SYSREG_PMCCNTR_EL0 HSR_SYSREG(3,3,c9,c13,0) +#define HSR_SYSREG_PMXEVTYPER_EL0 HSR_SYSREG(3,3,c9,c13,1) +#define HSR_SYSREG_PMXEVCNTR_EL0 HSR_SYSREG(3,3,c9,c13,2) + +#define HSR_SYSREG_PMUSERENR_EL0 HSR_SYSREG(3,3,c9,c14,0) +#define HSR_SYSREG_PMOVSSET_EL0 HSR_SYSREG(3,3,c9,c14,3) + +#define HSR_SYSREG_CNTPCT_EL0 HSR_SYSREG(3,3,c14,c0,0) +#define HSR_SYSREG_CNTP_TVAL_EL0 HSR_SYSREG(3,3,c14,c2,0) +#define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) +#define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) + +#endif /* __ASM_ARM_ARM64_HSR_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index 1811234249..f510925a2a 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -3,115 +3,6 @@ #include -/* AArch 64 System Register Encodings */ -#define __HSR_SYSREG_c0 0 -#define __HSR_SYSREG_c1 1 -#define __HSR_SYSREG_c2 2 -#define __HSR_SYSREG_c3 3 -#define __HSR_SYSREG_c4 4 -#define __HSR_SYSREG_c5 5 -#define __HSR_SYSREG_c6 6 -#define __HSR_SYSREG_c7 7 -#define __HSR_SYSREG_c8 8 -#define __HSR_SYSREG_c9 9 -#define __HSR_SYSREG_c10 10 -#define __HSR_SYSREG_c11 11 -#define __HSR_SYSREG_c12 12 -#define __HSR_SYSREG_c13 13 -#define __HSR_SYSREG_c14 14 -#define __HSR_SYSREG_c15 15 - -#define __HSR_SYSREG_0 0 -#define __HSR_SYSREG_1 1 -#define __HSR_SYSREG_2 2 -#define __HSR_SYSREG_3 3 -#define __HSR_SYSREG_4 4 -#define __HSR_SYSREG_5 5 -#define __HSR_SYSREG_6 6 -#define __HSR_SYSREG_7 7 - -/* These are used to decode traps with HSR.EC==HSR_EC_SYSREG */ -#define HSR_SYSREG(op0,op1,crn,crm,op2) \ - (((__HSR_SYSREG_##op0) << HSR_SYSREG_OP0_SHIFT) | \ - ((__HSR_SYSREG_##op1) << HSR_SYSREG_OP1_SHIFT) | \ - ((__HSR_SYSREG_##crn) << HSR_SYSREG_CRN_SHIFT) | \ - ((__HSR_SYSREG_##crm) << HSR_SYSREG_CRM_SHIFT) | \ - ((__HSR_SYSREG_##op2) << HSR_SYSREG_OP2_SHIFT)) - -#define HSR_SYSREG_DCISW HSR_SYSREG(1,0,c7,c6,2) -#define HSR_SYSREG_DCCSW HSR_SYSREG(1,0,c7,c10,2) -#define HSR_SYSREG_DCCISW HSR_SYSREG(1,0,c7,c14,2) - -#define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2) -#define HSR_SYSREG_MDRAR_EL1 HSR_SYSREG(2,0,c1,c0,0) -#define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4) -#define HSR_SYSREG_OSLSR_EL1 HSR_SYSREG(2,0,c1,c1,4) -#define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) -#define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) -#define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) - -#define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) -#define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) -#define HSR_SYSREG_DBGWVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,6) -#define HSR_SYSREG_DBGWCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,7) - -#define HSR_SYSREG_DBG_CASES(REG) case HSR_SYSREG_##REG##n_EL1(0): \ - case HSR_SYSREG_##REG##n_EL1(1): \ - case HSR_SYSREG_##REG##n_EL1(2): \ - case HSR_SYSREG_##REG##n_EL1(3): \ - case HSR_SYSREG_##REG##n_EL1(4): \ - case HSR_SYSREG_##REG##n_EL1(5): \ - case HSR_SYSREG_##REG##n_EL1(6): \ - case HSR_SYSREG_##REG##n_EL1(7): \ - case HSR_SYSREG_##REG##n_EL1(8): \ - case HSR_SYSREG_##REG##n_EL1(9): \ - case HSR_SYSREG_##REG##n_EL1(10): \ - case HSR_SYSREG_##REG##n_EL1(11): \ - case HSR_SYSREG_##REG##n_EL1(12): \ - case HSR_SYSREG_##REG##n_EL1(13): \ - case HSR_SYSREG_##REG##n_EL1(14): \ - case HSR_SYSREG_##REG##n_EL1(15) - -#define HSR_SYSREG_SCTLR_EL1 HSR_SYSREG(3,0,c1, c0,0) -#define HSR_SYSREG_ACTLR_EL1 HSR_SYSREG(3,0,c1, c0,1) -#define HSR_SYSREG_TTBR0_EL1 HSR_SYSREG(3,0,c2, c0,0) -#define HSR_SYSREG_TTBR1_EL1 HSR_SYSREG(3,0,c2, c0,1) -#define HSR_SYSREG_TCR_EL1 HSR_SYSREG(3,0,c2, c0,2) -#define HSR_SYSREG_AFSR0_EL1 HSR_SYSREG(3,0,c5, c1,0) -#define HSR_SYSREG_AFSR1_EL1 HSR_SYSREG(3,0,c5, c1,1) -#define HSR_SYSREG_ESR_EL1 HSR_SYSREG(3,0,c5, c2,0) -#define HSR_SYSREG_FAR_EL1 HSR_SYSREG(3,0,c6, c0,0) -#define HSR_SYSREG_PMINTENSET_EL1 HSR_SYSREG(3,0,c9,c14,1) -#define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2) -#define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0) -#define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0) -#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5) -#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6) -#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) -#define HSR_SYSREG_ICC_SRE_EL1 HSR_SYSREG(3,0,c12,c12,5) -#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1) - -#define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0) -#define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1) -#define HSR_SYSREG_PMCNTENCLR_EL0 HSR_SYSREG(3,3,c9,c12,2) -#define HSR_SYSREG_PMOVSCLR_EL0 HSR_SYSREG(3,3,c9,c12,3) -#define HSR_SYSREG_PMSWINC_EL0 HSR_SYSREG(3,3,c9,c12,4) -#define HSR_SYSREG_PMSELR_EL0 HSR_SYSREG(3,3,c9,c12,5) -#define HSR_SYSREG_PMCEID0_EL0 HSR_SYSREG(3,3,c9,c12,6) -#define HSR_SYSREG_PMCEID1_EL0 HSR_SYSREG(3,3,c9,c12,7) - -#define HSR_SYSREG_PMCCNTR_EL0 HSR_SYSREG(3,3,c9,c13,0) -#define HSR_SYSREG_PMXEVTYPER_EL0 HSR_SYSREG(3,3,c9,c13,1) -#define HSR_SYSREG_PMXEVCNTR_EL0 HSR_SYSREG(3,3,c9,c13,2) - -#define HSR_SYSREG_PMUSERENR_EL0 HSR_SYSREG(3,3,c9,c14,0) -#define HSR_SYSREG_PMOVSSET_EL0 HSR_SYSREG(3,3,c9,c14,3) - -#define HSR_SYSREG_CNTPCT_EL0 HSR_SYSREG(3,3,c14,c0,0) -#define HSR_SYSREG_CNTP_TVAL_EL0 HSR_SYSREG(3,3,c14,c2,0) -#define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) -#define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) - /* * GIC System register assembly aliases picked from kernel */ diff --git a/xen/include/asm-arm/hsr.h b/xen/include/asm-arm/hsr.h new file mode 100644 index 0000000000..29d4531f40 --- /dev/null +++ b/xen/include/asm-arm/hsr.h @@ -0,0 +1,217 @@ +#ifndef __ASM_ARM_HSR_H +#define __ASM_ARM_HSR_H + +#include + +#if defined(CONFIG_ARM_64) +# include +#endif + +/* HSR data abort size definition */ +enum dabt_size { + DABT_BYTE = 0, + DABT_HALF_WORD = 1, + DABT_WORD = 2, + DABT_DOUBLE_WORD = 3, +}; + +union hsr { + uint32_t bits; + struct { + unsigned long iss:25; /* Instruction Specific Syndrome */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + }; + + /* Common to all conditional exception classes (0x0N, except 0x00). */ + struct hsr_cond { + unsigned long iss:20; /* Instruction Specific Syndrome */ + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } cond; + + struct hsr_wfi_wfe { + unsigned long ti:1; /* Trapped instruction */ + unsigned long sbzp:19; + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } wfi_wfe; + + /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */ + struct hsr_cp32 { + unsigned long read:1; /* Direction */ + unsigned long crm:4; /* CRm */ + unsigned long reg:5; /* Rt */ + unsigned long crn:4; /* CRn */ + unsigned long op1:3; /* Op1 */ + unsigned long op2:3; /* Op2 */ + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */ + + struct hsr_cp64 { + unsigned long read:1; /* Direction */ + unsigned long crm:4; /* CRm */ + unsigned long reg1:5; /* Rt1 */ + unsigned long reg2:5; /* Rt2 */ + unsigned long sbzp2:1; + unsigned long op1:4; /* Op1 */ + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ + + struct hsr_cp { + unsigned long coproc:4; /* Number of coproc accessed */ + unsigned long sbz0p:1; + unsigned long tas:1; /* Trapped Advanced SIMD */ + unsigned long res0:14; + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } cp; /* HSR_EC_CP */ + + /* + * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 and + * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP + * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements + * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7: + * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition + * check was passed or instruction was unconditional. + */ + struct hsr_smc32 { + unsigned long res0:19; /* Reserved */ + unsigned long ccknownpass:1; /* Instruction passed conditional check */ + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } smc32; /* HSR_EC_SMC32 */ + +#ifdef CONFIG_ARM_64 + struct hsr_sysreg { + unsigned long read:1; /* Direction */ + unsigned long crm:4; /* CRm */ + unsigned long reg:5; /* Rt */ + unsigned long crn:4; /* CRn */ + unsigned long op1:3; /* Op1 */ + unsigned long op2:3; /* Op2 */ + unsigned long op0:2; /* Op0 */ + unsigned long res0:3; + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; + } sysreg; /* HSR_EC_SYSREG */ +#endif + + struct hsr_iabt { + unsigned long ifsc:6; /* Instruction fault status code */ + unsigned long res0:1; /* RES0 */ + unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ + unsigned long res1:1; /* RES0 */ + unsigned long eat:1; /* External abort type */ + unsigned long fnv:1; /* FAR not Valid */ + unsigned long res2:14; + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } iabt; /* HSR_EC_INSTR_ABORT_* */ + + struct hsr_dabt { + unsigned long dfsc:6; /* Data Fault Status Code */ + unsigned long write:1; /* Write / not Read */ + unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ + unsigned long cache:1; /* Cache Maintenance */ + unsigned long eat:1; /* External Abort Type */ + unsigned long fnv:1; /* FAR not Valid */ +#ifdef CONFIG_ARM_32 + unsigned long sbzp0:5; +#else + unsigned long sbzp0:3; + unsigned long ar:1; /* Acquire Release */ + unsigned long sf:1; /* Sixty Four bit register */ +#endif + unsigned long reg:5; /* Register */ + unsigned long sign:1; /* Sign extend */ + unsigned long size:2; /* Access Size */ + unsigned long valid:1; /* Syndrome Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } dabt; /* HSR_EC_DATA_ABORT_* */ + + /* Contain the common bits between DABT and IABT */ + struct hsr_xabt { + unsigned long fsc:6; /* Fault status code */ + unsigned long pad1:1; /* Not common */ + unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ + unsigned long pad2:1; /* Not common */ + unsigned long eat:1; /* External abort type */ + unsigned long fnv:1; /* FAR not Valid */ + unsigned long pad3:14; /* Not common */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } xabt; + +#ifdef CONFIG_ARM_64 + struct hsr_brk { + unsigned long comment:16; /* Comment */ + unsigned long res0:9; + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } brk; +#endif +}; + +/* HSR.EC == HSR_CP{15,14,10}_32 */ +#define HSR_CP32_OP2_MASK (0x000e0000) +#define HSR_CP32_OP2_SHIFT (17) +#define HSR_CP32_OP1_MASK (0x0001c000) +#define HSR_CP32_OP1_SHIFT (14) +#define HSR_CP32_CRN_MASK (0x00003c00) +#define HSR_CP32_CRN_SHIFT (10) +#define HSR_CP32_CRM_MASK (0x0000001e) +#define HSR_CP32_CRM_SHIFT (1) +#define HSR_CP32_REGS_MASK (HSR_CP32_OP1_MASK|HSR_CP32_OP2_MASK|\ + HSR_CP32_CRN_MASK|HSR_CP32_CRM_MASK) + +/* HSR.EC == HSR_CP{15,14}_64 */ +#define HSR_CP64_OP1_MASK (0x000f0000) +#define HSR_CP64_OP1_SHIFT (16) +#define HSR_CP64_CRM_MASK (0x0000001e) +#define HSR_CP64_CRM_SHIFT (1) +#define HSR_CP64_REGS_MASK (HSR_CP64_OP1_MASK|HSR_CP64_CRM_MASK) + +/* HSR.EC == HSR_SYSREG */ +#define HSR_SYSREG_OP0_MASK (0x00300000) +#define HSR_SYSREG_OP0_SHIFT (20) +#define HSR_SYSREG_OP1_MASK (0x0001c000) +#define HSR_SYSREG_OP1_SHIFT (14) +#define HSR_SYSREG_CRN_MASK (0x00003c00) +#define HSR_SYSREG_CRN_SHIFT (10) +#define HSR_SYSREG_CRM_MASK (0x0000001e) +#define HSR_SYSREG_CRM_SHIFT (1) +#define HSR_SYSREG_OP2_MASK (0x000e0000) +#define HSR_SYSREG_OP2_SHIFT (17) +#define HSR_SYSREG_REGS_MASK (HSR_SYSREG_OP0_MASK|HSR_SYSREG_OP1_MASK|\ + HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\ + HSR_SYSREG_OP2_MASK) + +/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */ +#define HSR_XXC_IMM_MASK (0xffff) + +#endif /* __ASM_ARM_HSR_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/mmio.h b/xen/include/asm-arm/mmio.h index c8dadb5006..3ed3f82bf7 100644 --- a/xen/include/asm-arm/mmio.h +++ b/xen/include/asm-arm/mmio.h @@ -21,6 +21,8 @@ #include #include + +#include #include #include diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 5b6bd0c38c..3592aa36d8 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -353,207 +353,8 @@ extern register_t __cpu_logical_map[]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] -/* HSR data abort size definition */ -enum dabt_size { - DABT_BYTE = 0, - DABT_HALF_WORD = 1, - DABT_WORD = 2, - DABT_DOUBLE_WORD = 3, -}; - -union hsr { - uint32_t bits; - struct { - unsigned long iss:25; /* Instruction Specific Syndrome */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - }; - - /* Common to all conditional exception classes (0x0N, except 0x00). */ - struct hsr_cond { - unsigned long iss:20; /* Instruction Specific Syndrome */ - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } cond; - - struct hsr_wfi_wfe { - unsigned long ti:1; /* Trapped instruction */ - unsigned long sbzp:19; - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } wfi_wfe; - - /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */ - struct hsr_cp32 { - unsigned long read:1; /* Direction */ - unsigned long crm:4; /* CRm */ - unsigned long reg:5; /* Rt */ - unsigned long crn:4; /* CRn */ - unsigned long op1:3; /* Op1 */ - unsigned long op2:3; /* Op2 */ - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */ - - struct hsr_cp64 { - unsigned long read:1; /* Direction */ - unsigned long crm:4; /* CRm */ - unsigned long reg1:5; /* Rt1 */ - unsigned long reg2:5; /* Rt2 */ - unsigned long sbzp2:1; - unsigned long op1:4; /* Op1 */ - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ - - struct hsr_cp { - unsigned long coproc:4; /* Number of coproc accessed */ - unsigned long sbz0p:1; - unsigned long tas:1; /* Trapped Advanced SIMD */ - unsigned long res0:14; - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } cp; /* HSR_EC_CP */ - - /* - * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 and - * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP - * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements - * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7: - * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition - * check was passed or instruction was unconditional. - */ - struct hsr_smc32 { - unsigned long res0:19; /* Reserved */ - unsigned long ccknownpass:1; /* Instruction passed conditional check */ - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } smc32; /* HSR_EC_SMC32 */ - -#ifdef CONFIG_ARM_64 - struct hsr_sysreg { - unsigned long read:1; /* Direction */ - unsigned long crm:4; /* CRm */ - unsigned long reg:5; /* Rt */ - unsigned long crn:4; /* CRn */ - unsigned long op1:3; /* Op1 */ - unsigned long op2:3; /* Op2 */ - unsigned long op0:2; /* Op0 */ - unsigned long res0:3; - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; - } sysreg; /* HSR_EC_SYSREG */ -#endif - - struct hsr_iabt { - unsigned long ifsc:6; /* Instruction fault status code */ - unsigned long res0:1; /* RES0 */ - unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ - unsigned long res1:1; /* RES0 */ - unsigned long eat:1; /* External abort type */ - unsigned long fnv:1; /* FAR not Valid */ - unsigned long res2:14; - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } iabt; /* HSR_EC_INSTR_ABORT_* */ - - struct hsr_dabt { - unsigned long dfsc:6; /* Data Fault Status Code */ - unsigned long write:1; /* Write / not Read */ - unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ - unsigned long cache:1; /* Cache Maintenance */ - unsigned long eat:1; /* External Abort Type */ - unsigned long fnv:1; /* FAR not Valid */ -#ifdef CONFIG_ARM_32 - unsigned long sbzp0:5; -#else - unsigned long sbzp0:3; - unsigned long ar:1; /* Acquire Release */ - unsigned long sf:1; /* Sixty Four bit register */ -#endif - unsigned long reg:5; /* Register */ - unsigned long sign:1; /* Sign extend */ - unsigned long size:2; /* Access Size */ - unsigned long valid:1; /* Syndrome Valid */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } dabt; /* HSR_EC_DATA_ABORT_* */ - - /* Contain the common bits between DABT and IABT */ - struct hsr_xabt { - unsigned long fsc:6; /* Fault status code */ - unsigned long pad1:1; /* Not common */ - unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ - unsigned long pad2:1; /* Not common */ - unsigned long eat:1; /* External abort type */ - unsigned long fnv:1; /* FAR not Valid */ - unsigned long pad3:14; /* Not common */ - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } xabt; - -#ifdef CONFIG_ARM_64 - struct hsr_brk { - unsigned long comment:16; /* Comment */ - unsigned long res0:9; - unsigned long len:1; /* Instruction length */ - unsigned long ec:6; /* Exception Class */ - } brk; -#endif - - -}; #endif -/* HSR.EC == HSR_CP{15,14,10}_32 */ -#define HSR_CP32_OP2_MASK (0x000e0000) -#define HSR_CP32_OP2_SHIFT (17) -#define HSR_CP32_OP1_MASK (0x0001c000) -#define HSR_CP32_OP1_SHIFT (14) -#define HSR_CP32_CRN_MASK (0x00003c00) -#define HSR_CP32_CRN_SHIFT (10) -#define HSR_CP32_CRM_MASK (0x0000001e) -#define HSR_CP32_CRM_SHIFT (1) -#define HSR_CP32_REGS_MASK (HSR_CP32_OP1_MASK|HSR_CP32_OP2_MASK|\ - HSR_CP32_CRN_MASK|HSR_CP32_CRM_MASK) - -/* HSR.EC == HSR_CP{15,14}_64 */ -#define HSR_CP64_OP1_MASK (0x000f0000) -#define HSR_CP64_OP1_SHIFT (16) -#define HSR_CP64_CRM_MASK (0x0000001e) -#define HSR_CP64_CRM_SHIFT (1) -#define HSR_CP64_REGS_MASK (HSR_CP64_OP1_MASK|HSR_CP64_CRM_MASK) - -/* HSR.EC == HSR_SYSREG */ -#define HSR_SYSREG_OP0_MASK (0x00300000) -#define HSR_SYSREG_OP0_SHIFT (20) -#define HSR_SYSREG_OP1_MASK (0x0001c000) -#define HSR_SYSREG_OP1_SHIFT (14) -#define HSR_SYSREG_CRN_MASK (0x00003c00) -#define HSR_SYSREG_CRN_SHIFT (10) -#define HSR_SYSREG_CRM_MASK (0x0000001e) -#define HSR_SYSREG_CRM_SHIFT (1) -#define HSR_SYSREG_OP2_MASK (0x000e0000) -#define HSR_SYSREG_OP2_SHIFT (17) -#define HSR_SYSREG_REGS_MASK (HSR_SYSREG_OP0_MASK|HSR_SYSREG_OP1_MASK|\ - HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\ - HSR_SYSREG_OP2_MASK) - -/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */ -#define HSR_XXC_IMM_MASK (0xffff) - /* Physical Address Register */ #define PAR_F (_AC(1,U)<<0) diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index c12e9e4082..8b6f09b6b8 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -1,6 +1,7 @@ #ifndef __ASM_ARM_TRAPS__ #define __ASM_ARM_TRAPS__ +#include #include #if defined(CONFIG_ARM_32) From patchwork Thu Oct 18 13:20:57 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id y65-v6si7646385ywa.11.2018.10.18.06.23.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F0-00034f-GB; Thu, 18 Oct 2018 13:21:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ez-00033a-7A for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:29 +0000 X-Inumbo-ID: eac8224a-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id eac8224a-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:53 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 858431596; Thu, 18 Oct 2018 06:21:27 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDACE3F59C; Thu, 18 Oct 2018 06:21:26 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:57 +0100 Message-Id: <20181018132109.31192-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 10/22] xen/arm: Move SYSREG accessors in sysregs.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" System registers accessors are self-contained and should not be included everywhere in Xen. Move the accessors in sysregs.h and include the file when necessary. With that change, it is not necessary to include processor.h in time.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/arm32/entry.S | 1 + xen/arch/arm/arm32/proc-v7.S | 1 + xen/arch/arm/gic-v3-lpi.c | 1 + xen/arch/arm/gic-v3.c | 1 + xen/include/asm-arm/arm32/processor.h | 62 ----------------------------- xen/include/asm-arm/arm32/sysregs.h | 74 +++++++++++++++++++++++++++++++++++ xen/include/asm-arm/arm64/processor.h | 25 ------------ xen/include/asm-arm/arm64/sysregs.h | 23 +++++++++++ xen/include/asm-arm/page.h | 1 + xen/include/asm-arm/percpu.h | 8 +--- xen/include/asm-arm/sysregs.h | 22 +++++++++++ xen/include/asm-arm/time.h | 2 +- 12 files changed, 126 insertions(+), 95 deletions(-) create mode 100644 xen/include/asm-arm/arm32/sysregs.h create mode 100644 xen/include/asm-arm/sysregs.h diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index f6908e3f16..0b4cd19abd 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -1,4 +1,5 @@ #include +#include #include #include #include diff --git a/xen/arch/arm/arm32/proc-v7.S b/xen/arch/arm/arm32/proc-v7.S index 2f3ff1e6c9..80a250d8e8 100644 --- a/xen/arch/arm/arm32/proc-v7.S +++ b/xen/arch/arm/arm32/proc-v7.S @@ -19,6 +19,7 @@ #include #include +#include ca15mp_init: ca7mp_init: diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index efd5cd62fb..e8c6e159ca 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -30,6 +30,7 @@ #include #include #include +#include /* * There could be a lot of LPIs on the host side, and they always go to diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a7ce94789c..264a981bab 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -42,6 +42,7 @@ #include #include #include +#include /* Global state */ static struct { diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index fb330812af..4e679f3273 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H -#include - #define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ @@ -60,66 +58,6 @@ struct cpu_user_regs #endif -/* Layout as used in assembly, with src/dest registers mixed in */ -#define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 -#define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm -#define CP32(r, name...) __CP32(r, name) -#define CP64(r, name...) __CP64(r, name) - -/* Stringified for inline assembly */ -#define LOAD_CP32(r, name...) "mrc " __stringify(CP32(%r, name)) ";" -#define STORE_CP32(r, name...) "mcr " __stringify(CP32(%r, name)) ";" -#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" -#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" - -/* Issue a CP operation which takes no argument, - * uses r0 as a placeholder register. */ -#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" - -#ifndef __ASSEMBLY__ - -/* C wrappers */ -#define READ_CP32(name...) ({ \ - register uint32_t _r; \ - asm volatile(LOAD_CP32(0, name) : "=r" (_r)); \ - _r; }) - -#define WRITE_CP32(v, name...) do { \ - register uint32_t _r = (v); \ - asm volatile(STORE_CP32(0, name) : : "r" (_r)); \ -} while (0) - -#define READ_CP64(name...) ({ \ - register uint64_t _r; \ - asm volatile(LOAD_CP64(0, name) : "=r" (_r)); \ - _r; }) - -#define WRITE_CP64(v, name...) do { \ - register uint64_t _r = (v); \ - asm volatile(STORE_CP64(0, name) : : "r" (_r)); \ -} while (0) - -/* - * C wrappers for accessing system registers. - * - * Registers come in 3 types: - * - those which are always 32-bit regardless of AArch32 vs AArch64 - * (use {READ,WRITE}_SYSREG32). - * - those which are always 64-bit regardless of AArch32 vs AArch64 - * (use {READ,WRITE}_SYSREG64). - * - those which vary between AArch32 and AArch64 (use {READ,WRITE}_SYSREG). - */ -#define READ_SYSREG32(R...) READ_CP32(R) -#define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) - -#define READ_SYSREG64(R...) READ_CP64(R) -#define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) - -#define READ_SYSREG(R...) READ_SYSREG32(R) -#define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) - -#endif /* __ASSEMBLY__ */ - #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ /* * Local variables: diff --git a/xen/include/asm-arm/arm32/sysregs.h b/xen/include/asm-arm/arm32/sysregs.h new file mode 100644 index 0000000000..b25b59a557 --- /dev/null +++ b/xen/include/asm-arm/arm32/sysregs.h @@ -0,0 +1,74 @@ +#ifndef __ASM_ARM_ARM32_SYSREGS_H +#define __ASM_ARM_ARM32_SYSREGS_H + +#include + +/* Layout as used in assembly, with src/dest registers mixed in */ +#define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 +#define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm +#define CP32(r, name...) __CP32(r, name) +#define CP64(r, name...) __CP64(r, name) + +/* Stringified for inline assembly */ +#define LOAD_CP32(r, name...) "mrc " __stringify(CP32(%r, name)) ";" +#define STORE_CP32(r, name...) "mcr " __stringify(CP32(%r, name)) ";" +#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" +#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" + +/* Issue a CP operation which takes no argument, + * uses r0 as a placeholder register. */ +#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" + +#ifndef __ASSEMBLY__ + +/* C wrappers */ +#define READ_CP32(name...) ({ \ + register uint32_t _r; \ + asm volatile(LOAD_CP32(0, name) : "=r" (_r)); \ + _r; }) + +#define WRITE_CP32(v, name...) do { \ + register uint32_t _r = (v); \ + asm volatile(STORE_CP32(0, name) : : "r" (_r)); \ +} while (0) + +#define READ_CP64(name...) ({ \ + register uint64_t _r; \ + asm volatile(LOAD_CP64(0, name) : "=r" (_r)); \ + _r; }) + +#define WRITE_CP64(v, name...) do { \ + register uint64_t _r = (v); \ + asm volatile(STORE_CP64(0, name) : : "r" (_r)); \ +} while (0) + +/* + * C wrappers for accessing system registers. + * + * Registers come in 3 types: + * - those which are always 32-bit regardless of AArch32 vs AArch64 + * (use {READ,WRITE}_SYSREG32). + * - those which are always 64-bit regardless of AArch32 vs AArch64 + * (use {READ,WRITE}_SYSREG64). + * - those which vary between AArch32 and AArch64 (use {READ,WRITE}_SYSREG). + */ +#define READ_SYSREG32(R...) READ_CP32(R) +#define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) + +#define READ_SYSREG64(R...) READ_CP64(R) +#define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) + +#define READ_SYSREG(R...) READ_SYSREG32(R) +#define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARM_ARM32_SYSREGS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index c18ab7203d..765de1b74b 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -3,8 +3,6 @@ #include -#include - #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ @@ -89,29 +87,6 @@ struct cpu_user_regs #undef __DECL_REG -/* Access to system registers */ - -#define READ_SYSREG32(name) ({ \ - uint32_t _r; \ - asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ - _r; }) -#define WRITE_SYSREG32(v, name) do { \ - uint32_t _r = v; \ - asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ -} while (0) - -#define WRITE_SYSREG64(v, name) do { \ - uint64_t _r = v; \ - asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ -} while (0) -#define READ_SYSREG64(name) ({ \ - uint64_t _r; \ - asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ - _r; }) - -#define READ_SYSREG(name) READ_SYSREG64(name) -#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index f510925a2a..08585a969e 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -57,6 +57,29 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) +/* Access to system registers */ + +#define READ_SYSREG32(name) ({ \ + uint32_t _r; \ + asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ + _r; }) +#define WRITE_SYSREG32(v, name) do { \ + uint32_t _r = v; \ + asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ +} while (0) + +#define WRITE_SYSREG64(v, name) do { \ + uint64_t _r = v; \ + asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ +} while (0) +#define READ_SYSREG64(name) ({ \ + uint64_t _r; \ + asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ + _r; }) + +#define READ_SYSREG(name) READ_SYSREG64(name) +#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index bcdea970ca..1a1713ce02 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -4,6 +4,7 @@ #include #include #include +#include #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index cdf64e0f77..6263e77251 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -4,13 +4,7 @@ #ifndef __ASSEMBLY__ #include -#if defined(CONFIG_ARM_32) -# include -#elif defined(CONFIG_ARM_64) -# include -#else -# error "unknown ARM variant" -#endif +#include extern char __per_cpu_start[], __per_cpu_data_end[]; extern unsigned long __per_cpu_offset[NR_CPUS]; diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h new file mode 100644 index 0000000000..5c5c51bbcd --- /dev/null +++ b/xen/include/asm-arm/sysregs.h @@ -0,0 +1,22 @@ +#ifndef __ASM_ARM_SYSREGS_H +#define __ASM_ARM_SYSREGS_H + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ASM_ARM_SYSREGS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + + diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index ea88e76304..9a7071a546 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -1,7 +1,7 @@ #ifndef __ARM_TIME_H__ #define __ARM_TIME_H__ -#include +#include #define DT_MATCH_TIMER \ DT_MATCH_COMPATIBLE("arm,armv7-timer"), \ From patchwork Thu Oct 18 13:20:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149131 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972680lji; 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[192.237.175.120]) by mx.google.com with ESMTPS id i10-v6si409637ywi.203.2018.10.18.06.23.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F0-00035V-QQ; Thu, 18 Oct 2018 13:21:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ez-00033k-DZ for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:29 +0000 X-Inumbo-ID: eb657735-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id eb657735-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:54 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A64D341; Thu, 18 Oct 2018 06:21:28 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C2B793F59C; Thu, 18 Oct 2018 06:21:27 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:58 +0100 Message-Id: <20181018132109.31192-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 11/22] xen/arm: Move out of processor.h traps related variable/function X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" do_unexpected_traps() is moved to traps.h while init_traps() and hyp_traps_vectors() are moved to setup.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/processor.h | 6 ------ xen/include/asm-arm/setup.h | 3 +++ xen/include/asm-arm/traps.h | 2 ++ 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 3592aa36d8..b05f17f35c 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -453,10 +453,6 @@ extern register_t __cpu_logical_map[]; #endif #ifndef __ASSEMBLY__ -extern uint32_t hyp_traps_vector[]; - -void init_traps(void); - void panic_PAR(uint64_t par); void show_execution_state(struct cpu_user_regs *regs); @@ -470,8 +466,6 @@ void show_registers(const struct cpu_user_regs *regs); #define cpu_to_core(_cpu) (0) #define cpu_to_socket(_cpu) (0) -void noreturn do_unexpected_trap(const char *msg, struct cpu_user_regs *regs); - struct vcpu; void vcpu_regs_hyp_to_user(const struct vcpu *vcpu, struct vcpu_guest_core_regs *regs); diff --git a/xen/include/asm-arm/setup.h b/xen/include/asm-arm/setup.h index 5f41ba0cba..11e1b2aacf 100644 --- a/xen/include/asm-arm/setup.h +++ b/xen/include/asm-arm/setup.h @@ -83,6 +83,9 @@ struct bootmodule *add_boot_module(bootmodule_kind kind, struct bootmodule *boot_module_find_by_kind(bootmodule_kind kind); const char *boot_module_kind_as_string(bootmodule_kind kind); +extern uint32_t hyp_traps_vector[]; +void init_traps(void); + #endif /* * Local variables: diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 8b6f09b6b8..3d60160310 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -46,6 +46,8 @@ void do_trap_hvc_smccc(struct cpu_user_regs *regs); int do_bug_frame(struct cpu_user_regs *regs, vaddr_t pc); +void noreturn do_unexpected_trap(const char *msg, struct cpu_user_regs *regs); + /* Functions for pending virtual abort checking window. */ void abort_guest_exit_start(void); void abort_guest_exit_end(void); From patchwork Thu Oct 18 13:20:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149139 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972854lji; Thu, 18 Oct 2018 06:23:34 -0700 (PDT) X-Google-Smtp-Source: ACcGV60S9TGnkqmIM03kupzsNpQeHBk55bxTDzRK2ZB0bj6HSSjnHqU0LAVM1aeCRNPq98KndVhd X-Received: by 2002:a25:3d85:: with SMTP id k127-v6mr13516587yba.371.1539869014721; Thu, 18 Oct 2018 06:23:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869014; cv=none; d=google.com; s=arc-20160816; b=bDHC7i60+B8QRsd/r1FGR7FSCZOVInx2YOk3hdGJodrGK9hiwQyodAnyz7BHuHUTz6 Hcm5nUg0DQJF4rI8v/8MSqc2jtzoqZgosMrPK5YQLxpnd93uZks59hj3fvuuYN3VuZDP Gc3kxzT0vZLCu3C/8Ak2QdKnH8pWCGd6IO1/lGoaPki/9vlxBjsCNZqnBYmp8DzowAIY Syq9xPG+MxoQIyYduO/grfUZHCmXMuPiTct4rV/hDhfmEVM5kjQ/ld93XyCK/waftm4b DwsY4d1KEHIvUhee2V2REGhAYnFcQtT75iBYCBOOZez9eUJ3Pvtz1utFcSaqaUGfZ31M l0YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Tdlr736qj9FPP2vgzYPtae3e4IrvwhLpFthQlAQUUfs=; b=XgdSuQLF2T9tXTwCrtWxmJ6xM9evWxre67lTlkpSVzqHLRGKpgMlmy0dDuMEx9j078 uMNrrsRW1gojoD1Q2loCx2MHN9g0tIYOmOCCAMaOW7+4K2A93ky3kmWzYCq+S9FTJ25B 5RTZYEoq5P8EHPOrYPwFO1/4NM9qgJBscrAfdx3S56DfsMolEe+YbKg6xiQEQVqR6GLR 6jztVo+fgYO+TmSRd3ToJwKMtdws0B/J3scbEek8+3J9XdMmMMyfztWUApVnfDE8FXzs fC6as6fBdMPabRi4fI0VtR5EJPguVz+6chQJYPsPEEnoATn595glI+d19X9yF5Nd8G66 xt3A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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Thu, 18 Oct 2018 15:18:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FADA1596; Thu, 18 Oct 2018 06:21:29 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C79B93F59C; Thu, 18 Oct 2018 06:21:28 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:59 +0100 Message-Id: <20181018132109.31192-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 12/22] xen/arm: Only include stringify.h when necessary X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/arm32/sysregs.h | 1 + xen/include/asm-arm/arm64/processor.h | 2 -- xen/include/asm-arm/cpregs.h | 2 -- 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/xen/include/asm-arm/arm32/sysregs.h b/xen/include/asm-arm/arm32/sysregs.h index b25b59a557..25cdcbfa4e 100644 --- a/xen/include/asm-arm/arm32/sysregs.h +++ b/xen/include/asm-arm/arm32/sysregs.h @@ -1,6 +1,7 @@ #ifndef __ASM_ARM_ARM32_SYSREGS_H #define __ASM_ARM_ARM32_SYSREGS_H +#include #include /* Layout as used in assembly, with src/dest registers mixed in */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index 765de1b74b..81dfc5e615 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_ARM64_PROCESSOR_H #define __ASM_ARM_ARM64_PROCESSOR_H -#include - #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 07e5791983..97a3c6f1c1 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H -#include - /* * AArch32 Co-processor registers. * From patchwork Thu Oct 18 13:21:00 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id x1-v6si8207513ywg.307.2018.10.18.06.23.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F2-000385-VL; Thu, 18 Oct 2018 13:21:32 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F1-00036l-OK for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:31 +0000 X-Inumbo-ID: 565643d8-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 565643d8-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94A21341; Thu, 18 Oct 2018 06:21:30 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CCD5C3F59C; Thu, 18 Oct 2018 06:21:29 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:00 +0100 Message-Id: <20181018132109.31192-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 13/22] xen/arm: Only include vreg.h when necessary X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/vgic-v2.c | 1 + xen/arch/arm/vgic-v3-its.c | 1 + xen/arch/arm/vpl011.c | 1 + xen/include/asm-arm/vgic.h | 1 - xen/include/asm-arm/vpl011.h | 1 - 5 files changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index f6c11f1e41..8526f9be04 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -31,6 +31,7 @@ #include #include #include +#include static struct { bool enabled; diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 9edd97c4e7..5b73c4ecd7 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -45,6 +45,7 @@ #include #include #include +#include /* * Data structure to describe a virtual ITS. diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index a281eabd7e..117e41c760 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -33,6 +33,7 @@ #include #include #include +#include /* * Since pl011 registers are 32-bit registers, all registers diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 374fdaa40d..760392f9ef 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -27,7 +27,6 @@ #include #include #include -#include struct pending_irq { diff --git a/xen/include/asm-arm/vpl011.h b/xen/include/asm-arm/vpl011.h index db95ff822f..a82869a53c 100644 --- a/xen/include/asm-arm/vpl011.h +++ b/xen/include/asm-arm/vpl011.h @@ -21,7 +21,6 @@ #include #include -#include #include /* helper macros */ From patchwork Thu Oct 18 13:21:01 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id 195-v6si8062949ybf.347.2018.10.18.06.23.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F4-0003Ac-Dm; Thu, 18 Oct 2018 13:21:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F2-00037x-UC for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:32 +0000 X-Inumbo-ID: ed488d23-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ed488d23-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:57 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A2E4C15BE; Thu, 18 Oct 2018 06:21:31 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D1D303F59C; Thu, 18 Oct 2018 06:21:30 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:01 +0100 Message-Id: <20181018132109.31192-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 14/22] xen/arm: Remove unnecessary includes in asm/vgic.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/vgic.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 760392f9ef..0316d87f66 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -22,11 +22,8 @@ #include #else -#include #include #include -#include -#include struct pending_irq { From patchwork Thu Oct 18 13:21:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149129 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972540lji; Thu, 18 Oct 2018 06:23:18 -0700 (PDT) X-Google-Smtp-Source: ACcGV627tRnmHzfGE3xTMCm3nYVdOpvKWq7h40ETmCYDq6aNHmmsGi4l8q3QcRtVaodFQkGlwm9d X-Received: by 2002:a81:1d42:: with SMTP id d63-v6mr19026279ywd.463.1539868998755; Thu, 18 Oct 2018 06:23:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868998; cv=none; d=google.com; s=arc-20160816; b=CwPOjT2l8A0QpNMuMH+jSXe7R8gqAKDXNLk3Ya1sQkU0zzfvvJ0ljVnuPsbeS74n+z OWRKmCKfdPBtpatVVtY+h0PAvUDFMD2+AcNNrJQ7uM7eOMsSv/LMSOCO8M7A33VupIzR yr2ufeInsANyWt1QEV2J+XyW9VeTEJy2zpXIN1Ebw6Mg9vpadWtlX5AUmhzTMjwfiixe RWAN03YoFcrRCEKHJVsByEIrvgtmFlfhsnt6m3xNZIx4GL/tp0pU0HDmm8VUIS08f7Eq QYSYgAxfpYx+6TFGNoOxjS/qp+qgMeHCqzP84DeEMKLb76jq1+cmIgtCsxv5h0BSgKgJ Sdkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=qZvdeS2i98JcyYHwem3ainUJLe4y3ZEYBNWBO6JrlJs=; b=qg6muhfFQuzvd/oMMtuZqLPDP9aUCiMcOe3uKxpdDKvDqpuxtR4qzEqilCdMusxt7P A5pABqnOrtkeqm6YsBHbaDEk2dSaML0lAsg4xiYEirQNE7fpaiHWz6gAqbjTGiBZ/1/P I4o6CqMIeRkf32/anHS2cqpF38q77tXEt+aI6BDTxsXvDwEnVrQqfpx3bQHylndmy3MV kSV8oi3MZrWE8jBzbWTOm3WzI+NziyENA5U6vaxisYearQQofUMf2oetUjkL/p5GqnG8 gJHTZ2P6mkTgPc39eBRSyofqt9su9H+OMSBlkU6yCspA77eVg3CNueTDs+/g++JQyR1b WjKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r7-v6si7739644ywd.74.2018.10.18.06.23.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F5-0003CS-Sh; Thu, 18 Oct 2018 13:21:35 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F4-0003AH-9l for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:34 +0000 X-Inumbo-ID: 57a9b428-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 57a9b428-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:46 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0797341; Thu, 18 Oct 2018 06:21:32 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DFFCE3F59C; Thu, 18 Oct 2018 06:21:31 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:02 +0100 Message-Id: <20181018132109.31192-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 15/22] xen/arm: Remove unnecessary includes in asm/mmio.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/mmio.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/xen/include/asm-arm/mmio.h b/xen/include/asm-arm/mmio.h index 3ed3f82bf7..8dbfb27682 100644 --- a/xen/include/asm-arm/mmio.h +++ b/xen/include/asm-arm/mmio.h @@ -23,8 +23,6 @@ #include #include -#include -#include #define MAX_IO_HANDLER 16 From patchwork Thu Oct 18 13:21:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149124 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972360lji; Thu, 18 Oct 2018 06:23:10 -0700 (PDT) X-Google-Smtp-Source: ACcGV63QzeDsEAsGC3j0c+hWputfHIqqnTyHSYyq4aj3GpdjLHvdzl2Q7mu16jtmixVzHUvaefe3 X-Received: by 2002:a0d:fbc2:: with SMTP id l185-v6mr15456542ywf.446.1539868990780; Thu, 18 Oct 2018 06:23:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868990; cv=none; d=google.com; s=arc-20160816; b=afnKsS9hPrALW71pJNobX5JNeDduxfZisyiLYJX9gQUsZm/1oppDuS8seCi6HN8a6R n7R6QBQznFZPK9zZUNpvzzV+WhPjjrPIdW4/6h5dEKNQJzJl1WpkdGHGXiR3VzVNtNaz S/ggsVZAp0jL5p+vbqPNWaZaKXkLp9MpKEAYp7GaIRwRKU/5xqV/E6AwZQEZcshwgmU9 k4HZvxXjwMaO0GG4+gPofwfcVe5JmP0Via2phxgyBFRZHTjWI88tMA29S+txSc0RVTQz hGXqt2VCHlhVo30CQn1lGF15qdlu/rz0aJhMlUT0Y60+1r4i75rXpTuk378ncdJII24+ MDow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=qkw5qDkX+dMYFFSPzvoqGydpnl0p6yC/ejAEKtmImIg=; b=clpEekggcw8yTzkRG8hzruCb9dY1DzRhNxzX36MpkPVM0ov1r+XpJS4r8l82p8xGLA Z1b4EPHKgHQTl8hSJhLHwItQnN5zrL0fTYxltOwEDdhRUXJxMqJMP51bn5V/usZAyG0O 6I9QKpI3mOyxOskR23sGoDl8FNGirmYE6LbaYPbI1o3Pmb1hpMcvVt97OQRk0kAYYump kwgak7qciAP0/70dBIYj1vH9mfTe3ESYvrfUI/t8bY2yDBB/Sft9sb44OMDibBqPIMVr XSHUkB6gVx5xHoVeypqFDEPoZ8dONnKgF0VSCe3V5h4YNTRl+mqNgnWr0dI7Vw3HwwP+ 2nAA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i8-v6si7547879ybk.356.2018.10.18.06.23.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F6-0003Di-Mc; Thu, 18 Oct 2018 13:21:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F5-0003Bg-8f for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:35 +0000 X-Inumbo-ID: ee7987df-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ee7987df-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:59 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B56601596; Thu, 18 Oct 2018 06:21:33 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ED9333F59C; Thu, 18 Oct 2018 06:21:32 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:03 +0100 Message-Id: <20181018132109.31192-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 16/22] xen/arm: Remove unnecessary includes in traps.c X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Also, include smccc.h instead of psci.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/traps.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0dd664cc08..9c3be17df8 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -42,12 +42,10 @@ #include #include #include -#include #include #include -#include -#include #include +#include #include #include #include From patchwork Thu Oct 18 13:21:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149126 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972400lji; Thu, 18 Oct 2018 06:23:12 -0700 (PDT) X-Google-Smtp-Source: ACcGV63fBON9+dSOPWidql4W0NxioaHdT33tZQiJOEHYX6/05FEyfi4yG6FKNF3r6L0foI60YlFI X-Received: by 2002:a25:8288:: with SMTP id r8-v6mr13530382ybk.370.1539868992619; Thu, 18 Oct 2018 06:23:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868992; cv=none; d=google.com; s=arc-20160816; b=VM9r40kd14HsLpDhrSTO3BLNqcsoqp/qC3m9y2f3QC2dxG5KDIwhrAO7rgtXf+xZaA pNtw9Bwb8TXLW6u5ECYGD+6XegCUl3YPZWUvRZH1krNKs2J2zCBRQkxbZlkA2sKT4Qt3 9XtxROM+zES8hvvW7sqMinwEPH8zsU1jKACFJc6Tvmn6j2yO5/YWqNZcSrFjhKOhgNx1 ed7wZD2FoKRjvB8SgRs471zNlhItT95afOPj2y+eSSPmEv1B03uOKR2Bk5cY/v84POq0 5WSREIEgHiQcm9rPe+4TVlpR8SNusWE0PIhQmood3WRuU5ZN5t1viBsVbWN4nOAjdrTv 521Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Wp7Z9ufWa38kXXA2nf7PUMQ2HC0TuXQtiIWkRkyZBxg=; b=PgiIZo+9TinryWJd38+r4D49mjiIhM5ccgdaXSvOLhjzyRa2Uc7GMaESr2HvRyY1I4 cm08j2JqWzIE2nM7dEnjAYmFvMwYXkfZrW8b7wonoXx4cWMQdyI6TXZzZw6yA4ojifKS aPqizZt3HxHBiyHXnzCM3yYqa8mlMicpfbFXkQn7Ur43cS0e25f/D+4gShZSRKjUWlIJ J0QYllsegBhfQwAELbhJNEJ/L43q4fb2EhDRHAAslc8HKWKPEIgyy44fhEypCFnqyoWg 0x2nz5LDX/T5Ebm/IS/MjEdSv6/D2aG6h0K496zrP6xVhw7TACKlJbwQ7IVHT17GojB9 E4Ag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id j66-v6si8075170ywe.442.2018.10.18.06.23.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F8-0003Gk-Dz; Thu, 18 Oct 2018 13:21:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F6-0003DJ-GQ for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:36 +0000 X-Inumbo-ID: ef1ef16b-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ef1ef16b-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:23:00 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C3001341; Thu, 18 Oct 2018 06:21:34 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F2B0E3F59C; Thu, 18 Oct 2018 06:21:33 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:04 +0100 Message-Id: <20181018132109.31192-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 17/22] xen/arm: Remove unnecessary includes in asm/p2m.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/p2m.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index c03557544a..be58125fb7 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -5,10 +5,7 @@ #include #include #include -#include /* for vm_event_response_t */ -#include #include -#include #define paddr_bits PADDR_BITS From patchwork Thu Oct 18 13:21:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149122 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972332lji; Thu, 18 Oct 2018 06:23:09 -0700 (PDT) X-Google-Smtp-Source: ACcGV61/wadC4eZrZGm7MPO8YybihIqYlul+veWR4fCTkuPJYIGCmuSqSwRz8elL0jVTkWGThuXU X-Received: by 2002:a81:130c:: with SMTP id 12-v6mr18652211ywt.340.1539868989488; Thu, 18 Oct 2018 06:23:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868989; cv=none; d=google.com; s=arc-20160816; b=gVdR597qKT9BMGRJqQZn1VCy12Y5VcRReDYRYzBwf4moZRO4popw0YIIEsBdPUSFsa b+tKYR3MiQ3jIRCql0MHHUysx3J2u9DHw6H9tJtx7/Rkdb8rzgJy7/z6E3zM9UgObOWO Pm9/1RH1OyPh8XRCi1mDzOZcG98fp/eCbapZVhxOUjTwBH/rSJqvycvEwpd0bswYUybM mx/ajgUECmPjVEDUoAqztNT8Nr3JWmkU3KN4OQ1B1WnpsB+W1Dz6XGj3YNs0FwgPCvZT 6EjtAVVxKu/iWIqijqLwG+GbeUI8aRpF3MhLtEwvTp7fMDPg0jzOHN4Igv/qZzGpwvLm iHsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=x1yYsTYMP7VUBA++mOIRttFToiFwFAV4mBtrLsfpQB0=; b=qGXj7YY4AD1MgT/9IewjhB3L16LKxiKZuHWCdC2vG3jCV6JlBYk/pyM7ADEFlc1ZvK fwhrmz34OCzV0ZOT0/t2mCQ5E8iHdw535zupq9oS8Fn4NrOX5TViuNzE//u7z6EVI4Bt 48xVXdDet+Nc22prHJX6lrdJ/lt/sLU7CKIyneNwJ1GC87KwdIYe9lQ5V4DGQfAzVQJA hPCGCLxqLWJA+ajwxQRu2Gb2zHySDI9t7muIcYKnJJcCuoeTzwtj7UOyeUbJr93zFGHW P79XnxxK3K/tuARR6zcYQIILa+fM8gAf0JGqbJzLNCNgKEeoWL/blyK4LHRPXJG639fw i9IA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h190-v6si8116865yba.238.2018.10.18.06.23.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F8-0003HZ-U0; Thu, 18 Oct 2018 13:21:38 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F7-0003Ej-9s for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:37 +0000 X-Inumbo-ID: 597526b3-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 597526b3-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:49 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0F2B1596; Thu, 18 Oct 2018 06:21:35 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C1BC3F59C; Thu, 18 Oct 2018 06:21:34 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:05 +0100 Message-Id: <20181018132109.31192-19-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 18/22] xen/arm: Remove unnecessary includes in asm-arm/acpi.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/acpi.h | 1 - 1 file changed, 1 deletion(-) diff --git a/xen/include/asm-arm/acpi.h b/xen/include/asm-arm/acpi.h index feec4fb0ac..50340281a9 100644 --- a/xen/include/asm-arm/acpi.h +++ b/xen/include/asm-arm/acpi.h @@ -23,7 +23,6 @@ #ifndef _ASM_ARM_ACPI_H #define _ASM_ARM_ACPI_H -#include #include #define COMPILER_DEPENDENT_INT64 long long From patchwork Thu Oct 18 13:21:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149123 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972359lji; Thu, 18 Oct 2018 06:23:10 -0700 (PDT) X-Google-Smtp-Source: ACcGV612L8LO4HGgrNE30NCO78fbbqzxNbwf19nNlvwz358fePKRoIkMejqd0x1r+o8BMzH13cBV X-Received: by 2002:a25:1841:: with SMTP id 62-v6mr18073515yby.271.1539868990647; Thu, 18 Oct 2018 06:23:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868990; cv=none; d=google.com; s=arc-20160816; b=zFyrPu9oL7sY5G+a1UK72qn7Cx53NDflGYwAiGJbhXGkTa303S+TVx96v9jJ3LDD9I al3NJy+5DxJrFRBD1LWa/xIImW9QEatsfVpop3FArC8mzvZEEh2z6r767eaGCldFopgF Y7GoDcVWwTxsZ0BEHpGghw9zKRm5b6P4VXWsrFa0hiI2eh05PzNDxuPrtOiM5aM1e3wG iaUc4qR7pwsWS+nYBjdN+ITTIEbfmLX0qSuv2PjMck6UZrQJYTZdeK0xl1D0WlJtBeBX WU1lLGNuaUFhsbE87JJgPuwaEYHbuIL820wKZwWlNvlUCtiz8pWCgJVv3IgVMyI0tFXF bLTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=9a0WOzC30IcEqCxer2V7xye7+h+SKVXJFywDifbNkuw=; b=y3XGf98rmHYQtz7ZQNh6IyO41EICw9WYawyunN91DZ1mLUExYBbwn4eBJmKS5RzID9 4Qbm9Y+TeeRjiPo+pGJ8qy5vminaAGY0IRUly7UMCn3MxN2WxQOJcpM+HKlMT3K+aRIV iMVaYFAYFwXzIARuTlcF4LYvmtAtfx75V0WFRN+NAeysSkfBi5qFnQoy5bqgYF/mcbhI G9QFsTwQ0DHs72X1UL5KKROFI2ejiczpuD4YOwWkFM+Dxy+JDZyRFGjtcD8ILpetGdrZ o4Zdc61SMwPVRkSlwlirNdHlY4LyOfreN7CKAnQeCVNyUJ7N6ik5QOW6MQFqtx2ihYPf gdZw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id k21-v6si7845947ywa.258.2018.10.18.06.23.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F9-0003Il-Gp; Thu, 18 Oct 2018 13:21:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F7-0003Fp-RX for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:37 +0000 X-Inumbo-ID: f0571b81-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id f0571b81-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:23:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF7B8341; Thu, 18 Oct 2018 06:21:36 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A79B3F59C; Thu, 18 Oct 2018 06:21:35 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:06 +0100 Message-Id: <20181018132109.31192-20-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 19/22] xen/arm: Remove unnecessary include in asm-arm/atomic.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/atomic.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/xen/include/asm-arm/atomic.h b/xen/include/asm-arm/atomic.h index 50f2835e35..263e8c3b6c 100644 --- a/xen/include/asm-arm/atomic.h +++ b/xen/include/asm-arm/atomic.h @@ -2,8 +2,6 @@ #define __ARCH_ARM_ATOMIC__ #include -#include -#include #define build_atomic_read(name, size, width, type, reg)\ static inline type name(const volatile type *addr) \ From patchwork Thu Oct 18 13:21:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149125 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972415lji; Thu, 18 Oct 2018 06:23:13 -0700 (PDT) X-Google-Smtp-Source: ACcGV62SVkhsAacUOweFw/JTlfmW2pgApaI+u/WZvEXSTCvu1F2Cb2IHzmTs5r5ZJdz8A+MzD8Pd X-Received: by 2002:a81:1f86:: with SMTP id f128-v6mr18330813ywf.395.1539868993341; Thu, 18 Oct 2018 06:23:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868993; cv=none; d=google.com; s=arc-20160816; b=Aq3F/KxPlrlhxsG7O4qk9D8XnfMSTrvKblsU5TqYdNMo9ZZkrDTwl5IDqqSIX0dIU+ w0ftU47RALmH9/y16+jTeZBJTgU2Affqd4Xxj8rEEbqT+DxPzuDoquMSd3zGczdT/fJy snFaNaHoRNnbeMEp8/4MFmu3n7eKBPwd5A/jBlm3AGVKT2fNlWrG7sBYY+BQHRGcVGMo g8+E29+f2edlhzPFdLtyTULl6+hihtnGVbJLNqUdIwM6jBP67NPvrAfRom7Dv1ig/0wO 23d0XkDxVCYgJBajgl/qCr5WVt76h7BYwQYXt18bEhKobgQ49BPFlTZI9DGcB+NTyNfc dSkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=sgsLrgq9JwEI1GVBkPt85GCaywUXko7rlXTEZiB6MZA=; b=X4wJY6kFcJ6Rz+p2B7FY8BqwOEVzKZWooRSMb7ig8neEdT19gIucz2V94aFpYs1CcN CI4yOOzWyyea9t2a8GIRhKobm6HBATp3MOY+uyhVawCfRI4wztUc7HfwCcOEYjF2cTh4 AUGVwBUpx5qB2dHJwjstv/cKCllSMMcUuSmyC9hU2z/S2dBO4REAnTQhm7mJXugRnfpv SCjy+faJ36G5zldKBpXCWp01w5Yw3Hi5WpNC+kPrQOqL88cagAJJYfXPETl/kn82vzNB i6c01E9HUJGPpYgxvXj6lhO7wy6xbdMn+bwQsh/EnQrw3AV2VcasIFtzA7YkNMR41nfY D3DA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r74-v6si7522675ywg.157.2018.10.18.06.23.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8FB-0003Lu-5Y; Thu, 18 Oct 2018 13:21:41 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F9-0003Io-Jt for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:39 +0000 X-Inumbo-ID: 5ab7e69e-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 5ab7e69e-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:51 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ED1A21596; Thu, 18 Oct 2018 06:21:37 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2893E3F59C; Thu, 18 Oct 2018 06:21:37 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:07 +0100 Message-Id: <20181018132109.31192-21-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 20/22] xen/arm: Remove unnecessary includes in asm/current.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/current.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/xen/include/asm-arm/current.h b/xen/include/asm-arm/current.h index f9819b34fc..c4af66fbb9 100644 --- a/xen/include/asm-arm/current.h +++ b/xen/include/asm-arm/current.h @@ -2,9 +2,7 @@ #define __ARM_CURRENT_H__ #include -#include -#include #include /* Tell whether the guest vCPU enabled Workaround 2 (i.e variant 4) */ From patchwork Thu Oct 18 13:21:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149128 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972448lji; Thu, 18 Oct 2018 06:23:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV63UTcRoC9nkSJ0T+Trht6a5heQvpRJcihDGIg59lqoLqdR7/1hY0tCgmeSH0pIkrdzA8KZE X-Received: by 2002:a25:38c3:: with SMTP id f186-v6mr18654580yba.289.1539868994862; Thu, 18 Oct 2018 06:23:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868994; cv=none; d=google.com; s=arc-20160816; b=e78oL7D3jptjg9fDjTfBBlKijRiVBIQvWhHyo96PXkak82Yj9Nq+RrUxKZV6ZVx4BN v6g4GnpNSgdstcFm2Nm1TwVzuMDjhFyjmOtb0A08l18BluIxoCWxmQ2IO43cxTiZNRZL 24fi91Ls8YiwFRPDt4YAJ6ECvYf3NdBsO7g/SjLS0vB9qB+h7W1AvEuOaTCwKzhIZWGA /BiN30m1JLwfSzdj1mZnIgsUWgq4KwfrsVr6zU73IpxdlOun0EJFZ0QMT+fgS5rxZvzK yNX1wW7M8RSWt0hSafciuQBDD+wJFPMsmnb72Yvmhxv0fx/xrfBjh6iKjAYC+UQVpwrR byjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=fleRsS/lK5iyvvQ86Wxm9FrcFgZLbAB2SYaWnn79nLI=; b=Jb37zNSaziwRONRcZm9SQp5lqHi74+3lOr4V3GkIAfj9dpEJGA17Stwkwk34Vyof1x qVWiUCPhq53I7yhna+sPj6U2ONlyhDPX0odI1Pbr7JYLVFfyR00D6Jo2c1vY5Y1gQDlX /dYkASWe+P8xoxJzlmVk+0ut3auq8eEVmQ+60Rm7TT1qfpAq/Oo9fNDLbU3t2rYJPa/D 6A8d1anV4AIL3kGK/J6KVYgnAno6XtCGAXEGRJvKY9k8xkyZo54x+OtcgXjqtxNbI82f 5wILZpHy1uyoOaYdXYVj7E8QtNrnIZs0ZPpHCehGky3qeWfOgVnXtIC/qNfhVqlwzuW9 mRNQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s2-v6si8306349ywa.453.2018.10.18.06.23.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8FB-0003Nl-Qh; Thu, 18 Oct 2018 13:21:41 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F9-0003JZ-VB for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:39 +0000 X-Inumbo-ID: f19456f0-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id f19456f0-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:23:04 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F28F3341; Thu, 18 Oct 2018 06:21:38 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3647E3F59C; Thu, 18 Oct 2018 06:21:38 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:08 +0100 Message-Id: <20181018132109.31192-22-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 21/22] xen/arm: platform: Don't include p2m.h in exynos5 and omap5 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" None of the platforms are using the p2m helpers. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/platforms/exynos5.c | 1 - xen/arch/arm/platforms/omap5.c | 1 - 2 files changed, 2 deletions(-) diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index e2c0b7b878..6560507092 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c index 7dbba95756..aee24e4d28 100644 --- a/xen/arch/arm/platforms/omap5.c +++ b/xen/arch/arm/platforms/omap5.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From patchwork Thu Oct 18 13:21:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149127 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972444lji; Thu, 18 Oct 2018 06:23:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV62FuLEpjF4So8468NJWGne5yTIJ4B63UMnLUtyvJNTmlElpge9w3GUBj3s4m4sAiS63nosA X-Received: by 2002:a25:4c83:: with SMTP id z125-v6mr10186079yba.491.1539868994720; Thu, 18 Oct 2018 06:23:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539868994; cv=none; d=google.com; s=arc-20160816; b=qh+aNLF0txE0X3Ckww6XUYnKkwWasy4bQ4UuZpBO/3bq8NmxD4oNw4R9uWHfU3A385 zmll1RFtZmMjB3856gztiDPEn6V0CpSutsg+WmHVhKvFN+KOHeDd1MHC4kwgQzYIjIws XmFnt8WFJUqYm5zmGb72uMA002qF5hcodxLSKj/iLF999P2Ra6xZO5e5ZHyjRS1Cwhmq 8AAdEltWUCRoO+MxOL0z9ZD8xpV4yJpbqdTqZaIeKT0q0M6mTfY9uank3oalTrJGSaU5 okFEVTTNRVT0rBn4k/QHSZFZ9xaGf4mgcgZEcZUVhkwO/SBgvahDSGzc2NvP6UfcgbG9 d+yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=W+Kx+/SWlp72fXlvHmfY+dIW8sgh8vx3EHnowfaBEHE=; b=z73QMidIkKwW3Xb2Dr/cLc1XXi6FHNycOhQX0cOslcrqlTakyCqGu5++6KbrSL+88N u9Uzglu45kYGm9EuMbnEoZieW0EDIrh4/IwVT/MfUuPGKVbIiQBfh+KsKOs5z8TvfMDR ofyDjqtGs3ZXd1wGo3MkHGJMvjd4Yl5tBj+8L3STol8hs2qYXCzGisfPLFhGpKBIrHNS jKc5x3l+peH4V71kJZbylnF8JW0p+U1BgimxqLwmLn+P5ujhT7uxVfNwoJeh0pWKFEHC 78QpeS8Oy1vPXcF5SSDraVdvBjuXy/Ei17snqdHgAegEhNDbidI4NJJUdHTk/rI1c6oj J9VQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id u11-v6si8411060ywl.64.2018.10.18.06.23.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8FC-0003PW-Sk; Thu, 18 Oct 2018 13:21:42 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8FA-0003LE-SR for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:40 +0000 X-Inumbo-ID: 5c062beb-d2d8-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 5c062beb-d2d8-11e8-a8a5-bc764e045a96; Thu, 18 Oct 2018 15:18:53 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 034BF1596; Thu, 18 Oct 2018 06:21:40 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BB4B3F59C; Thu, 18 Oct 2018 06:21:39 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:21:09 +0100 Message-Id: <20181018132109.31192-23-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 22/22] xen/arm: Move vgic_* helpers from gic.h to vgic.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Keep vgic_* helpers in a single place. At the same time remove gic.h from event.h since the helpers has now been moved to vgic.h (included by domain.h). Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/include/asm-arm/event.h | 1 - xen/include/asm-arm/gic.h | 3 --- xen/include/asm-arm/vgic.h | 5 +++++ 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index 2f51864043..b14c166ad6 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -1,7 +1,6 @@ #ifndef __ASM_EVENT_H__ #define __ASM_EVENT_H__ -#include #include void vcpu_kick(struct vcpu *v); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 22fa122e52..fab02f19f7 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -249,9 +249,7 @@ extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc); -extern void vgic_sync_to_lrs(void); extern void gic_clear_pending_irqs(struct vcpu *v); -extern int vgic_vcpu_pending_irq(struct vcpu *v); extern void init_maintenance_interrupt(void); extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq, @@ -306,7 +304,6 @@ extern unsigned int gic_number_lines(void); /* IRQ translation function for the device tree */ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type); -void vgic_sync_from_lrs(struct vcpu *v); struct gic_info { /* GIC version */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 0316d87f66..56ed5fe8fe 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -363,6 +363,11 @@ void vgic_v3_setup_hw(paddr_t dbase, unsigned int intid_bits); #endif +void vgic_sync_to_lrs(void); +void vgic_sync_from_lrs(struct vcpu *v); + +int vgic_vcpu_pending_irq(struct vcpu *v); + #endif /* __ASM_ARM_VGIC_H__ */ /*