From patchwork Fri Sep 3 23:24:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B44C433FE for ; Fri, 3 Sep 2021 23:24:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1DD5F60F42 for ; Fri, 3 Sep 2021 23:24:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350749AbhICXZ1 (ORCPT ); Fri, 3 Sep 2021 19:25:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350743AbhICXZ1 (ORCPT ); Fri, 3 Sep 2021 19:25:27 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79F0EC061757 for ; Fri, 3 Sep 2021 16:24:26 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id bq28so1327559lfb.7 for ; Fri, 03 Sep 2021 16:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R7uqxjyuLB/A9uxzpuHWctMI9qhXQKpKHnTYkEcX53s=; b=WI36iCTCyFBYI3TbxIuHLUBoZJnJtSghjlixiZs9/sOx3lYK22LgArqHK6GW+vteqJ xfypvXX6PwQnH0ET8TPLDXhYoQqdk+X9hcXwHGWgLyWXqSVZESmNZnPRpCRnDxQCQ8Ra I6gl97htfmXfOYYzjBJjpzsju6XcyUbg6rpXLz5YtmyuPZ/jEgOJozflKOElcyh70m3W MTcTzX0WGNoEPq+A3O4BzeHtK7a7NbPhT0V+PLKWEwvNP+AMCFQaF1g4ueKxOcGM1AYw Msmcpz6fJAk18palYN3pl2aWCTKlS6BjDei27ljJ95rEJ2N97fDo7weQmQbnEiAFb4PL wQtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R7uqxjyuLB/A9uxzpuHWctMI9qhXQKpKHnTYkEcX53s=; b=EuNH2E/SCWbF+TzrfivyPEX9XW3/hFE/ptI0qMF1ubCybSTFK+p5QrKgomgZQ98WbJ n2RbRqpQwkITWhYVs9z7LKlwB8HyVouLLcysdBwdMn7Y5D5teX6NzGLVbmE/S4AXpIAD qdqd9OVMs9I9xlcNX5KOlufZPvmNWejl4adDoZnOSYleBjz8vyAg2qjxq082AA3LOk5+ 8MhWsUlJKe0GB/v2IWLCKijG75KUUAX+4Sq8Ug52lZqI/IA09dA7Ep2HrmsAVVkX7vbe ucie5lqJt9T9BNIULbp1uTYwzi2wnbzkTzNJJarMYI6d6e/wkom9ZYS9aEQP6LY6zht/ lb7A== X-Gm-Message-State: AOAM532IhYZC7NeQ/UeCyE4cqoKkzbuYUYO7IulWQIaPpMKtLJtLvnpM bQ7+mPULBv8BmcOOx2AFgmgiIw== X-Google-Smtp-Source: ABdhPJx44XaDz7pE+2cD6TLlvDh3L5gFR8mqPzqFJ6IWl5Hl0h9mwgT+/SvWr/3haU1GYTSQ9b6/sg== X-Received: by 2002:a05:6512:130f:: with SMTP id x15mr948006lfu.571.1630711464776; Fri, 03 Sep 2021 16:24:24 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:24 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 01/11] interconnect: icc-rpm: move bus clocks handling into qnoc_probe Date: Sat, 4 Sep 2021 02:24:11 +0300 Message-Id: <20210903232421.1384199-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All icc-rpm drivers use the same set of bus clocks. Move handling of bus clocks to qnoc_probe. This both simplifies the code and allows using qnoc_probe as device's probe funcion. Signed-off-by: Dmitry Baryshkov Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten --- drivers/interconnect/qcom/icc-rpm.c | 22 ++++++++++++++-------- drivers/interconnect/qcom/icc-rpm.h | 5 ++--- drivers/interconnect/qcom/msm8916.c | 13 +------------ drivers/interconnect/qcom/msm8939.c | 13 +------------ drivers/interconnect/qcom/qcs404.c | 13 +------------ 5 files changed, 19 insertions(+), 47 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 54de49ca7808..394f515cc88d 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -86,8 +86,11 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) return 0; } -int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, - const struct clk_bulk_data *cd) +static const char * const bus_clocks[] = { + "bus", "bus_a", +}; + +int qnoc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct qcom_icc_desc *desc; @@ -97,6 +100,8 @@ int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; + const char * const * cds; + int cd_num; int ret; /* wait for the RPM proxy */ @@ -110,7 +115,10 @@ int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, qnodes = desc->nodes; num_nodes = desc->num_nodes; - qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); + cds = bus_clocks; + cd_num = ARRAY_SIZE(bus_clocks); + + qp = devm_kzalloc(dev, struct_size(qp, bus_clks, cd_num), GFP_KERNEL); if (!qp) return -ENOMEM; @@ -119,12 +127,10 @@ int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, if (!data) return -ENOMEM; - qp->bus_clks = devm_kmemdup(dev, cd, cd_size, - GFP_KERNEL); - if (!qp->bus_clks) - return -ENOMEM; - + for (i = 0; i < cd_num; i++) + qp->bus_clks[i].id = cds[i]; qp->num_clks = cd_num; + ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); if (ret) return ret; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 79a6f68249c1..f4b05c20c097 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -22,8 +22,8 @@ */ struct qcom_icc_provider { struct icc_provider provider; - struct clk_bulk_data *bus_clks; int num_clks; + struct clk_bulk_data bus_clks[]; }; /** @@ -66,8 +66,7 @@ struct qcom_icc_desc { } -int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, - const struct clk_bulk_data *cd); +int qnoc_probe(struct platform_device *pdev); int qnoc_remove(struct platform_device *pdev); #endif diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index fc3689c8947a..fc0d48d2997a 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -105,11 +105,6 @@ enum { MSM8916_SNOC_PNOC_SLV, }; -static const struct clk_bulk_data msm8916_bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, -}; - DEFINE_QNODE(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 8, -1, -1, MSM8916_BIMC_SNOC_SLV); DEFINE_QNODE(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1); DEFINE_QNODE(mas_apss, MSM8916_MASTER_AMPSS_M0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); @@ -305,12 +300,6 @@ static struct qcom_icc_desc msm8916_pcnoc = { .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), }; -static int msm8916_qnoc_probe(struct platform_device *pdev) -{ - return qnoc_probe(pdev, sizeof(msm8916_bus_clocks), - ARRAY_SIZE(msm8916_bus_clocks), msm8916_bus_clocks); -} - static const struct of_device_id msm8916_noc_of_match[] = { { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc }, { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc }, @@ -320,7 +309,7 @@ static const struct of_device_id msm8916_noc_of_match[] = { MODULE_DEVICE_TABLE(of, msm8916_noc_of_match); static struct platform_driver msm8916_noc_driver = { - .probe = msm8916_qnoc_probe, + .probe = qnoc_probe, .remove = qnoc_remove, .driver = { .name = "qnoc-msm8916", diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 20f31a1b4192..4a5a2ec64960 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -110,11 +110,6 @@ enum { MSM8939_SNOC_PNOC_SLV, }; -static const struct clk_bulk_data msm8939_bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, -}; - DEFINE_QNODE(bimc_snoc_mas, MSM8939_BIMC_SNOC_MAS, 8, -1, -1, MSM8939_BIMC_SNOC_SLV); DEFINE_QNODE(bimc_snoc_slv, MSM8939_BIMC_SNOC_SLV, 16, -1, 2, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_1); DEFINE_QNODE(mas_apss, MSM8939_MASTER_AMPSS_M0, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); @@ -326,12 +321,6 @@ static struct qcom_icc_desc msm8939_pcnoc = { .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), }; -static int msm8939_qnoc_probe(struct platform_device *pdev) -{ - return qnoc_probe(pdev, sizeof(msm8939_bus_clocks), - ARRAY_SIZE(msm8939_bus_clocks), msm8939_bus_clocks); -} - static const struct of_device_id msm8939_noc_of_match[] = { { .compatible = "qcom,msm8939-bimc", .data = &msm8939_bimc }, { .compatible = "qcom,msm8939-pcnoc", .data = &msm8939_pcnoc }, @@ -342,7 +331,7 @@ static const struct of_device_id msm8939_noc_of_match[] = { MODULE_DEVICE_TABLE(of, msm8939_noc_of_match); static struct platform_driver msm8939_noc_driver = { - .probe = msm8939_qnoc_probe, + .probe = qnoc_probe, .remove = qnoc_remove, .driver = { .name = "qnoc-msm8939", diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 36a7e30a00be..0f2fff230b13 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -92,11 +92,6 @@ enum { QCS404_SLAVE_LPASS, }; -static const struct clk_bulk_data qcs404_bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, -}; - DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); @@ -269,12 +264,6 @@ static struct qcom_icc_desc qcs404_snoc = { }; -static int qcs404_qnoc_probe(struct platform_device *pdev) -{ - return qnoc_probe(pdev, sizeof(qcs404_bus_clocks), - ARRAY_SIZE(qcs404_bus_clocks), qcs404_bus_clocks); -} - static const struct of_device_id qcs404_noc_of_match[] = { { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc }, { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc }, @@ -284,7 +273,7 @@ static const struct of_device_id qcs404_noc_of_match[] = { MODULE_DEVICE_TABLE(of, qcs404_noc_of_match); static struct platform_driver qcs404_noc_driver = { - .probe = qcs404_qnoc_probe, + .probe = qnoc_probe, .remove = qnoc_remove, .driver = { .name = "qnoc-qcs404", From patchwork Fri Sep 3 23:24:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 507063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D061BC433FE for ; Fri, 3 Sep 2021 23:24:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC901610E6 for ; Fri, 3 Sep 2021 23:24:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350743AbhICXZ3 (ORCPT ); Fri, 3 Sep 2021 19:25:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350752AbhICXZ2 (ORCPT ); Fri, 3 Sep 2021 19:25:28 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B1B7C061575 for ; Fri, 3 Sep 2021 16:24:27 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id x27so1347096lfu.5 for ; Fri, 03 Sep 2021 16:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aI8o2oPgEEMzxMibNBY+GnQvGWahR2uE+yIXUCRBH2Y=; b=kjjFvnPRiZ0fcWMlEaStGo+/LTspupWwmcgvhCoRCXNWemupcRaFp1s/IyTyPSzYH1 Jwp2BFmxSG2bWl2C1bmzOditpPzbbiy/urfgx+ygE2vATPr3MVuze2Te5LBwLIH6hLOC J1kt19yPviTRlCFa572W/t4rhlrUaI2wt8Gt6RyCMUrFL9XxTIS+9Aq/bwq3mBtMy/Wc kiOCUWXg8c6tRPTuyeYgYVdR96ZeeUB9lb2l1ZrgeRWOFmrsYSwLeHWmiuOmNuv8q9xw QGD1ydHZHZa04WJavM05IiMZz2rmrAU+pNr51SQDW+p02c2KGjVo6+5S7PnWasxtawSM zmtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aI8o2oPgEEMzxMibNBY+GnQvGWahR2uE+yIXUCRBH2Y=; b=JTRTCNoI6CJdvZMUX+GuFfpgxX0eLqcNRKupaf/KwJlGhyFBVObEEbF/7+ROjI8SmI Dvx4yXnBjj+gbT1QgZjxluDywhjZOE0OjH46gd8rPa2Rn+nUM6Qo+JpeVdEwbaB23nUr MuXTeSFp8fWl+pRHUBBFsJqjAW8Lu4oZuGqS0fbDeglM2bvMDpVIQUtOPMdKDG0JJEDu oXEnJZlWBsg4M8aumu35to7ayHnwA2HN9KKfFV7cMFS4qMAWhZjx7j3t3EQBHt2SDBMh RBqihbMMu92iVxjHPu1oX2c5+EY3eOdntLXiP1HJQa/wLNP56xEQJ7QTrNqVqy9nPRCp +d7g== X-Gm-Message-State: AOAM5320S8Yr+ylLwaudnGwp4h+arR3S3eOF0WkjcOQ3mP7Iwg1rOUg7 HNsEKL0YJP6OAWqBnoTfG93g1A== X-Google-Smtp-Source: ABdhPJwYpTkkwH6SIFIcaJQhvs5WOL9iZpJCvwADVf+uVE01wyaWkb6QtsAZfyYSHkPD5+EsT+ZjiQ== X-Received: by 2002:a05:6512:e89:: with SMTP id bi9mr904779lfb.95.1630711465760; Fri, 03 Sep 2021 16:24:25 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 02/11] interconnect: sdm660: expand DEFINE_QNODE macros Date: Sat, 4 Sep 2021 02:24:12 +0300 Message-Id: <20210903232421.1384199-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Expand DEFINE_QNODE macros, which with an addition of QoS become an ugly beast with tons of different arguments. While we are at it also move links lists to separate arrays. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdm660.c | 1742 ++++++++++++++++++++++++++-- 1 file changed, 1626 insertions(+), 116 deletions(-) diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index fb23a5b780a4..652f7cc9cad6 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -201,8 +201,6 @@ struct qcom_icc_provider { void __iomem *mmio; }; -#define SDM660_MAX_LINKS 34 - /** * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters * @areq_prio: node requests priority @@ -236,7 +234,7 @@ struct qcom_icc_qos { struct qcom_icc_node { unsigned char *name; u16 id; - u16 links[SDM660_MAX_LINKS]; + const u16 *links; u16 num_links; u16 buswidth; int mas_rpm_id; @@ -251,120 +249,1632 @@ struct qcom_icc_desc { const struct regmap_config *regmap_cfg; }; -#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ - _ap_owned, _qos_mode, _qos_prio, _qos_port, ...) \ - static struct qcom_icc_node _name = { \ - .name = #_name, \ - .id = _id, \ - .buswidth = _buswidth, \ - .mas_rpm_id = _mas_rpm_id, \ - .slv_rpm_id = _slv_rpm_id, \ - .qos.ap_owned = _ap_owned, \ - .qos.qos_mode = _qos_mode, \ - .qos.areq_prio = _qos_prio, \ - .qos.prio_level = _qos_prio, \ - .qos.qos_port = _qos_port, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ - .links = { __VA_ARGS__ }, \ - } +static const u16 mas_ipa_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_ipa = { + .name = "mas_ipa", + .id = SDM660_MASTER_IPA, + .buswidth = 8, + .mas_rpm_id = 59, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 3, + .num_links = ARRAY_SIZE(mas_ipa_links), + .links = mas_ipa_links, +}; + +static const u16 mas_cnoc_a2noc_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_cnoc_a2noc = { + .name = "mas_cnoc_a2noc", + .id = SDM660_MASTER_CNOC_A2NOC, + .buswidth = 8, + .mas_rpm_id = 146, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links), + .links = mas_cnoc_a2noc_links, +}; + +static const u16 mas_sdcc_1_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_sdcc_1 = { + .name = "mas_sdcc_1", + .id = SDM660_MASTER_SDCC_1, + .buswidth = 8, + .mas_rpm_id = 33, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_sdcc_1_links), + .links = mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_sdcc_2 = { + .name = "mas_sdcc_2", + .id = SDM660_MASTER_SDCC_2, + .buswidth = 8, + .mas_rpm_id = 35, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_sdcc_2_links), + .links = mas_sdcc_2_links, +}; + +static const u16 mas_blsp_1_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_blsp_1 = { + .name = "mas_blsp_1", + .id = SDM660_MASTER_BLSP_1, + .buswidth = 4, + .mas_rpm_id = 41, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_blsp_1_links), + .links = mas_blsp_1_links, +}; + +static const u16 mas_blsp_2_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_blsp_2 = { + .name = "mas_blsp_2", + .id = SDM660_MASTER_BLSP_2, + .buswidth = 4, + .mas_rpm_id = 39, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_blsp_2_links), + .links = mas_blsp_2_links, +}; + +static const u16 mas_ufs_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_ufs = { + .name = "mas_ufs", + .id = SDM660_MASTER_UFS, + .buswidth = 8, + .mas_rpm_id = 68, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 4, + .num_links = ARRAY_SIZE(mas_ufs_links), + .links = mas_ufs_links, +}; + +static const u16 mas_usb_hs_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_usb_hs = { + .name = "mas_usb_hs", + .id = SDM660_MASTER_USB_HS, + .buswidth = 8, + .mas_rpm_id = 42, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_usb_hs_links), + .links = mas_usb_hs_links, +}; + +static const u16 mas_usb3_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_usb3 = { + .name = "mas_usb3", + .id = SDM660_MASTER_USB3, + .buswidth = 8, + .mas_rpm_id = 32, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_usb3_links), + .links = mas_usb3_links, +}; + +static const u16 mas_crypto_links[] = { + SDM660_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_crypto = { + .name = "mas_crypto", + .id = SDM660_MASTER_CRYPTO_C0, + .buswidth = 8, + .mas_rpm_id = 23, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 11, + .num_links = ARRAY_SIZE(mas_crypto_links), + .links = mas_crypto_links, +}; + +static const u16 mas_gnoc_bimc_links[] = { + SDM660_SLAVE_EBI +}; + +static struct qcom_icc_node mas_gnoc_bimc = { + .name = "mas_gnoc_bimc", + .id = SDM660_MASTER_GNOC_BIMC, + .buswidth = 4, + .mas_rpm_id = 144, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_gnoc_bimc_links), + .links = mas_gnoc_bimc_links, +}; + +static const u16 mas_oxili_links[] = { + SDM660_SLAVE_HMSS_L3, + SDM660_SLAVE_EBI, + SDM660_SLAVE_BIMC_SNOC +}; + +static struct qcom_icc_node mas_oxili = { + .name = "mas_oxili", + .id = SDM660_MASTER_OXILI, + .buswidth = 4, + .mas_rpm_id = 6, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_oxili_links), + .links = mas_oxili_links, +}; + +static const u16 mas_mnoc_bimc_links[] = { + SDM660_SLAVE_HMSS_L3, + SDM660_SLAVE_EBI, + SDM660_SLAVE_BIMC_SNOC +}; + +static struct qcom_icc_node mas_mnoc_bimc = { + .name = "mas_mnoc_bimc", + .id = SDM660_MASTER_MNOC_BIMC, + .buswidth = 4, + .mas_rpm_id = 2, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_links), + .links = mas_mnoc_bimc_links, +}; + +static const u16 mas_snoc_bimc_links[] = { + SDM660_SLAVE_HMSS_L3, + SDM660_SLAVE_EBI +}; + +static struct qcom_icc_node mas_snoc_bimc = { + .name = "mas_snoc_bimc", + .id = SDM660_MASTER_SNOC_BIMC, + .buswidth = 4, + .mas_rpm_id = 3, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_snoc_bimc_links), + .links = mas_snoc_bimc_links, +}; + +static const u16 mas_pimem_links[] = { + SDM660_SLAVE_HMSS_L3, + SDM660_SLAVE_EBI +}; + +static struct qcom_icc_node mas_pimem = { + .name = "mas_pimem", + .id = SDM660_MASTER_PIMEM, + .buswidth = 4, + .mas_rpm_id = 113, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 4, + .num_links = ARRAY_SIZE(mas_pimem_links), + .links = mas_pimem_links, +}; + +static const u16 mas_snoc_cnoc_links[] = { + SDM660_SLAVE_CLK_CTL, + SDM660_SLAVE_QDSS_CFG, + SDM660_SLAVE_QM_CFG, + SDM660_SLAVE_SRVC_CNOC, + SDM660_SLAVE_UFS_CFG, + SDM660_SLAVE_TCSR, + SDM660_SLAVE_A2NOC_SMMU_CFG, + SDM660_SLAVE_SNOC_CFG, + SDM660_SLAVE_TLMM_SOUTH, + SDM660_SLAVE_MPM, + SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, + SDM660_SLAVE_SDCC_2, + SDM660_SLAVE_SDCC_1, + SDM660_SLAVE_SPDM, + SDM660_SLAVE_PMIC_ARB, + SDM660_SLAVE_PRNG, + SDM660_SLAVE_MSS_CFG, + SDM660_SLAVE_GPUSS_CFG, + SDM660_SLAVE_IMEM_CFG, + SDM660_SLAVE_USB3_0, + SDM660_SLAVE_A2NOC_CFG, + SDM660_SLAVE_TLMM_NORTH, + SDM660_SLAVE_USB_HS, + SDM660_SLAVE_PDM, + SDM660_SLAVE_TLMM_CENTER, + SDM660_SLAVE_AHB2PHY, + SDM660_SLAVE_BLSP_2, + SDM660_SLAVE_BLSP_1, + SDM660_SLAVE_PIMEM_CFG, + SDM660_SLAVE_GLM, + SDM660_SLAVE_MESSAGE_RAM, + SDM660_SLAVE_BIMC_CFG, + SDM660_SLAVE_CNOC_MNOC_CFG +}; + +static struct qcom_icc_node mas_snoc_cnoc = { + .name = "mas_snoc_cnoc", + .id = SDM660_MASTER_SNOC_CNOC, + .buswidth = 8, + .mas_rpm_id = 52, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), + .links = mas_snoc_cnoc_links, +}; + +static const u16 mas_qdss_dap_links[] = { + SDM660_SLAVE_CLK_CTL, + SDM660_SLAVE_QDSS_CFG, + SDM660_SLAVE_QM_CFG, + SDM660_SLAVE_SRVC_CNOC, + SDM660_SLAVE_UFS_CFG, + SDM660_SLAVE_TCSR, + SDM660_SLAVE_A2NOC_SMMU_CFG, + SDM660_SLAVE_SNOC_CFG, + SDM660_SLAVE_TLMM_SOUTH, + SDM660_SLAVE_MPM, + SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, + SDM660_SLAVE_SDCC_2, + SDM660_SLAVE_SDCC_1, + SDM660_SLAVE_SPDM, + SDM660_SLAVE_PMIC_ARB, + SDM660_SLAVE_PRNG, + SDM660_SLAVE_MSS_CFG, + SDM660_SLAVE_GPUSS_CFG, + SDM660_SLAVE_IMEM_CFG, + SDM660_SLAVE_USB3_0, + SDM660_SLAVE_A2NOC_CFG, + SDM660_SLAVE_TLMM_NORTH, + SDM660_SLAVE_USB_HS, + SDM660_SLAVE_PDM, + SDM660_SLAVE_TLMM_CENTER, + SDM660_SLAVE_AHB2PHY, + SDM660_SLAVE_BLSP_2, + SDM660_SLAVE_BLSP_1, + SDM660_SLAVE_PIMEM_CFG, + SDM660_SLAVE_GLM, + SDM660_SLAVE_MESSAGE_RAM, + SDM660_SLAVE_CNOC_A2NOC, + SDM660_SLAVE_BIMC_CFG, + SDM660_SLAVE_CNOC_MNOC_CFG +}; + +static struct qcom_icc_node mas_qdss_dap = { + .name = "mas_qdss_dap", + .id = SDM660_MASTER_QDSS_DAP, + .buswidth = 8, + .mas_rpm_id = 49, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_qdss_dap_links), + .links = mas_qdss_dap_links, +}; + +static const u16 mas_apss_proc_links[] = { + SDM660_SLAVE_GNOC_SNOC, + SDM660_SLAVE_GNOC_BIMC +}; + +static struct qcom_icc_node mas_apss_proc = { + .name = "mas_apss_proc", + .id = SDM660_MASTER_APPS_PROC, + .buswidth = 16, + .mas_rpm_id = 0, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_apss_proc_links), + .links = mas_apss_proc_links, +}; + +static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { + SDM660_SLAVE_VENUS_THROTTLE_CFG, + SDM660_SLAVE_VENUS_CFG, + SDM660_SLAVE_CAMERA_THROTTLE_CFG, + SDM660_SLAVE_SMMU_CFG, + SDM660_SLAVE_CAMERA_CFG, + SDM660_SLAVE_CSI_PHY_CFG, + SDM660_SLAVE_DISPLAY_THROTTLE_CFG, + SDM660_SLAVE_DISPLAY_CFG, + SDM660_SLAVE_MMSS_CLK_CFG, + SDM660_SLAVE_MNOC_MPU_CFG, + SDM660_SLAVE_MISC_CFG, + SDM660_SLAVE_MMSS_CLK_XPU_CFG +}; + +static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { + .name = "mas_cnoc_mnoc_mmss_cfg", + .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG, + .buswidth = 8, + .mas_rpm_id = 4, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), + .links = mas_cnoc_mnoc_mmss_cfg_links, +}; + +static const u16 mas_cnoc_mnoc_cfg_links[] = { + SDM660_SLAVE_SRVC_MNOC +}; + +static struct qcom_icc_node mas_cnoc_mnoc_cfg = { + .name = "mas_cnoc_mnoc_cfg", + .id = SDM660_MASTER_CNOC_MNOC_CFG, + .buswidth = 4, + .mas_rpm_id = 5, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), + .links = mas_cnoc_mnoc_cfg_links, +}; + +static const u16 mas_cpp_links[] = { + SDM660_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_cpp = { + .name = "mas_cpp", + .id = SDM660_MASTER_CPP, + .buswidth = 16, + .mas_rpm_id = 115, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 4, + .num_links = ARRAY_SIZE(mas_cpp_links), + .links = mas_cpp_links, +}; + +static const u16 mas_jpeg_links[] = { + SDM660_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_jpeg = { + .name = "mas_jpeg", + .id = SDM660_MASTER_JPEG, + .buswidth = 16, + .mas_rpm_id = 7, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 6, + .num_links = ARRAY_SIZE(mas_jpeg_links), + .links = mas_jpeg_links, +}; + +static const u16 mas_mdp_p0_links[] = { + SDM660_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_mdp_p0 = { + .name = "mas_mdp_p0", + .id = SDM660_MASTER_MDP_P0, + .buswidth = 16, + .mas_rpm_id = 8, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_mdp_p0_links), + .links = mas_mdp_p0_links, +}; + +static const u16 mas_mdp_p1_links[] = { + SDM660_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_mdp_p1 = { + .name = "mas_mdp_p1", + .id = SDM660_MASTER_MDP_P1, + .buswidth = 16, + .mas_rpm_id = 61, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_mdp_p1_links), + .links = mas_mdp_p1_links, +}; + +static const u16 mas_venus_links[] = { + SDM660_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_venus = { + .name = "mas_venus", + .id = SDM660_MASTER_VENUS, + .buswidth = 16, + .mas_rpm_id = 9, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_venus_links), + .links = mas_venus_links, +}; + +static const u16 mas_vfe_links[] = { + SDM660_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_vfe = { + .name = "mas_vfe", + .id = SDM660_MASTER_VFE, + .buswidth = 16, + .mas_rpm_id = 11, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 5, + .num_links = ARRAY_SIZE(mas_vfe_links), + .links = mas_vfe_links, +}; + +static const u16 mas_qdss_etr_links[] = { + SDM660_SLAVE_PIMEM, + SDM660_SLAVE_IMEM, + SDM660_SLAVE_SNOC_CNOC, + SDM660_SLAVE_SNOC_BIMC +}; + +static struct qcom_icc_node mas_qdss_etr = { + .name = "mas_qdss_etr", + .id = SDM660_MASTER_QDSS_ETR, + .buswidth = 8, + .mas_rpm_id = 31, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_qdss_etr_links), + .links = mas_qdss_etr_links, +}; + +static const u16 mas_qdss_bam_links[] = { + SDM660_SLAVE_PIMEM, + SDM660_SLAVE_IMEM, + SDM660_SLAVE_SNOC_CNOC, + SDM660_SLAVE_SNOC_BIMC +}; + +static struct qcom_icc_node mas_qdss_bam = { + .name = "mas_qdss_bam", + .id = SDM660_MASTER_QDSS_BAM, + .buswidth = 4, + .mas_rpm_id = 19, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_qdss_bam_links), + .links = mas_qdss_bam_links, +}; + +static const u16 mas_snoc_cfg_links[] = { + SDM660_SLAVE_SRVC_SNOC +}; + +static struct qcom_icc_node mas_snoc_cfg = { + .name = "mas_snoc_cfg", + .id = SDM660_MASTER_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = 20, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_snoc_cfg_links), + .links = mas_snoc_cfg_links, +}; + +static const u16 mas_bimc_snoc_links[] = { + SDM660_SLAVE_PIMEM, + SDM660_SLAVE_IPA, + SDM660_SLAVE_QDSS_STM, + SDM660_SLAVE_LPASS, + SDM660_SLAVE_HMSS, + SDM660_SLAVE_CDSP, + SDM660_SLAVE_SNOC_CNOC, + SDM660_SLAVE_WLAN, + SDM660_SLAVE_IMEM +}; + +static struct qcom_icc_node mas_bimc_snoc = { + .name = "mas_bimc_snoc", + .id = SDM660_MASTER_BIMC_SNOC, + .buswidth = 8, + .mas_rpm_id = 21, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_bimc_snoc_links), + .links = mas_bimc_snoc_links, +}; + +static const u16 mas_gnoc_snoc_links[] = { + SDM660_SLAVE_PIMEM, + SDM660_SLAVE_IPA, + SDM660_SLAVE_QDSS_STM, + SDM660_SLAVE_LPASS, + SDM660_SLAVE_HMSS, + SDM660_SLAVE_CDSP, + SDM660_SLAVE_SNOC_CNOC, + SDM660_SLAVE_WLAN, + SDM660_SLAVE_IMEM +}; + +static struct qcom_icc_node mas_gnoc_snoc = { + .name = "mas_gnoc_snoc", + .id = SDM660_MASTER_GNOC_SNOC, + .buswidth = 8, + .mas_rpm_id = 150, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_gnoc_snoc_links), + .links = mas_gnoc_snoc_links, +}; + +static const u16 mas_a2noc_snoc_links[] = { + SDM660_SLAVE_PIMEM, + SDM660_SLAVE_IPA, + SDM660_SLAVE_QDSS_STM, + SDM660_SLAVE_LPASS, + SDM660_SLAVE_HMSS, + SDM660_SLAVE_SNOC_BIMC, + SDM660_SLAVE_CDSP, + SDM660_SLAVE_SNOC_CNOC, + SDM660_SLAVE_WLAN, + SDM660_SLAVE_IMEM +}; + +static struct qcom_icc_node mas_a2noc_snoc = { + .name = "mas_a2noc_snoc", + .id = SDM660_MASTER_A2NOC_SNOC, + .buswidth = 16, + .mas_rpm_id = 112, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), + .links = mas_a2noc_snoc_links, +}; + +static const u16 slv_a2noc_snoc_links[] = { + SDM660_MASTER_A2NOC_SNOC +}; + +static struct qcom_icc_node slv_a2noc_snoc = { + .name = "slv_a2noc_snoc", + .id = SDM660_SLAVE_A2NOC_SNOC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 143, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), + .links = slv_a2noc_snoc_links, +}; + +static struct qcom_icc_node slv_ebi = { + .name = "slv_ebi", + .id = SDM660_SLAVE_EBI, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 0, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_hmss_l3 = { + .name = "slv_hmss_l3", + .id = SDM660_SLAVE_HMSS_L3, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 160, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static const u16 slv_bimc_snoc_links[] = { + SDM660_MASTER_BIMC_SNOC +}; + +static struct qcom_icc_node slv_bimc_snoc = { + .name = "slv_bimc_snoc", + .id = SDM660_SLAVE_BIMC_SNOC, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 2, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_bimc_snoc_links), + .links = slv_bimc_snoc_links, +}; + +static const u16 slv_cnoc_a2noc_links[] = { + SDM660_MASTER_CNOC_A2NOC +}; + +static struct qcom_icc_node slv_cnoc_a2noc = { + .name = "slv_cnoc_a2noc", + .id = SDM660_SLAVE_CNOC_A2NOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 208, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links), + .links = slv_cnoc_a2noc_links, +}; + +static struct qcom_icc_node slv_mpm = { + .name = "slv_mpm", + .id = SDM660_SLAVE_MPM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 62, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_pmic_arb = { + .name = "slv_pmic_arb", + .id = SDM660_SLAVE_PMIC_ARB, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 59, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_tlmm_north = { + .name = "slv_tlmm_north", + .id = SDM660_SLAVE_TLMM_NORTH, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 214, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_tcsr = { + .name = "slv_tcsr", + .id = SDM660_SLAVE_TCSR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 50, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_pimem_cfg = { + .name = "slv_pimem_cfg", + .id = SDM660_SLAVE_PIMEM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 167, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_imem_cfg = { + .name = "slv_imem_cfg", + .id = SDM660_SLAVE_IMEM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 54, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_message_ram = { + .name = "slv_message_ram", + .id = SDM660_SLAVE_MESSAGE_RAM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 55, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_glm = { + .name = "slv_glm", + .id = SDM660_SLAVE_GLM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 209, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_bimc_cfg = { + .name = "slv_bimc_cfg", + .id = SDM660_SLAVE_BIMC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 56, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_prng = { + .name = "slv_prng", + .id = SDM660_SLAVE_PRNG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 44, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_spdm = { + .name = "slv_spdm", + .id = SDM660_SLAVE_SPDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 60, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_qdss_cfg = { + .name = "slv_qdss_cfg", + .id = SDM660_SLAVE_QDSS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 63, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static const u16 slv_cnoc_mnoc_cfg_links[] = { + SDM660_MASTER_CNOC_MNOC_CFG +}; + +static struct qcom_icc_node slv_cnoc_mnoc_cfg = { + .name = "slv_cnoc_mnoc_cfg", + .id = SDM660_SLAVE_CNOC_MNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 66, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), + .links = slv_cnoc_mnoc_cfg_links, +}; + +static struct qcom_icc_node slv_snoc_cfg = { + .name = "slv_snoc_cfg", + .id = SDM660_SLAVE_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 70, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_qm_cfg = { + .name = "slv_qm_cfg", + .id = SDM660_SLAVE_QM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 212, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_clk_ctl = { + .name = "slv_clk_ctl", + .id = SDM660_SLAVE_CLK_CTL, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 47, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_mss_cfg = { + .name = "slv_mss_cfg", + .id = SDM660_SLAVE_MSS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 48, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_tlmm_south = { + .name = "slv_tlmm_south", + .id = SDM660_SLAVE_TLMM_SOUTH, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 217, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_ufs_cfg = { + .name = "slv_ufs_cfg", + .id = SDM660_SLAVE_UFS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 92, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_a2noc_cfg = { + .name = "slv_a2noc_cfg", + .id = SDM660_SLAVE_A2NOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 150, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_a2noc_smmu_cfg = { + .name = "slv_a2noc_smmu_cfg", + .id = SDM660_SLAVE_A2NOC_SMMU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 152, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_gpuss_cfg = { + .name = "slv_gpuss_cfg", + .id = SDM660_SLAVE_GPUSS_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 11, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_ahb2phy = { + .name = "slv_ahb2phy", + .id = SDM660_SLAVE_AHB2PHY, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 163, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_blsp_1 = { + .name = "slv_blsp_1", + .id = SDM660_SLAVE_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 39, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_sdcc_1 = { + .name = "slv_sdcc_1", + .id = SDM660_SLAVE_SDCC_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 31, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_sdcc_2 = { + .name = "slv_sdcc_2", + .id = SDM660_SLAVE_SDCC_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 33, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_tlmm_center = { + .name = "slv_tlmm_center", + .id = SDM660_SLAVE_TLMM_CENTER, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 218, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_blsp_2 = { + .name = "slv_blsp_2", + .id = SDM660_SLAVE_BLSP_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 37, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_pdm = { + .name = "slv_pdm", + .id = SDM660_SLAVE_PDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 41, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { + SDM660_MASTER_CNOC_MNOC_MMSS_CFG +}; + +static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { + .name = "slv_cnoc_mnoc_mmss_cfg", + .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 58, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), + .links = slv_cnoc_mnoc_mmss_cfg_links, +}; + +static struct qcom_icc_node slv_usb_hs = { + .name = "slv_usb_hs", + .id = SDM660_SLAVE_USB_HS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 40, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_usb3_0 = { + .name = "slv_usb3_0", + .id = SDM660_SLAVE_USB3_0, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 22, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_srvc_cnoc = { + .name = "slv_srvc_cnoc", + .id = SDM660_SLAVE_SRVC_CNOC, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 76, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static const u16 slv_gnoc_bimc_links[] = { + SDM660_MASTER_GNOC_BIMC +}; + +static struct qcom_icc_node slv_gnoc_bimc = { + .name = "slv_gnoc_bimc", + .id = SDM660_SLAVE_GNOC_BIMC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 210, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_gnoc_bimc_links), + .links = slv_gnoc_bimc_links, +}; + +static const u16 slv_gnoc_snoc_links[] = { + SDM660_MASTER_GNOC_SNOC +}; + +static struct qcom_icc_node slv_gnoc_snoc = { + .name = "slv_gnoc_snoc", + .id = SDM660_SLAVE_GNOC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 211, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_gnoc_snoc_links), + .links = slv_gnoc_snoc_links, +}; + +static struct qcom_icc_node slv_camera_cfg = { + .name = "slv_camera_cfg", + .id = SDM660_SLAVE_CAMERA_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 3, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_camera_throttle_cfg = { + .name = "slv_camera_throttle_cfg", + .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 154, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_misc_cfg = { + .name = "slv_misc_cfg", + .id = SDM660_SLAVE_MISC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 8, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; -DEFINE_QNODE(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, true, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI); -DEFINE_QNODE(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC); -DEFINE_QNODE(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC); -DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, false, -1, 0, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI); -DEFINE_QNODE(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI); -DEFINE_QNODE(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG); -DEFINE_QNODE(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG); -DEFINE_QNODE(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, true, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC); -DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG); -DEFINE_QNODE(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, true, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC); -DEFINE_QNODE(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp???? */ -DEFINE_QNODE(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp??? */ -DEFINE_QNODE(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC); -DEFINE_QNODE(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC); -DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, false, -1, 0, -1, SDM660_SLAVE_SRVC_SNOC); -DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); -DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); -DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); -DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, SDM660_MASTER_A2NOC_SNOC); -DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, false, -1, 0, -1, SDM660_MASTER_BIMC_SNOC); -DEFINE_QNODE(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, true, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC); -DEFINE_QNODE(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_cnoc_mnoc_cfg, SDM660_SLAVE_CNOC_MNOC_CFG, 4, -1, 66, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG); -DEFINE_QNODE(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, true, -1, 0, -1, SDM660_MASTER_GNOC_BIMC); -DEFINE_QNODE(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, true, -1, 0, -1, SDM660_MASTER_GNOC_SNOC); -DEFINE_QNODE(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, true, -1, 0, -1, SDM660_MASTER_MNOC_BIMC); -DEFINE_QNODE(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, false, -1, 0, -1, SDM660_MASTER_SNOC_BIMC); -DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, false, -1, 0, -1, SDM660_MASTER_SNOC_CNOC); -DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0); +static struct qcom_icc_node slv_venus_throttle_cfg = { + .name = "slv_venus_throttle_cfg", + .id = SDM660_SLAVE_VENUS_THROTTLE_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 178, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_venus_cfg = { + .name = "slv_venus_cfg", + .id = SDM660_SLAVE_VENUS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 10, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_mmss_clk_xpu_cfg = { + .name = "slv_mmss_clk_xpu_cfg", + .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 13, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_mmss_clk_cfg = { + .name = "slv_mmss_clk_cfg", + .id = SDM660_SLAVE_MMSS_CLK_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 12, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_mnoc_mpu_cfg = { + .name = "slv_mnoc_mpu_cfg", + .id = SDM660_SLAVE_MNOC_MPU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 14, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_display_cfg = { + .name = "slv_display_cfg", + .id = SDM660_SLAVE_DISPLAY_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 4, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_csi_phy_cfg = { + .name = "slv_csi_phy_cfg", + .id = SDM660_SLAVE_CSI_PHY_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 224, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_display_throttle_cfg = { + .name = "slv_display_throttle_cfg", + .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 156, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_smmu_cfg = { + .name = "slv_smmu_cfg", + .id = SDM660_SLAVE_SMMU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 205, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static const u16 slv_mnoc_bimc_links[] = { + SDM660_MASTER_MNOC_BIMC +}; + +static struct qcom_icc_node slv_mnoc_bimc = { + .name = "slv_mnoc_bimc", + .id = SDM660_SLAVE_MNOC_BIMC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 16, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), + .links = slv_mnoc_bimc_links, +}; + +static struct qcom_icc_node slv_srvc_mnoc = { + .name = "slv_srvc_mnoc", + .id = SDM660_SLAVE_SRVC_MNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 17, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_hmss = { + .name = "slv_hmss", + .id = SDM660_SLAVE_HMSS, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 20, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_lpass = { + .name = "slv_lpass", + .id = SDM660_SLAVE_LPASS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 21, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_wlan = { + .name = "slv_wlan", + .id = SDM660_SLAVE_WLAN, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 206, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_cdsp = { + .name = "slv_cdsp", + .id = SDM660_SLAVE_CDSP, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 221, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_ipa = { + .name = "slv_ipa", + .id = SDM660_SLAVE_IPA, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 183, + .qos.ap_owned = true, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static const u16 slv_snoc_bimc_links[] = { + SDM660_MASTER_SNOC_BIMC +}; + +static struct qcom_icc_node slv_snoc_bimc = { + .name = "slv_snoc_bimc", + .id = SDM660_SLAVE_SNOC_BIMC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 24, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_snoc_bimc_links), + .links = slv_snoc_bimc_links, +}; + +static const u16 slv_snoc_cnoc_links[] = { + SDM660_MASTER_SNOC_CNOC +}; + +static struct qcom_icc_node slv_snoc_cnoc = { + .name = "slv_snoc_cnoc", + .id = SDM660_SLAVE_SNOC_CNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 25, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), + .links = slv_snoc_cnoc_links, +}; + +static struct qcom_icc_node slv_imem = { + .name = "slv_imem", + .id = SDM660_SLAVE_IMEM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 26, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_pimem = { + .name = "slv_pimem", + .id = SDM660_SLAVE_PIMEM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 166, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_qdss_stm = { + .name = "slv_qdss_stm", + .id = SDM660_SLAVE_QDSS_STM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 30, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; + +static struct qcom_icc_node slv_srvc_snoc = { + .name = "slv_srvc_snoc", + .id = SDM660_SLAVE_SRVC_SNOC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 29, + .qos.ap_owned = false, + .qos.qos_mode = -1, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, +}; static struct qcom_icc_node *sdm660_a2noc_nodes[] = { [MASTER_IPA] = &mas_ipa, From patchwork Fri Sep 3 23:24:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506558 Delivered-To: patch@linaro.org Received: by 2002:a17:906:f46:0:0:0:0 with SMTP id h6csp1976425ejj; Fri, 3 Sep 2021 16:24:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4Ey7hqpIZo3r6SkQgtm7hAy2WMuYcVahU9EA4LF6kHkyiceedP2bpZXZjmOefoVjxeShX X-Received: by 2002:a17:907:7755:: with SMTP id kx21mr1354320ejc.463.1630711472887; Fri, 03 Sep 2021 16:24:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630711472; cv=none; d=google.com; s=arc-20160816; b=fvP3a2gcfsSOIuN2yUGviRwxqYJ3R68FQsFHFUWLiZ0awWrjNjADM4XoRME6nmnkQ2 Bo8a11VRK0hOXgrhTynaUbSPlcfuwhMHm2Y1Ckm19JE2HALHWTUvnUKs7DXHPdzhZI6N bPecbF8jktJ2CkxdofVAebNnEGYDw0gSHpwb6xkMgPjsiwI9FaM2ICfm1KQxlDEDNdv5 /zV7RIx7fdNAJXOjk1cHz0SHkcdozKHeuHzn4C+1OPhGfdpqOCFeQ6wie9nT0+fL736f OoWDnazxI6lfeRj+UXRW0bKQbubOazWQpO758vmrhhNnJembnLgD90GDbHFICbP/B1ug lokQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y2qKNkH9miQwx/yZCrfm0nDrmTjlabC/6w0wRqhqYr4=; b=rK3v0tBk+vpxKo+4c8tTUiYN2nGbB71CRXV2LuucsJaQV4Tm6xgo5USNYoUJTfQuRC H5m2XQrDDsh5ZGzdtSPRmA9wDU7c0tbbCQGcSgxLObgHBGYls0foo2Tk0eQhsAkRTpQq uuSAoaqyHXi0iS/iM8QNHyLJgT/FnhZHyl+UGMp3Ls6nWSPovmVYQHB88ijxKSMI7//B i1rZYFnFEzJmxWc2yRSuiZFCQMJMYUQxny89n4Yn3HhB8trw72QskTdjj+azfjcnOImD pERvWM1wzmTq0YOtk4PZXmZM08m8dVfDI+px7voOAxdEc7IanTu8B54mM+TdZbWaqS7V 1eCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lTDPQ0ih; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp5si572394ejc.132.2021.09.03.16.24.32; Fri, 03 Sep 2021 16:24:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lTDPQ0ih; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350752AbhICXZb (ORCPT + 16 others); Fri, 3 Sep 2021 19:25:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350753AbhICXZ3 (ORCPT ); Fri, 3 Sep 2021 19:25:29 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46713C061760 for ; Fri, 3 Sep 2021 16:24:28 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id z2so1369781lft.1 for ; Fri, 03 Sep 2021 16:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y2qKNkH9miQwx/yZCrfm0nDrmTjlabC/6w0wRqhqYr4=; b=lTDPQ0ihkHV5m2XHhCBrtcMQUd5ouw+RKjMU8v64pkcMT00shLuQO+lVMvuFebBeGv uqRDZCbgawMr22ups20hPRpaa3ycgZpS87QcawR6urfKlQESj9FiXpTvWyfmxl8oTQG3 JfH26pCixCumeFU8RsYs7XzzK6CxgYYsXTHTXFJ7JoVY+d8Vr1jfPUliLwFRTHEpahmh abclOitnXPrfqt1zz9nnbl5hhzEnBFTaHcuhEOFnzUEu/b0P6CxH15CMSeMexcjVdQZr gyQQfceYHzm2PMSiuiUZ13D4J5Pdx9qjEYbWwCujHxkki7O+NS2C5ovpoUlvtwRTKvVJ elXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y2qKNkH9miQwx/yZCrfm0nDrmTjlabC/6w0wRqhqYr4=; b=MqOv058FBLDuPKd2MpGQfRzz4MeJyj5cadxYv+66mQmEZ9+Ag0rT2ubwJ9+yvJFS3s +rkijhwtAMtmUMclduYW5IHv4+grs1yomNrIcF+qnYl1BZ8q2/qHebjAvSEczuotumGV J6jHg8beS0+xPD+X0EBGcmA17PMbDeceyvBKrP3TyfMnYrUxJUJa9eXnAY9vhj5h4mtJ jQkqd3pF+IjWpJ/OxgTNfP2Jnhav7bomgenROX7FNt1O8+hhat00nB8xHZO3mTZ7tMON 6vcl+D+GLblyZgj4ihgrzwyOhV9TmkwjLg9jzy0w7se1rdqrW6Skxb7NbYweNA3g2ts8 Tf5w== X-Gm-Message-State: AOAM530mPwngQJh2IiJobsPpR6AnpRA4meya+NSXciHu9ly7u7QsGxzU fnYHkt82JmDt15suPZoZraboug== X-Received: by 2002:a05:6512:388e:: with SMTP id n14mr967256lft.242.1630711466499; Fri, 03 Sep 2021 16:24:26 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 03/11] interconnect: sdm660: drop default/unused values Date: Sat, 4 Sep 2021 02:24:13 +0300 Message-Id: <20210903232421.1384199-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Simplify qnode setup by removing unused/default values. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdm660.c | 407 +++++------------------------ 1 file changed, 64 insertions(+), 343 deletions(-) -- 2.33.0 Reviewed-by: AngeloGioacchino Del Regno Tested-by: Marijn Suijten diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 652f7cc9cad6..4a72f9677d4e 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -35,6 +35,7 @@ #define M_BKE_EN_EN_BMASK 0x1 /* Valid for both NoC and BIMC */ +#define NOC_QOS_MODE_INVALID -1 #define NOC_QOS_MODE_FIXED 0x0 #define NOC_QOS_MODE_LIMITER 0x1 #define NOC_QOS_MODE_BYPASS 0x2 @@ -279,10 +280,7 @@ static struct qcom_icc_node mas_cnoc_a2noc = { .mas_rpm_id = 146, .slv_rpm_id = -1, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links), .links = mas_cnoc_a2noc_links, }; @@ -297,11 +295,6 @@ static struct qcom_icc_node mas_sdcc_1 = { .buswidth = 8, .mas_rpm_id = 33, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_sdcc_1_links), .links = mas_sdcc_1_links, }; @@ -316,11 +309,6 @@ static struct qcom_icc_node mas_sdcc_2 = { .buswidth = 8, .mas_rpm_id = 35, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_sdcc_2_links), .links = mas_sdcc_2_links, }; @@ -335,11 +323,6 @@ static struct qcom_icc_node mas_blsp_1 = { .buswidth = 4, .mas_rpm_id = 41, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_blsp_1_links), .links = mas_blsp_1_links, }; @@ -354,11 +337,6 @@ static struct qcom_icc_node mas_blsp_2 = { .buswidth = 4, .mas_rpm_id = 39, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_blsp_2_links), .links = mas_blsp_2_links, }; @@ -511,11 +489,6 @@ static struct qcom_icc_node mas_snoc_bimc = { .buswidth = 4, .mas_rpm_id = 3, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_snoc_bimc_links), .links = mas_snoc_bimc_links, }; @@ -583,10 +556,7 @@ static struct qcom_icc_node mas_snoc_cnoc = { .mas_rpm_id = 52, .slv_rpm_id = -1, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), .links = mas_snoc_cnoc_links, }; @@ -635,10 +605,7 @@ static struct qcom_icc_node mas_qdss_dap = { .mas_rpm_id = 49, .slv_rpm_id = -1, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mas_qdss_dap_links), .links = mas_qdss_dap_links, }; @@ -655,10 +622,7 @@ static struct qcom_icc_node mas_apss_proc = { .mas_rpm_id = 0, .slv_rpm_id = -1, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mas_apss_proc_links), .links = mas_apss_proc_links, }; @@ -685,10 +649,7 @@ static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { .mas_rpm_id = 4, .slv_rpm_id = -1, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), .links = mas_cnoc_mnoc_mmss_cfg_links, }; @@ -704,10 +665,7 @@ static struct qcom_icc_node mas_cnoc_mnoc_cfg = { .mas_rpm_id = 5, .slv_rpm_id = -1, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), .links = mas_cnoc_mnoc_cfg_links, }; @@ -880,11 +838,6 @@ static struct qcom_icc_node mas_snoc_cfg = { .buswidth = 4, .mas_rpm_id = 20, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_snoc_cfg_links), .links = mas_snoc_cfg_links, }; @@ -907,11 +860,6 @@ static struct qcom_icc_node mas_bimc_snoc = { .buswidth = 8, .mas_rpm_id = 21, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_bimc_snoc_links), .links = mas_bimc_snoc_links, }; @@ -934,11 +882,6 @@ static struct qcom_icc_node mas_gnoc_snoc = { .buswidth = 8, .mas_rpm_id = 150, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_gnoc_snoc_links), .links = mas_gnoc_snoc_links, }; @@ -962,11 +905,6 @@ static struct qcom_icc_node mas_a2noc_snoc = { .buswidth = 16, .mas_rpm_id = 112, .slv_rpm_id = -1, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), .links = mas_a2noc_snoc_links, }; @@ -981,11 +919,6 @@ static struct qcom_icc_node slv_a2noc_snoc = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = 143, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), .links = slv_a2noc_snoc_links, }; @@ -996,11 +929,6 @@ static struct qcom_icc_node slv_ebi = { .buswidth = 4, .mas_rpm_id = -1, .slv_rpm_id = 0, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static struct qcom_icc_node slv_hmss_l3 = { @@ -1009,11 +937,6 @@ static struct qcom_icc_node slv_hmss_l3 = { .buswidth = 4, .mas_rpm_id = -1, .slv_rpm_id = 160, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static const u16 slv_bimc_snoc_links[] = { @@ -1026,11 +949,6 @@ static struct qcom_icc_node slv_bimc_snoc = { .buswidth = 4, .mas_rpm_id = -1, .slv_rpm_id = 2, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(slv_bimc_snoc_links), .links = slv_bimc_snoc_links, }; @@ -1046,10 +964,7 @@ static struct qcom_icc_node slv_cnoc_a2noc = { .mas_rpm_id = -1, .slv_rpm_id = 208, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links), .links = slv_cnoc_a2noc_links, }; @@ -1061,10 +976,7 @@ static struct qcom_icc_node slv_mpm = { .mas_rpm_id = -1, .slv_rpm_id = 62, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_pmic_arb = { @@ -1074,10 +986,7 @@ static struct qcom_icc_node slv_pmic_arb = { .mas_rpm_id = -1, .slv_rpm_id = 59, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_tlmm_north = { @@ -1087,10 +996,7 @@ static struct qcom_icc_node slv_tlmm_north = { .mas_rpm_id = -1, .slv_rpm_id = 214, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_tcsr = { @@ -1100,10 +1006,7 @@ static struct qcom_icc_node slv_tcsr = { .mas_rpm_id = -1, .slv_rpm_id = 50, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_pimem_cfg = { @@ -1113,10 +1016,7 @@ static struct qcom_icc_node slv_pimem_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 167, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_imem_cfg = { @@ -1126,10 +1026,7 @@ static struct qcom_icc_node slv_imem_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 54, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_message_ram = { @@ -1139,10 +1036,7 @@ static struct qcom_icc_node slv_message_ram = { .mas_rpm_id = -1, .slv_rpm_id = 55, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_glm = { @@ -1152,10 +1046,7 @@ static struct qcom_icc_node slv_glm = { .mas_rpm_id = -1, .slv_rpm_id = 209, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_bimc_cfg = { @@ -1165,10 +1056,7 @@ static struct qcom_icc_node slv_bimc_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 56, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_prng = { @@ -1178,10 +1066,7 @@ static struct qcom_icc_node slv_prng = { .mas_rpm_id = -1, .slv_rpm_id = 44, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_spdm = { @@ -1191,10 +1076,7 @@ static struct qcom_icc_node slv_spdm = { .mas_rpm_id = -1, .slv_rpm_id = 60, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_qdss_cfg = { @@ -1204,10 +1086,7 @@ static struct qcom_icc_node slv_qdss_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 63, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static const u16 slv_cnoc_mnoc_cfg_links[] = { @@ -1221,10 +1100,7 @@ static struct qcom_icc_node slv_cnoc_mnoc_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 66, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), .links = slv_cnoc_mnoc_cfg_links, }; @@ -1236,10 +1112,7 @@ static struct qcom_icc_node slv_snoc_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 70, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_qm_cfg = { @@ -1249,10 +1122,7 @@ static struct qcom_icc_node slv_qm_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 212, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_clk_ctl = { @@ -1262,10 +1132,7 @@ static struct qcom_icc_node slv_clk_ctl = { .mas_rpm_id = -1, .slv_rpm_id = 47, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_mss_cfg = { @@ -1275,10 +1142,7 @@ static struct qcom_icc_node slv_mss_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 48, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_tlmm_south = { @@ -1288,10 +1152,7 @@ static struct qcom_icc_node slv_tlmm_south = { .mas_rpm_id = -1, .slv_rpm_id = 217, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_ufs_cfg = { @@ -1301,10 +1162,7 @@ static struct qcom_icc_node slv_ufs_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 92, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_a2noc_cfg = { @@ -1314,10 +1172,7 @@ static struct qcom_icc_node slv_a2noc_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 150, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_a2noc_smmu_cfg = { @@ -1327,10 +1182,7 @@ static struct qcom_icc_node slv_a2noc_smmu_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 152, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_gpuss_cfg = { @@ -1340,10 +1192,7 @@ static struct qcom_icc_node slv_gpuss_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 11, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_ahb2phy = { @@ -1353,10 +1202,7 @@ static struct qcom_icc_node slv_ahb2phy = { .mas_rpm_id = -1, .slv_rpm_id = 163, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_blsp_1 = { @@ -1366,10 +1212,7 @@ static struct qcom_icc_node slv_blsp_1 = { .mas_rpm_id = -1, .slv_rpm_id = 39, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_sdcc_1 = { @@ -1379,10 +1222,7 @@ static struct qcom_icc_node slv_sdcc_1 = { .mas_rpm_id = -1, .slv_rpm_id = 31, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_sdcc_2 = { @@ -1392,10 +1232,7 @@ static struct qcom_icc_node slv_sdcc_2 = { .mas_rpm_id = -1, .slv_rpm_id = 33, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_tlmm_center = { @@ -1405,10 +1242,7 @@ static struct qcom_icc_node slv_tlmm_center = { .mas_rpm_id = -1, .slv_rpm_id = 218, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_blsp_2 = { @@ -1418,10 +1252,7 @@ static struct qcom_icc_node slv_blsp_2 = { .mas_rpm_id = -1, .slv_rpm_id = 37, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_pdm = { @@ -1431,10 +1262,7 @@ static struct qcom_icc_node slv_pdm = { .mas_rpm_id = -1, .slv_rpm_id = 41, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { @@ -1448,10 +1276,7 @@ static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 58, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), .links = slv_cnoc_mnoc_mmss_cfg_links, }; @@ -1463,10 +1288,7 @@ static struct qcom_icc_node slv_usb_hs = { .mas_rpm_id = -1, .slv_rpm_id = 40, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_usb3_0 = { @@ -1476,10 +1298,7 @@ static struct qcom_icc_node slv_usb3_0 = { .mas_rpm_id = -1, .slv_rpm_id = 22, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_srvc_cnoc = { @@ -1489,10 +1308,7 @@ static struct qcom_icc_node slv_srvc_cnoc = { .mas_rpm_id = -1, .slv_rpm_id = 76, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static const u16 slv_gnoc_bimc_links[] = { @@ -1506,10 +1322,7 @@ static struct qcom_icc_node slv_gnoc_bimc = { .mas_rpm_id = -1, .slv_rpm_id = 210, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(slv_gnoc_bimc_links), .links = slv_gnoc_bimc_links, }; @@ -1525,10 +1338,7 @@ static struct qcom_icc_node slv_gnoc_snoc = { .mas_rpm_id = -1, .slv_rpm_id = 211, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(slv_gnoc_snoc_links), .links = slv_gnoc_snoc_links, }; @@ -1540,10 +1350,7 @@ static struct qcom_icc_node slv_camera_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 3, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_camera_throttle_cfg = { @@ -1553,10 +1360,7 @@ static struct qcom_icc_node slv_camera_throttle_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 154, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_misc_cfg = { @@ -1566,10 +1370,7 @@ static struct qcom_icc_node slv_misc_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 8, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_venus_throttle_cfg = { @@ -1579,10 +1380,7 @@ static struct qcom_icc_node slv_venus_throttle_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 178, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_venus_cfg = { @@ -1592,10 +1390,7 @@ static struct qcom_icc_node slv_venus_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 10, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_mmss_clk_xpu_cfg = { @@ -1605,10 +1400,7 @@ static struct qcom_icc_node slv_mmss_clk_xpu_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 13, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_mmss_clk_cfg = { @@ -1618,10 +1410,7 @@ static struct qcom_icc_node slv_mmss_clk_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 12, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_mnoc_mpu_cfg = { @@ -1631,10 +1420,7 @@ static struct qcom_icc_node slv_mnoc_mpu_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 14, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_display_cfg = { @@ -1644,10 +1430,7 @@ static struct qcom_icc_node slv_display_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 4, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_csi_phy_cfg = { @@ -1657,10 +1440,7 @@ static struct qcom_icc_node slv_csi_phy_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 224, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_display_throttle_cfg = { @@ -1670,10 +1450,7 @@ static struct qcom_icc_node slv_display_throttle_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 156, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_smmu_cfg = { @@ -1683,10 +1460,7 @@ static struct qcom_icc_node slv_smmu_cfg = { .mas_rpm_id = -1, .slv_rpm_id = 205, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static const u16 slv_mnoc_bimc_links[] = { @@ -1700,10 +1474,7 @@ static struct qcom_icc_node slv_mnoc_bimc = { .mas_rpm_id = -1, .slv_rpm_id = 16, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), .links = slv_mnoc_bimc_links, }; @@ -1715,10 +1486,7 @@ static struct qcom_icc_node slv_srvc_mnoc = { .mas_rpm_id = -1, .slv_rpm_id = 17, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_hmss = { @@ -1728,10 +1496,7 @@ static struct qcom_icc_node slv_hmss = { .mas_rpm_id = -1, .slv_rpm_id = 20, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_lpass = { @@ -1741,10 +1506,7 @@ static struct qcom_icc_node slv_lpass = { .mas_rpm_id = -1, .slv_rpm_id = 21, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_wlan = { @@ -1753,11 +1515,6 @@ static struct qcom_icc_node slv_wlan = { .buswidth = 4, .mas_rpm_id = -1, .slv_rpm_id = 206, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static struct qcom_icc_node slv_cdsp = { @@ -1767,10 +1524,7 @@ static struct qcom_icc_node slv_cdsp = { .mas_rpm_id = -1, .slv_rpm_id = 221, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static struct qcom_icc_node slv_ipa = { @@ -1780,10 +1534,7 @@ static struct qcom_icc_node slv_ipa = { .mas_rpm_id = -1, .slv_rpm_id = 183, .qos.ap_owned = true, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, + .qos.qos_mode = NOC_QOS_MODE_INVALID, }; static const u16 slv_snoc_bimc_links[] = { @@ -1796,11 +1547,6 @@ static struct qcom_icc_node slv_snoc_bimc = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = 24, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(slv_snoc_bimc_links), .links = slv_snoc_bimc_links, }; @@ -1815,11 +1561,6 @@ static struct qcom_icc_node slv_snoc_cnoc = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = 25, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), .links = slv_snoc_cnoc_links, }; @@ -1830,11 +1571,6 @@ static struct qcom_icc_node slv_imem = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = 26, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static struct qcom_icc_node slv_pimem = { @@ -1843,11 +1579,6 @@ static struct qcom_icc_node slv_pimem = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = 166, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static struct qcom_icc_node slv_qdss_stm = { @@ -1856,11 +1587,6 @@ static struct qcom_icc_node slv_qdss_stm = { .buswidth = 4, .mas_rpm_id = -1, .slv_rpm_id = 30, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static struct qcom_icc_node slv_srvc_snoc = { @@ -1869,11 +1595,6 @@ static struct qcom_icc_node slv_srvc_snoc = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = 29, - .qos.ap_owned = false, - .qos.qos_mode = -1, - .qos.areq_prio = 0, - .qos.prio_level = 0, - .qos.qos_port = -1, }; static struct qcom_icc_node *sdm660_a2noc_nodes[] = { @@ -2113,7 +1834,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, provider = src->provider; qp = to_qcom_provider(provider); - if (qn->qos.qos_mode != -1) + if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) mode = qn->qos.qos_mode; /* QoS Priority: The QoS Health parameters are getting considered @@ -2171,7 +1892,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) return 0; } - if (qn->qos.qos_mode != -1) + if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) mode = qn->qos.qos_mode; if (mode == NOC_QOS_MODE_FIXED) { @@ -2264,7 +1985,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); if (ret) return ret; - } else if (qn->qos.qos_mode != -1) { + } else if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) { /* set bandwidth directly from the AP */ ret = qcom_icc_qos_set(src, sum_bw); if (ret) From patchwork Fri Sep 3 23:24:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9DD4C4167B for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E7F9610E8 for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350758AbhICXZd (ORCPT ); Fri, 3 Sep 2021 19:25:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350756AbhICXZa (ORCPT ); Fri, 3 Sep 2021 19:25:30 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 241E6C061575 for ; Fri, 3 Sep 2021 16:24:29 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id x27so1347194lfu.5 for ; Fri, 03 Sep 2021 16:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bIVYnIat1O2YrpA62nFbzI57fBhDDuxw43SGRZZi6rE=; b=TtTjy+szOvOtFpcsHfGysk/rTVizKvoqLHXo6jtaSCJHdeuY8mgPf+cwmi5RBuG5pR wUTILcADy/XY2LxFAfobY5pnyYUiLd8P0sdJ+8IYDCEaFV4UUlbrUVxMZVeTAseV/rU+ WmMBgK+Pi4SyFoD7g6qvWzzN7MbH513ABmhvobekqA8VbMZRvR3sE4Lhzz0IJl/41NN+ gWCspoGVtUQbnyWob+JpUL8yh8PB6DZK//6CjqWfSW06Zq5W8g9sg9uEANGQDiXQW4CO EcGnUZJS6sX/fCjkAgati/oaujh3amuXnsAC23UxHLgv8zVJpQz0R+vRd7uIxfeFF+xk zXkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bIVYnIat1O2YrpA62nFbzI57fBhDDuxw43SGRZZi6rE=; b=nDOwc7rqlmtvpmKB7UdhgBW1HSXD8YGAyBImmurrEgGlAsA24MmszwgRXHhC9mg3ou Vo3f3ZbnI4Qd930sndl0ClfAqs2/knF+qw+OefikbHPw6X+nX+i91cvM9uh0DZoNG9Li 4YItFGjQlgX0Kez0Sc8vuJvsyU5Gc0Lz3O9rG16fNam1j/DlP02ZsdyTtyIKRyM32cpR fgN3WAAvmg0r2BqG9PbnPDjZYl0iQsGfmSTfUCx68cfqp+xJmsw0qvTmmaXXQx0+8whM 0fETlPWqdXsZ9yBjwoKVcSZkZqNa7v2x0juLO/WvO2dfvvgWxuClLIb54CW/NjDTkrdo QbFw== X-Gm-Message-State: AOAM530RLFnb/8lTlLyR4pUT2v2p6u2N6nTUcIk3wut9WB9qsrCcI5tf 3QpP7jSzl/gm/YOrQAgHQVr2TMiDbj5ysw== X-Google-Smtp-Source: ABdhPJz/j3sWGZk6c8+Mq/zbaTOaFQMVq8p4CRRbZxRL9xpXeg+mz2KFqu2r63YZD2jbTuzlVOScdw== X-Received: by 2002:a05:6512:2246:: with SMTP id i6mr918801lfu.360.1630711467317; Fri, 03 Sep 2021 16:24:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 04/11] interconnect: sdm660: merge common code into icc-rpm Date: Sat, 4 Sep 2021 02:24:14 +0300 Message-Id: <20210903232421.1384199-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Other RPM interconnect drivers might also use QoS support. Move AP-owned nodes support from SDM660 driver to common icc-rpm.c. Signed-off-by: Dmitry Baryshkov Reviewed-by: AngeloGioacchino Del Regno Tested-by: Marijn Suijten --- drivers/interconnect/qcom/icc-rpm.c | 241 ++++++++++++-- drivers/interconnect/qcom/icc-rpm.h | 42 ++- drivers/interconnect/qcom/sdm660.c | 485 ++-------------------------- 3 files changed, 274 insertions(+), 494 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 394f515cc88d..b8bac738c64f 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -11,60 +11,228 @@ #include #include #include +#include #include #include "smd-rpm.h" #include "icc-rpm.h" -static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +/* BIMC QoS */ +#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n)) +#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n)) +#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i)) + +#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000 +#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300 +#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3 +#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8 +#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f + +#define M_BKE_EN_EN_BMASK 0x1 + +/* NoC QoS */ +#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000)) +#define NOC_QOS_PRIORITY_P1_MASK 0xc +#define NOC_QOS_PRIORITY_P0_MASK 0x3 +#define NOC_QOS_PRIORITY_P1_SHIFT 0x2 + +#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) +#define NOC_QOS_MODEn_MASK 0x3 + +static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, + struct qcom_icc_qos *qos, + int regnum) +{ + u32 val; + u32 mask; + + val = qos->prio_level; + mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK; + + val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT; + mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK; + + /* LIMITCMDS is not present on M_BKE_HEALTH_3 */ + if (regnum != 3) { + val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT; + mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; + } + + return regmap_update_bits(rmap, + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + mask, val); +} + +static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw) { struct qcom_icc_provider *qp; struct qcom_icc_node *qn; struct icc_provider *provider; - struct icc_node *n; - u64 sum_bw; - u64 max_peak_bw; - u64 rate; - u32 agg_avg = 0; - u32 agg_peak = 0; - int ret, i; + u32 mode = NOC_QOS_MODE_BYPASS; + u32 val = 0; + int i, rc = 0; qn = src->data; provider = src->provider; qp = to_qcom_provider(provider); - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); + if (qn->qos.qos_mode != -1) + mode = qn->qos.qos_mode; + + /* QoS Priority: The QoS Health parameters are getting considered + * only if we are NOT in Bypass Mode. + */ + if (mode != NOC_QOS_MODE_BYPASS) { + for (i = 3; i >= 0; i--) { + rc = qcom_icc_bimc_set_qos_health(qp->regmap, + &qn->qos, i); + if (rc) + return rc; + } - sum_bw = icc_units_to_bps(agg_avg); - max_peak_bw = icc_units_to_bps(agg_peak); + /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */ + val = 1; + } + + return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), + M_BKE_EN_EN_BMASK, val); +} + +static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, + struct qcom_icc_qos *qos) +{ + u32 val; + int rc; + + /* Must be updated one at a time, P1 first, P0 last */ + val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; + rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_P1_MASK, val); + if (rc) + return rc; + + return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_P0_MASK, qos->prio_level); +} + +static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + u32 mode = NOC_QOS_MODE_BYPASS; + int rc = 0; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + if (qn->qos.qos_port < 0) { + dev_dbg(src->provider->dev, + "NoC QoS: Skipping %s: vote aggregated on parent.\n", + qn->name); + return 0; + } + + if (qn->qos.qos_mode != -1) + mode = qn->qos.qos_mode; + + if (mode == NOC_QOS_MODE_FIXED) { + dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", + qn->name); + rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); + if (rc) + return rc; + } else if (mode == NOC_QOS_MODE_BYPASS) { + dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n", + qn->name); + } + + return regmap_update_bits(qp->regmap, + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + NOC_QOS_MODEn_MASK, mode); +} - /* send bandwidth request message to the RPM processor */ - if (qn->mas_rpm_id != -1) { +static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) +{ + struct qcom_icc_provider *qp = to_qcom_provider(node->provider); + struct qcom_icc_node *qn = node->data; + + dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); + + if (qp->is_bimc_node) + return qcom_icc_set_bimc_qos(node, sum_bw); + + return qcom_icc_set_noc_qos(node, sum_bw); +} + +static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) +{ + int ret = 0; + + if (mas_rpm_id != -1) { ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, RPM_BUS_MASTER_REQ, - qn->mas_rpm_id, + mas_rpm_id, sum_bw); if (ret) { pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", - qn->mas_rpm_id, ret); + mas_rpm_id, ret); return ret; } } - if (qn->slv_rpm_id != -1) { + if (slv_rpm_id != -1) { ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, RPM_BUS_SLAVE_REQ, - qn->slv_rpm_id, + slv_rpm_id, sum_bw); if (ret) { pr_err("qcom_icc_rpm_smd_send slv %d error %d\n", - qn->slv_rpm_id, ret); + slv_rpm_id, ret); return ret; } } + return ret; +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + struct icc_node *n; + u64 sum_bw; + u64 max_peak_bw; + u64 rate; + u32 agg_avg = 0; + u32 agg_peak = 0; + int ret, i; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + list_for_each_entry(n, &provider->nodes, node_list) + provider->aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + sum_bw = icc_units_to_bps(agg_avg); + max_peak_bw = icc_units_to_bps(agg_peak); + + if (!qn->qos.ap_owned) { + /* send bandwidth request message to the RPM processor */ + ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); + if (ret) + return ret; + } else if (qn->qos.qos_mode != -1) { + /* set bandwidth directly from the AP */ + ret = qcom_icc_qos_set(src, sum_bw); + if (ret) + return ret; + } + rate = max(sum_bw, max_peak_bw); do_div(rate, qn->buswidth); @@ -115,8 +283,13 @@ int qnoc_probe(struct platform_device *pdev) qnodes = desc->nodes; num_nodes = desc->num_nodes; - cds = bus_clocks; - cd_num = ARRAY_SIZE(bus_clocks); + if (desc->num_clocks) { + cds = desc->clocks; + cd_num = desc->num_clocks; + } else { + cds = bus_clocks; + cd_num = ARRAY_SIZE(bus_clocks); + } qp = devm_kzalloc(dev, struct_size(qp, bus_clks, cd_num), GFP_KERNEL); if (!qp) @@ -131,6 +304,30 @@ int qnoc_probe(struct platform_device *pdev) qp->bus_clks[i].id = cds[i]; qp->num_clks = cd_num; + qp->is_bimc_node = desc->is_bimc_node; + + if (desc->regmap_cfg) { + struct resource *res; + void __iomem *mmio; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + mmio = devm_ioremap_resource(dev, res); + + if (IS_ERR(mmio)) { + dev_err(dev, "Cannot ioremap interconnect bus resource\n"); + return PTR_ERR(mmio); + } + + qp->regmap = devm_regmap_init_mmio(dev, mmio, desc->regmap_cfg); + if (IS_ERR(qp->regmap)) { + dev_err(dev, "Cannot regmap interconnect bus resource\n"); + return PTR_ERR(qp->regmap); + } + } + ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); if (ret) return ret; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index f4b05c20c097..868585c80f38 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -9,8 +9,6 @@ #define RPM_BUS_MASTER_REQ 0x73616d62 #define RPM_BUS_SLAVE_REQ 0x766c7362 -#define QCOM_MAX_LINKS 12 - #define to_qcom_provider(_provider) \ container_of(_provider, struct qcom_icc_provider, provider) @@ -19,13 +17,35 @@ * @provider: generic interconnect provider * @bus_clks: the clk_bulk_data table of bus clocks * @num_clks: the total number of clk_bulk_data entries + * @is_bimc_node: indicates whether to use bimc specific setting + * @regmap: regmap for QoS registers read/write access */ struct qcom_icc_provider { struct icc_provider provider; int num_clks; + bool is_bimc_node; + struct regmap *regmap; struct clk_bulk_data bus_clks[]; }; +/** + * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters + * @areq_prio: node requests priority + * @prio_level: priority level for bus communication + * @limit_commands: activate/deactivate limiter mode during runtime + * @ap_owned: indicates if the node is owned by the AP or by the RPM + * @qos_mode: default qos mode for this node + * @qos_port: qos port number for finding qos registers of this node + */ +struct qcom_icc_qos { + u32 areq_prio; + u32 prio_level; + bool limit_commands; + bool ap_owned; + int qos_mode; + int qos_port; +}; + /** * struct qcom_icc_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs @@ -35,36 +55,48 @@ struct qcom_icc_provider { * @buswidth: width of the interconnect between a node and the bus (bytes) * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves + * @qos: NoC QoS setting parameters * @rate: current bus clock rate in Hz */ struct qcom_icc_node { unsigned char *name; u16 id; - u16 links[QCOM_MAX_LINKS]; + const u16 *links; u16 num_links; u16 buswidth; int mas_rpm_id; int slv_rpm_id; + struct qcom_icc_qos qos; u64 rate; }; struct qcom_icc_desc { struct qcom_icc_node **nodes; size_t num_nodes; + const char ** clocks; + size_t num_clocks; + bool is_bimc_node; + const struct regmap_config *regmap_cfg; }; #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ ...) \ + static const u16 _name ## _links[] = { __VA_ARGS__ }; \ + \ static struct qcom_icc_node _name = { \ .name = #_name, \ .id = _id, \ .buswidth = _buswidth, \ .mas_rpm_id = _mas_rpm_id, \ .slv_rpm_id = _slv_rpm_id, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ - .links = { __VA_ARGS__ }, \ + .num_links = ARRAY_SIZE(_name ## _links), \ + .links = _name ## _links, \ } +/* Valid for both NoC and BIMC */ +#define NOC_QOS_MODE_INVALID -1 +#define NOC_QOS_MODE_FIXED 0x0 +#define NOC_QOS_MODE_BYPASS 0x2 int qnoc_probe(struct platform_device *pdev); int qnoc_remove(struct platform_device *pdev); diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 4a72f9677d4e..384dd3661757 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -16,42 +16,9 @@ #include #include +#include "icc-rpm.h" #include "smd-rpm.h" -#define RPM_BUS_MASTER_REQ 0x73616d62 -#define RPM_BUS_SLAVE_REQ 0x766c7362 - -/* BIMC QoS */ -#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n)) -#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n)) -#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i)) - -#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000 -#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300 -#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3 -#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8 -#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f - -#define M_BKE_EN_EN_BMASK 0x1 - -/* Valid for both NoC and BIMC */ -#define NOC_QOS_MODE_INVALID -1 -#define NOC_QOS_MODE_FIXED 0x0 -#define NOC_QOS_MODE_LIMITER 0x1 -#define NOC_QOS_MODE_BYPASS 0x2 - -/* NoC QoS */ -#define NOC_PERM_MODE_FIXED 1 -#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS) - -#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000)) -#define NOC_QOS_PRIORITY_P1_MASK 0xc -#define NOC_QOS_PRIORITY_P0_MASK 0x3 -#define NOC_QOS_PRIORITY_P1_SHIFT 0x2 - -#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) -#define NOC_QOS_MODEn_MASK 0x3 - enum { SDM660_MASTER_IPA = 1, SDM660_MASTER_CNOC_A2NOC, @@ -160,94 +127,20 @@ enum { SDM660_SNOC, }; -#define to_qcom_provider(_provider) \ - container_of(_provider, struct qcom_icc_provider, provider) - -static const struct clk_bulk_data bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, +static const char * bus_mm_clocks[] = { + "bus", + "bus_a", + "iface", }; -static const struct clk_bulk_data bus_mm_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, - { .id = "iface" }, -}; - -static const struct clk_bulk_data bus_a2noc_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, - { .id = "ipa" }, - { .id = "ufs_axi" }, - { .id = "aggre2_ufs_axi" }, - { .id = "aggre2_usb3_axi" }, - { .id = "cfg_noc_usb2_axi" }, -}; - -/** - * struct qcom_icc_provider - Qualcomm specific interconnect provider - * @provider: generic interconnect provider - * @bus_clks: the clk_bulk_data table of bus clocks - * @num_clks: the total number of clk_bulk_data entries - * @is_bimc_node: indicates whether to use bimc specific setting - * @regmap: regmap for QoS registers read/write access - * @mmio: NoC base iospace - */ -struct qcom_icc_provider { - struct icc_provider provider; - struct clk_bulk_data *bus_clks; - int num_clks; - bool is_bimc_node; - struct regmap *regmap; - void __iomem *mmio; -}; - -/** - * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters - * @areq_prio: node requests priority - * @prio_level: priority level for bus communication - * @limit_commands: activate/deactivate limiter mode during runtime - * @ap_owned: indicates if the node is owned by the AP or by the RPM - * @qos_mode: default qos mode for this node - * @qos_port: qos port number for finding qos registers of this node - */ -struct qcom_icc_qos { - u32 areq_prio; - u32 prio_level; - bool limit_commands; - bool ap_owned; - int qos_mode; - int qos_port; -}; - -/** - * struct qcom_icc_node - Qualcomm specific interconnect nodes - * @name: the node name used in debugfs - * @id: a unique node identifier - * @links: an array of nodes where we can go next while traversing - * @num_links: the total number of @links - * @buswidth: width of the interconnect between a node and the bus (bytes) - * @mas_rpm_id: RPM id for devices that are bus masters - * @slv_rpm_id: RPM id for devices that are bus slaves - * @qos: NoC QoS setting parameters - * @rate: current bus clock rate in Hz - */ -struct qcom_icc_node { - unsigned char *name; - u16 id; - const u16 *links; - u16 num_links; - u16 buswidth; - int mas_rpm_id; - int slv_rpm_id; - struct qcom_icc_qos qos; - u64 rate; -}; - -struct qcom_icc_desc { - struct qcom_icc_node **nodes; - size_t num_nodes; - const struct regmap_config *regmap_cfg; +static const char * bus_a2noc_clocks[] = { + "bus", + "bus_a", + "ipa", + "ufs_axi", + "aggre2_ufs_axi", + "aggre2_usb3_axi", + "cfg_noc_usb2_axi", }; static const u16 mas_ipa_links[] = { @@ -1622,6 +1515,8 @@ static const struct regmap_config sdm660_a2noc_regmap_config = { static struct qcom_icc_desc sdm660_a2noc = { .nodes = sdm660_a2noc_nodes, .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), + .clocks = bus_a2noc_clocks, + .num_clocks = ARRAY_SIZE(bus_a2noc_clocks), .regmap_cfg = &sdm660_a2noc_regmap_config, }; @@ -1647,6 +1542,7 @@ static const struct regmap_config sdm660_bimc_regmap_config = { static struct qcom_icc_desc sdm660_bimc = { .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), + .is_bimc_node = true, .regmap_cfg = &sdm660_bimc_regmap_config, }; @@ -1759,6 +1655,8 @@ static const struct regmap_config sdm660_mnoc_regmap_config = { static struct qcom_icc_desc sdm660_mnoc = { .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), + .clocks = bus_mm_clocks, + .num_clocks = ARRAY_SIZE(bus_mm_clocks), .regmap_cfg = &sdm660_mnoc_regmap_config, }; @@ -1796,353 +1694,6 @@ static struct qcom_icc_desc sdm660_snoc = { .regmap_cfg = &sdm660_snoc_regmap_config, }; -static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, - struct qcom_icc_qos *qos, - int regnum) -{ - u32 val; - u32 mask; - - val = qos->prio_level; - mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK; - - val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT; - mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK; - - /* LIMITCMDS is not present on M_BKE_HEALTH_3 */ - if (regnum != 3) { - val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT; - mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; - } - - return regmap_update_bits(rmap, - M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), - mask, val); -} - -static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, - bool bypass_mode) -{ - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - u32 mode = NOC_QOS_MODE_BYPASS; - u32 val = 0; - int i, rc = 0; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) - mode = qn->qos.qos_mode; - - /* QoS Priority: The QoS Health parameters are getting considered - * only if we are NOT in Bypass Mode. - */ - if (mode != NOC_QOS_MODE_BYPASS) { - for (i = 3; i >= 0; i--) { - rc = qcom_icc_bimc_set_qos_health(qp->regmap, - &qn->qos, i); - if (rc) - return rc; - } - - /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */ - val = 1; - } - - return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), - M_BKE_EN_EN_BMASK, val); -} - -static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, - struct qcom_icc_qos *qos) -{ - u32 val; - int rc; - - /* Must be updated one at a time, P1 first, P0 last */ - val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; - rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), - NOC_QOS_PRIORITY_P1_MASK, val); - if (rc) - return rc; - - return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), - NOC_QOS_PRIORITY_P0_MASK, qos->prio_level); -} - -static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) -{ - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - u32 mode = NOC_QOS_MODE_BYPASS; - int rc = 0; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - if (qn->qos.qos_port < 0) { - dev_dbg(src->provider->dev, - "NoC QoS: Skipping %s: vote aggregated on parent.\n", - qn->name); - return 0; - } - - if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) - mode = qn->qos.qos_mode; - - if (mode == NOC_QOS_MODE_FIXED) { - dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", - qn->name); - rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); - if (rc) - return rc; - } else if (mode == NOC_QOS_MODE_BYPASS) { - dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n", - qn->name); - } - - return regmap_update_bits(qp->regmap, - NOC_QOS_MODEn_ADDR(qn->qos.qos_port), - NOC_QOS_MODEn_MASK, mode); -} - -static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) -{ - struct qcom_icc_provider *qp = to_qcom_provider(node->provider); - struct qcom_icc_node *qn = node->data; - - dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); - - if (qp->is_bimc_node) - return qcom_icc_set_bimc_qos(node, sum_bw, - (qn->qos.qos_mode == NOC_QOS_MODE_BYPASS)); - - return qcom_icc_set_noc_qos(node, sum_bw); -} - -static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) -{ - int ret = 0; - - if (mas_rpm_id != -1) { - ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, - RPM_BUS_MASTER_REQ, - mas_rpm_id, - sum_bw); - if (ret) { - pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", - mas_rpm_id, ret); - return ret; - } - } - - if (slv_rpm_id != -1) { - ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, - RPM_BUS_SLAVE_REQ, - slv_rpm_id, - sum_bw); - if (ret) { - pr_err("qcom_icc_rpm_smd_send slv %d error %d\n", - slv_rpm_id, ret); - return ret; - } - } - - return ret; -} - -static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) -{ - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - struct icc_node *n; - u64 sum_bw; - u64 max_peak_bw; - u64 rate; - u32 agg_avg = 0; - u32 agg_peak = 0; - int ret, i; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); - - sum_bw = icc_units_to_bps(agg_avg); - max_peak_bw = icc_units_to_bps(agg_peak); - - if (!qn->qos.ap_owned) { - /* send bandwidth request message to the RPM processor */ - ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); - if (ret) - return ret; - } else if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) { - /* set bandwidth directly from the AP */ - ret = qcom_icc_qos_set(src, sum_bw); - if (ret) - return ret; - } - - rate = max(sum_bw, max_peak_bw); - - do_div(rate, qn->buswidth); - - if (qn->rate == rate) - return 0; - - for (i = 0; i < qp->num_clks; i++) { - ret = clk_set_rate(qp->bus_clks[i].clk, rate); - if (ret) { - pr_err("%s clk_set_rate error: %d\n", - qp->bus_clks[i].id, ret); - return ret; - } - } - - qn->rate = rate; - - return 0; -} - -static int qnoc_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct qcom_icc_desc *desc; - struct icc_onecell_data *data; - struct icc_provider *provider; - struct qcom_icc_node **qnodes; - struct qcom_icc_provider *qp; - struct icc_node *node; - struct resource *res; - size_t num_nodes, i; - int ret; - - /* wait for the RPM proxy */ - if (!qcom_icc_rpm_smd_available()) - return -EPROBE_DEFER; - - desc = of_device_get_match_data(dev); - if (!desc) - return -EINVAL; - - qnodes = desc->nodes; - num_nodes = desc->num_nodes; - - qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); - if (!qp) - return -ENOMEM; - - data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), - GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (of_device_is_compatible(dev->of_node, "qcom,sdm660-mnoc")) { - qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks, - sizeof(bus_mm_clocks), GFP_KERNEL); - qp->num_clks = ARRAY_SIZE(bus_mm_clocks); - } else if (of_device_is_compatible(dev->of_node, "qcom,sdm660-a2noc")) { - qp->bus_clks = devm_kmemdup(dev, bus_a2noc_clocks, - sizeof(bus_a2noc_clocks), GFP_KERNEL); - qp->num_clks = ARRAY_SIZE(bus_a2noc_clocks); - } else { - if (of_device_is_compatible(dev->of_node, "qcom,sdm660-bimc")) - qp->is_bimc_node = true; - - qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks), - GFP_KERNEL); - qp->num_clks = ARRAY_SIZE(bus_clocks); - } - if (!qp->bus_clks) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - - qp->mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(qp->mmio)) { - dev_err(dev, "Cannot ioremap interconnect bus resource\n"); - return PTR_ERR(qp->mmio); - } - - qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg); - if (IS_ERR(qp->regmap)) { - dev_err(dev, "Cannot regmap interconnect bus resource\n"); - return PTR_ERR(qp->regmap); - } - - ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); - if (ret) - return ret; - - ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); - if (ret) - return ret; - - provider = &qp->provider; - INIT_LIST_HEAD(&provider->nodes); - provider->dev = dev; - provider->set = qcom_icc_set; - provider->aggregate = icc_std_aggregate; - provider->xlate = of_icc_xlate_onecell; - provider->data = data; - - ret = icc_provider_add(provider); - if (ret) { - dev_err(dev, "error adding interconnect provider: %d\n", ret); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - return ret; - } - - for (i = 0; i < num_nodes; i++) { - size_t j; - - node = icc_node_create(qnodes[i]->id); - if (IS_ERR(node)) { - ret = PTR_ERR(node); - goto err; - } - - node->name = qnodes[i]->name; - node->data = qnodes[i]; - icc_node_add(node, provider); - - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - - data->nodes[i] = node; - } - data->num_nodes = num_nodes; - platform_set_drvdata(pdev, qp); - - return 0; -err: - icc_nodes_remove(provider); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - icc_provider_del(provider); - - return ret; -} - -static int qnoc_remove(struct platform_device *pdev) -{ - struct qcom_icc_provider *qp = platform_get_drvdata(pdev); - - icc_nodes_remove(&qp->provider); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - return icc_provider_del(&qp->provider); -} - static const struct of_device_id sdm660_noc_of_match[] = { { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc }, { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc }, From patchwork Fri Sep 3 23:24:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 507064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5095EC433EF for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C0A56112F for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350764AbhICXZc (ORCPT ); Fri, 3 Sep 2021 19:25:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350758AbhICXZa (ORCPT ); Fri, 3 Sep 2021 19:25:30 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5090C061764 for ; Fri, 3 Sep 2021 16:24:29 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id i28so1151096ljm.7 for ; Fri, 03 Sep 2021 16:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sghiWtzlQ2rh7GwVQZPgVNRESKtI3sTnOWU+E5ytGWY=; b=qel2ha5l98HDglOR7KVyNaIQV6oghHJprK7J0b/eW0gJALtdPnrjGtTZlaae1gL0U+ zhc4+Bpv5EsP+88w9WMWAmKL7Gy5SmygUiImm/t2l3Vlb0G8UVSvlWi+MYAyyJSXEzxz L0GnP476/FNq2ItPdX4RpOVkl8BUtAZF/vXYJrJxALptUGVy9u8gJFa2aM9gx2bWD3Yn cvVxa1Ch1BcLswqrIiuhpuRHaA1cKQp30CBV/yUiANUPXalNBcsgVPimbRfFwg1iljM+ 8VVs9Ue0ACefayagCcPPvN5as6nNbHY/n/MaAnXEYtnNSMedS9P8tCkizqNR9YQ0Wlkr dehg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sghiWtzlQ2rh7GwVQZPgVNRESKtI3sTnOWU+E5ytGWY=; b=jVgQM7Z6uD3Q3deiDT3SBnz393zuOnYm8ftxRQYNTO1k4Mlb9GlBMkiKDutJ36v2qj Cn/IOG47xVutJ0iAQnBScuk3noAo2J1u5JFbc5XD3wA8aXbbP7CAv0uJsbXI3K7gTCwW +YYN8pZka5FSdI7LvxqQtxs4XhJEp4iyGhLtX2wmBdOdZpEn0PDVecfNBKOctqxrzH2D Wix4atHvQsaK+thTNQ0lm/My39pueMvg6TJtWAcMCLMsiI69fMg5B1pzDbdY5HBM0HCS mcd40J9nQb/ac+7LLUulTGcVkneQ6TTibbgJ2TowcjqgJY/8XCJrdGTMOg+TnookO7hD UVog== X-Gm-Message-State: AOAM530xPJNTHanOTEEimiKJyiBYPNYdiCfl/te+UxYy+Lyic49vfTfo EKUuXQvKoMYN47V2WncciAYeFb0cgB+eMg== X-Google-Smtp-Source: ABdhPJz7hzfKas67Hx3clwBLUCMwQpaomk+7Uwg/sYd87Ekj8t6SP/fQP0iqQccJiOhLhmxPfAk5aQ== X-Received: by 2002:a2e:991a:: with SMTP id v26mr987286lji.111.1630711468129; Fri, 03 Sep 2021 16:24:28 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 05/11] interconnect: icc-rpm: add support for QoS reg offset Date: Sat, 4 Sep 2021 02:24:15 +0300 Message-Id: <20210903232421.1384199-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDM660 driver expects to have QoS registers at the beginning of NoC address space (sdm660 platform shifts NoC base address). Add support for using QoS register offset, so that other platforms do not have to change existing device trees. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 24 ++++++++++++++---------- drivers/interconnect/qcom/icc-rpm.h | 3 +++ 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index b8bac738c64f..384b571fffec 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -39,7 +39,7 @@ #define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) #define NOC_QOS_MODEn_MASK 0x3 -static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, +static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos, int regnum) { @@ -58,8 +58,8 @@ static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; } - return regmap_update_bits(rmap, - M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), mask, val); } @@ -84,7 +84,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw) */ if (mode != NOC_QOS_MODE_BYPASS) { for (i = 3; i >= 0; i--) { - rc = qcom_icc_bimc_set_qos_health(qp->regmap, + rc = qcom_icc_bimc_set_qos_health(qp, &qn->qos, i); if (rc) return rc; @@ -94,11 +94,12 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw) val = 1; } - return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port), M_BKE_EN_EN_BMASK, val); } -static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, +static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos) { u32 val; @@ -106,12 +107,14 @@ static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, /* Must be updated one at a time, P1 first, P0 last */ val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; - rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + rc = regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), NOC_QOS_PRIORITY_P1_MASK, val); if (rc) return rc; - return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), NOC_QOS_PRIORITY_P0_MASK, qos->prio_level); } @@ -140,7 +143,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) if (mode == NOC_QOS_MODE_FIXED) { dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", qn->name); - rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); + rc = qcom_icc_noc_set_qos_priority(qp, &qn->qos); if (rc) return rc; } else if (mode == NOC_QOS_MODE_BYPASS) { @@ -149,7 +152,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) } return regmap_update_bits(qp->regmap, - NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), NOC_QOS_MODEn_MASK, mode); } @@ -305,6 +308,7 @@ int qnoc_probe(struct platform_device *pdev) qp->num_clks = cd_num; qp->is_bimc_node = desc->is_bimc_node; + qp->qos_offset = desc->qos_offset; if (desc->regmap_cfg) { struct resource *res; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 868585c80f38..f6746dabdf28 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -18,6 +18,7 @@ * @bus_clks: the clk_bulk_data table of bus clocks * @num_clks: the total number of clk_bulk_data entries * @is_bimc_node: indicates whether to use bimc specific setting + * @qos_offset: offset to QoS registers * @regmap: regmap for QoS registers read/write access */ struct qcom_icc_provider { @@ -25,6 +26,7 @@ struct qcom_icc_provider { int num_clks; bool is_bimc_node; struct regmap *regmap; + unsigned int qos_offset; struct clk_bulk_data bus_clks[]; }; @@ -77,6 +79,7 @@ struct qcom_icc_desc { size_t num_clocks; bool is_bimc_node; const struct regmap_config *regmap_cfg; + unsigned int qos_offset; }; #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ From patchwork Fri Sep 3 23:24:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5A59C4167D for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C910B610D2 for ; Fri, 3 Sep 2021 23:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350760AbhICXZd (ORCPT ); Fri, 3 Sep 2021 19:25:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350761AbhICXZb (ORCPT ); Fri, 3 Sep 2021 19:25:31 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A653AC0613C1 for ; Fri, 3 Sep 2021 16:24:30 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id t19so1289332lfe.13 for ; Fri, 03 Sep 2021 16:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BK0nmG2Nn2tbXUcW+f0zKb3IRo/TN9Pu/HCMinwTCJo=; b=YfQ4Q+I9ZUnc6bJsYEPBcQ8oHtCtpqWiVnm+5wCdB+BDNtQPvyZBwZSH9XAjMW0VBo xSlA2/0wUchqtfQvS6x3xMx8cV7rWHDhrhqea3IGJB/DqWGLd+8lpDuTmFtDqN7hMzw1 kPz6ORiyqaRFKoMNfbimugj8qjeppY4b51Lbd/aLtj6EXfvmYARQmuKVFXljYI4HZfRt pSJQA3IvPTZky1sD09SR5FFGv3hVbiyM1YYEjztcUedaya2CuFwllXJk+w7IFN4skZXh wUDjdUH0ndG//JsnXq2lBhDixAFN0PbxuW1eIEhiTswhB5QAcI/rFwcaMSIOVvq3GLO+ HCbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BK0nmG2Nn2tbXUcW+f0zKb3IRo/TN9Pu/HCMinwTCJo=; b=tqIaam/kbD42ZnKNe/xbf/s+zbWhYLuaPH8iz3hGmJbJrY6A7HMXZ/3GXSHyiJxvdG Nrj7MCgN/rFFRoN7jSeUjcTGPCLRZxAVZQ58FWcEPjQtN65GnA4jM20YET5ntCUtZK/n xTObTgiQnTw/DvBEpjAt4M2DUOdqKOVRqg/OqD5kagpTb2hk+MCN23stE1K0Kv0DwH2O GGPC3HbpgVJ8jFtSpnjIgA8EgObkNBzlWJLL2R2Nw4R1+Kk3qv47IcBKODg6a9+rIJtn SrP0UlaFdmX6r+ddvjHcu0YHq64PlcvjbXLsdRKBDnfcnIP4DhFzK28UyHoG7Ef9VVx2 oQfg== X-Gm-Message-State: AOAM5301P6RwlEU2cY66dvC2UkiA3w/65fq6/bYvZW4LDXz9L9mHH/hW gRhhDw0MdzqzOigZKKQ+yXc0bA== X-Google-Smtp-Source: ABdhPJzYq0jstbq4vUkyGh3c4Sh0MZjCRlNXZUsw7hsdBz5qHKlfkAEykQrCSa/HT+b2XGmyM1pHDQ== X-Received: by 2002:a05:6512:3f90:: with SMTP id x16mr979457lfa.518.1630711468845; Fri, 03 Sep 2021 16:24:28 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 06/11] interconnect: msm8916: expand DEFINE_QNODE macros Date: Sat, 4 Sep 2021 02:24:16 +0300 Message-Id: <20210903232421.1384199-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to adding AP-owned nodes support to msm8916 expand DEFINE_QNODE macros in the driver. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Reviewed-by: AngeloGioacchino Del Regno --- drivers/interconnect/qcom/msm8916.c | 1101 ++++++++++++++++++++++++--- 1 file changed, 1016 insertions(+), 85 deletions(-) diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index fc0d48d2997a..b7d662875c89 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -105,91 +105,1022 @@ enum { MSM8916_SNOC_PNOC_SLV, }; -DEFINE_QNODE(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 8, -1, -1, MSM8916_BIMC_SNOC_SLV); -DEFINE_QNODE(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1); -DEFINE_QNODE(mas_apss, MSM8916_MASTER_AMPSS_M0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_audio, MSM8916_MASTER_LPASS, 4, -1, -1, MSM8916_PNOC_MAS_0); -DEFINE_QNODE(mas_blsp_1, MSM8916_MASTER_BLSP_1, 4, -1, -1, MSM8916_PNOC_MAS_1); -DEFINE_QNODE(mas_dehr, MSM8916_MASTER_DEHR, 4, -1, -1, MSM8916_PNOC_MAS_0); -DEFINE_QNODE(mas_gfx, MSM8916_MASTER_GRAPHICS_3D, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_jpeg, MSM8916_MASTER_JPEG, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mas_mdp, MSM8916_MASTER_MDP_PORT0, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mas_pcnoc_crypto_0, MSM8916_MASTER_CRYPTO_CORE0, 8, -1, -1, MSM8916_PNOC_INT_1); -DEFINE_QNODE(mas_pcnoc_sdcc_1, MSM8916_MASTER_SDCC_1, 8, -1, -1, MSM8916_PNOC_INT_1); -DEFINE_QNODE(mas_pcnoc_sdcc_2, MSM8916_MASTER_SDCC_2, 8, -1, -1, MSM8916_PNOC_INT_1); -DEFINE_QNODE(mas_qdss_bam, MSM8916_MASTER_QDSS_BAM, 8, -1, -1, MSM8916_SNOC_QDSS_INT); -DEFINE_QNODE(mas_qdss_etr, MSM8916_MASTER_QDSS_ETR, 8, -1, -1, MSM8916_SNOC_QDSS_INT); -DEFINE_QNODE(mas_snoc_cfg, MSM8916_MASTER_SNOC_CFG, 4, -1, -1, MSM8916_SNOC_QDSS_INT); -DEFINE_QNODE(mas_spdm, MSM8916_MASTER_SPDM, 4, -1, -1, MSM8916_PNOC_MAS_0); -DEFINE_QNODE(mas_tcu0, MSM8916_MASTER_TCU0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_tcu1, MSM8916_MASTER_TCU1, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_usb_hs, MSM8916_MASTER_USB_HS, 4, -1, -1, MSM8916_PNOC_MAS_1); -DEFINE_QNODE(mas_vfe, MSM8916_MASTER_VFE, 16, -1, -1, MSM8916_SNOC_MM_INT_1, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mas_video, MSM8916_MASTER_VIDEO_P0, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mm_int_0, MSM8916_SNOC_MM_INT_0, 16, -1, -1, MSM8916_SNOC_MM_INT_BIMC); -DEFINE_QNODE(mm_int_1, MSM8916_SNOC_MM_INT_1, 16, -1, -1, MSM8916_SNOC_MM_INT_BIMC); -DEFINE_QNODE(mm_int_2, MSM8916_SNOC_MM_INT_2, 16, -1, -1, MSM8916_SNOC_INT_0); -DEFINE_QNODE(mm_int_bimc, MSM8916_SNOC_MM_INT_BIMC, 16, -1, -1, MSM8916_SNOC_BIMC_1_MAS); -DEFINE_QNODE(pcnoc_int_0, MSM8916_PNOC_INT_0, 8, -1, -1, MSM8916_PNOC_SNOC_MAS, MSM8916_PNOC_SLV_0, MSM8916_PNOC_SLV_1, MSM8916_PNOC_SLV_2, MSM8916_PNOC_SLV_3, MSM8916_PNOC_SLV_4, MSM8916_PNOC_SLV_8, MSM8916_PNOC_SLV_9); -DEFINE_QNODE(pcnoc_int_1, MSM8916_PNOC_INT_1, 8, -1, -1, MSM8916_PNOC_SNOC_MAS); -DEFINE_QNODE(pcnoc_m_0, MSM8916_PNOC_MAS_0, 8, -1, -1, MSM8916_PNOC_INT_0); -DEFINE_QNODE(pcnoc_m_1, MSM8916_PNOC_MAS_1, 8, -1, -1, MSM8916_PNOC_SNOC_MAS); -DEFINE_QNODE(pcnoc_s_0, MSM8916_PNOC_SLV_0, 4, -1, -1, MSM8916_SLAVE_CLK_CTL, MSM8916_SLAVE_TLMM, MSM8916_SLAVE_TCSR, MSM8916_SLAVE_SECURITY, MSM8916_SLAVE_MSS); -DEFINE_QNODE(pcnoc_s_1, MSM8916_PNOC_SLV_1, 4, -1, -1, MSM8916_SLAVE_IMEM_CFG, MSM8916_SLAVE_CRYPTO_0_CFG, MSM8916_SLAVE_MSG_RAM, MSM8916_SLAVE_PDM, MSM8916_SLAVE_PRNG); -DEFINE_QNODE(pcnoc_s_2, MSM8916_PNOC_SLV_2, 4, -1, -1, MSM8916_SLAVE_SPDM, MSM8916_SLAVE_BOOT_ROM, MSM8916_SLAVE_BIMC_CFG, MSM8916_SLAVE_PNOC_CFG, MSM8916_SLAVE_PMIC_ARB); -DEFINE_QNODE(pcnoc_s_3, MSM8916_PNOC_SLV_3, 4, -1, -1, MSM8916_SLAVE_MPM, MSM8916_SLAVE_SNOC_CFG, MSM8916_SLAVE_RBCPR_CFG, MSM8916_SLAVE_QDSS_CFG, MSM8916_SLAVE_DEHR_CFG); -DEFINE_QNODE(pcnoc_s_4, MSM8916_PNOC_SLV_4, 4, -1, -1, MSM8916_SLAVE_VENUS_CFG, MSM8916_SLAVE_CAMERA_CFG, MSM8916_SLAVE_DISPLAY_CFG); -DEFINE_QNODE(pcnoc_s_8, MSM8916_PNOC_SLV_8, 4, -1, -1, MSM8916_SLAVE_USB_HS, MSM8916_SLAVE_SDCC_1, MSM8916_SLAVE_BLSP_1); -DEFINE_QNODE(pcnoc_s_9, MSM8916_PNOC_SLV_9, 4, -1, -1, MSM8916_SLAVE_SDCC_2, MSM8916_SLAVE_LPASS, MSM8916_SLAVE_GRAPHICS_3D_CFG); -DEFINE_QNODE(pcnoc_snoc_mas, MSM8916_PNOC_SNOC_MAS, 8, 29, -1, MSM8916_PNOC_SNOC_SLV); -DEFINE_QNODE(pcnoc_snoc_slv, MSM8916_PNOC_SNOC_SLV, 8, -1, 45, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC, MSM8916_SNOC_INT_1); -DEFINE_QNODE(qdss_int, MSM8916_SNOC_QDSS_INT, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC); -DEFINE_QNODE(slv_apps_l2, MSM8916_SLAVE_AMPSS_L2, 8, -1, -1, 0); -DEFINE_QNODE(slv_apss, MSM8916_SLAVE_APSS, 4, -1, -1, 0); -DEFINE_QNODE(slv_audio, MSM8916_SLAVE_LPASS, 4, -1, -1, 0); -DEFINE_QNODE(slv_bimc_cfg, MSM8916_SLAVE_BIMC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_blsp_1, MSM8916_SLAVE_BLSP_1, 4, -1, -1, 0); -DEFINE_QNODE(slv_boot_rom, MSM8916_SLAVE_BOOT_ROM, 4, -1, -1, 0); -DEFINE_QNODE(slv_camera_cfg, MSM8916_SLAVE_CAMERA_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_cats_0, MSM8916_SLAVE_CATS_128, 16, -1, -1, 0); -DEFINE_QNODE(slv_cats_1, MSM8916_SLAVE_OCMEM_64, 8, -1, -1, 0); -DEFINE_QNODE(slv_clk_ctl, MSM8916_SLAVE_CLK_CTL, 4, -1, -1, 0); -DEFINE_QNODE(slv_crypto_0_cfg, MSM8916_SLAVE_CRYPTO_0_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_dehr_cfg, MSM8916_SLAVE_DEHR_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_display_cfg, MSM8916_SLAVE_DISPLAY_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_ebi_ch0, MSM8916_SLAVE_EBI_CH0, 8, -1, 0, 0); -DEFINE_QNODE(slv_gfx_cfg, MSM8916_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_imem_cfg, MSM8916_SLAVE_IMEM_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_imem, MSM8916_SLAVE_IMEM, 8, -1, 26, 0); -DEFINE_QNODE(slv_mpm, MSM8916_SLAVE_MPM, 4, -1, -1, 0); -DEFINE_QNODE(slv_msg_ram, MSM8916_SLAVE_MSG_RAM, 4, -1, -1, 0); -DEFINE_QNODE(slv_mss, MSM8916_SLAVE_MSS, 4, -1, -1, 0); -DEFINE_QNODE(slv_pdm, MSM8916_SLAVE_PDM, 4, -1, -1, 0); -DEFINE_QNODE(slv_pmic_arb, MSM8916_SLAVE_PMIC_ARB, 4, -1, -1, 0); -DEFINE_QNODE(slv_pcnoc_cfg, MSM8916_SLAVE_PNOC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_prng, MSM8916_SLAVE_PRNG, 4, -1, -1, 0); -DEFINE_QNODE(slv_qdss_cfg, MSM8916_SLAVE_QDSS_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_qdss_stm, MSM8916_SLAVE_QDSS_STM, 4, -1, 30, 0); -DEFINE_QNODE(slv_rbcpr_cfg, MSM8916_SLAVE_RBCPR_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_sdcc_1, MSM8916_SLAVE_SDCC_1, 4, -1, -1, 0); -DEFINE_QNODE(slv_sdcc_2, MSM8916_SLAVE_SDCC_2, 4, -1, -1, 0); -DEFINE_QNODE(slv_security, MSM8916_SLAVE_SECURITY, 4, -1, -1, 0); -DEFINE_QNODE(slv_snoc_cfg, MSM8916_SLAVE_SNOC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_spdm, MSM8916_SLAVE_SPDM, 4, -1, -1, 0); -DEFINE_QNODE(slv_srvc_snoc, MSM8916_SLAVE_SRVC_SNOC, 8, -1, -1, 0); -DEFINE_QNODE(slv_tcsr, MSM8916_SLAVE_TCSR, 4, -1, -1, 0); -DEFINE_QNODE(slv_tlmm, MSM8916_SLAVE_TLMM, 4, -1, -1, 0); -DEFINE_QNODE(slv_usb_hs, MSM8916_SLAVE_USB_HS, 4, -1, -1, 0); -DEFINE_QNODE(slv_venus_cfg, MSM8916_SLAVE_VENUS_CFG, 4, -1, -1, 0); -DEFINE_QNODE(snoc_bimc_0_mas, MSM8916_SNOC_BIMC_0_MAS, 8, 3, -1, MSM8916_SNOC_BIMC_0_SLV); -DEFINE_QNODE(snoc_bimc_0_slv, MSM8916_SNOC_BIMC_0_SLV, 8, -1, 24, MSM8916_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_bimc_1_mas, MSM8916_SNOC_BIMC_1_MAS, 16, -1, -1, MSM8916_SNOC_BIMC_1_SLV); -DEFINE_QNODE(snoc_bimc_1_slv, MSM8916_SNOC_BIMC_1_SLV, 8, -1, -1, MSM8916_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_int_0, MSM8916_SNOC_INT_0, 8, 99, 130, MSM8916_SLAVE_QDSS_STM, MSM8916_SLAVE_IMEM, MSM8916_SNOC_PNOC_MAS); -DEFINE_QNODE(snoc_int_1, MSM8916_SNOC_INT_1, 8, -1, -1, MSM8916_SLAVE_APSS, MSM8916_SLAVE_CATS_128, MSM8916_SLAVE_OCMEM_64); -DEFINE_QNODE(snoc_int_bimc, MSM8916_SNOC_INT_BIMC, 8, 101, 132, MSM8916_SNOC_BIMC_0_MAS); -DEFINE_QNODE(snoc_pcnoc_mas, MSM8916_SNOC_PNOC_MAS, 8, -1, -1, MSM8916_SNOC_PNOC_SLV); -DEFINE_QNODE(snoc_pcnoc_slv, MSM8916_SNOC_PNOC_SLV, 8, -1, -1, MSM8916_PNOC_INT_0); +static const u16 bimc_snoc_mas_links[] = { + MSM8916_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node bimc_snoc_mas = { + .name = "bimc_snoc_mas", + .id = MSM8916_BIMC_SNOC_MAS, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(bimc_snoc_mas_links), + .links = bimc_snoc_mas_links, +}; + +static const u16 bimc_snoc_slv_links[] = { + MSM8916_SNOC_INT_0, + MSM8916_SNOC_INT_1 +}; + +static struct qcom_icc_node bimc_snoc_slv = { + .name = "bimc_snoc_slv", + .id = MSM8916_BIMC_SNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(bimc_snoc_slv_links), + .links = bimc_snoc_slv_links, +}; + +static const u16 mas_apss_links[] = { + MSM8916_SLAVE_EBI_CH0, + MSM8916_BIMC_SNOC_MAS, + MSM8916_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_apss = { + .name = "mas_apss", + .id = MSM8916_MASTER_AMPSS_M0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_apss_links), + .links = mas_apss_links, +}; + +static const u16 mas_audio_links[] = { + MSM8916_PNOC_MAS_0 +}; + +static struct qcom_icc_node mas_audio = { + .name = "mas_audio", + .id = MSM8916_MASTER_LPASS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_audio_links), + .links = mas_audio_links, +}; + +static const u16 mas_blsp_1_links[] = { + MSM8916_PNOC_MAS_1 +}; + +static struct qcom_icc_node mas_blsp_1 = { + .name = "mas_blsp_1", + .id = MSM8916_MASTER_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_blsp_1_links), + .links = mas_blsp_1_links, +}; + +static const u16 mas_dehr_links[] = { + MSM8916_PNOC_MAS_0 +}; + +static struct qcom_icc_node mas_dehr = { + .name = "mas_dehr", + .id = MSM8916_MASTER_DEHR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_dehr_links), + .links = mas_dehr_links, +}; + +static const u16 mas_gfx_links[] = { + MSM8916_SLAVE_EBI_CH0, + MSM8916_BIMC_SNOC_MAS, + MSM8916_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_gfx = { + .name = "mas_gfx", + .id = MSM8916_MASTER_GRAPHICS_3D, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_gfx_links), + .links = mas_gfx_links, +}; + +static const u16 mas_jpeg_links[] = { + MSM8916_SNOC_MM_INT_0, + MSM8916_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_jpeg = { + .name = "mas_jpeg", + .id = MSM8916_MASTER_JPEG, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_jpeg_links), + .links = mas_jpeg_links, +}; + +static const u16 mas_mdp_links[] = { + MSM8916_SNOC_MM_INT_0, + MSM8916_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_mdp = { + .name = "mas_mdp", + .id = MSM8916_MASTER_MDP_PORT0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_mdp_links), + .links = mas_mdp_links, +}; + +static const u16 mas_pcnoc_crypto_0_links[] = { + MSM8916_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcnoc_crypto_0 = { + .name = "mas_pcnoc_crypto_0", + .id = MSM8916_MASTER_CRYPTO_CORE0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links), + .links = mas_pcnoc_crypto_0_links, +}; + +static const u16 mas_pcnoc_sdcc_1_links[] = { + MSM8916_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcnoc_sdcc_1 = { + .name = "mas_pcnoc_sdcc_1", + .id = MSM8916_MASTER_SDCC_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links), + .links = mas_pcnoc_sdcc_1_links, +}; + +static const u16 mas_pcnoc_sdcc_2_links[] = { + MSM8916_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcnoc_sdcc_2 = { + .name = "mas_pcnoc_sdcc_2", + .id = MSM8916_MASTER_SDCC_2, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links), + .links = mas_pcnoc_sdcc_2_links, +}; + +static const u16 mas_qdss_bam_links[] = { + MSM8916_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam = { + .name = "mas_qdss_bam", + .id = MSM8916_MASTER_QDSS_BAM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_bam_links), + .links = mas_qdss_bam_links, +}; + +static const u16 mas_qdss_etr_links[] = { + MSM8916_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr = { + .name = "mas_qdss_etr", + .id = MSM8916_MASTER_QDSS_ETR, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_etr_links), + .links = mas_qdss_etr_links, +}; + +static const u16 mas_snoc_cfg_links[] = { + MSM8916_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_snoc_cfg = { + .name = "mas_snoc_cfg", + .id = MSM8916_MASTER_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_cfg_links), + .links = mas_snoc_cfg_links, +}; + +static const u16 mas_spdm_links[] = { + MSM8916_PNOC_MAS_0 +}; + +static struct qcom_icc_node mas_spdm = { + .name = "mas_spdm", + .id = MSM8916_MASTER_SPDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_spdm_links), + .links = mas_spdm_links, +}; + +static const u16 mas_tcu0_links[] = { + MSM8916_SLAVE_EBI_CH0, + MSM8916_BIMC_SNOC_MAS, + MSM8916_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_tcu0 = { + .name = "mas_tcu0", + .id = MSM8916_MASTER_TCU0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_tcu0_links), + .links = mas_tcu0_links, +}; + +static const u16 mas_tcu1_links[] = { + MSM8916_SLAVE_EBI_CH0, + MSM8916_BIMC_SNOC_MAS, + MSM8916_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_tcu1 = { + .name = "mas_tcu1", + .id = MSM8916_MASTER_TCU1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_tcu1_links), + .links = mas_tcu1_links, +}; + +static const u16 mas_usb_hs_links[] = { + MSM8916_PNOC_MAS_1 +}; + +static struct qcom_icc_node mas_usb_hs = { + .name = "mas_usb_hs", + .id = MSM8916_MASTER_USB_HS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_usb_hs_links), + .links = mas_usb_hs_links, +}; + +static const u16 mas_vfe_links[] = { + MSM8916_SNOC_MM_INT_1, + MSM8916_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_vfe = { + .name = "mas_vfe", + .id = MSM8916_MASTER_VFE, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_vfe_links), + .links = mas_vfe_links, +}; + +static const u16 mas_video_links[] = { + MSM8916_SNOC_MM_INT_0, + MSM8916_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_video = { + .name = "mas_video", + .id = MSM8916_MASTER_VIDEO_P0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_video_links), + .links = mas_video_links, +}; + +static const u16 mm_int_0_links[] = { + MSM8916_SNOC_MM_INT_BIMC +}; + +static struct qcom_icc_node mm_int_0 = { + .name = "mm_int_0", + .id = MSM8916_SNOC_MM_INT_0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_0_links), + .links = mm_int_0_links, +}; + +static const u16 mm_int_1_links[] = { + MSM8916_SNOC_MM_INT_BIMC +}; + +static struct qcom_icc_node mm_int_1 = { + .name = "mm_int_1", + .id = MSM8916_SNOC_MM_INT_1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_1_links), + .links = mm_int_1_links, +}; + +static const u16 mm_int_2_links[] = { + MSM8916_SNOC_INT_0 +}; + +static struct qcom_icc_node mm_int_2 = { + .name = "mm_int_2", + .id = MSM8916_SNOC_MM_INT_2, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_2_links), + .links = mm_int_2_links, +}; + +static const u16 mm_int_bimc_links[] = { + MSM8916_SNOC_BIMC_1_MAS +}; + +static struct qcom_icc_node mm_int_bimc = { + .name = "mm_int_bimc", + .id = MSM8916_SNOC_MM_INT_BIMC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_bimc_links), + .links = mm_int_bimc_links, +}; + +static const u16 pcnoc_int_0_links[] = { + MSM8916_PNOC_SNOC_MAS, + MSM8916_PNOC_SLV_0, + MSM8916_PNOC_SLV_1, + MSM8916_PNOC_SLV_2, + MSM8916_PNOC_SLV_3, + MSM8916_PNOC_SLV_4, + MSM8916_PNOC_SLV_8, + MSM8916_PNOC_SLV_9 +}; + +static struct qcom_icc_node pcnoc_int_0 = { + .name = "pcnoc_int_0", + .id = MSM8916_PNOC_INT_0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_int_0_links), + .links = pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_1_links[] = { + MSM8916_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node pcnoc_int_1 = { + .name = "pcnoc_int_1", + .id = MSM8916_PNOC_INT_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_int_1_links), + .links = pcnoc_int_1_links, +}; + +static const u16 pcnoc_m_0_links[] = { + MSM8916_PNOC_INT_0 +}; + +static struct qcom_icc_node pcnoc_m_0 = { + .name = "pcnoc_m_0", + .id = MSM8916_PNOC_MAS_0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_m_0_links), + .links = pcnoc_m_0_links, +}; + +static const u16 pcnoc_m_1_links[] = { + MSM8916_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node pcnoc_m_1 = { + .name = "pcnoc_m_1", + .id = MSM8916_PNOC_MAS_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_m_1_links), + .links = pcnoc_m_1_links, +}; + +static const u16 pcnoc_s_0_links[] = { + MSM8916_SLAVE_CLK_CTL, + MSM8916_SLAVE_TLMM, + MSM8916_SLAVE_TCSR, + MSM8916_SLAVE_SECURITY, + MSM8916_SLAVE_MSS +}; + +static struct qcom_icc_node pcnoc_s_0 = { + .name = "pcnoc_s_0", + .id = MSM8916_PNOC_SLV_0, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_0_links), + .links = pcnoc_s_0_links, +}; + +static const u16 pcnoc_s_1_links[] = { + MSM8916_SLAVE_IMEM_CFG, + MSM8916_SLAVE_CRYPTO_0_CFG, + MSM8916_SLAVE_MSG_RAM, + MSM8916_SLAVE_PDM, + MSM8916_SLAVE_PRNG +}; + +static struct qcom_icc_node pcnoc_s_1 = { + .name = "pcnoc_s_1", + .id = MSM8916_PNOC_SLV_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_1_links), + .links = pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] = { + MSM8916_SLAVE_SPDM, + MSM8916_SLAVE_BOOT_ROM, + MSM8916_SLAVE_BIMC_CFG, + MSM8916_SLAVE_PNOC_CFG, + MSM8916_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_2 = { + .name = "pcnoc_s_2", + .id = MSM8916_PNOC_SLV_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_2_links), + .links = pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] = { + MSM8916_SLAVE_MPM, + MSM8916_SLAVE_SNOC_CFG, + MSM8916_SLAVE_RBCPR_CFG, + MSM8916_SLAVE_QDSS_CFG, + MSM8916_SLAVE_DEHR_CFG +}; + +static struct qcom_icc_node pcnoc_s_3 = { + .name = "pcnoc_s_3", + .id = MSM8916_PNOC_SLV_3, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_3_links), + .links = pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] = { + MSM8916_SLAVE_VENUS_CFG, + MSM8916_SLAVE_CAMERA_CFG, + MSM8916_SLAVE_DISPLAY_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 = { + .name = "pcnoc_s_4", + .id = MSM8916_PNOC_SLV_4, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_4_links), + .links = pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_8_links[] = { + MSM8916_SLAVE_USB_HS, + MSM8916_SLAVE_SDCC_1, + MSM8916_SLAVE_BLSP_1 +}; + +static struct qcom_icc_node pcnoc_s_8 = { + .name = "pcnoc_s_8", + .id = MSM8916_PNOC_SLV_8, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_8_links), + .links = pcnoc_s_8_links, +}; + +static const u16 pcnoc_s_9_links[] = { + MSM8916_SLAVE_SDCC_2, + MSM8916_SLAVE_LPASS, + MSM8916_SLAVE_GRAPHICS_3D_CFG +}; + +static struct qcom_icc_node pcnoc_s_9 = { + .name = "pcnoc_s_9", + .id = MSM8916_PNOC_SLV_9, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_9_links), + .links = pcnoc_s_9_links, +}; + +static const u16 pcnoc_snoc_mas_links[] = { + MSM8916_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_snoc_mas = { + .name = "pcnoc_snoc_mas", + .id = MSM8916_PNOC_SNOC_MAS, + .buswidth = 8, + .mas_rpm_id = 29, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links), + .links = pcnoc_snoc_mas_links, +}; + +static const u16 pcnoc_snoc_slv_links[] = { + MSM8916_SNOC_INT_0, + MSM8916_SNOC_INT_BIMC, + MSM8916_SNOC_INT_1 +}; + +static struct qcom_icc_node pcnoc_snoc_slv = { + .name = "pcnoc_snoc_slv", + .id = MSM8916_PNOC_SNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 45, + .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links), + .links = pcnoc_snoc_slv_links, +}; + +static const u16 qdss_int_links[] = { + MSM8916_SNOC_INT_0, + MSM8916_SNOC_INT_BIMC +}; + +static struct qcom_icc_node qdss_int = { + .name = "qdss_int", + .id = MSM8916_SNOC_QDSS_INT, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qdss_int_links), + .links = qdss_int_links, +}; + +static struct qcom_icc_node slv_apps_l2 = { + .name = "slv_apps_l2", + .id = MSM8916_SLAVE_AMPSS_L2, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_apss = { + .name = "slv_apss", + .id = MSM8916_SLAVE_APSS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_audio = { + .name = "slv_audio", + .id = MSM8916_SLAVE_LPASS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_bimc_cfg = { + .name = "slv_bimc_cfg", + .id = MSM8916_SLAVE_BIMC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_blsp_1 = { + .name = "slv_blsp_1", + .id = MSM8916_SLAVE_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_boot_rom = { + .name = "slv_boot_rom", + .id = MSM8916_SLAVE_BOOT_ROM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_camera_cfg = { + .name = "slv_camera_cfg", + .id = MSM8916_SLAVE_CAMERA_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_cats_0 = { + .name = "slv_cats_0", + .id = MSM8916_SLAVE_CATS_128, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_cats_1 = { + .name = "slv_cats_1", + .id = MSM8916_SLAVE_OCMEM_64, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_clk_ctl = { + .name = "slv_clk_ctl", + .id = MSM8916_SLAVE_CLK_CTL, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_crypto_0_cfg = { + .name = "slv_crypto_0_cfg", + .id = MSM8916_SLAVE_CRYPTO_0_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_dehr_cfg = { + .name = "slv_dehr_cfg", + .id = MSM8916_SLAVE_DEHR_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_display_cfg = { + .name = "slv_display_cfg", + .id = MSM8916_SLAVE_DISPLAY_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_ebi_ch0 = { + .name = "slv_ebi_ch0", + .id = MSM8916_SLAVE_EBI_CH0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 0, +}; + +static struct qcom_icc_node slv_gfx_cfg = { + .name = "slv_gfx_cfg", + .id = MSM8916_SLAVE_GRAPHICS_3D_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_imem_cfg = { + .name = "slv_imem_cfg", + .id = MSM8916_SLAVE_IMEM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_imem = { + .name = "slv_imem", + .id = MSM8916_SLAVE_IMEM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 26, +}; + +static struct qcom_icc_node slv_mpm = { + .name = "slv_mpm", + .id = MSM8916_SLAVE_MPM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_msg_ram = { + .name = "slv_msg_ram", + .id = MSM8916_SLAVE_MSG_RAM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_mss = { + .name = "slv_mss", + .id = MSM8916_SLAVE_MSS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pdm = { + .name = "slv_pdm", + .id = MSM8916_SLAVE_PDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pmic_arb = { + .name = "slv_pmic_arb", + .id = MSM8916_SLAVE_PMIC_ARB, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pcnoc_cfg = { + .name = "slv_pcnoc_cfg", + .id = MSM8916_SLAVE_PNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_prng = { + .name = "slv_prng", + .id = MSM8916_SLAVE_PRNG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_qdss_cfg = { + .name = "slv_qdss_cfg", + .id = MSM8916_SLAVE_QDSS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_qdss_stm = { + .name = "slv_qdss_stm", + .id = MSM8916_SLAVE_QDSS_STM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 30, +}; + +static struct qcom_icc_node slv_rbcpr_cfg = { + .name = "slv_rbcpr_cfg", + .id = MSM8916_SLAVE_RBCPR_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_sdcc_1 = { + .name = "slv_sdcc_1", + .id = MSM8916_SLAVE_SDCC_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_sdcc_2 = { + .name = "slv_sdcc_2", + .id = MSM8916_SLAVE_SDCC_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_security = { + .name = "slv_security", + .id = MSM8916_SLAVE_SECURITY, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_snoc_cfg = { + .name = "slv_snoc_cfg", + .id = MSM8916_SLAVE_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_spdm = { + .name = "slv_spdm", + .id = MSM8916_SLAVE_SPDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_srvc_snoc = { + .name = "slv_srvc_snoc", + .id = MSM8916_SLAVE_SRVC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_tcsr = { + .name = "slv_tcsr", + .id = MSM8916_SLAVE_TCSR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_tlmm = { + .name = "slv_tlmm", + .id = MSM8916_SLAVE_TLMM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_usb_hs = { + .name = "slv_usb_hs", + .id = MSM8916_SLAVE_USB_HS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_venus_cfg = { + .name = "slv_venus_cfg", + .id = MSM8916_SLAVE_VENUS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static const u16 snoc_bimc_0_mas_links[] = { + MSM8916_SNOC_BIMC_0_SLV +}; + +static struct qcom_icc_node snoc_bimc_0_mas = { + .name = "snoc_bimc_0_mas", + .id = MSM8916_SNOC_BIMC_0_MAS, + .buswidth = 8, + .mas_rpm_id = 3, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links), + .links = snoc_bimc_0_mas_links, +}; + +static const u16 snoc_bimc_0_slv_links[] = { + MSM8916_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node snoc_bimc_0_slv = { + .name = "snoc_bimc_0_slv", + .id = MSM8916_SNOC_BIMC_0_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 24, + .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links), + .links = snoc_bimc_0_slv_links, +}; + +static const u16 snoc_bimc_1_mas_links[] = { + MSM8916_SNOC_BIMC_1_SLV +}; + +static struct qcom_icc_node snoc_bimc_1_mas = { + .name = "snoc_bimc_1_mas", + .id = MSM8916_SNOC_BIMC_1_MAS, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links), + .links = snoc_bimc_1_mas_links, +}; + +static const u16 snoc_bimc_1_slv_links[] = { + MSM8916_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node snoc_bimc_1_slv = { + .name = "snoc_bimc_1_slv", + .id = MSM8916_SNOC_BIMC_1_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links), + .links = snoc_bimc_1_slv_links, +}; + +static const u16 snoc_int_0_links[] = { + MSM8916_SLAVE_QDSS_STM, + MSM8916_SLAVE_IMEM, + MSM8916_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node snoc_int_0 = { + .name = "snoc_int_0", + .id = MSM8916_SNOC_INT_0, + .buswidth = 8, + .mas_rpm_id = 99, + .slv_rpm_id = 130, + .num_links = ARRAY_SIZE(snoc_int_0_links), + .links = snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] = { + MSM8916_SLAVE_APSS, + MSM8916_SLAVE_CATS_128, + MSM8916_SLAVE_OCMEM_64 +}; + +static struct qcom_icc_node snoc_int_1 = { + .name = "snoc_int_1", + .id = MSM8916_SNOC_INT_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_int_1_links), + .links = snoc_int_1_links, +}; + +static const u16 snoc_int_bimc_links[] = { + MSM8916_SNOC_BIMC_0_MAS +}; + +static struct qcom_icc_node snoc_int_bimc = { + .name = "snoc_int_bimc", + .id = MSM8916_SNOC_INT_BIMC, + .buswidth = 8, + .mas_rpm_id = 101, + .slv_rpm_id = 132, + .num_links = ARRAY_SIZE(snoc_int_bimc_links), + .links = snoc_int_bimc_links, +}; + +static const u16 snoc_pcnoc_mas_links[] = { + MSM8916_SNOC_PNOC_SLV +}; + +static struct qcom_icc_node snoc_pcnoc_mas = { + .name = "snoc_pcnoc_mas", + .id = MSM8916_SNOC_PNOC_MAS, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links), + .links = snoc_pcnoc_mas_links, +}; + +static const u16 snoc_pcnoc_slv_links[] = { + MSM8916_PNOC_INT_0 +}; + +static struct qcom_icc_node snoc_pcnoc_slv = { + .name = "snoc_pcnoc_slv", + .id = MSM8916_SNOC_PNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links), + .links = snoc_pcnoc_slv_links, +}; static struct qcom_icc_node *msm8916_snoc_nodes[] = { [BIMC_SNOC_SLV] = &bimc_snoc_slv, From patchwork Fri Sep 3 23:24:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506562 Delivered-To: patch@linaro.org Received: by 2002:a17:906:f46:0:0:0:0 with SMTP id h6csp1976468ejj; Fri, 3 Sep 2021 16:24:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTwA1wzGLqisdDN7hOpZ2YVC+ND6ooiQjzST9l4qEDm4BAwhDb+hRC/y554iZyufkiPjZD X-Received: by 2002:a17:906:4994:: with SMTP id p20mr1426194eju.38.1630711476569; Fri, 03 Sep 2021 16:24:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630711476; cv=none; d=google.com; s=arc-20160816; b=YZpj8edEsZmHR758bXAMXQFx3Tt9y4sX+AFf0FGGPjU/1Xc8wLWsY0EUT1lWIk74L2 GtEu1+4cOfG50DxOLHcJ1BC2e0d1B4KZGYTv/iq58MmWysvcCGBeUAhkJK3evOjuIbPX 0Ct+TYIxl54sr6Ol+5cZ572kLJK2+fyZbJ17uQrmhupfikz5/1YtcU0QBfV+5KqioD1v bMfOABukLo+CKovqORM9BW36vxg0pFfMf4GV90hDeWvDOfIZfEVJn0zH9DIz37oKdVtM +qjx5MDE4LSnm8B/oiUUm6KsRMDJ/PDvi++AF9RH2lTPqdhHevy6RFKcVrEeaBWVBPTN eQJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/7Kdp2CKOY1yGai6IQY1GYNP9YfYyRE9SQ+6a6eqD+8=; b=Ta9RBhVV9ymFeQtsUIpACpdkfboA+6iXglmRzHaF/YRB+LpR6wV+vt0k/zJz2XLfL5 DH3PolNRDhSBAbp2SoUMfcktHDhmXiwdDpFYleh8fqzmaulVWfEeG3eqGVyHtVN86DHU F6ByfEfb7jk2lC01djBk3n5TOEjexuh2FbuDoA5scfYIz1+fKrReL1H4kmBXV9pYvqrB qhD7KghsRFKPxeSAzSoSPJuuzMyxUrjBjCJ3tgjzmsvjUBvDzN5fZ+/TyteLUbM6vhMg xMLDCZ+IbD+mQV9BoHLUOAIXF+2q7dl4viLypu67yqI85JzJFiAcIHRuMwF0jsj2JfIw QuQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vB3rbYLE; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp5si572394ejc.132.2021.09.03.16.24.36; Fri, 03 Sep 2021 16:24:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vB3rbYLE; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350771AbhICXZd (ORCPT + 16 others); Fri, 3 Sep 2021 19:25:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350762AbhICXZc (ORCPT ); Fri, 3 Sep 2021 19:25:32 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55CFAC061796 for ; Fri, 3 Sep 2021 16:24:31 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id c8so1356911lfi.3 for ; Fri, 03 Sep 2021 16:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/7Kdp2CKOY1yGai6IQY1GYNP9YfYyRE9SQ+6a6eqD+8=; b=vB3rbYLE1lskBpE97QU7Kqfxte89BZHzsrgdhR2W7CNncvcwEeF0MMgWaksRXq6an9 CzK0bO3FiipnWzLKoRYpk9C2Cst9m4IOFDidhzkmLCBilsxXMmE08OTmViWM9iL0FElm CDGG3TWF3jdBxoWz3KvRLJEJCiWF26YbSl+vEdPbaoKo/n/BvwK1BruWvsU8Yf5Bctwh D52gIs5+hqwzHFlAEVWFdhH51w+FgKcibTZXwFJhyBlfhFgpD12dygtPID1pfaaRNOjP nQ+Gc9sDrOeMKFAFjcbw2UgdtuBpwHO2rLnHKPvDZSVMM3ZXGGw7CId6ui82thj7Jkq1 Xu4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/7Kdp2CKOY1yGai6IQY1GYNP9YfYyRE9SQ+6a6eqD+8=; b=FMNQpml14rLbe5Xk2n4oy8xqIaZHovj+RRB42ADYUIkeYm08HDOfAAuiL9k3FXSpGE LwSgz2pr6sh91wj2OBvut3J174CMbjYT1AI2nWoMezzGo1oSTmRhGuBl6gjGWOedrOAS zgHy5fAkykuNjQv6ZyfwQdFQ+ClwZYlRlPkKbjPJgG5dtzRoLCq+Zpeh9WnDKT1z4YOK bS3wypBmCu5NmhpnpcIsN1DcIl6YW4mF9ylp4LoiEecB1CH5WRJijIVM/O45A/XwnZyA e7Tml4dNv3YcIr/kInoEKvfiPxJTSoMghJVdti2wH0DwGMzTEBqE9p1UW0hEw+bxcf3f PoJQ== X-Gm-Message-State: AOAM531iWEWKqiQn9wKKAhwIWGlvKeQqxgqF9TufOLc3GTAi6lbXjEdH 0a4iGDPQIIzlWqGAlKSGDsftPg== X-Received: by 2002:ac2:4f8f:: with SMTP id z15mr949643lfs.361.1630711469656; Fri, 03 Sep 2021 16:24:29 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 07/11] interconnect: msm8916: add support for AP-owned nodes Date: Sat, 4 Sep 2021 02:24:17 +0300 Message-Id: <20210903232421.1384199-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Port support for AP-owned nodes from the downstream device tree. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/msm8916.c | 100 ++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) -- 2.33.0 Reviewed-by: AngeloGioacchino Del Regno diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index b7d662875c89..e3c995b11357 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -115,6 +116,8 @@ static struct qcom_icc_node bimc_snoc_mas = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(bimc_snoc_mas_links), .links = bimc_snoc_mas_links, }; @@ -130,6 +133,8 @@ static struct qcom_icc_node bimc_snoc_slv = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(bimc_snoc_slv_links), .links = bimc_snoc_slv_links, }; @@ -146,6 +151,11 @@ static struct qcom_icc_node mas_apss = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 0, .num_links = ARRAY_SIZE(mas_apss_links), .links = mas_apss_links, }; @@ -204,6 +214,11 @@ static struct qcom_icc_node mas_gfx = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 2, .num_links = ARRAY_SIZE(mas_gfx_links), .links = mas_gfx_links, }; @@ -219,6 +234,11 @@ static struct qcom_icc_node mas_jpeg = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 6, .num_links = ARRAY_SIZE(mas_jpeg_links), .links = mas_jpeg_links, }; @@ -234,6 +254,11 @@ static struct qcom_icc_node mas_mdp = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 7, .num_links = ARRAY_SIZE(mas_mdp_links), .links = mas_mdp_links, }; @@ -290,6 +315,11 @@ static struct qcom_icc_node mas_qdss_bam = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 11, .num_links = ARRAY_SIZE(mas_qdss_bam_links), .links = mas_qdss_bam_links, }; @@ -304,6 +334,11 @@ static struct qcom_icc_node mas_qdss_etr = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 10, .num_links = ARRAY_SIZE(mas_qdss_etr_links), .links = mas_qdss_etr_links, }; @@ -348,6 +383,11 @@ static struct qcom_icc_node mas_tcu0 = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .qos.prio_level = 2, + .qos.qos_port = 5, .num_links = ARRAY_SIZE(mas_tcu0_links), .links = mas_tcu0_links, }; @@ -364,6 +404,11 @@ static struct qcom_icc_node mas_tcu1 = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .qos.prio_level = 2, + .qos.qos_port = 6, .num_links = ARRAY_SIZE(mas_tcu1_links), .links = mas_tcu1_links, }; @@ -393,6 +438,11 @@ static struct qcom_icc_node mas_vfe = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 9, .num_links = ARRAY_SIZE(mas_vfe_links), .links = mas_vfe_links, }; @@ -408,6 +458,11 @@ static struct qcom_icc_node mas_video = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 8, .num_links = ARRAY_SIZE(mas_video_links), .links = mas_video_links, }; @@ -422,6 +477,8 @@ static struct qcom_icc_node mm_int_0 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_0_links), .links = mm_int_0_links, }; @@ -436,6 +493,8 @@ static struct qcom_icc_node mm_int_1 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_1_links), .links = mm_int_1_links, }; @@ -450,6 +509,8 @@ static struct qcom_icc_node mm_int_2 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_2_links), .links = mm_int_2_links, }; @@ -464,6 +525,8 @@ static struct qcom_icc_node mm_int_bimc = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_bimc_links), .links = mm_int_bimc_links, }; @@ -692,6 +755,8 @@ static struct qcom_icc_node qdss_int = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(qdss_int_links), .links = qdss_int_links, }; @@ -1030,6 +1095,8 @@ static struct qcom_icc_node snoc_bimc_1_mas = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links), .links = snoc_bimc_1_mas_links, }; @@ -1044,6 +1111,8 @@ static struct qcom_icc_node snoc_bimc_1_slv = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links), .links = snoc_bimc_1_slv_links, }; @@ -1151,9 +1220,19 @@ static struct qcom_icc_node *msm8916_snoc_nodes[] = { [SNOC_QDSS_INT] = &qdss_int, }; +static const struct regmap_config msm8916_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8916_snoc = { .nodes = msm8916_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), + .regmap_cfg = &msm8916_snoc_regmap_config, + .qos_offset = 0x7000, }; static struct qcom_icc_node *msm8916_bimc_nodes[] = { @@ -1168,9 +1247,20 @@ static struct qcom_icc_node *msm8916_bimc_nodes[] = { [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv, }; +static const struct regmap_config msm8916_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x62000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8916_bimc = { .nodes = msm8916_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), + .is_bimc_node = true, + .regmap_cfg = &msm8916_bimc_regmap_config, + .qos_offset = 0x8000, }; static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { @@ -1226,9 +1316,19 @@ static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, }; +static const struct regmap_config msm8916_pcnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x11000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8916_pcnoc = { .nodes = msm8916_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), + .regmap_cfg = &msm8916_pcnoc_regmap_config, + .qos_offset = 0x7000, }; static const struct of_device_id msm8916_noc_of_match[] = { From patchwork Fri Sep 3 23:24:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 507060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE481C19F38 for ; Fri, 3 Sep 2021 23:24:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8FE88610E6 for ; Fri, 3 Sep 2021 23:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350762AbhICXZe (ORCPT ); Fri, 3 Sep 2021 19:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350766AbhICXZd (ORCPT ); Fri, 3 Sep 2021 19:25:33 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FEDFC061575 for ; Fri, 3 Sep 2021 16:24:32 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id m28so1336365lfj.6 for ; Fri, 03 Sep 2021 16:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MBgWE9CD+62OBLMCx6celmgsTidthdgiHa7EwEMmZxY=; b=aO3bUL/I6kPqmKOygXFGtX6wlyEl2/JpLWMlCpOmSgfp2UxAKZiPYCOOZBVn4IZR4o G6/JWt6qNiRBqOlI7P+tyYXeU4R+nWD7YY5O6mJnB/Y5EuWJXph1Znl5EJYhF8SbrK6T sf5meiib+a0oWkBZMQfkG/U+Zu76TUZma83GPFsyxJ5Ph/AphrTdwx7uOQRdmK6vmuhq ReQ2F8rwkj2YIACbzZvKcCQf8NACJhiaVdo0ywVY7bqar984HZ1/NOPjZzrE4svJwd9c Mw88zErUxO/s3ztesNZqaK76NIDQPJmWySB3wC86YRO27GbpRPl9VaDunL6aV2Ja2a8i tRxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MBgWE9CD+62OBLMCx6celmgsTidthdgiHa7EwEMmZxY=; b=GjmTmGwjZVTsLp9AcbpGtih4N1Uieo8AAcFbs0TeQLsQUfwlI1qA0+X+3bJxwIXKBA xdVdV59V84tc2F5JtgP6Yr9PE5aYh5QAXT0EIjqZIDRG2t0FQC8kOnHYtdbOFrBc2sMv /lMd3+sMi6CagSW3dlsA61ok/RKyVOKa0gcWDEdFriyNCwzLnMb4JDjVqmtlXjndFLyu bhrL3lhhafO5JTi3k1Jfkb3cXh4luBKBwAY7IQ9MTu1ID2kJiJOIVOlvjsUVC+Qw9SBd weyqCmhx41GqPqFA0C/nLB3GIb+lDDrdwADKclhYM1WWN1UYDxJQBSm5lZykscybObG8 8NEA== X-Gm-Message-State: AOAM531lUn1lBzHOt7vJiWNIlRgiV2Pw7kyH/Pin3q37KlTWF90SC4vz 79buOpu6gJ4wxjqjUyX8GXxjXA== X-Google-Smtp-Source: ABdhPJyMowfNaFqavlextDF3wfARdsWmwqtVbtN5ojGfUP5rn7YKqokEkKX9+vdNkzZXcxrqFIWHkg== X-Received: by 2002:a05:6512:108d:: with SMTP id j13mr959759lfg.113.1630711470602; Fri, 03 Sep 2021 16:24:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 08/11] interconnect: msm8939: expand DEFINE_QNODE macros Date: Sat, 4 Sep 2021 02:24:18 +0300 Message-Id: <20210903232421.1384199-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to adding AP-owned nodes support to msm8939 expand DEFINE_QNODE macros in the driver. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Reviewed-by: AngeloGioacchino Del Regno --- drivers/interconnect/qcom/msm8939.c | 1155 ++++++++++++++++++++++++--- 1 file changed, 1066 insertions(+), 89 deletions(-) diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 4a5a2ec64960..4671538c8994 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -110,95 +110,1072 @@ enum { MSM8939_SNOC_PNOC_SLV, }; -DEFINE_QNODE(bimc_snoc_mas, MSM8939_BIMC_SNOC_MAS, 8, -1, -1, MSM8939_BIMC_SNOC_SLV); -DEFINE_QNODE(bimc_snoc_slv, MSM8939_BIMC_SNOC_SLV, 16, -1, 2, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_1); -DEFINE_QNODE(mas_apss, MSM8939_MASTER_AMPSS_M0, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_audio, MSM8939_MASTER_LPASS, 4, -1, -1, MSM8939_PNOC_MAS_0); -DEFINE_QNODE(mas_blsp_1, MSM8939_MASTER_BLSP_1, 4, -1, -1, MSM8939_PNOC_MAS_1); -DEFINE_QNODE(mas_dehr, MSM8939_MASTER_DEHR, 4, -1, -1, MSM8939_PNOC_MAS_0); -DEFINE_QNODE(mas_gfx, MSM8939_MASTER_GRAPHICS_3D, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_jpeg, MSM8939_MASTER_JPEG, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_mdp0, MSM8939_MASTER_MDP_PORT0, 16, -1, -1, MSM8939_SNOC_MM_INT_1, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_mdp1, MSM8939_MASTER_MDP_PORT1, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_cpp, MSM8939_MASTER_CPP, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_pcnoc_crypto_0, MSM8939_MASTER_CRYPTO_CORE0, 8, -1, -1, MSM8939_PNOC_INT_1); -DEFINE_QNODE(mas_pcnoc_sdcc_1, MSM8939_MASTER_SDCC_1, 8, -1, -1, MSM8939_PNOC_INT_1); -DEFINE_QNODE(mas_pcnoc_sdcc_2, MSM8939_MASTER_SDCC_2, 8, -1, -1, MSM8939_PNOC_INT_1); -DEFINE_QNODE(mas_qdss_bam, MSM8939_MASTER_QDSS_BAM, 8, -1, -1, MSM8939_SNOC_QDSS_INT); -DEFINE_QNODE(mas_qdss_etr, MSM8939_MASTER_QDSS_ETR, 8, -1, -1, MSM8939_SNOC_QDSS_INT); -DEFINE_QNODE(mas_snoc_cfg, MSM8939_MASTER_SNOC_CFG, 4, -1, -1, MSM8939_SLAVE_SRVC_SNOC); -DEFINE_QNODE(mas_spdm, MSM8939_MASTER_SPDM, 4, -1, -1, MSM8939_PNOC_MAS_0); -DEFINE_QNODE(mas_tcu0, MSM8939_MASTER_TCU0, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_usb_hs1, MSM8939_MASTER_USB_HS1, 4, -1, -1, MSM8939_PNOC_MAS_1); -DEFINE_QNODE(mas_usb_hs2, MSM8939_MASTER_USB_HS2, 4, -1, -1, MSM8939_PNOC_MAS_1); -DEFINE_QNODE(mas_vfe, MSM8939_MASTER_VFE, 16, -1, -1, MSM8939_SNOC_MM_INT_1, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_video, MSM8939_MASTER_VIDEO_P0, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mm_int_0, MSM8939_SNOC_MM_INT_0, 16, -1, -1, MSM8939_SNOC_BIMC_2_MAS); -DEFINE_QNODE(mm_int_1, MSM8939_SNOC_MM_INT_1, 16, -1, -1, MSM8939_SNOC_BIMC_1_MAS); -DEFINE_QNODE(mm_int_2, MSM8939_SNOC_MM_INT_2, 16, -1, -1, MSM8939_SNOC_INT_0); -DEFINE_QNODE(pcnoc_int_0, MSM8939_PNOC_INT_0, 8, -1, -1, MSM8939_PNOC_SNOC_MAS, MSM8939_PNOC_SLV_0, MSM8939_PNOC_SLV_1, MSM8939_PNOC_SLV_2, MSM8939_PNOC_SLV_3, MSM8939_PNOC_SLV_4, MSM8939_PNOC_SLV_8, MSM8939_PNOC_SLV_9); -DEFINE_QNODE(pcnoc_int_1, MSM8939_PNOC_INT_1, 8, -1, -1, MSM8939_PNOC_SNOC_MAS); -DEFINE_QNODE(pcnoc_m_0, MSM8939_PNOC_MAS_0, 8, -1, -1, MSM8939_PNOC_INT_0); -DEFINE_QNODE(pcnoc_m_1, MSM8939_PNOC_MAS_1, 8, -1, -1, MSM8939_PNOC_SNOC_MAS); -DEFINE_QNODE(pcnoc_s_0, MSM8939_PNOC_SLV_0, 4, -1, -1, MSM8939_SLAVE_CLK_CTL, MSM8939_SLAVE_TLMM, MSM8939_SLAVE_TCSR, MSM8939_SLAVE_SECURITY, MSM8939_SLAVE_MSS); -DEFINE_QNODE(pcnoc_s_1, MSM8939_PNOC_SLV_1, 4, -1, -1, MSM8939_SLAVE_IMEM_CFG, MSM8939_SLAVE_CRYPTO_0_CFG, MSM8939_SLAVE_MSG_RAM, MSM8939_SLAVE_PDM, MSM8939_SLAVE_PRNG); -DEFINE_QNODE(pcnoc_s_2, MSM8939_PNOC_SLV_2, 4, -1, -1, MSM8939_SLAVE_SPDM, MSM8939_SLAVE_BOOT_ROM, MSM8939_SLAVE_BIMC_CFG, MSM8939_SLAVE_PNOC_CFG, MSM8939_SLAVE_PMIC_ARB); -DEFINE_QNODE(pcnoc_s_3, MSM8939_PNOC_SLV_3, 4, -1, -1, MSM8939_SLAVE_MPM, MSM8939_SLAVE_SNOC_CFG, MSM8939_SLAVE_RBCPR_CFG, MSM8939_SLAVE_QDSS_CFG, MSM8939_SLAVE_DEHR_CFG); -DEFINE_QNODE(pcnoc_s_4, MSM8939_PNOC_SLV_4, 4, -1, -1, MSM8939_SLAVE_VENUS_CFG, MSM8939_SLAVE_CAMERA_CFG, MSM8939_SLAVE_DISPLAY_CFG); -DEFINE_QNODE(pcnoc_s_8, MSM8939_PNOC_SLV_8, 4, -1, -1, MSM8939_SLAVE_USB_HS1, MSM8939_SLAVE_SDCC_1, MSM8939_SLAVE_BLSP_1); -DEFINE_QNODE(pcnoc_s_9, MSM8939_PNOC_SLV_9, 4, -1, -1, MSM8939_SLAVE_SDCC_2, MSM8939_SLAVE_LPASS, MSM8939_SLAVE_USB_HS2); -DEFINE_QNODE(pcnoc_snoc_mas, MSM8939_PNOC_SNOC_MAS, 8, 29, -1, MSM8939_PNOC_SNOC_SLV); -DEFINE_QNODE(pcnoc_snoc_slv, MSM8939_PNOC_SNOC_SLV, 8, -1, 45, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_BIMC, MSM8939_SNOC_INT_1); -DEFINE_QNODE(qdss_int, MSM8939_SNOC_QDSS_INT, 8, -1, -1, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_BIMC); -DEFINE_QNODE(slv_apps_l2, MSM8939_SLAVE_AMPSS_L2, 16, -1, -1, 0); -DEFINE_QNODE(slv_apss, MSM8939_SLAVE_APSS, 4, -1, -1, 0); -DEFINE_QNODE(slv_audio, MSM8939_SLAVE_LPASS, 4, -1, -1, 0); -DEFINE_QNODE(slv_bimc_cfg, MSM8939_SLAVE_BIMC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_blsp_1, MSM8939_SLAVE_BLSP_1, 4, -1, -1, 0); -DEFINE_QNODE(slv_boot_rom, MSM8939_SLAVE_BOOT_ROM, 4, -1, -1, 0); -DEFINE_QNODE(slv_camera_cfg, MSM8939_SLAVE_CAMERA_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_cats_0, MSM8939_SLAVE_CATS_128, 16, -1, -1, 0); -DEFINE_QNODE(slv_cats_1, MSM8939_SLAVE_OCMEM_64, 8, -1, -1, 0); -DEFINE_QNODE(slv_clk_ctl, MSM8939_SLAVE_CLK_CTL, 4, -1, -1, 0); -DEFINE_QNODE(slv_crypto_0_cfg, MSM8939_SLAVE_CRYPTO_0_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_dehr_cfg, MSM8939_SLAVE_DEHR_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_display_cfg, MSM8939_SLAVE_DISPLAY_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_ebi_ch0, MSM8939_SLAVE_EBI_CH0, 16, -1, 0, 0); -DEFINE_QNODE(slv_gfx_cfg, MSM8939_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_imem_cfg, MSM8939_SLAVE_IMEM_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_imem, MSM8939_SLAVE_IMEM, 8, -1, 26, 0); -DEFINE_QNODE(slv_mpm, MSM8939_SLAVE_MPM, 4, -1, -1, 0); -DEFINE_QNODE(slv_msg_ram, MSM8939_SLAVE_MSG_RAM, 4, -1, -1, 0); -DEFINE_QNODE(slv_mss, MSM8939_SLAVE_MSS, 4, -1, -1, 0); -DEFINE_QNODE(slv_pdm, MSM8939_SLAVE_PDM, 4, -1, -1, 0); -DEFINE_QNODE(slv_pmic_arb, MSM8939_SLAVE_PMIC_ARB, 4, -1, -1, 0); -DEFINE_QNODE(slv_pcnoc_cfg, MSM8939_SLAVE_PNOC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_prng, MSM8939_SLAVE_PRNG, 4, -1, -1, 0); -DEFINE_QNODE(slv_qdss_cfg, MSM8939_SLAVE_QDSS_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_qdss_stm, MSM8939_SLAVE_QDSS_STM, 4, -1, 30, 0); -DEFINE_QNODE(slv_rbcpr_cfg, MSM8939_SLAVE_RBCPR_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_sdcc_1, MSM8939_SLAVE_SDCC_1, 4, -1, -1, 0); -DEFINE_QNODE(slv_sdcc_2, MSM8939_SLAVE_SDCC_2, 4, -1, -1, 0); -DEFINE_QNODE(slv_security, MSM8939_SLAVE_SECURITY, 4, -1, -1, 0); -DEFINE_QNODE(slv_snoc_cfg, MSM8939_SLAVE_SNOC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_spdm, MSM8939_SLAVE_SPDM, 4, -1, -1, 0); -DEFINE_QNODE(slv_srvc_snoc, MSM8939_SLAVE_SRVC_SNOC, 8, -1, -1, 0); -DEFINE_QNODE(slv_tcsr, MSM8939_SLAVE_TCSR, 4, -1, -1, 0); -DEFINE_QNODE(slv_tlmm, MSM8939_SLAVE_TLMM, 4, -1, -1, 0); -DEFINE_QNODE(slv_usb_hs1, MSM8939_SLAVE_USB_HS1, 4, -1, -1, 0); -DEFINE_QNODE(slv_usb_hs2, MSM8939_SLAVE_USB_HS2, 4, -1, -1, 0); -DEFINE_QNODE(slv_venus_cfg, MSM8939_SLAVE_VENUS_CFG, 4, -1, -1, 0); -DEFINE_QNODE(snoc_bimc_0_mas, MSM8939_SNOC_BIMC_0_MAS, 16, -1, -1, MSM8939_SNOC_BIMC_0_SLV); -DEFINE_QNODE(snoc_bimc_0_slv, MSM8939_SNOC_BIMC_0_SLV, 16, -1, -1, MSM8939_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_bimc_1_mas, MSM8939_SNOC_BIMC_1_MAS, 16, 76, -1, MSM8939_SNOC_BIMC_1_SLV); -DEFINE_QNODE(snoc_bimc_1_slv, MSM8939_SNOC_BIMC_1_SLV, 16, -1, 104, MSM8939_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_bimc_2_mas, MSM8939_SNOC_BIMC_2_MAS, 16, -1, -1, MSM8939_SNOC_BIMC_2_SLV); -DEFINE_QNODE(snoc_bimc_2_slv, MSM8939_SNOC_BIMC_2_SLV, 16, -1, -1, MSM8939_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_int_0, MSM8939_SNOC_INT_0, 8, 99, 130, MSM8939_SLAVE_QDSS_STM, MSM8939_SLAVE_IMEM, MSM8939_SNOC_PNOC_MAS); -DEFINE_QNODE(snoc_int_1, MSM8939_SNOC_INT_1, 8, -1, -1, MSM8939_SLAVE_APSS, MSM8939_SLAVE_CATS_128, MSM8939_SLAVE_OCMEM_64); -DEFINE_QNODE(snoc_int_bimc, MSM8939_SNOC_INT_BIMC, 8, 101, 132, MSM8939_SNOC_BIMC_1_MAS); -DEFINE_QNODE(snoc_pcnoc_mas, MSM8939_SNOC_PNOC_MAS, 8, -1, -1, MSM8939_SNOC_PNOC_SLV); -DEFINE_QNODE(snoc_pcnoc_slv, MSM8939_SNOC_PNOC_SLV, 8, -1, -1, MSM8939_PNOC_INT_0); +static const u16 bimc_snoc_mas_links[] = { + MSM8939_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node bimc_snoc_mas = { + .name = "bimc_snoc_mas", + .id = MSM8939_BIMC_SNOC_MAS, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(bimc_snoc_mas_links), + .links = bimc_snoc_mas_links, +}; + +static const u16 bimc_snoc_slv_links[] = { + MSM8939_SNOC_INT_0, + MSM8939_SNOC_INT_1 +}; + +static struct qcom_icc_node bimc_snoc_slv = { + .name = "bimc_snoc_slv", + .id = MSM8939_BIMC_SNOC_SLV, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 2, + .num_links = ARRAY_SIZE(bimc_snoc_slv_links), + .links = bimc_snoc_slv_links, +}; + +static const u16 mas_apss_links[] = { + MSM8939_SLAVE_EBI_CH0, + MSM8939_BIMC_SNOC_MAS, + MSM8939_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_apss = { + .name = "mas_apss", + .id = MSM8939_MASTER_AMPSS_M0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_apss_links), + .links = mas_apss_links, +}; + +static const u16 mas_audio_links[] = { + MSM8939_PNOC_MAS_0 +}; + +static struct qcom_icc_node mas_audio = { + .name = "mas_audio", + .id = MSM8939_MASTER_LPASS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_audio_links), + .links = mas_audio_links, +}; + +static const u16 mas_blsp_1_links[] = { + MSM8939_PNOC_MAS_1 +}; + +static struct qcom_icc_node mas_blsp_1 = { + .name = "mas_blsp_1", + .id = MSM8939_MASTER_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_blsp_1_links), + .links = mas_blsp_1_links, +}; + +static const u16 mas_dehr_links[] = { + MSM8939_PNOC_MAS_0 +}; + +static struct qcom_icc_node mas_dehr = { + .name = "mas_dehr", + .id = MSM8939_MASTER_DEHR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_dehr_links), + .links = mas_dehr_links, +}; + +static const u16 mas_gfx_links[] = { + MSM8939_SLAVE_EBI_CH0, + MSM8939_BIMC_SNOC_MAS, + MSM8939_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_gfx = { + .name = "mas_gfx", + .id = MSM8939_MASTER_GRAPHICS_3D, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_gfx_links), + .links = mas_gfx_links, +}; + +static const u16 mas_jpeg_links[] = { + MSM8939_SNOC_MM_INT_0, + MSM8939_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_jpeg = { + .name = "mas_jpeg", + .id = MSM8939_MASTER_JPEG, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_jpeg_links), + .links = mas_jpeg_links, +}; + +static const u16 mas_mdp0_links[] = { + MSM8939_SNOC_MM_INT_1, + MSM8939_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_mdp0 = { + .name = "mas_mdp0", + .id = MSM8939_MASTER_MDP_PORT0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_mdp0_links), + .links = mas_mdp0_links, +}; + +static const u16 mas_mdp1_links[] = { + MSM8939_SNOC_MM_INT_0, + MSM8939_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_mdp1 = { + .name = "mas_mdp1", + .id = MSM8939_MASTER_MDP_PORT1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_mdp1_links), + .links = mas_mdp1_links, +}; + +static const u16 mas_cpp_links[] = { + MSM8939_SNOC_MM_INT_0, + MSM8939_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_cpp = { + .name = "mas_cpp", + .id = MSM8939_MASTER_CPP, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_cpp_links), + .links = mas_cpp_links, +}; + +static const u16 mas_pcnoc_crypto_0_links[] = { + MSM8939_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcnoc_crypto_0 = { + .name = "mas_pcnoc_crypto_0", + .id = MSM8939_MASTER_CRYPTO_CORE0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links), + .links = mas_pcnoc_crypto_0_links, +}; + +static const u16 mas_pcnoc_sdcc_1_links[] = { + MSM8939_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcnoc_sdcc_1 = { + .name = "mas_pcnoc_sdcc_1", + .id = MSM8939_MASTER_SDCC_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links), + .links = mas_pcnoc_sdcc_1_links, +}; + +static const u16 mas_pcnoc_sdcc_2_links[] = { + MSM8939_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcnoc_sdcc_2 = { + .name = "mas_pcnoc_sdcc_2", + .id = MSM8939_MASTER_SDCC_2, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links), + .links = mas_pcnoc_sdcc_2_links, +}; + +static const u16 mas_qdss_bam_links[] = { + MSM8939_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam = { + .name = "mas_qdss_bam", + .id = MSM8939_MASTER_QDSS_BAM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_bam_links), + .links = mas_qdss_bam_links, +}; + +static const u16 mas_qdss_etr_links[] = { + MSM8939_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr = { + .name = "mas_qdss_etr", + .id = MSM8939_MASTER_QDSS_ETR, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_etr_links), + .links = mas_qdss_etr_links, +}; + +static const u16 mas_snoc_cfg_links[] = { + MSM8939_SLAVE_SRVC_SNOC +}; + +static struct qcom_icc_node mas_snoc_cfg = { + .name = "mas_snoc_cfg", + .id = MSM8939_MASTER_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_cfg_links), + .links = mas_snoc_cfg_links, +}; + +static const u16 mas_spdm_links[] = { + MSM8939_PNOC_MAS_0 +}; + +static struct qcom_icc_node mas_spdm = { + .name = "mas_spdm", + .id = MSM8939_MASTER_SPDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_spdm_links), + .links = mas_spdm_links, +}; + +static const u16 mas_tcu0_links[] = { + MSM8939_SLAVE_EBI_CH0, + MSM8939_BIMC_SNOC_MAS, + MSM8939_SLAVE_AMPSS_L2 +}; + +static struct qcom_icc_node mas_tcu0 = { + .name = "mas_tcu0", + .id = MSM8939_MASTER_TCU0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_tcu0_links), + .links = mas_tcu0_links, +}; + +static const u16 mas_usb_hs1_links[] = { + MSM8939_PNOC_MAS_1 +}; + +static struct qcom_icc_node mas_usb_hs1 = { + .name = "mas_usb_hs1", + .id = MSM8939_MASTER_USB_HS1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_usb_hs1_links), + .links = mas_usb_hs1_links, +}; + +static const u16 mas_usb_hs2_links[] = { + MSM8939_PNOC_MAS_1 +}; + +static struct qcom_icc_node mas_usb_hs2 = { + .name = "mas_usb_hs2", + .id = MSM8939_MASTER_USB_HS2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_usb_hs2_links), + .links = mas_usb_hs2_links, +}; + +static const u16 mas_vfe_links[] = { + MSM8939_SNOC_MM_INT_1, + MSM8939_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_vfe = { + .name = "mas_vfe", + .id = MSM8939_MASTER_VFE, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_vfe_links), + .links = mas_vfe_links, +}; + +static const u16 mas_video_links[] = { + MSM8939_SNOC_MM_INT_0, + MSM8939_SNOC_MM_INT_2 +}; + +static struct qcom_icc_node mas_video = { + .name = "mas_video", + .id = MSM8939_MASTER_VIDEO_P0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_video_links), + .links = mas_video_links, +}; + +static const u16 mm_int_0_links[] = { + MSM8939_SNOC_BIMC_2_MAS +}; + +static struct qcom_icc_node mm_int_0 = { + .name = "mm_int_0", + .id = MSM8939_SNOC_MM_INT_0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_0_links), + .links = mm_int_0_links, +}; + +static const u16 mm_int_1_links[] = { + MSM8939_SNOC_BIMC_1_MAS +}; + +static struct qcom_icc_node mm_int_1 = { + .name = "mm_int_1", + .id = MSM8939_SNOC_MM_INT_1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_1_links), + .links = mm_int_1_links, +}; + +static const u16 mm_int_2_links[] = { + MSM8939_SNOC_INT_0 +}; + +static struct qcom_icc_node mm_int_2 = { + .name = "mm_int_2", + .id = MSM8939_SNOC_MM_INT_2, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mm_int_2_links), + .links = mm_int_2_links, +}; + +static const u16 pcnoc_int_0_links[] = { + MSM8939_PNOC_SNOC_MAS, + MSM8939_PNOC_SLV_0, + MSM8939_PNOC_SLV_1, + MSM8939_PNOC_SLV_2, + MSM8939_PNOC_SLV_3, + MSM8939_PNOC_SLV_4, + MSM8939_PNOC_SLV_8, + MSM8939_PNOC_SLV_9 +}; + +static struct qcom_icc_node pcnoc_int_0 = { + .name = "pcnoc_int_0", + .id = MSM8939_PNOC_INT_0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_int_0_links), + .links = pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_1_links[] = { + MSM8939_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node pcnoc_int_1 = { + .name = "pcnoc_int_1", + .id = MSM8939_PNOC_INT_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_int_1_links), + .links = pcnoc_int_1_links, +}; + +static const u16 pcnoc_m_0_links[] = { + MSM8939_PNOC_INT_0 +}; + +static struct qcom_icc_node pcnoc_m_0 = { + .name = "pcnoc_m_0", + .id = MSM8939_PNOC_MAS_0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_m_0_links), + .links = pcnoc_m_0_links, +}; + +static const u16 pcnoc_m_1_links[] = { + MSM8939_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node pcnoc_m_1 = { + .name = "pcnoc_m_1", + .id = MSM8939_PNOC_MAS_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_m_1_links), + .links = pcnoc_m_1_links, +}; + +static const u16 pcnoc_s_0_links[] = { + MSM8939_SLAVE_CLK_CTL, + MSM8939_SLAVE_TLMM, + MSM8939_SLAVE_TCSR, + MSM8939_SLAVE_SECURITY, + MSM8939_SLAVE_MSS +}; + +static struct qcom_icc_node pcnoc_s_0 = { + .name = "pcnoc_s_0", + .id = MSM8939_PNOC_SLV_0, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_0_links), + .links = pcnoc_s_0_links, +}; + +static const u16 pcnoc_s_1_links[] = { + MSM8939_SLAVE_IMEM_CFG, + MSM8939_SLAVE_CRYPTO_0_CFG, + MSM8939_SLAVE_MSG_RAM, + MSM8939_SLAVE_PDM, + MSM8939_SLAVE_PRNG +}; + +static struct qcom_icc_node pcnoc_s_1 = { + .name = "pcnoc_s_1", + .id = MSM8939_PNOC_SLV_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_1_links), + .links = pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] = { + MSM8939_SLAVE_SPDM, + MSM8939_SLAVE_BOOT_ROM, + MSM8939_SLAVE_BIMC_CFG, + MSM8939_SLAVE_PNOC_CFG, + MSM8939_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_2 = { + .name = "pcnoc_s_2", + .id = MSM8939_PNOC_SLV_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_2_links), + .links = pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] = { + MSM8939_SLAVE_MPM, + MSM8939_SLAVE_SNOC_CFG, + MSM8939_SLAVE_RBCPR_CFG, + MSM8939_SLAVE_QDSS_CFG, + MSM8939_SLAVE_DEHR_CFG +}; + +static struct qcom_icc_node pcnoc_s_3 = { + .name = "pcnoc_s_3", + .id = MSM8939_PNOC_SLV_3, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_3_links), + .links = pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] = { + MSM8939_SLAVE_VENUS_CFG, + MSM8939_SLAVE_CAMERA_CFG, + MSM8939_SLAVE_DISPLAY_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 = { + .name = "pcnoc_s_4", + .id = MSM8939_PNOC_SLV_4, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_4_links), + .links = pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_8_links[] = { + MSM8939_SLAVE_USB_HS1, + MSM8939_SLAVE_SDCC_1, + MSM8939_SLAVE_BLSP_1 +}; + +static struct qcom_icc_node pcnoc_s_8 = { + .name = "pcnoc_s_8", + .id = MSM8939_PNOC_SLV_8, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_8_links), + .links = pcnoc_s_8_links, +}; + +static const u16 pcnoc_s_9_links[] = { + MSM8939_SLAVE_SDCC_2, + MSM8939_SLAVE_LPASS, + MSM8939_SLAVE_USB_HS2 +}; + +static struct qcom_icc_node pcnoc_s_9 = { + .name = "pcnoc_s_9", + .id = MSM8939_PNOC_SLV_9, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_9_links), + .links = pcnoc_s_9_links, +}; + +static const u16 pcnoc_snoc_mas_links[] = { + MSM8939_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_snoc_mas = { + .name = "pcnoc_snoc_mas", + .id = MSM8939_PNOC_SNOC_MAS, + .buswidth = 8, + .mas_rpm_id = 29, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links), + .links = pcnoc_snoc_mas_links, +}; + +static const u16 pcnoc_snoc_slv_links[] = { + MSM8939_SNOC_INT_0, + MSM8939_SNOC_INT_BIMC, + MSM8939_SNOC_INT_1 +}; + +static struct qcom_icc_node pcnoc_snoc_slv = { + .name = "pcnoc_snoc_slv", + .id = MSM8939_PNOC_SNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 45, + .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links), + .links = pcnoc_snoc_slv_links, +}; + +static const u16 qdss_int_links[] = { + MSM8939_SNOC_INT_0, + MSM8939_SNOC_INT_BIMC +}; + +static struct qcom_icc_node qdss_int = { + .name = "qdss_int", + .id = MSM8939_SNOC_QDSS_INT, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qdss_int_links), + .links = qdss_int_links, +}; + +static struct qcom_icc_node slv_apps_l2 = { + .name = "slv_apps_l2", + .id = MSM8939_SLAVE_AMPSS_L2, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_apss = { + .name = "slv_apss", + .id = MSM8939_SLAVE_APSS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_audio = { + .name = "slv_audio", + .id = MSM8939_SLAVE_LPASS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_bimc_cfg = { + .name = "slv_bimc_cfg", + .id = MSM8939_SLAVE_BIMC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_blsp_1 = { + .name = "slv_blsp_1", + .id = MSM8939_SLAVE_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_boot_rom = { + .name = "slv_boot_rom", + .id = MSM8939_SLAVE_BOOT_ROM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_camera_cfg = { + .name = "slv_camera_cfg", + .id = MSM8939_SLAVE_CAMERA_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_cats_0 = { + .name = "slv_cats_0", + .id = MSM8939_SLAVE_CATS_128, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_cats_1 = { + .name = "slv_cats_1", + .id = MSM8939_SLAVE_OCMEM_64, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_clk_ctl = { + .name = "slv_clk_ctl", + .id = MSM8939_SLAVE_CLK_CTL, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_crypto_0_cfg = { + .name = "slv_crypto_0_cfg", + .id = MSM8939_SLAVE_CRYPTO_0_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_dehr_cfg = { + .name = "slv_dehr_cfg", + .id = MSM8939_SLAVE_DEHR_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_display_cfg = { + .name = "slv_display_cfg", + .id = MSM8939_SLAVE_DISPLAY_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_ebi_ch0 = { + .name = "slv_ebi_ch0", + .id = MSM8939_SLAVE_EBI_CH0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 0, +}; + +static struct qcom_icc_node slv_gfx_cfg = { + .name = "slv_gfx_cfg", + .id = MSM8939_SLAVE_GRAPHICS_3D_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_imem_cfg = { + .name = "slv_imem_cfg", + .id = MSM8939_SLAVE_IMEM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_imem = { + .name = "slv_imem", + .id = MSM8939_SLAVE_IMEM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 26, +}; + +static struct qcom_icc_node slv_mpm = { + .name = "slv_mpm", + .id = MSM8939_SLAVE_MPM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_msg_ram = { + .name = "slv_msg_ram", + .id = MSM8939_SLAVE_MSG_RAM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_mss = { + .name = "slv_mss", + .id = MSM8939_SLAVE_MSS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pdm = { + .name = "slv_pdm", + .id = MSM8939_SLAVE_PDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pmic_arb = { + .name = "slv_pmic_arb", + .id = MSM8939_SLAVE_PMIC_ARB, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pcnoc_cfg = { + .name = "slv_pcnoc_cfg", + .id = MSM8939_SLAVE_PNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_prng = { + .name = "slv_prng", + .id = MSM8939_SLAVE_PRNG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_qdss_cfg = { + .name = "slv_qdss_cfg", + .id = MSM8939_SLAVE_QDSS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_qdss_stm = { + .name = "slv_qdss_stm", + .id = MSM8939_SLAVE_QDSS_STM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 30, +}; + +static struct qcom_icc_node slv_rbcpr_cfg = { + .name = "slv_rbcpr_cfg", + .id = MSM8939_SLAVE_RBCPR_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_sdcc_1 = { + .name = "slv_sdcc_1", + .id = MSM8939_SLAVE_SDCC_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_sdcc_2 = { + .name = "slv_sdcc_2", + .id = MSM8939_SLAVE_SDCC_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_security = { + .name = "slv_security", + .id = MSM8939_SLAVE_SECURITY, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_snoc_cfg = { + .name = "slv_snoc_cfg", + .id = MSM8939_SLAVE_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_spdm = { + .name = "slv_spdm", + .id = MSM8939_SLAVE_SPDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_srvc_snoc = { + .name = "slv_srvc_snoc", + .id = MSM8939_SLAVE_SRVC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_tcsr = { + .name = "slv_tcsr", + .id = MSM8939_SLAVE_TCSR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_tlmm = { + .name = "slv_tlmm", + .id = MSM8939_SLAVE_TLMM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_usb_hs1 = { + .name = "slv_usb_hs1", + .id = MSM8939_SLAVE_USB_HS1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_usb_hs2 = { + .name = "slv_usb_hs2", + .id = MSM8939_SLAVE_USB_HS2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_venus_cfg = { + .name = "slv_venus_cfg", + .id = MSM8939_SLAVE_VENUS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static const u16 snoc_bimc_0_mas_links[] = { + MSM8939_SNOC_BIMC_0_SLV +}; + +static struct qcom_icc_node snoc_bimc_0_mas = { + .name = "snoc_bimc_0_mas", + .id = MSM8939_SNOC_BIMC_0_MAS, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links), + .links = snoc_bimc_0_mas_links, +}; + +static const u16 snoc_bimc_0_slv_links[] = { + MSM8939_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node snoc_bimc_0_slv = { + .name = "snoc_bimc_0_slv", + .id = MSM8939_SNOC_BIMC_0_SLV, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links), + .links = snoc_bimc_0_slv_links, +}; + +static const u16 snoc_bimc_1_mas_links[] = { + MSM8939_SNOC_BIMC_1_SLV +}; + +static struct qcom_icc_node snoc_bimc_1_mas = { + .name = "snoc_bimc_1_mas", + .id = MSM8939_SNOC_BIMC_1_MAS, + .buswidth = 16, + .mas_rpm_id = 76, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links), + .links = snoc_bimc_1_mas_links, +}; + +static const u16 snoc_bimc_1_slv_links[] = { + MSM8939_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node snoc_bimc_1_slv = { + .name = "snoc_bimc_1_slv", + .id = MSM8939_SNOC_BIMC_1_SLV, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 104, + .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links), + .links = snoc_bimc_1_slv_links, +}; + +static const u16 snoc_bimc_2_mas_links[] = { + MSM8939_SNOC_BIMC_2_SLV +}; + +static struct qcom_icc_node snoc_bimc_2_mas = { + .name = "snoc_bimc_2_mas", + .id = MSM8939_SNOC_BIMC_2_MAS, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_2_mas_links), + .links = snoc_bimc_2_mas_links, +}; + +static const u16 snoc_bimc_2_slv_links[] = { + MSM8939_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node snoc_bimc_2_slv = { + .name = "snoc_bimc_2_slv", + .id = MSM8939_SNOC_BIMC_2_SLV, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_bimc_2_slv_links), + .links = snoc_bimc_2_slv_links, +}; + +static const u16 snoc_int_0_links[] = { + MSM8939_SLAVE_QDSS_STM, + MSM8939_SLAVE_IMEM, + MSM8939_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node snoc_int_0 = { + .name = "snoc_int_0", + .id = MSM8939_SNOC_INT_0, + .buswidth = 8, + .mas_rpm_id = 99, + .slv_rpm_id = 130, + .num_links = ARRAY_SIZE(snoc_int_0_links), + .links = snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] = { + MSM8939_SLAVE_APSS, + MSM8939_SLAVE_CATS_128, + MSM8939_SLAVE_OCMEM_64 +}; + +static struct qcom_icc_node snoc_int_1 = { + .name = "snoc_int_1", + .id = MSM8939_SNOC_INT_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_int_1_links), + .links = snoc_int_1_links, +}; + +static const u16 snoc_int_bimc_links[] = { + MSM8939_SNOC_BIMC_1_MAS +}; + +static struct qcom_icc_node snoc_int_bimc = { + .name = "snoc_int_bimc", + .id = MSM8939_SNOC_INT_BIMC, + .buswidth = 8, + .mas_rpm_id = 101, + .slv_rpm_id = 132, + .num_links = ARRAY_SIZE(snoc_int_bimc_links), + .links = snoc_int_bimc_links, +}; + +static const u16 snoc_pcnoc_mas_links[] = { + MSM8939_SNOC_PNOC_SLV +}; + +static struct qcom_icc_node snoc_pcnoc_mas = { + .name = "snoc_pcnoc_mas", + .id = MSM8939_SNOC_PNOC_MAS, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links), + .links = snoc_pcnoc_mas_links, +}; + +static const u16 snoc_pcnoc_slv_links[] = { + MSM8939_PNOC_INT_0 +}; + +static struct qcom_icc_node snoc_pcnoc_slv = { + .name = "snoc_pcnoc_slv", + .id = MSM8939_SNOC_PNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links), + .links = snoc_pcnoc_slv_links, +}; static struct qcom_icc_node *msm8939_snoc_nodes[] = { [BIMC_SNOC_SLV] = &bimc_snoc_slv, From patchwork Fri Sep 3 23:24:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506564 Delivered-To: patch@linaro.org Received: by 2002:a17:906:f46:0:0:0:0 with SMTP id h6csp1976490ejj; Fri, 3 Sep 2021 16:24:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7iRJgm8zE7mVppWxzNqtjEvQDWOFPtCR0msK3EgvHp62oEzJa4ifnzThxlxJVLvEGekgC X-Received: by 2002:a05:6402:2210:: with SMTP id cq16mr1437743edb.348.1630711478346; Fri, 03 Sep 2021 16:24:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630711478; cv=none; d=google.com; s=arc-20160816; b=EORsRZ6dnGH0+umUzw1SJylRmeZ3uv+dA5AIWffdSX9QFnL4MdMF5dujJacBdwT7+s I7YRuicIXJ6o5y7202bELDAiyRkQf/7q7KZBVeMuIz8ul48sh2zEphptTgm0HgPgAnLS DREUHPmMVAhB48Qk+zmADHI0ZIGfaw8lohwKfUqvzafOvQ4zXeGQVuKVNIWmugBIbqrf LQPThbcQILyZyWSGC45fsATwu7PARMF0sCqHUGw1Qj0p7OE+TMXwXedXqO/0GocmJkOy QS/fs8aU+3Ncx/c2kLyiuyqp4glIyDXdDqJR84+d2KykVNk/Xtfa1C4SeC8QSoY3MktA cWBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mpmkely3snBZj1eVUyvD0B60pqPU0GFtLzvraxIrCD8=; b=MQNlqDcHXk4RscnGCcIxCenGuDFEsVpmrrWG5GcyjYagfARiAhuDzAUMja2qgTaGXB udQbBo4++MSbmyDr5XeD0+jY2l8LeoTWN/qgI6PrtLBtoIuId5rvRx4GOfuBaWY25pFF 0K/Ql4aTN3cbRb9hoqGauwE7qDR1mn9YrJoCK9MBZWiAWxiWzDn7suXord/0hixIsK31 /y0n6+OOEhHHoArDSVYoNC70fMnn8M6+ory3r0o9YFGHlh0GtI2DVWCiG/lBzaOfYwcL IsVC5epn+hGNf90KoSLEyvKiVGN36wJ5jX80LZg+GusNEgXkIIrfxxWkOE3OZcc/hg6W zd+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJA8zc7Q; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp5si572394ejc.132.2021.09.03.16.24.38; Fri, 03 Sep 2021 16:24:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJA8zc7Q; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350766AbhICXZe (ORCPT + 16 others); Fri, 3 Sep 2021 19:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350767AbhICXZd (ORCPT ); Fri, 3 Sep 2021 19:25:33 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03E32C061764 for ; Fri, 3 Sep 2021 16:24:33 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id t19so1289440lfe.13 for ; Fri, 03 Sep 2021 16:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mpmkely3snBZj1eVUyvD0B60pqPU0GFtLzvraxIrCD8=; b=RJA8zc7Qm1G1hR0lwds+t5dPjBlhjr9qL6wONe/sDwwA8VmZRXsCcFP3YYifnSnk0g cvvS+ZPPtkFXwyFItmXadomofG2s108ZbdSwbxSC2kMY4SkFH9GapF+4DAz1foCb/o7w PzZkiw0UK0hxxbX2EhwGdetw9tAOztqb5KyBPdITKsyLCB74lRkscmRN4fgZfPdn6V48 RyDBsdiBIZjQSlkU87aNDWTCDTxaZ14viUy9szuWBH59+Dkco0bMNvfmTg0OEnYXB014 8AMqi8q4ASChSU+fxG4QZNJYLt/TCimyRcjnVGW9z0JGJgnJBz0SqnLIyiBCxV52nEjo 9DjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mpmkely3snBZj1eVUyvD0B60pqPU0GFtLzvraxIrCD8=; b=famNJEZZqRUa962iwPaWLFeZuY5Ys2X482ZVfKRLKNpBwUULWeR88IabAkdDiVT04N DaZsug5Mq5aANDx6kuG3Cb9mLhBG3gP+Y9UO1uBza02k6UHgpGjTAsKrCui8nWg68lLI myDzxT+IIZhoGCu0q2MaZQcPrNyCiQlYN7SFMbAR+/9aV2TRXnSf1basJgGQQ0jZDyzX fPZzidsZ1zft4bvW0caObUkDqx1Ka/DyG8WnrIG9+s4WkY3bE0nUFM4qWti1sWN2zqVk 0DfkwhoDsYt9HgYEpQhd70802oWLgK/kYNV/a25NTLM0FTdabTVyVT3ZxYH8Yr2yn3vZ X+hQ== X-Gm-Message-State: AOAM533hhIm1FahENfrik7p/QB5/gK935xlfDl6693hL3RoCuN7XfJPz 8DEv5psxqA0EmFK54h35PRUnJA== X-Received: by 2002:a05:6512:30b:: with SMTP id t11mr978642lfp.166.1630711471362; Fri, 03 Sep 2021 16:24:31 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 09/11] interconnect: msm8939: add support for AP-owned nodes Date: Sat, 4 Sep 2021 02:24:19 +0300 Message-Id: <20210903232421.1384199-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Port support for AP-owned nodes from the downstream device tree. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/msm8939.c | 115 ++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) -- 2.33.0 Reviewed-by: AngeloGioacchino Del Regno diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 4671538c8994..16272a477bd8 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -120,6 +121,8 @@ static struct qcom_icc_node bimc_snoc_mas = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(bimc_snoc_mas_links), .links = bimc_snoc_mas_links, }; @@ -151,6 +154,11 @@ static struct qcom_icc_node mas_apss = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 0, .num_links = ARRAY_SIZE(mas_apss_links), .links = mas_apss_links, }; @@ -209,6 +217,11 @@ static struct qcom_icc_node mas_gfx = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 2, .num_links = ARRAY_SIZE(mas_gfx_links), .links = mas_gfx_links, }; @@ -224,6 +237,11 @@ static struct qcom_icc_node mas_jpeg = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 6, .num_links = ARRAY_SIZE(mas_jpeg_links), .links = mas_jpeg_links, }; @@ -239,6 +257,11 @@ static struct qcom_icc_node mas_mdp0 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 7, .num_links = ARRAY_SIZE(mas_mdp0_links), .links = mas_mdp0_links, }; @@ -254,6 +277,11 @@ static struct qcom_icc_node mas_mdp1 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 13, .num_links = ARRAY_SIZE(mas_mdp1_links), .links = mas_mdp1_links, }; @@ -269,6 +297,11 @@ static struct qcom_icc_node mas_cpp = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 12, .num_links = ARRAY_SIZE(mas_cpp_links), .links = mas_cpp_links, }; @@ -325,6 +358,11 @@ static struct qcom_icc_node mas_qdss_bam = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 11, .num_links = ARRAY_SIZE(mas_qdss_bam_links), .links = mas_qdss_bam_links, }; @@ -339,6 +377,11 @@ static struct qcom_icc_node mas_qdss_etr = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 10, .num_links = ARRAY_SIZE(mas_qdss_etr_links), .links = mas_qdss_etr_links, }; @@ -383,6 +426,11 @@ static struct qcom_icc_node mas_tcu0 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .qos.prio_level = 2, + .qos.qos_port = 6, .num_links = ARRAY_SIZE(mas_tcu0_links), .links = mas_tcu0_links, }; @@ -426,6 +474,11 @@ static struct qcom_icc_node mas_vfe = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 9, .num_links = ARRAY_SIZE(mas_vfe_links), .links = mas_vfe_links, }; @@ -441,6 +494,11 @@ static struct qcom_icc_node mas_video = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 8, .num_links = ARRAY_SIZE(mas_video_links), .links = mas_video_links, }; @@ -455,6 +513,8 @@ static struct qcom_icc_node mm_int_0 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_0_links), .links = mm_int_0_links, }; @@ -469,6 +529,8 @@ static struct qcom_icc_node mm_int_1 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_1_links), .links = mm_int_1_links, }; @@ -483,6 +545,8 @@ static struct qcom_icc_node mm_int_2 = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(mm_int_2_links), .links = mm_int_2_links, }; @@ -711,6 +775,8 @@ static struct qcom_icc_node qdss_int = { .buswidth = 8, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(qdss_int_links), .links = qdss_int_links, }; @@ -1029,6 +1095,8 @@ static struct qcom_icc_node snoc_bimc_0_mas = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links), .links = snoc_bimc_0_mas_links, }; @@ -1043,6 +1111,8 @@ static struct qcom_icc_node snoc_bimc_0_slv = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links), .links = snoc_bimc_0_slv_links, }; @@ -1085,6 +1155,8 @@ static struct qcom_icc_node snoc_bimc_2_mas = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(snoc_bimc_2_mas_links), .links = snoc_bimc_2_mas_links, }; @@ -1099,6 +1171,8 @@ static struct qcom_icc_node snoc_bimc_2_slv = { .buswidth = 16, .mas_rpm_id = -1, .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, .num_links = ARRAY_SIZE(snoc_bimc_2_slv_links), .links = snoc_bimc_2_slv_links, }; @@ -1199,9 +1273,19 @@ static struct qcom_icc_node *msm8939_snoc_nodes[] = { [SNOC_QDSS_INT] = &qdss_int, }; +static const struct regmap_config msm8939_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14080, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_snoc = { .nodes = msm8939_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), + .regmap_cfg = &msm8939_snoc_regmap_config, + .qos_offset = 0x7000, }; static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { @@ -1216,9 +1300,19 @@ static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { [SNOC_MM_INT_2] = &mm_int_2, }; +static const struct regmap_config msm8939_snoc_mm_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14080, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_snoc_mm = { .nodes = msm8939_snoc_mm_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), + .regmap_cfg = &msm8939_snoc_mm_regmap_config, + .qos_offset = 0x7000, }; static struct qcom_icc_node *msm8939_bimc_nodes[] = { @@ -1233,9 +1327,20 @@ static struct qcom_icc_node *msm8939_bimc_nodes[] = { [SNOC_BIMC_2_SLV] = &snoc_bimc_2_slv, }; +static const struct regmap_config msm8939_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x62000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_bimc = { .nodes = msm8939_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), + .is_bimc_node = true, + .regmap_cfg = &msm8939_bimc_regmap_config, + .qos_offset = 0x8000, }; static struct qcom_icc_node *msm8939_pcnoc_nodes[] = { @@ -1293,9 +1398,19 @@ static struct qcom_icc_node *msm8939_pcnoc_nodes[] = { [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, }; +static const struct regmap_config msm8939_pcnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x11000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_pcnoc = { .nodes = msm8939_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), + .regmap_cfg = &msm8939_pcnoc_regmap_config, + .qos_offset = 0x7000, }; static const struct of_device_id msm8939_noc_of_match[] = { From patchwork Fri Sep 3 23:24:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506565 Delivered-To: patch@linaro.org Received: by 2002:a17:906:f46:0:0:0:0 with SMTP id h6csp1976505ejj; Fri, 3 Sep 2021 16:24:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyn6pdoRXPLRrJGNWFU9lxGHk6ByLG9IFgAantZjISTTRsi9nmwyPG1UtxTt1GleIIUGcV7 X-Received: by 2002:a17:906:bfe3:: with SMTP id vr3mr1331736ejb.521.1630711479214; Fri, 03 Sep 2021 16:24:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630711479; cv=none; d=google.com; s=arc-20160816; b=HdsYez/jUDxN++qSdYtSnp5TcvM1/7itLSYbFzlBXEGli0ulSM8Z4pd2AmW+7pXuSk e+2vuRy1zrFoWE7rx0LEsEVC1IxP+sPW9UXk69a+lzncz97ckClTQ1cV7G8aSvuiDjQO i26cgepR7drKutD5pZoeR+fbNyJdeDF5oGHxnZDr6nnzSTdar2aE2oYm9jGUJ+JPli55 BrRQdD+1SMYxpoW7ThDhkhJZEHUEhn564DkBT49sLeFbBfPeHgOaWLUoo0ZDsPs7nFzl 9JU4/lpeFBqiIhr+UQCmcb1uqJy/oogOEGHBizZur1tf2wOq3IMLvY6y4CXTHBDolvSq YT0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UUkdu7UGjA2OFB74Zoe9X+G2ubB5+YozYf7BNpJaLrM=; b=j8jh5UfbEBbNdb6+8ACMB5/FvnXEF5KELMqZ5U6j+P58dlI0/284w3dRAhWEcyYLLH F+TOvZ1Aa3LDS9b91W9o6BSqmvpSZgHvfLDssFFDZBmuS5OudqL5l1elWefv47WYNFCi VXTaVbFXmbaFIv2Z/tjoWfzy3G7iEVKd0fbNHcNMDpl3/ysta+qdP4oFAYbrbr1CxdrX eKFzLYtyxHIUYMiQpmhKD46AqoHLnczcr79S2cV+nUOru+Wy5Lmo+y6t8XijqInLvlyM q4z0cdwfd/TbaQPHzkppopl2FxK5W7/qEZU/9ahACzJL/6Jhk+li09vAw+Z8vJT71P0n rHWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i8ionofU; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp5si572394ejc.132.2021.09.03.16.24.38; Fri, 03 Sep 2021 16:24:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i8ionofU; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350774AbhICXZf (ORCPT + 16 others); Fri, 3 Sep 2021 19:25:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350767AbhICXZe (ORCPT ); Fri, 3 Sep 2021 19:25:34 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 048FBC061757 for ; Fri, 3 Sep 2021 16:24:34 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id s10so1303526lfr.11 for ; Fri, 03 Sep 2021 16:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UUkdu7UGjA2OFB74Zoe9X+G2ubB5+YozYf7BNpJaLrM=; b=i8ionofUJFXvK8ukRaL1KKbnjwYtXY8SmYuG7YmQXBQWREO2DI7Nf0R2qMHX7MNpg8 0Xf4FHhKaoYjpI9HG3IX1KxTA1TjJJyDd5cZMweDaiAHxxwVA27gXbKZiuKutEoh0SfU K3LJJTsIig/udQzk2kmUgcppj0FLBRFIzsgCexcjFdJYpoF1PKzg8L6F1fcuguJ+ZvD/ J+BvEd7XyAdaYYxv91Jz5GMneqlh9fOoX5ER1CGFyjaGGYMwXT3eb2rLLYnKPNhCJy7v 5FMt5UZxCLaFWOwk/6GXTcFKrYUN0ANgidshECEjmz1uPpTihjqUuOAkhxIkppulS44C 5dkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UUkdu7UGjA2OFB74Zoe9X+G2ubB5+YozYf7BNpJaLrM=; b=nNU4qLo3mQh5NabodVM59AwOACrsT5loDMWA/B2HTsIf2oY61QwQLNFp6F9YEphiSe 5E1kMpjf2xmgyrUCoPHAFKBRDhUvdZJNGBHZqg9eqtOkTcCVzipP0XOuPDsTe5c1r2/X cQ1hCph/tEiiJpyuA+Lx+CcJVQO4EcBQbOCQug/6v9a2V2MKil4rFOigaWuR/3SbGEt/ C3663jnKPvMhnogxCgf5FGXmDKeA5ELTMTa9t08OKRa/OMcuY479PEnIUYIr2rUwImpL LFksKT+LmLV97PSPMnhtWbteOT+K89d158xkGU+mZAcQ2CxNz7kwuau8tDYvV/rDhyw2 u8hQ== X-Gm-Message-State: AOAM533ZOooU7xJlmGoY4tRpN9r944tFpcHCYPaSolQbgVSb7KnY9kLP 2dL/qHCzj6sNZ3bt1iVzb22htQ== X-Received: by 2002:a05:6512:3408:: with SMTP id i8mr918942lfr.659.1630711472171; Fri, 03 Sep 2021 16:24:32 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 10/11] interconnect: qcs404: expand DEFINE_QNODE macros Date: Sat, 4 Sep 2021 02:24:20 +0300 Message-Id: <20210903232421.1384199-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To follow the example of the rest of icc-rpm.h drivers, expand DEFINE_QNODE macros in the driver. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/qcs404.c | 954 ++++++++++++++++++++++++++--- 1 file changed, 881 insertions(+), 73 deletions(-) -- 2.33.0 Reviewed-by: AngeloGioacchino Del Regno diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 0f2fff230b13..416c8bff8efa 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -92,79 +92,887 @@ enum { QCS404_SLAVE_LPASS, }; -DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); -DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); -DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); -DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0); -DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); -DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3); -DEFINE_QNODE(mas_blsp_1, QCS404_MASTER_BLSP_1, 4, 41, -1, QCS404_PNOC_INT_3); -DEFINE_QNODE(mas_blsp_2, QCS404_MASTER_BLSP_2, 4, 39, -1, QCS404_PNOC_INT_3); -DEFINE_QNODE(mas_xi_usb_hs1, QCS404_MASTER_XM_USB_HS1, 8, 138, -1, QCS404_PNOC_INT_0); -DEFINE_QNODE(mas_crypto, QCS404_MASTER_CRYPTO_CORE0, 8, 23, -1, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2); -DEFINE_QNODE(mas_sdcc_1, QCS404_MASTER_SDCC_1, 8, 33, -1, QCS404_PNOC_INT_0); -DEFINE_QNODE(mas_sdcc_2, QCS404_MASTER_SDCC_2, 8, 35, -1, QCS404_PNOC_INT_0); -DEFINE_QNODE(mas_snoc_pcnoc, QCS404_SNOC_PNOC_MAS, 8, 77, -1, QCS404_PNOC_INT_2); -DEFINE_QNODE(mas_qpic, QCS404_MASTER_QPIC, 4, -1, -1, QCS404_PNOC_INT_0); -DEFINE_QNODE(mas_qdss_bam, QCS404_MASTER_QDSS_BAM, 4, -1, -1, QCS404_SNOC_QDSS_INT); -DEFINE_QNODE(mas_bimc_snoc, QCS404_BIMC_SNOC_MAS, 8, 21, -1, QCS404_SLAVE_OCMEM_64, QCS404_SLAVE_CATS_128, QCS404_SNOC_INT_0, QCS404_SNOC_INT_1); -DEFINE_QNODE(mas_pcnoc_snoc, QCS404_PNOC_SNOC_MAS, 8, 29, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_2, QCS404_SNOC_INT_0); -DEFINE_QNODE(mas_qdss_etr, QCS404_MASTER_QDSS_ETR, 8, -1, -1, QCS404_SNOC_QDSS_INT); -DEFINE_QNODE(mas_emac, QCS404_MASTER_EMAC, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1); -DEFINE_QNODE(mas_pcie, QCS404_MASTER_PCIE, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1); -DEFINE_QNODE(mas_usb3, QCS404_MASTER_USB3, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1); -DEFINE_QNODE(pcnoc_int_0, QCS404_PNOC_INT_0, 8, 85, 114, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2); -DEFINE_QNODE(pcnoc_int_2, QCS404_PNOC_INT_2, 8, 124, 184, QCS404_PNOC_SLV_10, QCS404_SLAVE_TCU, QCS404_PNOC_SLV_11, QCS404_PNOC_SLV_2, QCS404_PNOC_SLV_3, QCS404_PNOC_SLV_0, QCS404_PNOC_SLV_1, QCS404_PNOC_SLV_6, QCS404_PNOC_SLV_7, QCS404_PNOC_SLV_4, QCS404_PNOC_SLV_8, QCS404_PNOC_SLV_9); -DEFINE_QNODE(pcnoc_int_3, QCS404_PNOC_INT_3, 8, 125, 185, QCS404_PNOC_SNOC_SLV); -DEFINE_QNODE(pcnoc_s_0, QCS404_PNOC_SLV_0, 4, 89, 118, QCS404_SLAVE_PRNG, QCS404_SLAVE_SPDM_WRAPPER, QCS404_SLAVE_PDM); -DEFINE_QNODE(pcnoc_s_1, QCS404_PNOC_SLV_1, 4, 90, 119, QCS404_SLAVE_TCSR); -DEFINE_QNODE(pcnoc_s_2, QCS404_PNOC_SLV_2, 4, -1, -1, QCS404_SLAVE_GRAPHICS_3D_CFG); -DEFINE_QNODE(pcnoc_s_3, QCS404_PNOC_SLV_3, 4, 92, 121, QCS404_SLAVE_MESSAGE_RAM); -DEFINE_QNODE(pcnoc_s_4, QCS404_PNOC_SLV_4, 4, 93, 122, QCS404_SLAVE_SNOC_CFG); -DEFINE_QNODE(pcnoc_s_6, QCS404_PNOC_SLV_6, 4, 94, 123, QCS404_SLAVE_BLSP_1, QCS404_SLAVE_TLMM_NORTH, QCS404_SLAVE_EMAC_CFG); -DEFINE_QNODE(pcnoc_s_7, QCS404_PNOC_SLV_7, 4, 95, 124, QCS404_SLAVE_TLMM_SOUTH, QCS404_SLAVE_DISPLAY_CFG, QCS404_SLAVE_SDCC_1, QCS404_SLAVE_PCIE_1, QCS404_SLAVE_SDCC_2); -DEFINE_QNODE(pcnoc_s_8, QCS404_PNOC_SLV_8, 4, 96, 125, QCS404_SLAVE_CRYPTO_0_CFG); -DEFINE_QNODE(pcnoc_s_9, QCS404_PNOC_SLV_9, 4, 97, 126, QCS404_SLAVE_BLSP_2, QCS404_SLAVE_TLMM_EAST, QCS404_SLAVE_PMIC_ARB); -DEFINE_QNODE(pcnoc_s_10, QCS404_PNOC_SLV_10, 4, 157, -1, QCS404_SLAVE_USB_HS); -DEFINE_QNODE(pcnoc_s_11, QCS404_PNOC_SLV_11, 4, 158, 246, QCS404_SLAVE_USB3); -DEFINE_QNODE(qdss_int, QCS404_SNOC_QDSS_INT, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1); -DEFINE_QNODE(snoc_int_0, QCS404_SNOC_INT_0, 8, 99, 130, QCS404_SLAVE_LPASS, QCS404_SLAVE_APPSS, QCS404_SLAVE_WCSS); -DEFINE_QNODE(snoc_int_1, QCS404_SNOC_INT_1, 8, 100, 131, QCS404_SNOC_PNOC_SLV, QCS404_SNOC_INT_2); -DEFINE_QNODE(snoc_int_2, QCS404_SNOC_INT_2, 8, 134, 197, QCS404_SLAVE_QDSS_STM, QCS404_SLAVE_OCIMEM); -DEFINE_QNODE(slv_ebi, QCS404_SLAVE_EBI_CH0, 8, -1, 0, 0); -DEFINE_QNODE(slv_bimc_snoc, QCS404_BIMC_SNOC_SLV, 8, -1, 2, QCS404_BIMC_SNOC_MAS); -DEFINE_QNODE(slv_spdm, QCS404_SLAVE_SPDM_WRAPPER, 4, -1, -1, 0); -DEFINE_QNODE(slv_pdm, QCS404_SLAVE_PDM, 4, -1, 41, 0); -DEFINE_QNODE(slv_prng, QCS404_SLAVE_PRNG, 4, -1, 44, 0); -DEFINE_QNODE(slv_tcsr, QCS404_SLAVE_TCSR, 4, -1, 50, 0); -DEFINE_QNODE(slv_snoc_cfg, QCS404_SLAVE_SNOC_CFG, 4, -1, 70, 0); -DEFINE_QNODE(slv_message_ram, QCS404_SLAVE_MESSAGE_RAM, 4, -1, 55, 0); -DEFINE_QNODE(slv_disp_ss_cfg, QCS404_SLAVE_DISPLAY_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_gpu_cfg, QCS404_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_blsp_1, QCS404_SLAVE_BLSP_1, 4, -1, 39, 0); -DEFINE_QNODE(slv_tlmm_north, QCS404_SLAVE_TLMM_NORTH, 4, -1, 214, 0); -DEFINE_QNODE(slv_pcie, QCS404_SLAVE_PCIE_1, 4, -1, -1, 0); -DEFINE_QNODE(slv_ethernet, QCS404_SLAVE_EMAC_CFG, 4, -1, -1, 0); -DEFINE_QNODE(slv_blsp_2, QCS404_SLAVE_BLSP_2, 4, -1, 37, 0); -DEFINE_QNODE(slv_tlmm_east, QCS404_SLAVE_TLMM_EAST, 4, -1, 213, 0); -DEFINE_QNODE(slv_tcu, QCS404_SLAVE_TCU, 8, -1, -1, 0); -DEFINE_QNODE(slv_pmic_arb, QCS404_SLAVE_PMIC_ARB, 4, -1, 59, 0); -DEFINE_QNODE(slv_sdcc_1, QCS404_SLAVE_SDCC_1, 4, -1, 31, 0); -DEFINE_QNODE(slv_sdcc_2, QCS404_SLAVE_SDCC_2, 4, -1, 33, 0); -DEFINE_QNODE(slv_tlmm_south, QCS404_SLAVE_TLMM_SOUTH, 4, -1, -1, 0); -DEFINE_QNODE(slv_usb_hs, QCS404_SLAVE_USB_HS, 4, -1, 40, 0); -DEFINE_QNODE(slv_usb3, QCS404_SLAVE_USB3, 4, -1, 22, 0); -DEFINE_QNODE(slv_crypto_0_cfg, QCS404_SLAVE_CRYPTO_0_CFG, 4, -1, 52, 0); -DEFINE_QNODE(slv_pcnoc_snoc, QCS404_PNOC_SNOC_SLV, 8, -1, 45, QCS404_PNOC_SNOC_MAS); -DEFINE_QNODE(slv_kpss_ahb, QCS404_SLAVE_APPSS, 4, -1, -1, 0); -DEFINE_QNODE(slv_wcss, QCS404_SLAVE_WCSS, 4, -1, 23, 0); -DEFINE_QNODE(slv_snoc_bimc_1, QCS404_SNOC_BIMC_1_SLV, 8, -1, 104, QCS404_SNOC_BIMC_1_MAS); -DEFINE_QNODE(slv_imem, QCS404_SLAVE_OCIMEM, 8, -1, 26, 0); -DEFINE_QNODE(slv_snoc_pcnoc, QCS404_SNOC_PNOC_SLV, 8, -1, 28, QCS404_SNOC_PNOC_MAS); -DEFINE_QNODE(slv_qdss_stm, QCS404_SLAVE_QDSS_STM, 4, -1, 30, 0); -DEFINE_QNODE(slv_cats_0, QCS404_SLAVE_CATS_128, 16, -1, -1, 0); -DEFINE_QNODE(slv_cats_1, QCS404_SLAVE_OCMEM_64, 8, -1, -1, 0); -DEFINE_QNODE(slv_lpass, QCS404_SLAVE_LPASS, 4, -1, -1, 0); +static const u16 mas_apps_proc_links[] = { + QCS404_SLAVE_EBI_CH0, + QCS404_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_apps_proc = { + .name = "mas_apps_proc", + .id = QCS404_MASTER_AMPSS_M0, + .buswidth = 8, + .mas_rpm_id = 0, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_apps_proc_links), + .links = mas_apps_proc_links, +}; + +static const u16 mas_oxili_links[] = { + QCS404_SLAVE_EBI_CH0, + QCS404_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_oxili = { + .name = "mas_oxili", + .id = QCS404_MASTER_GRAPHICS_3D, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_oxili_links), + .links = mas_oxili_links, +}; + +static const u16 mas_mdp_links[] = { + QCS404_SLAVE_EBI_CH0, + QCS404_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_mdp = { + .name = "mas_mdp", + .id = QCS404_MASTER_MDP_PORT0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_mdp_links), + .links = mas_mdp_links, +}; + +static const u16 mas_snoc_bimc_1_links[] = { + QCS404_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc_1 = { + .name = "mas_snoc_bimc_1", + .id = QCS404_SNOC_BIMC_1_MAS, + .buswidth = 8, + .mas_rpm_id = 76, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links), + .links = mas_snoc_bimc_1_links, +}; + +static const u16 mas_tcu_0_links[] = { + QCS404_SLAVE_EBI_CH0, + QCS404_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_tcu_0 = { + .name = "mas_tcu_0", + .id = QCS404_MASTER_TCU_0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_tcu_0_links), + .links = mas_tcu_0_links, +}; + +static const u16 mas_spdm_links[] = { + QCS404_PNOC_INT_3 +}; + +static struct qcom_icc_node mas_spdm = { + .name = "mas_spdm", + .id = QCS404_MASTER_SPDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_spdm_links), + .links = mas_spdm_links, +}; + +static const u16 mas_blsp_1_links[] = { + QCS404_PNOC_INT_3 +}; + +static struct qcom_icc_node mas_blsp_1 = { + .name = "mas_blsp_1", + .id = QCS404_MASTER_BLSP_1, + .buswidth = 4, + .mas_rpm_id = 41, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_blsp_1_links), + .links = mas_blsp_1_links, +}; + +static const u16 mas_blsp_2_links[] = { + QCS404_PNOC_INT_3 +}; + +static struct qcom_icc_node mas_blsp_2 = { + .name = "mas_blsp_2", + .id = QCS404_MASTER_BLSP_2, + .buswidth = 4, + .mas_rpm_id = 39, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_blsp_2_links), + .links = mas_blsp_2_links, +}; + +static const u16 mas_xi_usb_hs1_links[] = { + QCS404_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_xi_usb_hs1 = { + .name = "mas_xi_usb_hs1", + .id = QCS404_MASTER_XM_USB_HS1, + .buswidth = 8, + .mas_rpm_id = 138, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_xi_usb_hs1_links), + .links = mas_xi_usb_hs1_links, +}; + +static const u16 mas_crypto_links[] = { + QCS404_PNOC_SNOC_SLV, + QCS404_PNOC_INT_2 +}; + +static struct qcom_icc_node mas_crypto = { + .name = "mas_crypto", + .id = QCS404_MASTER_CRYPTO_CORE0, + .buswidth = 8, + .mas_rpm_id = 23, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_crypto_links), + .links = mas_crypto_links, +}; + +static const u16 mas_sdcc_1_links[] = { + QCS404_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_sdcc_1 = { + .name = "mas_sdcc_1", + .id = QCS404_MASTER_SDCC_1, + .buswidth = 8, + .mas_rpm_id = 33, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_sdcc_1_links), + .links = mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] = { + QCS404_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_sdcc_2 = { + .name = "mas_sdcc_2", + .id = QCS404_MASTER_SDCC_2, + .buswidth = 8, + .mas_rpm_id = 35, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_sdcc_2_links), + .links = mas_sdcc_2_links, +}; + +static const u16 mas_snoc_pcnoc_links[] = { + QCS404_PNOC_INT_2 +}; + +static struct qcom_icc_node mas_snoc_pcnoc = { + .name = "mas_snoc_pcnoc", + .id = QCS404_SNOC_PNOC_MAS, + .buswidth = 8, + .mas_rpm_id = 77, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), + .links = mas_snoc_pcnoc_links, +}; + +static const u16 mas_qpic_links[] = { + QCS404_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_qpic = { + .name = "mas_qpic", + .id = QCS404_MASTER_QPIC, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qpic_links), + .links = mas_qpic_links, +}; + +static const u16 mas_qdss_bam_links[] = { + QCS404_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam = { + .name = "mas_qdss_bam", + .id = QCS404_MASTER_QDSS_BAM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_bam_links), + .links = mas_qdss_bam_links, +}; + +static const u16 mas_bimc_snoc_links[] = { + QCS404_SLAVE_OCMEM_64, + QCS404_SLAVE_CATS_128, + QCS404_SNOC_INT_0, + QCS404_SNOC_INT_1 +}; + +static struct qcom_icc_node mas_bimc_snoc = { + .name = "mas_bimc_snoc", + .id = QCS404_BIMC_SNOC_MAS, + .buswidth = 8, + .mas_rpm_id = 21, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_bimc_snoc_links), + .links = mas_bimc_snoc_links, +}; + +static const u16 mas_pcnoc_snoc_links[] = { + QCS404_SNOC_BIMC_1_SLV, + QCS404_SNOC_INT_2, + QCS404_SNOC_INT_0 +}; + +static struct qcom_icc_node mas_pcnoc_snoc = { + .name = "mas_pcnoc_snoc", + .id = QCS404_PNOC_SNOC_MAS, + .buswidth = 8, + .mas_rpm_id = 29, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), + .links = mas_pcnoc_snoc_links, +}; + +static const u16 mas_qdss_etr_links[] = { + QCS404_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr = { + .name = "mas_qdss_etr", + .id = QCS404_MASTER_QDSS_ETR, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_etr_links), + .links = mas_qdss_etr_links, +}; + +static const u16 mas_emac_links[] = { + QCS404_SNOC_BIMC_1_SLV, + QCS404_SNOC_INT_1 +}; + +static struct qcom_icc_node mas_emac = { + .name = "mas_emac", + .id = QCS404_MASTER_EMAC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_emac_links), + .links = mas_emac_links, +}; + +static const u16 mas_pcie_links[] = { + QCS404_SNOC_BIMC_1_SLV, + QCS404_SNOC_INT_1 +}; + +static struct qcom_icc_node mas_pcie = { + .name = "mas_pcie", + .id = QCS404_MASTER_PCIE, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pcie_links), + .links = mas_pcie_links, +}; + +static const u16 mas_usb3_links[] = { + QCS404_SNOC_BIMC_1_SLV, + QCS404_SNOC_INT_1 +}; + +static struct qcom_icc_node mas_usb3 = { + .name = "mas_usb3", + .id = QCS404_MASTER_USB3, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_usb3_links), + .links = mas_usb3_links, +}; + +static const u16 pcnoc_int_0_links[] = { + QCS404_PNOC_SNOC_SLV, + QCS404_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_0 = { + .name = "pcnoc_int_0", + .id = QCS404_PNOC_INT_0, + .buswidth = 8, + .mas_rpm_id = 85, + .slv_rpm_id = 114, + .num_links = ARRAY_SIZE(pcnoc_int_0_links), + .links = pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_2_links[] = { + QCS404_PNOC_SLV_10, + QCS404_SLAVE_TCU, + QCS404_PNOC_SLV_11, + QCS404_PNOC_SLV_2, + QCS404_PNOC_SLV_3, + QCS404_PNOC_SLV_0, + QCS404_PNOC_SLV_1, + QCS404_PNOC_SLV_6, + QCS404_PNOC_SLV_7, + QCS404_PNOC_SLV_4, + QCS404_PNOC_SLV_8, + QCS404_PNOC_SLV_9 +}; + +static struct qcom_icc_node pcnoc_int_2 = { + .name = "pcnoc_int_2", + .id = QCS404_PNOC_INT_2, + .buswidth = 8, + .mas_rpm_id = 124, + .slv_rpm_id = 184, + .num_links = ARRAY_SIZE(pcnoc_int_2_links), + .links = pcnoc_int_2_links, +}; + +static const u16 pcnoc_int_3_links[] = { + QCS404_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_int_3 = { + .name = "pcnoc_int_3", + .id = QCS404_PNOC_INT_3, + .buswidth = 8, + .mas_rpm_id = 125, + .slv_rpm_id = 185, + .num_links = ARRAY_SIZE(pcnoc_int_3_links), + .links = pcnoc_int_3_links, +}; + +static const u16 pcnoc_s_0_links[] = { + QCS404_SLAVE_PRNG, + QCS404_SLAVE_SPDM_WRAPPER, + QCS404_SLAVE_PDM +}; + +static struct qcom_icc_node pcnoc_s_0 = { + .name = "pcnoc_s_0", + .id = QCS404_PNOC_SLV_0, + .buswidth = 4, + .mas_rpm_id = 89, + .slv_rpm_id = 118, + .num_links = ARRAY_SIZE(pcnoc_s_0_links), + .links = pcnoc_s_0_links, +}; + +static const u16 pcnoc_s_1_links[] = { + QCS404_SLAVE_TCSR +}; + +static struct qcom_icc_node pcnoc_s_1 = { + .name = "pcnoc_s_1", + .id = QCS404_PNOC_SLV_1, + .buswidth = 4, + .mas_rpm_id = 90, + .slv_rpm_id = 119, + .num_links = ARRAY_SIZE(pcnoc_s_1_links), + .links = pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] = { + QCS404_SLAVE_GRAPHICS_3D_CFG +}; + +static struct qcom_icc_node pcnoc_s_2 = { + .name = "pcnoc_s_2", + .id = QCS404_PNOC_SLV_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_2_links), + .links = pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] = { + QCS404_SLAVE_MESSAGE_RAM +}; + +static struct qcom_icc_node pcnoc_s_3 = { + .name = "pcnoc_s_3", + .id = QCS404_PNOC_SLV_3, + .buswidth = 4, + .mas_rpm_id = 92, + .slv_rpm_id = 121, + .num_links = ARRAY_SIZE(pcnoc_s_3_links), + .links = pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] = { + QCS404_SLAVE_SNOC_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 = { + .name = "pcnoc_s_4", + .id = QCS404_PNOC_SLV_4, + .buswidth = 4, + .mas_rpm_id = 93, + .slv_rpm_id = 122, + .num_links = ARRAY_SIZE(pcnoc_s_4_links), + .links = pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_6_links[] = { + QCS404_SLAVE_BLSP_1, + QCS404_SLAVE_TLMM_NORTH, + QCS404_SLAVE_EMAC_CFG +}; + +static struct qcom_icc_node pcnoc_s_6 = { + .name = "pcnoc_s_6", + .id = QCS404_PNOC_SLV_6, + .buswidth = 4, + .mas_rpm_id = 94, + .slv_rpm_id = 123, + .num_links = ARRAY_SIZE(pcnoc_s_6_links), + .links = pcnoc_s_6_links, +}; + +static const u16 pcnoc_s_7_links[] = { + QCS404_SLAVE_TLMM_SOUTH, + QCS404_SLAVE_DISPLAY_CFG, + QCS404_SLAVE_SDCC_1, + QCS404_SLAVE_PCIE_1, + QCS404_SLAVE_SDCC_2 +}; + +static struct qcom_icc_node pcnoc_s_7 = { + .name = "pcnoc_s_7", + .id = QCS404_PNOC_SLV_7, + .buswidth = 4, + .mas_rpm_id = 95, + .slv_rpm_id = 124, + .num_links = ARRAY_SIZE(pcnoc_s_7_links), + .links = pcnoc_s_7_links, +}; + +static const u16 pcnoc_s_8_links[] = { + QCS404_SLAVE_CRYPTO_0_CFG +}; + +static struct qcom_icc_node pcnoc_s_8 = { + .name = "pcnoc_s_8", + .id = QCS404_PNOC_SLV_8, + .buswidth = 4, + .mas_rpm_id = 96, + .slv_rpm_id = 125, + .num_links = ARRAY_SIZE(pcnoc_s_8_links), + .links = pcnoc_s_8_links, +}; + +static const u16 pcnoc_s_9_links[] = { + QCS404_SLAVE_BLSP_2, + QCS404_SLAVE_TLMM_EAST, + QCS404_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_9 = { + .name = "pcnoc_s_9", + .id = QCS404_PNOC_SLV_9, + .buswidth = 4, + .mas_rpm_id = 97, + .slv_rpm_id = 126, + .num_links = ARRAY_SIZE(pcnoc_s_9_links), + .links = pcnoc_s_9_links, +}; + +static const u16 pcnoc_s_10_links[] = { + QCS404_SLAVE_USB_HS +}; + +static struct qcom_icc_node pcnoc_s_10 = { + .name = "pcnoc_s_10", + .id = QCS404_PNOC_SLV_10, + .buswidth = 4, + .mas_rpm_id = 157, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(pcnoc_s_10_links), + .links = pcnoc_s_10_links, +}; + +static const u16 pcnoc_s_11_links[] = { + QCS404_SLAVE_USB3 +}; + +static struct qcom_icc_node pcnoc_s_11 = { + .name = "pcnoc_s_11", + .id = QCS404_PNOC_SLV_11, + .buswidth = 4, + .mas_rpm_id = 158, + .slv_rpm_id = 246, + .num_links = ARRAY_SIZE(pcnoc_s_11_links), + .links = pcnoc_s_11_links, +}; + +static const u16 qdss_int_links[] = { + QCS404_SNOC_BIMC_1_SLV, + QCS404_SNOC_INT_1 +}; + +static struct qcom_icc_node qdss_int = { + .name = "qdss_int", + .id = QCS404_SNOC_QDSS_INT, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(qdss_int_links), + .links = qdss_int_links, +}; + +static const u16 snoc_int_0_links[] = { + QCS404_SLAVE_LPASS, + QCS404_SLAVE_APPSS, + QCS404_SLAVE_WCSS +}; + +static struct qcom_icc_node snoc_int_0 = { + .name = "snoc_int_0", + .id = QCS404_SNOC_INT_0, + .buswidth = 8, + .mas_rpm_id = 99, + .slv_rpm_id = 130, + .num_links = ARRAY_SIZE(snoc_int_0_links), + .links = snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] = { + QCS404_SNOC_PNOC_SLV, + QCS404_SNOC_INT_2 +}; + +static struct qcom_icc_node snoc_int_1 = { + .name = "snoc_int_1", + .id = QCS404_SNOC_INT_1, + .buswidth = 8, + .mas_rpm_id = 100, + .slv_rpm_id = 131, + .num_links = ARRAY_SIZE(snoc_int_1_links), + .links = snoc_int_1_links, +}; + +static const u16 snoc_int_2_links[] = { + QCS404_SLAVE_QDSS_STM, + QCS404_SLAVE_OCIMEM +}; + +static struct qcom_icc_node snoc_int_2 = { + .name = "snoc_int_2", + .id = QCS404_SNOC_INT_2, + .buswidth = 8, + .mas_rpm_id = 134, + .slv_rpm_id = 197, + .num_links = ARRAY_SIZE(snoc_int_2_links), + .links = snoc_int_2_links, +}; + +static struct qcom_icc_node slv_ebi = { + .name = "slv_ebi", + .id = QCS404_SLAVE_EBI_CH0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 0, +}; + +static const u16 slv_bimc_snoc_links[] = { + QCS404_BIMC_SNOC_MAS +}; + +static struct qcom_icc_node slv_bimc_snoc = { + .name = "slv_bimc_snoc", + .id = QCS404_BIMC_SNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 2, + .num_links = ARRAY_SIZE(slv_bimc_snoc_links), + .links = slv_bimc_snoc_links, +}; + +static struct qcom_icc_node slv_spdm = { + .name = "slv_spdm", + .id = QCS404_SLAVE_SPDM_WRAPPER, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pdm = { + .name = "slv_pdm", + .id = QCS404_SLAVE_PDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 41, +}; + +static struct qcom_icc_node slv_prng = { + .name = "slv_prng", + .id = QCS404_SLAVE_PRNG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 44, +}; + +static struct qcom_icc_node slv_tcsr = { + .name = "slv_tcsr", + .id = QCS404_SLAVE_TCSR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 50, +}; + +static struct qcom_icc_node slv_snoc_cfg = { + .name = "slv_snoc_cfg", + .id = QCS404_SLAVE_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 70, +}; + +static struct qcom_icc_node slv_message_ram = { + .name = "slv_message_ram", + .id = QCS404_SLAVE_MESSAGE_RAM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 55, +}; + +static struct qcom_icc_node slv_disp_ss_cfg = { + .name = "slv_disp_ss_cfg", + .id = QCS404_SLAVE_DISPLAY_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_gpu_cfg = { + .name = "slv_gpu_cfg", + .id = QCS404_SLAVE_GRAPHICS_3D_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_blsp_1 = { + .name = "slv_blsp_1", + .id = QCS404_SLAVE_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 39, +}; + +static struct qcom_icc_node slv_tlmm_north = { + .name = "slv_tlmm_north", + .id = QCS404_SLAVE_TLMM_NORTH, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 214, +}; + +static struct qcom_icc_node slv_pcie = { + .name = "slv_pcie", + .id = QCS404_SLAVE_PCIE_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_ethernet = { + .name = "slv_ethernet", + .id = QCS404_SLAVE_EMAC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_blsp_2 = { + .name = "slv_blsp_2", + .id = QCS404_SLAVE_BLSP_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 37, +}; + +static struct qcom_icc_node slv_tlmm_east = { + .name = "slv_tlmm_east", + .id = QCS404_SLAVE_TLMM_EAST, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 213, +}; + +static struct qcom_icc_node slv_tcu = { + .name = "slv_tcu", + .id = QCS404_SLAVE_TCU, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_pmic_arb = { + .name = "slv_pmic_arb", + .id = QCS404_SLAVE_PMIC_ARB, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 59, +}; + +static struct qcom_icc_node slv_sdcc_1 = { + .name = "slv_sdcc_1", + .id = QCS404_SLAVE_SDCC_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 31, +}; + +static struct qcom_icc_node slv_sdcc_2 = { + .name = "slv_sdcc_2", + .id = QCS404_SLAVE_SDCC_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 33, +}; + +static struct qcom_icc_node slv_tlmm_south = { + .name = "slv_tlmm_south", + .id = QCS404_SLAVE_TLMM_SOUTH, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_usb_hs = { + .name = "slv_usb_hs", + .id = QCS404_SLAVE_USB_HS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 40, +}; + +static struct qcom_icc_node slv_usb3 = { + .name = "slv_usb3", + .id = QCS404_SLAVE_USB3, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 22, +}; + +static struct qcom_icc_node slv_crypto_0_cfg = { + .name = "slv_crypto_0_cfg", + .id = QCS404_SLAVE_CRYPTO_0_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 52, +}; + +static const u16 slv_pcnoc_snoc_links[] = { + QCS404_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node slv_pcnoc_snoc = { + .name = "slv_pcnoc_snoc", + .id = QCS404_PNOC_SNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 45, + .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), + .links = slv_pcnoc_snoc_links, +}; + +static struct qcom_icc_node slv_kpss_ahb = { + .name = "slv_kpss_ahb", + .id = QCS404_SLAVE_APPSS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_wcss = { + .name = "slv_wcss", + .id = QCS404_SLAVE_WCSS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 23, +}; + +static const u16 slv_snoc_bimc_1_links[] = { + QCS404_SNOC_BIMC_1_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc_1 = { + .name = "slv_snoc_bimc_1", + .id = QCS404_SNOC_BIMC_1_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 104, + .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links), + .links = slv_snoc_bimc_1_links, +}; + +static struct qcom_icc_node slv_imem = { + .name = "slv_imem", + .id = QCS404_SLAVE_OCIMEM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 26, +}; + +static const u16 slv_snoc_pcnoc_links[] = { + QCS404_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node slv_snoc_pcnoc = { + .name = "slv_snoc_pcnoc", + .id = QCS404_SNOC_PNOC_SLV, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 28, + .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), + .links = slv_snoc_pcnoc_links, +}; + +static struct qcom_icc_node slv_qdss_stm = { + .name = "slv_qdss_stm", + .id = QCS404_SLAVE_QDSS_STM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 30, +}; + +static struct qcom_icc_node slv_cats_0 = { + .name = "slv_cats_0", + .id = QCS404_SLAVE_CATS_128, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_cats_1 = { + .name = "slv_cats_1", + .id = QCS404_SLAVE_OCMEM_64, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; + +static struct qcom_icc_node slv_lpass = { + .name = "slv_lpass", + .id = QCS404_SLAVE_LPASS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = -1, +}; static struct qcom_icc_node *qcs404_bimc_nodes[] = { [MASTER_AMPSS_M0] = &mas_apps_proc, From patchwork Fri Sep 3 23:24:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 506566 Delivered-To: patch@linaro.org Received: by 2002:a17:906:f46:0:0:0:0 with SMTP id h6csp1976513ejj; Fri, 3 Sep 2021 16:24:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkhjbas0JhWQpat9NHDi7J2naanh6bbJtKKj4O2uPIMrBbMXEAIM/SrFvPL6TCKE0+n8ME X-Received: by 2002:a17:906:781:: with SMTP id l1mr1366808ejc.289.1630711480081; Fri, 03 Sep 2021 16:24:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630711480; cv=none; d=google.com; s=arc-20160816; b=SkMDZKBtdo7AEeNlSTr3R28j+9pUB2NAbFhr0juZ+ZusaA+xcZt942ius4LLvakj0L GguGEwyPPS0FfUAqeH5RYlNupwG1I/CEeVv2xe25s//g938s8eETRVNEZoZRYhVqfZop CidzUgSwTWkQwz+sHld8k2pWRVnHmwMtSWgzeB//KIWvyZkNrV+nN1xwlDAv3krE68LP XHwuo5OueLARF6ztIn/IDbkGS2U83wst0Vj19YvvcPIrWXbEOQWzmb807mPkzM+rlo7d 20EIwP/EBPa2mebhKnKjVvLzLiBWoa6uLepoZ8t0AzjrHC506nHuAxZ+YKcdrsbU+WA0 4O2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kd2nb9s2Osi8MHIbxM1lxmxPOFNi6CuNMu2QVLL3eSM=; b=p+c0SYosd/9/YKhHoIGEBkBnEnA4Xb2l+YtY4q2lkRutoaRscIRdezYnIBeSf0eeJ/ VAj4Vw+e72GqqAETJkFe4OjgzLrzEpHRzSHcmXg2lYtgPNCbWXrZ1k9SCdCWVCX90dvt h+j8992BSE5tzhY+cikp8HUAyJp3fLf80uSAL0USG+WK53c5ZkogihxxzviJ3NQkrxmS /RkpecY1XR5ztFanuKvLB3JjnN3Owo/zq7kflDuw3sIOKfWQY7MPyd8ymhsGqktuoHc2 NCeHer0Hw7qn44cgw1iUW/A5e2/BKm4mua2awpwmVN3O2D3zJ1mf/wsmy70U/EvtGn7F 5nSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A0iD2EDz; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp5si572394ejc.132.2021.09.03.16.24.39; Fri, 03 Sep 2021 16:24:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A0iD2EDz; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350767AbhICXZg (ORCPT + 16 others); Fri, 3 Sep 2021 19:25:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350773AbhICXZf (ORCPT ); Fri, 3 Sep 2021 19:25:35 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BC63C061760 for ; Fri, 3 Sep 2021 16:24:34 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id t19so1289500lfe.13 for ; Fri, 03 Sep 2021 16:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kd2nb9s2Osi8MHIbxM1lxmxPOFNi6CuNMu2QVLL3eSM=; b=A0iD2EDzSQdJZv8n6FQutX3dJCkT59Q64Yxf6q6obbCwFZdilR4HHsjrto8qUvxGkI oIpYFABP8TeWMJS2neJ5wyk1vCPnAdY134lE/LbiT4QYe90ct1NEGG5Sp6IHoxoE3ldI LNRC+Pvw63SaD5SgLTA+5aaTisjPXgS9V95iq6ZdbVHouzZM59bNOnG7sFRgqzFywNtq IEqLqntxXcwEuIeaQ6C0ZC2/PUPjiQLNX3t7hadsdxar1wnpixmIZbbiQtSk3twQ3I0F IptoKWrIr1kKNX33WomwS5l+mcqOQuSecFoy8jN6avi6bNMRHAaaUuwgZkV+MMmrRzRr nUTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kd2nb9s2Osi8MHIbxM1lxmxPOFNi6CuNMu2QVLL3eSM=; b=suritMshfmoSAd/2cI782+lLtABC5J3jhinb8hxulu17bWxQLs0F6i5vD3u4tBed5a QWH+UiJ9X4T6xbuWn9sWZgmUZ5VvcfPVRTssgUcnPsO4+NpKL2c77A9EUOn6WbF15qVr ulfZfmgjx/Xh7cLESnPorOOKNRpCQDosafGykf5r9lfqNceiMu/UFuaXuIqkG3kiZVDX qpqluRHVvyVj3u111pZdurZMDHSq/emSF+QX7No29K2yVE9iaMqlVPl8JV4LzyQ1uB+V k+eI5/PpfhLjpjceNjgBDlWGIabfcYkpJBYsTEhkRYuCAH8bCxXGcjbNsPivsUhgpC06 AZTw== X-Gm-Message-State: AOAM533obgjHfsimVwmZKk7ZLUuezHcU+9qHGU6ADiyejeKWBTLi2TAR taj5E3CjL9PF+iM9HM1zsTIvxg== X-Received: by 2002:a19:c1cc:: with SMTP id r195mr953895lff.504.1630711472895; Fri, 03 Sep 2021 16:24:32 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w3sm56924ljm.13.2021.09.03.16.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 16:24:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: AngeloGioacchino Del Regno , Shawn Guo , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 11/11] interconnect: qcom: drop DEFINE_QNODE macro Date: Sat, 4 Sep 2021 02:24:21 +0300 Message-Id: <20210903232421.1384199-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> References: <20210903232421.1384199-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop DEFINE_QNODE macro which has become unused. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.h | 14 -------------- 1 file changed, 14 deletions(-) -- 2.33.0 Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index f6746dabdf28..0b53fae089ac 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -82,20 +82,6 @@ struct qcom_icc_desc { unsigned int qos_offset; }; -#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ - ...) \ - static const u16 _name ## _links[] = { __VA_ARGS__ }; \ - \ - static struct qcom_icc_node _name = { \ - .name = #_name, \ - .id = _id, \ - .buswidth = _buswidth, \ - .mas_rpm_id = _mas_rpm_id, \ - .slv_rpm_id = _slv_rpm_id, \ - .num_links = ARRAY_SIZE(_name ## _links), \ - .links = _name ## _links, \ - } - /* Valid for both NoC and BIMC */ #define NOC_QOS_MODE_INVALID -1 #define NOC_QOS_MODE_FIXED 0x0