From patchwork Fri Sep 3 06:16:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fengquan Chen X-Patchwork-Id: 506694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EF43C433F5 for ; Fri, 3 Sep 2021 06:17:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F71A601FA for ; Fri, 3 Sep 2021 06:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347341AbhICGSN (ORCPT ); Fri, 3 Sep 2021 02:18:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:53324 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1347331AbhICGSJ (ORCPT ); Fri, 3 Sep 2021 02:18:09 -0400 X-UUID: a55b464e52ea4dab8d1043f97825893c-20210903 X-UUID: a55b464e52ea4dab8d1043f97825893c-20210903 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 804399799; Fri, 03 Sep 2021 14:17:05 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 3 Sep 2021 14:17:04 +0800 Received: from localhost.localdomain (10.17.3.154) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 3 Sep 2021 14:17:03 +0800 From: Fengquan Chen To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Matthias Brugger , , , , , CC: , , , , , , Subject: [v2, 2/2] dt-bindings: watchdog: mtk-wdt: add disable_wdt_extrst support Date: Fri, 3 Sep 2021 14:16:23 +0800 Message-ID: <20210903061623.10715-3-Fengquan.Chen@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903061623.10715-1-Fengquan.Chen@mediatek.com> References: <20210903061623.10715-1-Fengquan.Chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch add a description and example of disable_wdt_extrst element for watchdog on MTK Socs Signed-off-by: fengquan.chen --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index e36ba60de829..c202d6fa5801 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -17,6 +17,7 @@ Required properties: - reg : Specifies base physical address and size of the registers. Optional properties: +- mediatek,disable-extrst: disable send output reset signal - timeout-sec: contains the watchdog timeout in seconds. - #reset-cells: Should be 1. @@ -25,6 +26,7 @@ Example: watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; + mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; timeout-sec = <10>; #reset-cells = <1>;