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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 1/7] decodetree: Add !extern flag to argument sets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow argument sets to be shared between two decoders by avoiding a re-declaration error. Make sure that anonymous argument sets have unique names. Signed-off-by: Richard Henderson --- scripts/decodetree.py | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) -- 2.17.2 Reviewed-by: Bastian Koppelmann Reviewed-by: Philippe Mathieu-Daudé diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 277f9a9bba..a9b10452ef 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -63,13 +63,16 @@ # # *** Argument set syntax: # -# args_def := '&' identifier ( args_elt )+ +# args_def := '&' identifier ( args_elt )+ ( !extern )? # args_elt := identifier # # Each args_elt defines an argument within the argument set. # Each argument set will be rendered as a C structure "arg_$name" # with each of the fields being one of the member arguments. # +# If !extern is specified, the backing structure is assumed to +# have been already declared, typically via a second decoder. +# # Argument set examples: # # ®3 ra rb rc @@ -169,6 +172,7 @@ input_file = '' output_file = None output_fd = None insntype = 'uint32_t' +decode_function = 'decode' re_ident = '[a-zA-Z][a-zA-Z0-9_]*' @@ -394,8 +398,9 @@ class FunctionField: class Arguments: """Class representing the extracted fields of a format""" - def __init__(self, nm, flds): + def __init__(self, nm, flds, extern): self.name = nm + self.extern = extern self.fields = sorted(flds) def __str__(self): @@ -405,10 +410,11 @@ class Arguments: return 'arg_' + self.name def output_def(self): - output('typedef struct {\n') - for n in self.fields: - output(' int ', n, ';\n') - output('} ', self.struct_name(), ';\n\n') + if not self.extern: + output('typedef struct {\n') + for n in self.fields: + output(' int ', n, ';\n') + output('} ', self.struct_name(), ';\n\n') # end Arguments @@ -542,7 +548,11 @@ def parse_arguments(lineno, name, toks): global re_ident flds = [] + extern = False for t in toks: + if re_fullmatch('!extern', t): + extern = True + continue if not re_fullmatch(re_ident, t): error(lineno, 'invalid argument set token "{0}"'.format(t)) if t in flds: @@ -551,7 +561,7 @@ def parse_arguments(lineno, name, toks): if name in arguments: error(lineno, 'duplicate argument set', name) - arguments[name] = Arguments(name, flds) + arguments[name] = Arguments(name, flds, extern) # end parse_arguments @@ -575,13 +585,14 @@ def add_field_byname(lineno, flds, new_name, old_name): def infer_argument_set(flds): global arguments + global decode_function for arg in arguments.values(): if eq_fields_for_args(flds, arg.fields): return arg - name = str(len(arguments)) - arg = Arguments(name, flds.keys()) + name = decode_function + str(len(arguments)) + arg = Arguments(name, flds.keys(), False) arguments[name] = arg return arg @@ -589,6 +600,7 @@ def infer_argument_set(flds): def infer_format(arg, fieldmask, flds): global arguments global formats + global decode_function const_flds = {} var_flds = {} @@ -608,7 +620,7 @@ def infer_format(arg, fieldmask, flds): continue return (fmt, const_flds) - name = 'Fmt_' + str(len(formats)) + name = decode_function + '_Fmt_' + str(len(formats)) if not arg: arg = infer_argument_set(flds) @@ -973,8 +985,8 @@ def main(): global insnwidth global insntype global insnmask + global decode_function - decode_function = 'decode' decode_scope = 'static ' long_opts = ['decode=', 'translate=', 'output=', 'insnwidth='] From patchwork Tue Oct 23 12:04:49 2018 Content-Type: text/plain; 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X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PATCH 2/7] decodetree: Remove "insn" argument from trans_* expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? Needs simultaneous corresponding changes to all translators using decodetree. --- scripts/decodetree.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/scripts/decodetree.py b/scripts/decodetree.py index a9b10452ef..c0bb447095 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -468,8 +468,7 @@ class Pattern(General): output('typedef ', self.base.base.struct_name(), ' arg_', self.name, ';\n') output(translate_scope, 'bool ', translate_prefix, '_', self.name, - '(DisasContext *ctx, arg_', self.name, - ' *a, ', insntype, ' insn);\n') + '(DisasContext *ctx, arg_', self.name, ' *a);\n') def output_code(self, i, extracted, outerbits, outermask): global translate_prefix @@ -481,7 +480,7 @@ class Pattern(General): for n, f in self.fields.items(): output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') output(ind, 'return ', translate_prefix, '_', self.name, - '(ctx, &u.f_', arg, ', insn);\n') + '(ctx, &u.f_', arg, ');\n') # end Pattern From patchwork Tue Oct 23 12:04:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149444 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp610732ljp; Tue, 23 Oct 2018 05:08:42 -0700 (PDT) X-Google-Smtp-Source: AJdET5f1vSAHkRuKdlqsax8yFdZ8Bh7zj5rxLHOJDENLLVn5LOrB+xAAtC8JcuGAmqG7V0UZl8ak X-Received: by 2002:ae9:f00f:: with SMTP id l15-v6mr393930qkg.64.1540296522424; Tue, 23 Oct 2018 05:08:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540296522; cv=none; d=google.com; s=arc-20160816; b=Kri9TbIqIhQc6uls2HS5nzfIWtetd79u5Qa33dfJkCiFhkTk3fglX5isR/BsJp4ucz SW0Bb9ktfVsUdmn2SxchTPfyCMVfwzK5/+L+2uVY2rqxS+ZKKbRce5REUuxG4HSSyMJ+ T6LSfpHAgJq4KY50AcRB1/bC0pq2Zm+rMadp0aS5qa3Iu8aDb7NZaBeRPxSpiWdMw4cX PAgu789iZqt5NdpD7MF4zA4lFxKcgLxRixjI7nWyBi9MdqhUhxRkYoXwmX5ObNlvSjLZ 0W7c7Lf7oUqEZd2ggmYMXtKvWO+woDMvfWrZxSSqYQZIck8GOqRPOirXKIBohqHqfc+D naMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HUdSHOaXUmp3dWcgavyhflg8xyNI59WdQfPkNUAOTGA=; b=XfWJRhUtZNsEtUJ3As9tf6uySL98VxRExxbx1wYJFLjHlQIHR7FzZrHaEbKmpzNkC6 ckrGzMlXEszJPbg4anv2W5GUpEAz922GaSdkZF0955ePp10JH2RA7fq/zzcyAhzwgzZI RC+YruKj1OaQtmgOVRPmUZNCh2QMXuldZrlGiMJq7p8lJaW0Bwt2XybqsYUzflOw/+hC iaPZbT4UvjuUDyO2saTp/AmzoLhHlnr1R5f9z+ABch4Bsyxlfcz8coTepIJDqZFtlUyx cPlZtUMnmRHUPNrPu6MYTFTekJuqoNUux8NyIv0Igo+/Qe44og6pG7vvqfbUivbKbPNv gJpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HRaR+oeE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [PATCH 3/7] target/riscv: Update for decodetree insn argument change X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? Should be merged back into previous patches. ??? Additional changes required for compact mode. --- .../riscv/insn_trans/trans_privileged.inc.c | 19 ++- target/riscv/insn_trans/trans_rva.inc.c | 44 +++--- target/riscv/insn_trans/trans_rvc.inc.c | 148 +++++++++--------- target/riscv/insn_trans/trans_rvd.inc.c | 64 ++++---- target/riscv/insn_trans/trans_rvf.inc.c | 60 +++---- target/riscv/insn_trans/trans_rvi.inc.c | 114 +++++++------- target/riscv/insn_trans/trans_rvm.inc.c | 26 +-- 7 files changed, 234 insertions(+), 241 deletions(-) -- 2.17.2 Reviewed-by: Bastian Koppelmann diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c index 9534adb025..999e7f0f9e 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -18,7 +18,7 @@ * this program. If not, see . */ -static bool trans_ecall(DisasContext *ctx, arg_ecall *a, uint32_t insn) +static bool trans_ecall(DisasContext *ctx, arg_ecall *a) { /* always generates U-level ECALL, fixed in do_interrupt handler */ generate_exception(ctx, RISCV_EXCP_U_ECALL); @@ -27,7 +27,7 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a, uint32_t insn) return true; } -static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a, uint32_t insn) +static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) { generate_exception(ctx, RISCV_EXCP_BREAKPOINT); tcg_gen_exit_tb(NULL, 0); /* no chaining */ @@ -35,13 +35,13 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a, uint32_t insn) return true; } -static bool trans_uret(DisasContext *ctx, arg_uret *a, uint32_t insn) +static bool trans_uret(DisasContext *ctx, arg_uret *a) { gen_exception_illegal(ctx); return true; } -static bool trans_sret(DisasContext *ctx, arg_sret *a, uint32_t insn) +static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); @@ -59,13 +59,13 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a, uint32_t insn) #endif } -static bool trans_hret(DisasContext *ctx, arg_hret *a, uint32_t insn) +static bool trans_hret(DisasContext *ctx, arg_hret *a) { gen_exception_illegal(ctx); return true; } -static bool trans_mret(DisasContext *ctx, arg_mret *a, uint32_t insn) +static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); @@ -78,7 +78,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a, uint32_t insn) #endif } -static bool trans_wfi(DisasContext *ctx, arg_wfi *a, uint32_t insn) +static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); @@ -89,8 +89,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a, uint32_t insn) #endif } -static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a, - uint32_t insn) +static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY gen_helper_tlb_flush(cpu_env); @@ -100,7 +99,7 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a, #endif } -static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a, uint32_t insn) +static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) { #ifndef CONFIG_USER_ONLY gen_helper_tlb_flush(cpu_env); diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c index 7e368dc321..e658bf32c4 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -89,62 +89,62 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, return true; } -static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a, uint32_t insn) +static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) { return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); } -static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a, uint32_t insn) +static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) { return gen_sc(ctx, a, (MO_ALIGN | MO_TESL)); } -static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a, uint32_t insn) +static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a, uint32_t insn) +static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a, uint32_t insn) +static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a, uint32_t insn) +static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a, uint32_t insn) +static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a, uint32_t insn) +static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a, uint32_t insn) +static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a, uint32_t insn) +static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a, uint32_t insn) +static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL)); } -static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a, uint32_t insn) +static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { #ifdef TARGET_RISCV64 return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); @@ -153,7 +153,7 @@ static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a, uint32_t insn) #endif } -static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a, uint32_t insn) +static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { #ifdef TARGET_RISCV64 return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); @@ -162,7 +162,7 @@ static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a, uint32_t insn) #endif } -static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a, uint32_t insn) +static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); @@ -171,7 +171,7 @@ static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a, uint32_t insn) #endif } -static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a, uint32_t insn) +static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ)); @@ -180,7 +180,7 @@ static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a, uint32_t insn) #endif } -static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a, uint32_t insn) +static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ)); @@ -189,7 +189,7 @@ static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a, uint32_t insn) #endif } -static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a, uint32_t insn) +static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ)); @@ -198,7 +198,7 @@ static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a, uint32_t insn) #endif } -static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a, uint32_t insn) +static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ)); @@ -207,7 +207,7 @@ static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a, uint32_t insn) #endif } -static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a, uint32_t insn) +static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ)); @@ -216,7 +216,7 @@ static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a, uint32_t insn) #endif } -static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a, uint32_t insn) +static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ)); @@ -225,7 +225,7 @@ static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a, uint32_t insn) #endif } -static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a, uint32_t insn) +static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ)); @@ -234,7 +234,7 @@ static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a, uint32_t insn) #endif } -static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a, uint32_t insn) +static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { #ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ)); diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index 593dfb82a3..7e2668c03d 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -18,30 +18,29 @@ * this program. If not, see . */ -static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a, - uint16_t insn) +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) { if (a->nzuimm == 0) { /* Reserved in ISA */ return false; } arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm }; - return trans_addi(ctx, &arg, insn); + return trans_addi(ctx, &arg); } -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a, uint16_t insn) +static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) { arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; - return trans_fld(ctx, &arg, insn); + return trans_fld(ctx, &arg); } -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a, uint16_t insn) +static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) { arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; - return trans_lw(ctx, &arg, insn); + return trans_lw(ctx, &arg); } -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a, uint16_t insn) +static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 /* C.FLW ( RV32FC-only ) */ @@ -52,25 +51,25 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a, uint16_t insn) #else /* C.LD ( RV64C/RV128C-only ) */ arg_c_fld tmp; - extract_cl_d(&tmp, insn); + extract_cl_d(&tmp, 0); // FIXME arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm }; - return trans_ld(ctx, &arg, insn); + return trans_ld(ctx, &arg); #endif } -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a, uint16_t insn) +static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) { arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; - return trans_fsd(ctx, &arg, insn); + return trans_fsd(ctx, &arg); } -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a, uint16_t insn) +static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) { arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; - return trans_sw(ctx, &arg, insn); + return trans_sw(ctx, &arg); } -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a, uint16_t insn) +static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) { #ifdef TARGET_RISCV32 /* C.FSW ( RV32FC-only ) */ @@ -81,24 +80,23 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a, uint16_t insn) #else /* C.SD ( RV64C/RV128C-only ) */ arg_c_fsd tmp; - extract_cs_d(&tmp, insn); + extract_cs_d(&tmp, 0); // FIXME arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm }; - return trans_sd(ctx, &arg, insn); + return trans_sd(ctx, &arg); #endif } -static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a, uint16_t insn) +static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) { if (a->imm == 0) { /* Hint: insn is valid but does not affect state */ return true; } arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_addi(ctx, &arg, insn); + return trans_addi(ctx, &arg); } -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a, - uint16_t insn) +static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) { #ifdef TARGET_RISCV32 /* C.JAL */ @@ -107,27 +105,26 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a, #else /* C.ADDIW */ arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_addiw(ctx, &arg, insn); + return trans_addiw(ctx, &arg); #endif } -static bool trans_c_li(DisasContext *ctx, arg_c_li *a, uint16_t insn) +static bool trans_c_li(DisasContext *ctx, arg_c_li *a) { if (a->rd == 0) { /* Hint: insn is valid but does not affect state */ return true; } arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm }; - return trans_addi(ctx, &arg, insn); + return trans_addi(ctx, &arg); } -static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a, - uint16_t insn) +static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) { if (a->rd == 2) { /* C.ADDI16SP */ arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp }; - return trans_addi(ctx, &arg, insn); + return trans_addi(ctx, &arg); } else if (a->imm_lui != 0) { /* C.LUI */ if (a->rd == 0) { @@ -135,12 +132,12 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a, return true; } arg_lui arg = { .rd = a->rd, .imm = a->imm_lui }; - return trans_lui(ctx, &arg, insn); + return trans_lui(ctx, &arg); } return false; } -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a, uint16_t insn) +static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a) { int shamt = a->shamt; if (shamt == 0) { @@ -153,10 +150,10 @@ static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a, uint16_t insn) } arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt }; - return trans_srli(ctx, &arg, insn); + return trans_srli(ctx, &arg); } -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a, uint16_t insn) +static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a) { if (a->shamt == 0) { /* Reserved in ISA */ @@ -170,70 +167,70 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a, uint16_t insn) #endif arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt }; - return trans_srai(ctx, &arg, insn); + return trans_srai(ctx, &arg); } -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a, uint16_t insn) +static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a) { arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_andi(ctx, &arg, insn); + return trans_andi(ctx, &arg); } -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a, uint16_t insn) +static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a) { arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_sub(ctx, &arg, insn); + return trans_sub(ctx, &arg); } -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a, uint16_t insn) +static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a) { arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_xor(ctx, &arg, insn); + return trans_xor(ctx, &arg); } -static bool trans_c_or(DisasContext *ctx, arg_c_or *a, uint16_t insn) +static bool trans_c_or(DisasContext *ctx, arg_c_or *a) { arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_or(ctx, &arg, insn); + return trans_or(ctx, &arg); } -static bool trans_c_and(DisasContext *ctx, arg_c_and *a, uint16_t insn) +static bool trans_c_and(DisasContext *ctx, arg_c_and *a) { arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_and(ctx, &arg, insn); + return trans_and(ctx, &arg); } -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a, uint16_t insn) +static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_subw(ctx, &arg, insn); + return trans_subw(ctx, &arg); } -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a, uint16_t insn) +static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) { arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_addw(ctx, &arg, insn); + return trans_addw(ctx, &arg); } -static bool trans_c_j(DisasContext *ctx, arg_c_j *a, uint16_t insn) +static bool trans_c_j(DisasContext *ctx, arg_c_j *a) { arg_jal arg = { .rd = 0, .imm = a->imm }; - return trans_jal(ctx, &arg, insn); + return trans_jal(ctx, &arg); } -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a, uint16_t insn) +static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a) { arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm }; - return trans_beq(ctx, &arg, insn); + return trans_beq(ctx, &arg); } -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a, uint16_t insn) +static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a) { arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm }; - return trans_bne(ctx, &arg, insn); + return trans_bne(ctx, &arg); } -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a, uint16_t insn) +static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) { int shamt = a->shamt; if (shamt == 0) { @@ -246,85 +243,82 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a, uint16_t insn) } arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt }; - return trans_slli(ctx, &arg, insn); + return trans_slli(ctx, &arg); } -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a, uint16_t insn) +static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a) { arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm }; - return trans_fld(ctx, &arg, insn); + return trans_fld(ctx, &arg); } -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a, uint16_t insn) +static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) { arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm }; - return trans_lw(ctx, &arg, insn); + return trans_lw(ctx, &arg); } -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a, - uint16_t insn) +static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) { #ifdef TARGET_RISCV32 /* C.FLWSP */ arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp }; - return trans_flw(ctx, &arg_flw, insn); + return trans_flw(ctx, &arg_flw); #else /* C.LDSP */ arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp }; - return trans_ld(ctx, &arg_ld, insn); + return trans_ld(ctx, &arg_ld); #endif return false; } -static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a, uint16_t insn) +static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) { if (a->rd != 0 && a->rs2 == 0) { /* C.JR */ arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 }; - return trans_jalr(ctx, &arg, insn); + return trans_jalr(ctx, &arg); } else if (a->rd != 0 && a->rs2 != 0) { /* C.MV */ arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 }; - return trans_add(ctx, &arg, insn); + return trans_add(ctx, &arg); } return false; } -static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a, - uint16_t insn) +static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a) { if (a->rd == 0 && a->rs2 == 0) { /* C.EBREAK */ arg_ebreak arg = { }; - return trans_ebreak(ctx, &arg, insn); + return trans_ebreak(ctx, &arg); } else if (a->rd != 0) { if (a->rs2 == 0) { /* C.JALR */ arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 }; - return trans_jalr(ctx, &arg, insn); + return trans_jalr(ctx, &arg); } else { /* C.ADD */ arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_add(ctx, &arg, insn); + return trans_add(ctx, &arg); } } return false; } -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a, uint16_t insn) +static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a) { arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm }; - return trans_fsd(ctx, &arg, insn); + return trans_fsd(ctx, &arg); } -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a, uint16_t insn) +static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) { arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm }; - return trans_sw(ctx, &arg, insn); + return trans_sw(ctx, &arg); } -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a, - uint16_t insn) +static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 /* C.FSWSP */ @@ -333,5 +327,5 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a, #endif /* C.SDSP */ arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp }; - return trans_sd(ctx, &a_sd, insn); + return trans_sd(ctx, &a_sd); } diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index 665cf54e25..4b2face7c5 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -18,7 +18,7 @@ * this program. If not, see . */ -static bool trans_fld(DisasContext *ctx, arg_fld *a, uint32_t insn) +static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); @@ -31,7 +31,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a, uint32_t insn) return true; } -static bool trans_fsd(DisasContext *ctx, arg_fsd *a, uint32_t insn) +static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); @@ -44,7 +44,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a, uint32_t insn) return true; } -static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a, uint32_t insn) +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -53,7 +53,7 @@ static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a, uint32_t insn) return true; } -static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a, uint32_t insn) +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -62,7 +62,7 @@ static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a, uint32_t insn) return true; } -static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a, uint32_t insn) +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -71,7 +71,7 @@ static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a, uint32_t insn) return true; } -static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a, uint32_t insn) +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -80,7 +80,7 @@ static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a, uint32_t insn) return true; } -static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a, uint32_t insn) +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a) { REQUIRE_FPU; @@ -91,7 +91,7 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a, uint32_t insn) return true; } -static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a, uint32_t insn) +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a) { REQUIRE_FPU; @@ -102,7 +102,7 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a, uint32_t insn) return true; } -static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a, uint32_t insn) +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a) { REQUIRE_FPU; @@ -113,7 +113,7 @@ static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a, uint32_t insn) return true; } -static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a, uint32_t insn) +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a) { REQUIRE_FPU; @@ -124,7 +124,7 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a, uint32_t insn) return true; } -static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a, uint32_t insn) +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a) { REQUIRE_FPU; @@ -134,7 +134,7 @@ static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a, uint32_t insn) return true; } -static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a, uint32_t insn) +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a) { if (a->rs1 == a->rs2) { /* FMOV */ tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); @@ -145,7 +145,7 @@ static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a, uint32_t insn) return true; } -static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a, uint32_t insn) +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a) { REQUIRE_FPU; if (a->rs1 == a->rs2) { /* FNEG */ @@ -159,7 +159,7 @@ static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a, uint32_t insn) return true; } -static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a, uint32_t insn) +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a) { REQUIRE_FPU; if (a->rs1 == a->rs2) { /* FABS */ @@ -173,7 +173,7 @@ static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a, uint32_t insn) return true; } -static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a, uint32_t insn) +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a) { REQUIRE_FPU; @@ -183,7 +183,7 @@ static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a, uint32_t insn) return true; } -static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a, uint32_t insn) +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a) { REQUIRE_FPU; @@ -193,7 +193,7 @@ static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a, uint32_t insn) return true; } -static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a, uint32_t insn) +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) { REQUIRE_FPU; @@ -203,7 +203,7 @@ static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a, uint32_t insn) return true; } -static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a, uint32_t insn) +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) { REQUIRE_FPU; @@ -213,7 +213,7 @@ static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a, uint32_t insn) return true; } -static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a, uint32_t insn) +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) { REQUIRE_FPU; @@ -225,7 +225,7 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a, uint32_t insn) return true; } -static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a, uint32_t insn) +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) { REQUIRE_FPU; @@ -237,7 +237,7 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a, uint32_t insn) return true; } -static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a, uint32_t insn) +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) { REQUIRE_FPU; @@ -249,7 +249,7 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a, uint32_t insn) return true; } -static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn) +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -264,7 +264,7 @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn) return true; } -static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a, uint32_t insn) +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a) { REQUIRE_FPU; @@ -277,7 +277,7 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a, uint32_t insn) return true; } -static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a, uint32_t insn) +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a) { REQUIRE_FPU; @@ -290,7 +290,7 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a, uint32_t insn) return true; } -static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a, uint32_t insn) +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a) { REQUIRE_FPU; @@ -304,7 +304,7 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a, uint32_t insn) return true; } -static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a, uint32_t insn) +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) { REQUIRE_FPU; @@ -318,7 +318,7 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a, uint32_t insn) return true; } -static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a, uint32_t insn) +static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -334,7 +334,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a, uint32_t insn) return true; } -static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a, uint32_t insn) +static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -350,7 +350,7 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a, uint32_t insn) return true; } -static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a, uint32_t insn) +static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -362,7 +362,7 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a, uint32_t insn) return true; } -static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a, uint32_t insn) +static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -379,7 +379,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a, uint32_t insn) return true; } -static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a, uint32_t insn) +static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -396,7 +396,7 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a, uint32_t insn) return true; } -static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a, uint32_t insn) +static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index bd79ef96f8..6f055e77bf 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -23,7 +23,7 @@ return false; \ } while (0) -static bool trans_flw(DisasContext *ctx, arg_flw *a, uint32_t insn) +static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); @@ -38,7 +38,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a, uint32_t insn) return true; } -static bool trans_fsw(DisasContext *ctx, arg_fsw *a, uint32_t insn) +static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); @@ -52,7 +52,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a, uint32_t insn) return true; } -static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a, uint32_t insn) +static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -61,7 +61,7 @@ static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a, uint32_t insn) return true; } -static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a, uint32_t insn) +static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -70,7 +70,7 @@ static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a, uint32_t insn) return true; } -static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a, uint32_t insn) +static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -79,7 +79,7 @@ static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a, uint32_t insn) return true; } -static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a, uint32_t insn) +static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) { REQUIRE_FPU; gen_set_rm(ctx, a->rm); @@ -88,7 +88,7 @@ static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a, uint32_t insn) return true; } -static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a, uint32_t insn) +static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) { REQUIRE_FPU; @@ -98,7 +98,7 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a, uint32_t insn) return true; } -static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a, uint32_t insn) +static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) { REQUIRE_FPU; @@ -108,7 +108,7 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a, uint32_t insn) return true; } -static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a, uint32_t insn) +static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) { REQUIRE_FPU; @@ -118,7 +118,7 @@ static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a, uint32_t insn) return true; } -static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a, uint32_t insn) +static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) { REQUIRE_FPU; @@ -128,7 +128,7 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a, uint32_t insn) return true; } -static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a, uint32_t insn) +static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) { REQUIRE_FPU; @@ -137,7 +137,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a, uint32_t insn) return true; } -static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a, uint32_t insn) +static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) { REQUIRE_FPU; if (a->rs1 == a->rs2) { /* FMOV */ @@ -149,7 +149,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a, uint32_t insn) return true; } -static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a, uint32_t insn) +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) { REQUIRE_FPU; if (a->rs1 == a->rs2) { /* FNEG */ @@ -163,7 +163,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a, uint32_t insn) return true; } -static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a, uint32_t insn) +static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) { REQUIRE_FPU; if (a->rs1 == a->rs2) { /* FABS */ @@ -177,7 +177,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a, uint32_t insn) return true; } -static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a, uint32_t insn) +static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) { REQUIRE_FPU; @@ -186,7 +186,7 @@ static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a, uint32_t insn) return true; } -static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a, uint32_t insn) +static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) { REQUIRE_FPU; @@ -195,7 +195,7 @@ static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a, uint32_t insn) return true; } -static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a, uint32_t insn) +static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a) { REQUIRE_FPU; @@ -208,7 +208,7 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a, uint32_t insn) return true; } -static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a, uint32_t insn) +static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a) { REQUIRE_FPU; @@ -221,7 +221,7 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a, uint32_t insn) return true; } -static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a, uint32_t insn) +static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) { /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ REQUIRE_FPU; @@ -240,7 +240,7 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a, uint32_t insn) return true; } -static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a, uint32_t insn) +static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) { REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -250,7 +250,7 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a, uint32_t insn) return true; } -static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a, uint32_t insn) +static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) { REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -260,7 +260,7 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a, uint32_t insn) return true; } -static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a, uint32_t insn) +static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) { REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -270,7 +270,7 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a, uint32_t insn) return true; } -static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a, uint32_t insn) +static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a) { REQUIRE_FPU; @@ -284,7 +284,7 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a, uint32_t insn) return true; } -static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a, uint32_t insn) +static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a) { REQUIRE_FPU; @@ -299,7 +299,7 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a, uint32_t insn) return true; } -static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a, uint32_t insn) +static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a) { REQUIRE_FPU; @@ -314,7 +314,7 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a, uint32_t insn) return true; } -static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a, uint32_t insn) +static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) { /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */ REQUIRE_FPU; @@ -333,7 +333,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a, uint32_t insn) return true; } -static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn) +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -349,7 +349,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn) #endif } -static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn) +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -365,7 +365,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn) #endif } -static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn) +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; @@ -383,7 +383,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn) #endif } -static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a, uint32_t insn) +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) { #if defined(TARGET_RISCV64) REQUIRE_FPU; diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 0455f0bf91..2ef355019d 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -18,7 +18,7 @@ * this program. If not, see . */ -static bool trans_lui(DisasContext *ctx, arg_lui *a, uint32_t insn) +static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd != 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); @@ -26,7 +26,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a, uint32_t insn) return true; } -static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn) +static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { if (a->rd != 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); @@ -34,13 +34,13 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn) return true; } -static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn) +static bool trans_jal(DisasContext *ctx, arg_jal *a) { gen_jal(ctx->env, ctx, a->rd, a->imm); return true; } -static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn) +static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { /* no chaining with JALR */ TCGLabel *misaligned = NULL; @@ -99,32 +99,32 @@ static bool gen_branch(DisasContext *ctx, arg_branch *a, TCGCond cond) return true; } -static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn) +static bool trans_beq(DisasContext *ctx, arg_beq *a) { return gen_branch(ctx, a, TCG_COND_EQ); } -static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn) +static bool trans_bne(DisasContext *ctx, arg_bne *a) { return gen_branch(ctx, a, TCG_COND_NE); } -static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn) +static bool trans_blt(DisasContext *ctx, arg_blt *a) { return gen_branch(ctx, a, TCG_COND_LT); } -static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn) +static bool trans_bge(DisasContext *ctx, arg_bge *a) { return gen_branch(ctx, a, TCG_COND_GE); } -static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn) +static bool trans_bltu(DisasContext *ctx, arg_bltu *a) { return gen_branch(ctx, a, TCG_COND_LTU); } -static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn) +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) { return gen_branch(ctx, a, TCG_COND_GEU); } @@ -143,32 +143,32 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, int memop) return true; } -static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn) +static bool trans_lb(DisasContext *ctx, arg_lb *a) { return gen_load(ctx, a, MO_SB); } -static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn) +static bool trans_lh(DisasContext *ctx, arg_lh *a) { return gen_load(ctx, a, MO_TESW); } -static bool trans_lw(DisasContext *ctx, arg_lw *a, uint32_t insn) +static bool trans_lw(DisasContext *ctx, arg_lw *a) { return gen_load(ctx, a, MO_TESL); } -static bool trans_lbu(DisasContext *ctx, arg_lbu *a, uint32_t insn) +static bool trans_lbu(DisasContext *ctx, arg_lbu *a) { return gen_load(ctx, a, MO_UB); } -static bool trans_lhu(DisasContext *ctx, arg_lhu *a, uint32_t insn) +static bool trans_lhu(DisasContext *ctx, arg_lhu *a) { return gen_load(ctx, a, MO_TEUW); } -static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn) +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { #ifdef TARGET_RISCV64 return gen_load(ctx, a, MO_TEUL); @@ -177,7 +177,7 @@ static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn) #endif } -static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn) +static bool trans_ld(DisasContext *ctx, arg_ld *a) { #ifdef TARGET_RISCV64 return gen_load(ctx, a, MO_TEQ); @@ -201,22 +201,22 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, int memop) } -static bool trans_sb(DisasContext *ctx, arg_sb *a, uint32_t insn) +static bool trans_sb(DisasContext *ctx, arg_sb *a) { return gen_store(ctx, a, MO_SB); } -static bool trans_sh(DisasContext *ctx, arg_sh *a, uint32_t insn) +static bool trans_sh(DisasContext *ctx, arg_sh *a) { return gen_store(ctx, a, MO_TESW); } -static bool trans_sw(DisasContext *ctx, arg_sw *a, uint32_t insn) +static bool trans_sw(DisasContext *ctx, arg_sw *a) { return gen_store(ctx, a, MO_TESL); } -static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn) +static bool trans_sd(DisasContext *ctx, arg_sd *a) { #ifdef TARGET_RISCV64 return gen_store(ctx, a, MO_TEQ); @@ -225,12 +225,12 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn) #endif } -static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn) +static bool trans_addi(DisasContext *ctx, arg_addi *a) { return gen_arith_imm(ctx, a, &tcg_gen_add_tl); } -static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn) +static bool trans_slti(DisasContext *ctx, arg_slti *a) { TCGv source1; source1 = tcg_temp_new(); @@ -243,7 +243,7 @@ static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn) return true; } -static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn) +static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { TCGv source1; source1 = tcg_temp_new(); @@ -256,22 +256,22 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn) return true; } -static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn) +static bool trans_xori(DisasContext *ctx, arg_xori *a) { return gen_arith_imm(ctx, a, &tcg_gen_xor_tl); } -static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn) +static bool trans_ori(DisasContext *ctx, arg_ori *a) { return gen_arith_imm(ctx, a, &tcg_gen_or_tl); } -static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn) +static bool trans_andi(DisasContext *ctx, arg_andi *a) { return gen_arith_imm(ctx, a, &tcg_gen_and_tl); } -static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn) +static bool trans_slli(DisasContext *ctx, arg_slli *a) { if (a->rd != 0) { TCGv t = tcg_temp_new(); @@ -289,7 +289,7 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn) return true; } -static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn) +static bool trans_srli(DisasContext *ctx, arg_srli *a) { if (a->rd != 0) { TCGv t = tcg_temp_new(); @@ -301,7 +301,7 @@ static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn) return true; } -static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn) +static bool trans_srai(DisasContext *ctx, arg_srai *a) { if (a->rd != 0) { TCGv t = tcg_temp_new(); @@ -313,23 +313,23 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn) return true; } -static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn) +static bool trans_add(DisasContext *ctx, arg_add *a) { return gen_arith(ctx, a, &tcg_gen_add_tl); } -static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn) +static bool trans_sub(DisasContext *ctx, arg_sub *a) { return gen_arith(ctx, a, &tcg_gen_sub_tl); } -static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn) +static bool trans_sll(DisasContext *ctx, arg_sll *a) { return gen_shift(ctx, a, &tcg_gen_shl_tl); } -static bool trans_slt(DisasContext *ctx, arg_slt *a, uint32_t insn) +static bool trans_slt(DisasContext *ctx, arg_slt *a) { TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -345,7 +345,7 @@ static bool trans_slt(DisasContext *ctx, arg_slt *a, uint32_t insn) return true; } -static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn) +static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -361,33 +361,33 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn) return true; } -static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn) +static bool trans_xor(DisasContext *ctx, arg_xor *a) { return gen_arith(ctx, a, &tcg_gen_xor_tl); } -static bool trans_srl(DisasContext *ctx, arg_srl *a, uint32_t insn) +static bool trans_srl(DisasContext *ctx, arg_srl *a) { return gen_shift(ctx, a, &tcg_gen_shr_tl); } -static bool trans_sra(DisasContext *ctx, arg_sra *a, uint32_t insn) +static bool trans_sra(DisasContext *ctx, arg_sra *a) { return gen_shift(ctx, a, &tcg_gen_sar_tl); } -static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn) +static bool trans_or(DisasContext *ctx, arg_or *a) { return gen_arith(ctx, a, &tcg_gen_or_tl); } -static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn) +static bool trans_and(DisasContext *ctx, arg_and *a) { return gen_arith(ctx, a, &tcg_gen_and_tl); } -static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn) +static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { #ifdef TARGET_RISCV64 bool res = gen_arith_imm(ctx, a, &tcg_gen_add_tl); @@ -398,7 +398,7 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn) #endif } -static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn) +static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { #ifdef TARGET_RISCV64 TCGv source1; @@ -416,7 +416,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn) #endif } -static bool trans_srliw(DisasContext *ctx, arg_srliw *a, uint32_t insn) +static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { #ifdef TARGET_RISCV64 TCGv t = tcg_temp_new(); @@ -432,7 +432,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a, uint32_t insn) #endif } -static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a, uint32_t insn) +static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { #ifdef TARGET_RISCV64 TCGv t = tcg_temp_new(); @@ -448,7 +448,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a, uint32_t insn) #endif } -static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn) +static bool trans_addw(DisasContext *ctx, arg_addw *a) { #if !defined(TARGET_RISCV64) return false; @@ -456,7 +456,7 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn) return gen_arith(ctx, a, &tcg_gen_add_tl); } -static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn) +static bool trans_subw(DisasContext *ctx, arg_subw *a) { #if !defined(TARGET_RISCV64) return false; @@ -464,7 +464,7 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn) return gen_arith(ctx, a, &tcg_gen_sub_tl); } -static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn) +static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { #if !defined(TARGET_RISCV64) return false; @@ -484,7 +484,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn) return true; } -static bool trans_srlw(DisasContext *ctx, arg_srlw *a, uint32_t insn) +static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { #if !defined(TARGET_RISCV64) return false; @@ -506,7 +506,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a, uint32_t insn) return true; } -static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn) +static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { #if !defined(TARGET_RISCV64) return false; @@ -529,7 +529,7 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn) return true; } -static bool trans_fence(DisasContext *ctx, arg_fence *a, uint32_t insn) +static bool trans_fence(DisasContext *ctx, arg_fence *a) { #ifndef CONFIG_USER_ONLY /* FENCE is a full memory barrier. */ @@ -537,7 +537,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a, uint32_t insn) #endif return true; } -static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a, uint32_t insn) +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) { #ifndef CONFIG_USER_ONLY /* FENCE_I is a no-op in QEMU, @@ -574,7 +574,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a, uint32_t insn) } while (0) -static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a, uint32_t insn) +static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) { TCGv source1, csr_store, dest, rs1_pass; RISCV_OP_CSR_PRE; @@ -583,7 +583,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a, uint32_t insn) return true; } -static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a, uint32_t insn) +static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a) { TCGv source1, csr_store, dest, rs1_pass; RISCV_OP_CSR_PRE; @@ -592,7 +592,7 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a, uint32_t insn) return true; } -static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a, uint32_t insn) +static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) { TCGv source1, csr_store, dest, rs1_pass; RISCV_OP_CSR_PRE; @@ -601,7 +601,7 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a, uint32_t insn) return true; } -static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a, uint32_t insn) +static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) { TCGv source1, csr_store, dest, rs1_pass; RISCV_OP_CSR_PRE; @@ -610,7 +610,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a, uint32_t insn) return true; } -static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a, uint32_t insn) +static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a) { TCGv source1, csr_store, dest, rs1_pass; RISCV_OP_CSR_PRE; @@ -619,7 +619,7 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a, uint32_t insn) return true; } -static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a, uint32_t insn) +static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a) { TCGv source1, csr_store, dest, rs1_pass; RISCV_OP_CSR_PRE; diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c index 0bc9b4347a..7809bcb187 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -19,12 +19,12 @@ */ -static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn) +static bool trans_mul(DisasContext *ctx, arg_mul *a) { return gen_arith(ctx, a, &tcg_gen_mul_tl); } -static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn) +static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -39,12 +39,12 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn) return true; } -static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn) +static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { return gen_arith(ctx, a, &gen_mulhsu); } -static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn) +static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -59,27 +59,27 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn) return true; } -static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn) +static bool trans_div(DisasContext *ctx, arg_div *a) { return gen_arith(ctx, a, &gen_div); } -static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn) +static bool trans_divu(DisasContext *ctx, arg_divu *a) { return gen_arith(ctx, a, &gen_divu); } -static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn) +static bool trans_rem(DisasContext *ctx, arg_rem *a) { return gen_arith(ctx, a, &gen_rem); } -static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn) +static bool trans_remu(DisasContext *ctx, arg_remu *a) { return gen_arith(ctx, a, &gen_remu); } -static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn) +static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { #ifdef TARGET_RISCV64 return gen_arith(ctx, a, &tcg_gen_mul_tl); @@ -88,7 +88,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn) #endif } -static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn) +static bool trans_divw(DisasContext *ctx, arg_divw *a) { #ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_div); @@ -97,7 +97,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn) #endif } -static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn) +static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { #ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_divu); @@ -106,7 +106,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn) #endif } -static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn) +static bool trans_remw(DisasContext *ctx, arg_remw *a) { #ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_rem); @@ -115,7 +115,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn) #endif } -static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn) +static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { #ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_remu); From patchwork Tue Oct 23 12:04:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149442 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp609905ljp; Tue, 23 Oct 2018 05:08:03 -0700 (PDT) X-Google-Smtp-Source: AJdET5e3u5eYBMfx27yakqHP2pN4/O3aswBu5xVmmq6lxqx+Q1sRaDdIahPVEjL8K1FADWbtmjZn X-Received: by 2002:a37:a016:: with SMTP id j22-v6mr11610772qke.74.1540296483705; Tue, 23 Oct 2018 05:08:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540296483; cv=none; d=google.com; s=arc-20160816; b=nxGnCmf7dHr9Zie/e+RRWs9zENfxbnD7UrHHWS7UZwSR7b18hyZz12NX7GOgPGEYmF 2stl3fuBpDMs2waCWLxfvWMl87Bdd6VFGXUrHlM2xW6jR9cSzsyD/SArfOWntEK28Ivu pe+xj888/DT5UIyGlw0ZV35VZ9ycsmnyF7Gm0ynHBehLPG2nXgVf5p4ZcQlwFJl5nx/t FAn8itKOySZRD2luFsZ+75KCQhLTgR8QbT3N1HJIkHqJGC99roaK85MCXVzjiYJH7h49 qrjgsKTn3yCBO6LtbtRQUOJqMz0Df4XQ8Urik1AUBksvIBM5kqT9scmDuBtuLI+ploVz 5ZDg== ARC-Message-Signature: i=1; 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X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PATCH 4/7] target/riscv: Rename some argument sets in insn32.decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For format x, use &x for the argument set and @x for the extract. This is less confusing than e.g. "arith" for format R. --- target/riscv/insn_trans/trans_rvi.inc.c | 2 +- target/riscv/translate.c | 10 +++++----- target/riscv/insn32.decode | 12 ++++++------ 3 files changed, 12 insertions(+), 12 deletions(-) -- 2.17.2 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bastian Koppelmann diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 2ef355019d..7e676fe2e4 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -72,7 +72,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) return true; } -static bool gen_branch(DisasContext *ctx, arg_branch *a, TCGCond cond) +static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l = gen_new_label(); TCGv source1, source2; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ece163e69f..e7fe8720ac 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -326,7 +326,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" -static bool gen_arith_imm(DisasContext *ctx, arg_arith_imm *a, +static bool gen_arith_imm(DisasContext *ctx, arg_i *a, void(*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; @@ -344,7 +344,7 @@ static bool gen_arith_imm(DisasContext *ctx, arg_arith_imm *a, return true; } -static bool gen_arith(DisasContext *ctx, arg_arith *a, +static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; @@ -363,7 +363,7 @@ static bool gen_arith(DisasContext *ctx, arg_arith *a, } #ifdef TARGET_RISCV64 -static bool gen_arith_w(DisasContext *ctx, arg_arith *a, +static bool gen_arith_w(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; @@ -384,8 +384,8 @@ static bool gen_arith_w(DisasContext *ctx, arg_arith *a, } #endif -static bool gen_shift(DisasContext *ctx, arg_arith *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_shift(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) { TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1541c254df..77e093a060 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -38,17 +38,17 @@ %imm_u 12:s20 !function=ex_shift_12 # Argument sets: -&branch imm rs2 rs1 -&arith_imm imm rs1 rd -&arith rd rs1 rs2 +&b imm rs2 rs1 +&i imm rs1 rd +&r rd rs1 rs2 &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd # Formats 32: -@r ....... ..... ..... ... ..... ....... &arith %rs2 %rs1 %rd -@i ............ ..... ... ..... ....... &arith_imm imm=%imm_i %rs1 %rd -@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1 +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd +@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd +@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 @s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd @j .................... ..... ....... imm=%imm_j %rd From patchwork Tue Oct 23 12:04:52 2018 Content-Type: text/plain; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 5/7] target/riscv: Convert @cs_2 insns to share translation functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These all expand simply to R format instructions. --- target/riscv/insn_trans/trans_rvc.inc.c | 36 ------------------------- target/riscv/translate.c | 20 +++++++++++--- target/riscv/insn16.decode | 17 +++++++----- 3 files changed, 26 insertions(+), 47 deletions(-) -- 2.17.2 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bastian Koppelmann diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index 7e2668c03d..152c1c9bca 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -176,42 +176,6 @@ static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a) return trans_andi(ctx, &arg); } -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a) -{ - arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_sub(ctx, &arg); -} - -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a) -{ - arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_xor(ctx, &arg); -} - -static bool trans_c_or(DisasContext *ctx, arg_c_or *a) -{ - arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_or(ctx, &arg); -} - -static bool trans_c_and(DisasContext *ctx, arg_c_and *a) -{ - arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_and(ctx, &arg); -} - -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) -{ - arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_subw(ctx, &arg); -} - -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) -{ - arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_addw(ctx, &arg); -} - static bool trans_c_j(DisasContext *ctx, arg_c_j *a) { arg_jal arg = { .rd = 0, .imm = a->imm }; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e7fe8720ac..f4d2a56f9a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -322,10 +322,25 @@ static int ex_rvc_register(int reg) return 8 + reg; } +/* + * Include the auto-generated decoders. + * Note that the 16-bit decoder reuses some of the trans_* functions + * from the 32-bit decoder, which results in duplicate declarations + * of the relevant helpers. Suppress the warning. + */ bool decode_insn32(DisasContext *ctx, uint32_t insn); -/* Include the auto-generated decoder for 32 bit insn */ +bool decode_insn16(DisasContext *ctx, uint16_t insn); + #include "decode_insn32.inc.c" +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wredundant-decls" + +#include "decode_insn16.inc.c" + +#pragma GCC diagnostic pop + + static bool gen_arith_imm(DisasContext *ctx, arg_i *a, void(*func)(TCGv, TCGv, TCGv)) { @@ -410,9 +425,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" -bool decode_insn16(DisasContext *ctx, uint16_t insn); -/* auto-generated decoder*/ -#include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" static void decode_opc(DisasContext *ctx) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 138290c450..16525486ae 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -39,6 +39,9 @@ %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 %imm_lui 12:s1 2:5 !function=ex_shift_12 +# Argument sets imported from insn32.decode: +&r rd rs1 rs2 !extern + # Argument sets: &cl rs1 rd &cl_dw uimm rs1 rd @@ -65,7 +68,7 @@ @cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 @cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 @cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 -@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3 +@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3 @cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 @cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 @cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3 @@ -104,12 +107,12 @@ c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI c_srli 100 . 00 ... ..... 01 @c_shift c_srai 100 . 01 ... ..... 01 @c_shift c_andi 100 . 10 ... ..... 01 @c_andi -c_sub 100 0 11 ... 00 ... 01 @cs_2 -c_xor 100 0 11 ... 01 ... 01 @cs_2 -c_or 100 0 11 ... 10 ... 01 @cs_2 -c_and 100 0 11 ... 11 ... 01 @cs_2 -c_subw 100 1 11 ... 00 ... 01 @cs_2 -c_addw 100 1 11 ... 01 ... 01 @cs_2 +sub 100 0 11 ... 00 ... 01 @cs_2 +xor 100 0 11 ... 01 ... 01 @cs_2 +or 100 0 11 ... 10 ... 01 @cs_2 +and 100 0 11 ... 11 ... 01 @cs_2 +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 c_j 101 ........... 01 @cj c_beqz 110 ... ... ..... 01 @cb c_bnez 111 ... ... ..... 01 @cb From patchwork Tue Oct 23 12:04:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149447 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp613502ljp; Tue, 23 Oct 2018 05:10:49 -0700 (PDT) X-Google-Smtp-Source: ACcGV63bnYDBYPAbj6TbpIBfouhkli6Oavjed85hIFaBCLrXsUySV9XbR6NyRm21ZDiznG/ZMjjn X-Received: by 2002:ac8:1307:: with SMTP id e7-v6mr48844773qtj.22.1540296649481; Tue, 23 Oct 2018 05:10:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540296649; cv=none; d=google.com; s=arc-20160816; b=a+YHfoyfH74AXgi2CL61QAbhaCM6cwU7FimApN5ZKaxBHs3ydMMFUFvdCMvW8gbuHt uPcMKSsXDVCStsb9tiB4FdWGmDtx9SsYNh1wsuYqrGW9hoRuPmracQOZscJ0E0bZPZCx mFl6rblGOtEdWGeomjxqEI764hLicqSMgKF3UR4EIPuvL8KKAuYpG4UAIBtpShCgSiQr 4siiJGuY5q9AqlRxpJEXdNOypzOObSRKvtoqlMzogh73H/E6t1b7JNzmWT3yDubLBTJE ga4fzPBktw5FJt3knfKiKo+yt0ToXeuImTIdoqADvibeDgFgHIYsy93aKcsjJnjA3QnW jU+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RTaiyY8LfZoty6sS2ZcskVQFgv0plfpgxuAOOpuK5Ik=; b=phMohP+VCRtv7WvV1NCrXVAuC588j67g542glg+S4CK+BI+z638Mfl7WqhoBq342/Y mPwGWndF4yKKjv2gFA5PkQFRuQJZSLZrs0ngPJu/3fXu82S9Troqh0JlLZDrX8NDDDHK 0yRFPdj1X6xL2lUXrcYUACVZzHPZwDu5t5VqZD03vWl+NC8jN2ZbvDzbHOrEHDYLtyhZ KQNfnUZhvBN2UHSkcKMrxWD8OlZS4LQJFmFF8jC+cdtlJHLeM2gOa7UDRuTSIHX7Af0j qxUMCs2b05ImNlToiULUZnUGlqEsppC6Jn3BanGERfuyYgVmrTb5S91C45lQ76y7ZTCi 3irg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vbery97x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::331 Subject: [Qemu-devel] [PATCH 6/7] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" --- target/riscv/insn_trans/trans_rvc.inc.c | 34 +++---------------------- target/riscv/insn16.decode | 18 +++++++------ target/riscv/insn32.decode | 3 ++- 3 files changed, 16 insertions(+), 39 deletions(-) -- 2.17.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index 152c1c9bca..c5ffb3bf7c 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) return trans_addi(ctx, &arg); } -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) -{ - arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) -{ - arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 @@ -50,25 +38,12 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) return trans_flw(ctx, &arg, insn); #else /* C.LD ( RV64C/RV128C-only ) */ - arg_c_fld tmp; + arg_i tmp; extract_cl_d(&tmp, 0); // FIXME - arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm }; - return trans_ld(ctx, &arg); + return trans_ld(ctx, &tmp); #endif } -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) -{ - arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) -{ - arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; - return trans_sw(ctx, &arg); -} - static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) { #ifdef TARGET_RISCV32 @@ -79,10 +54,9 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) return trans_fsw(ctx, &arg, insn); #else /* C.SD ( RV64C/RV128C-only ) */ - arg_c_fsd tmp; + arg_s tmp; extract_cs_d(&tmp, 0); // FIXME - arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm }; - return trans_sd(ctx, &arg); + return trans_sd(ctx, &tmp); #endif } diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 16525486ae..73b385ad19 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -41,6 +41,8 @@ # Argument sets imported from insn32.decode: &r rd rs1 rs2 !extern +&i imm rs1 rd !extern +&s imm rs1 rs2 !extern # Argument sets: &cl rs1 rd @@ -64,13 +66,13 @@ @cr .... ..... ..... .. &cr rs2=%rs2_5 %rd @ci ... . ..... ..... .. &ci imm=%imm_ci %rd @ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 -@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 -@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 +@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 +@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 @cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 @cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 @cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3 -@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 -@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 +@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 +@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 @cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3 @cj ... ........... .. &c_j imm=%imm_cj @@ -92,11 +94,11 @@ # *** RV64C Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw -c_fld 001 ... ... .. ... 00 @cl_d -c_lw 010 ... ... .. ... 00 @cl_w +fld 001 ... ... .. ... 00 @cl_d +lw 010 ... ... .. ... 00 @cl_w c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually -c_fsd 101 ... ... .. ... 00 @cs_d -c_sw 110 ... ... .. ... 00 @cs_w +fsd 101 ... ... .. ... 00 @cs_d +sw 110 ... ... .. ... 00 @cs_w c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually # *** RV64C Standard Extension (Quadrant 1) *** diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 77e093a060..e1fccc57c6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -40,6 +40,7 @@ # Argument sets: &b imm rs2 rs1 &i imm rs1 rd +&s imm rs2 rs1 &r rd rs1 rs2 &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd @@ -49,7 +50,7 @@ @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 -@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 +@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd @j .................... ..... ....... imm=%imm_j %rd From patchwork Tue Oct 23 12:04:54 2018 Content-Type: text/plain; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id v78-v6si1034158qkg.90.2018.10.23.05.10.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 23 Oct 2018 05:10:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LNYy6OHv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40748 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEvWB-0003UY-QH for patch@linaro.org; Tue, 23 Oct 2018 08:10:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEvRE-000693-A6 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 08:05:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEvR7-0007rW-Vk for qemu-devel@nongnu.org; Tue, 23 Oct 2018 08:05:31 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:37200) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEvR2-0007jJ-7T for qemu-devel@nongnu.org; Tue, 23 Oct 2018 08:05:23 -0400 Received: by mail-wm1-x331.google.com with SMTP id x19-v6so1501090wmc.2 for ; Tue, 23 Oct 2018 05:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dGi0LtNhdYIXhVq/VjMncb6UXtUWHhY9us0Czd5QDls=; b=LNYy6OHvbOucMsQ8pxeSPBMh63hT1gIsoOw3BUQwVF/CvD+H0RpE+9/haotGR0Y48q JgmZP2GSTh7HDMbSjxXZDGTKeAc7R60hQzbrXXfuB2+42LGWsmq6/SJPSaIDN09Xmn2F b1/H0lQsWk8+fgneklKjcUd02StELFvtLSxvc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dGi0LtNhdYIXhVq/VjMncb6UXtUWHhY9us0Czd5QDls=; b=D6qp81BiQNQMDR+vI36OsJazzmVAkg8KvARMGMfTT4/MPCDpa+u1buwEcwso44+UMS UpAEtopmasO3lTx6GSvzRBOuBE0pt1v7URDlOyLmzHKTBIZKPtPAf5Sf5pwrWDpsKCAa CXnMWvPoynvsI6B3AkZxOVQW30GuM2CqtktLH+R8+XpmBgaK2LlKjqiqEpbrYpOsoTaW deXrmmOzHmQqGIr33jkt68mVfAXDXFt9XJhmkMZ7Wx3bkK2DmJj9PAd6nim72O3tY/gM uxkqyzYwppPuViwkBN/X5CFzTe3eHhk4hk9jYoK1//rM4oO7681ntbY37b/H8Y1f/J+3 AZwQ== X-Gm-Message-State: ABuFfoigKYn3AdH9x0Aim/NkdeM/pMDlJeRlO0J42uGw57/b28/cvzhS LNjGehlI7IQ5WxzMhpJiE4If58NABEk= X-Received: by 2002:a1c:1804:: with SMTP id 4-v6mr19359332wmy.29.1540296312817; Tue, 23 Oct 2018 05:05:12 -0700 (PDT) Received: from cloudburst.twiddle.net.net ([185.7.230.213]) by smtp.gmail.com with ESMTPSA id a1-v6sm1009200wrt.79.2018.10.23.05.05.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 05:05:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 13:04:54 +0100 Message-Id: <20181023120454.28553-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023120454.28553-1-richard.henderson@linaro.org> References: <20181023120454.28553-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 Subject: [Qemu-devel] [PATCH 7/7] target/riscv: Splice decodetree inputs for riscv32 vs riscv64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, palmer@sifive.com, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, mjc@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This primarily solves the case for RVC that several insns are completely different, decode and all, between the two. But it also means that we need less ifdefing for RV{I,M,A,F,D}. --- target/riscv/insn_trans/trans_rva.inc.c | 46 +--------------- target/riscv/insn_trans/trans_rvc.inc.c | 71 ------------------------- target/riscv/insn_trans/trans_rvd.inc.c | 26 +-------- target/riscv/insn_trans/trans_rvf.inc.c | 18 +------ target/riscv/insn_trans/trans_rvi.inc.c | 49 +++-------------- target/riscv/insn_trans/trans_rvm.inc.c | 22 +------- target/riscv/Makefile.objs | 23 ++++++-- target/riscv/insn16-32.decode | 31 +++++++++++ target/riscv/insn16-64.decode | 33 ++++++++++++ target/riscv/insn16.decode | 24 +++------ target/riscv/insn32.decode | 53 +----------------- target/riscv/insn64.decode | 71 +++++++++++++++++++++++++ 12 files changed, 176 insertions(+), 291 deletions(-) create mode 100644 target/riscv/insn16-32.decode create mode 100644 target/riscv/insn16-64.decode create mode 100644 target/riscv/insn64.decode -- 2.17.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c index e658bf32c4..e63d8a5127 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -144,101 +144,59 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL)); } +#ifdef TARGET_RISCV64 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { -#ifdef TARGET_RISCV64 return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); -#else - return false; -#endif } static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { -#ifdef TARGET_RISCV64 return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { -#ifdef TARGET_RISCV64 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ)); -#else - return false; -#endif } +#endif /* TARGET_RISCV64 */ diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index c5ffb3bf7c..e77bcdb2c6 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -28,38 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) return trans_addi(ctx, &arg); } -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLW ( RV32FC-only ) */ - arg_c_lw tmp; - extract_cl_w(&tmp, insn); - arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm }; - return trans_flw(ctx, &arg, insn); -#else - /* C.LD ( RV64C/RV128C-only ) */ - arg_i tmp; - extract_cl_d(&tmp, 0); // FIXME - return trans_ld(ctx, &tmp); -#endif -} - -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSW ( RV32FC-only ) */ - arg_c_sw tmp; - extract_cs_w(&tmp, insn); - arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm }; - return trans_fsw(ctx, &arg, insn); -#else - /* C.SD ( RV64C/RV128C-only ) */ - arg_s tmp; - extract_cs_d(&tmp, 0); // FIXME - return trans_sd(ctx, &tmp); -#endif -} - static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) { if (a->imm == 0) { @@ -70,19 +38,6 @@ static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) return trans_addi(ctx, &arg); } -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) -{ -#ifdef TARGET_RISCV32 - /* C.JAL */ - arg_jal arg = { .rd = 1, .imm = a->imm }; - return trans_jal(ctx, &arg, insn); -#else - /* C.ADDIW */ - arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_addiw(ctx, &arg); -#endif -} - static bool trans_c_li(DisasContext *ctx, arg_c_li *a) { if (a->rd == 0) { @@ -196,20 +151,6 @@ static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) return trans_lw(ctx, &arg); } -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLWSP */ - arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp }; - return trans_flw(ctx, &arg_flw); -#else - /* C.LDSP */ - arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp }; - return trans_ld(ctx, &arg_ld); -#endif - return false; -} - static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) { if (a->rd != 0 && a->rs2 == 0) { @@ -255,15 +196,3 @@ static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm }; return trans_sw(ctx, &arg); } - -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSWSP */ - arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp }; - return trans_fsw(ctx, &a_fsw, insn); -#endif - /* C.SDSP */ - arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp }; - return trans_sd(ctx, &a_sd); -} diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index 4b2face7c5..fab6621d08 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -318,9 +318,9 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) return true; } +#ifdef TARGET_RISCV64 static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -328,15 +328,11 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); gen_set_gpr(a->rd, t0); tcg_temp_free(t0); -#else - gen_exception_illegal(ctx); -#endif return true; } static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -344,27 +340,19 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); gen_set_gpr(a->rd, t0); tcg_temp_free(t0); -#else - gen_exception_illegal(ctx); -#endif return true; } static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; gen_set_gpr(a->rd, cpu_fpr[a->rs1]); -#else - gen_exception_illegal(ctx); -#endif return true; } static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -373,15 +361,11 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); tcg_temp_free(t0); -#else - gen_exception_illegal(ctx); -#endif return true; } static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -390,15 +374,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); tcg_temp_free(t0); -#else - gen_exception_illegal(ctx); -#endif return true; } static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -406,8 +386,6 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) tcg_gen_mov_tl(cpu_fpr[a->rd], t0); tcg_temp_free(t0); -#else - gen_exception_illegal(ctx); -#endif return true; } +#endif /* TARGET_RISCV64 */ diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 6f055e77bf..0007cf0980 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -333,9 +333,9 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) return true; } +#ifdef TARGET_RISCV64 static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -344,14 +344,10 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); return true; -#else - return false; -#endif } static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -360,14 +356,10 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); return true; -#else - return false; -#endif } static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -378,14 +370,10 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) tcg_temp_free(t0); return true; -#else - return false; -#endif } static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) { -#if defined(TARGET_RISCV64) REQUIRE_FPU; TCGv t0 = tcg_temp_new(); @@ -396,7 +384,5 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) tcg_temp_free(t0); return true; -#else - return false; -#endif } +#endif /* TARGET_RISCV64 */ diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 7e676fe2e4..16bfd23739 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -168,23 +168,17 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } +#ifdef TARGET_RISCV64 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { -#ifdef TARGET_RISCV64 return gen_load(ctx, a, MO_TEUL); -#else - return false; -#endif } static bool trans_ld(DisasContext *ctx, arg_ld *a) { -#ifdef TARGET_RISCV64 return gen_load(ctx, a, MO_TEQ); -#else - return false; -#endif } +#endif /* TARGET_RISCV64 */ static bool gen_store(DisasContext *ctx, arg_sb *a, int memop) { @@ -216,14 +210,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) return gen_store(ctx, a, MO_TESL); } +#ifdef TARGET_RISCV64 static bool trans_sd(DisasContext *ctx, arg_sd *a) { -#ifdef TARGET_RISCV64 return gen_store(ctx, a, MO_TEQ); -#else - return false; -#endif } +#endif static bool trans_addi(DisasContext *ctx, arg_addi *a) { @@ -387,20 +379,16 @@ static bool trans_and(DisasContext *ctx, arg_and *a) return gen_arith(ctx, a, &tcg_gen_and_tl); } +#ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { -#ifdef TARGET_RISCV64 bool res = gen_arith_imm(ctx, a, &tcg_gen_add_tl); tcg_gen_ext32s_tl(cpu_gpr[a->rd], cpu_gpr[a->rd]); return res; -#else - return false; -#endif } static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { -#ifdef TARGET_RISCV64 TCGv source1; source1 = tcg_temp_new(); gen_get_gpr(source1, a->rs1); @@ -411,14 +399,10 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) tcg_temp_free(source1); return true; -#else - return false; -#endif } static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { -#ifdef TARGET_RISCV64 TCGv t = tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); @@ -427,14 +411,10 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) gen_set_gpr(a->rd, t); tcg_temp_free(t); return true; -#else - return false; -#endif } static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { -#ifdef TARGET_RISCV64 TCGv t = tcg_temp_new(); gen_get_gpr(t, a->rs1); tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); @@ -443,32 +423,20 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) gen_set_gpr(a->rd, t); tcg_temp_free(t); return true; -#else - return false; -#endif } static bool trans_addw(DisasContext *ctx, arg_addw *a) { -#if !defined(TARGET_RISCV64) - return false; -#endif return gen_arith(ctx, a, &tcg_gen_add_tl); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { -#if !defined(TARGET_RISCV64) - return false; -#endif return gen_arith(ctx, a, &tcg_gen_sub_tl); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { -#if !defined(TARGET_RISCV64) - return false; -#endif TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -486,9 +454,6 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a) static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { -#if !defined(TARGET_RISCV64) - return false; -#endif TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -508,9 +473,6 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a) static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { -#if !defined(TARGET_RISCV64) - return false; -#endif TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); @@ -528,6 +490,7 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) tcg_temp_free(source2); return true; } +#endif /* TARGET_RISCV64 */ static bool trans_fence(DisasContext *ctx, arg_fence *a) { diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c index 7809bcb187..ee0ff4deb9 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -79,47 +79,29 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a) return gen_arith(ctx, a, &gen_remu); } +#ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { -#ifdef TARGET_RISCV64 return gen_arith(ctx, a, &tcg_gen_mul_tl); -#else - return false; -#endif } static bool trans_divw(DisasContext *ctx, arg_divw *a) { -#ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_div); -#else - return false; -#endif } static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { -#ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_divu); -#else - return false; -#endif } static bool trans_remw(DisasContext *ctx, arg_remw *a) { -#ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_rem); -#else - return false; -#endif } static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { -#ifdef TARGET_RISCV64 return gen_arith_w(ctx, a, &gen_remu); -#else - return false; -#endif } +#endif /* TARGET_RISCV64 */ diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index ec7326f1c7..45cc2e8c8a 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -2,14 +2,29 @@ obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/riscv/decode_insn32.inc.c: \ - $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) +decode32-y = $(SRC_PATH)/target/riscv/insn32.decode +decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn64.decode + +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode + +target/riscv/insn32.decode: $(decode32-y) + $(call quiet-command, \ + cat $(decode32-y) > target/riscv/insn32.decode, \ + "CAT", $(TARGET_DIR)$@) + +target/riscv/insn16.decode: $(decode16-y) + $(call quiet-command, \ + cat $(decode16-y) > target/riscv/insn16.decode, \ + "CAT", $(TARGET_DIR)$@) + +target/riscv/decode_insn32.inc.c: target/riscv/insn32.decode $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ "GEN", $(TARGET_DIR)$@) -target/riscv/decode_insn16.inc.c: \ - $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) +target/riscv/decode_insn16.inc.c: target/riscv/insn16.decode $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \ "GEN", $(TARGET_DIR)$@) diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode new file mode 100644 index 0000000000..efb7f5bdc8 --- /dev/null +++ b/target/riscv/insn16-32.decode @@ -0,0 +1,31 @@ +# +# RISC-V translation routines for the RVC Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This is concatenated with insn16.decode for risc32 targets. +# All of the fields and formats are there. + +# *** RV32C Standard Extension (Quadrant 0) *** +flw 011 ... ... .. ... 00 @cl_w +fsw 111 ... ... .. ... 00 @cs_w + +# *** RV32C Standard Extension (Quadrant 1) *** +jal 001 ...... ..... 01 &j imm=%imm_cj rd=1 + +# *** RV32C Standard Extension (Quadrant 2) *** +flw 011 . ..... ..... 10 &i imm=%uimm_6bit_lw %rd rs1=2 +fsw 111 ...... ..... 10 &s imm=%uimm_6bit_sw rs2=%rs2_5 rs1=2 diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode new file mode 100644 index 0000000000..163fd5014a --- /dev/null +++ b/target/riscv/insn16-64.decode @@ -0,0 +1,33 @@ +# +# RISC-V translation routines for the RVC Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This is concatenated with insn16.decode for risc64 targets. +# All of the fields and formats are there. + +# *** RV64C Standard Extension (Quadrant 0) *** +ld 011 ... ... .. ... 00 @cl_d +sd 111 ... ... .. ... 00 @cs_d + +# *** RV64C Standard Extension (Quadrant 1) *** +addiw 001 . ..... ..... 01 @ci +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + +# *** RV64C Standard Extension (Quadrant 2) *** +ld 011 . ..... ..... 10 &i imm=%uimm_6bit_ld %rd rs1=2 +sd 111 . ..... ..... 10 &s imm=%uimm_6bit_sw rs2=%rs2_5 rs1=2 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 73b385ad19..345629b649 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -42,6 +42,7 @@ # Argument sets imported from insn32.decode: &r rd rs1 rs2 !extern &i imm rs1 rd !extern +&j imm rd !extern &s imm rs1 rs2 !extern # Argument sets: @@ -64,12 +65,10 @@ # Formats 16: @cr .... ..... ..... .. &cr rs2=%rs2_5 %rd -@ci ... . ..... ..... .. &ci imm=%imm_ci %rd +@ci ... . ..... ..... .. &i imm=%imm_ci %rd rs1=%rd @ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 -@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 -@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 @cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3 @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 @@ -82,28 +81,21 @@ @c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5 @c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp %rd -@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \ - uimm_ldsp=%uimm_6bit_ld %rd -@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=%uimm_6bit_sw \ - uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5 @c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit @c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit -@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3 +@c_andi ... . .. ... ..... .. &i imm=%imm_ci rd=%rs1_3 rs1=%rs1_3 -# *** RV64C Standard Extension (Quadrant 0) *** +# *** RVC Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw fld 001 ... ... .. ... 00 @cl_d lw 010 ... ... .. ... 00 @cl_w -c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w -c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually -# *** RV64C Standard Extension (Quadrant 1) *** +# *** RVC Standard Extension (Quadrant 1) *** c_addi 000 . ..... ..... 01 @ci -c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually c_li 010 . ..... ..... 01 @ci c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI c_srli 100 . 00 ... ..... 01 @c_shift @@ -113,19 +105,15 @@ sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 or 100 0 11 ... 10 ... 01 @cs_2 and 100 0 11 ... 11 ... 01 @cs_2 -subw 100 1 11 ... 00 ... 01 @cs_2 -addw 100 1 11 ... 01 ... 01 @cs_2 c_j 101 ........... 01 @cj c_beqz 110 ... ... ..... 01 @cb c_bnez 111 ... ... ..... 01 @cb -# *** RV64C Standard Extension (Quadrant 2) *** +# *** RVC Standard Extension (Quadrant 2) *** c_slli 000 . ..... ..... 10 @c_shift2 c_fldsp 001 . ..... ..... 10 @c_ld c_lwsp 010 . ..... ..... 10 @c_lw -c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 c_jr_mv 100 0 ..... ..... 10 @cr c_ebreak_jalr_add 100 1 ..... ..... 10 @cr c_fsdsp 101 ...... ..... 10 @c_sd c_swsp 110 . ..... ..... 10 @c_sw -c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e1fccc57c6..7fcc9a3074 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -23,7 +23,6 @@ %rd 7:5 %sh6 20:6 -%sh5 20:5 %csr 20:12 %rm 12:3 @@ -40,6 +39,7 @@ # Argument sets: &b imm rs2 rs1 &i imm rs1 rd +&j imm rd &s imm rs2 rs1 &r rd rs1 rs2 &shift shamt rs1 rd @@ -52,10 +52,9 @@ @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd -@j .................... ..... ....... imm=%imm_j %rd +@j .................... ..... ....... &j imm=%imm_j %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd -@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @csr ............ ..... ... ..... ....... %csr %rs1 %rd @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd @@ -129,20 +128,6 @@ csrrsi ............ ..... 110 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr -# *** RV64I Base Instruction Set (in addition to RV32I) *** -lwu ............ ..... 110 ..... 0000011 @i -ld ............ ..... 011 ..... 0000011 @i -sd ....... ..... ..... 011 ..... 0100011 @s -addiw ............ ..... 000 ..... 0011011 @i -slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 -srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 -sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 -addw 0000000 ..... ..... 000 ..... 0111011 @r -subw 0100000 ..... ..... 000 ..... 0111011 @r -sllw 0000000 ..... ..... 001 ..... 0111011 @r -srlw 0000000 ..... ..... 101 ..... 0111011 @r -sraw 0100000 ..... ..... 101 ..... 0111011 @r - # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r mulh 0000001 ..... ..... 001 ..... 0110011 @r @@ -153,13 +138,6 @@ divu 0000001 ..... ..... 101 ..... 0110011 @r rem 0000001 ..... ..... 110 ..... 0110011 @r remu 0000001 ..... ..... 111 ..... 0110011 @r -# *** RV64M Standard Extension (in addition to RV32M) *** -mulw 0000001 ..... ..... 000 ..... 0111011 @r -divw 0000001 ..... ..... 100 ..... 0111011 @r -divuw 0000001 ..... ..... 101 ..... 0111011 @r -remw 0000001 ..... ..... 110 ..... 0111011 @r -remuw 0000001 ..... ..... 111 ..... 0111011 @r - # *** RV32A Standard Extension *** lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st @@ -173,19 +151,6 @@ amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st -# *** RV64A Standard Extension (in addition to RV32A) *** -lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld -sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st -amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st -amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st -amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st -amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st -amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st -amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st -amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st -amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st -amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st - # *** RV32F Standard Extension *** flw ............ ..... 010 ..... 0000111 @i fsw ....... ..... ..... 010 ..... 0100111 @s @@ -214,12 +179,6 @@ fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 -# *** RV64F Standard Extension (in addition to RV32F) *** -fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm -fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm -fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm - # *** RV32D Standard Extension *** fld ............ ..... 011 ..... 0000111 @i fsd ....... ..... ..... 011 ..... 0100111 @s @@ -247,11 +206,3 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm - -# *** RV64D Standard Extension (in addition to RV32D) *** -fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm -fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 -fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm -fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm -fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 diff --git a/target/riscv/insn64.decode b/target/riscv/insn64.decode new file mode 100644 index 0000000000..92ac363a11 --- /dev/null +++ b/target/riscv/insn64.decode @@ -0,0 +1,71 @@ +# +# RISC-V translation routines for the RV Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# This is concatenated with insn32.decode for risc64 targets. +# Most of the fields and formats are there. + +%sh5 20:5 +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd + +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s +addiw ............ ..... 000 ..... 0011011 @i +slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 +srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 +sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 +addw 0000000 ..... ..... 000 ..... 0111011 @r +subw 0100000 ..... ..... 000 ..... 0111011 @r +sllw 0000000 ..... ..... 001 ..... 0111011 @r +srlw 0000000 ..... ..... 101 ..... 0111011 @r +sraw 0100000 ..... ..... 101 ..... 0111011 @r + +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r + +# *** RV64A Standard Extension (in addition to RV32A) *** +lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld +sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st +amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st +amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st +amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st +amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st +amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st +amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st +amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st +amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st +amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st + +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm + +# *** RV64D Standard Extension (in addition to RV32D) *** +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2