From patchwork Tue Oct 23 19:06:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 149468 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1081131ljp; Tue, 23 Oct 2018 12:07:32 -0700 (PDT) X-Google-Smtp-Source: ACcGV61oAnrQHDqgIWq7V28QAJYBHMjQzhv8qC+pruZmCtUzJClZHFbB3/AiqMSHEhyQ+kCvop4l X-Received: by 2002:a63:9a19:: with SMTP id o25-v6mr48068170pge.440.1540321652595; Tue, 23 Oct 2018 12:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540321652; cv=none; d=google.com; s=arc-20160816; b=bLcXB3ZU/OH35IsYHfykR9dts7Aa7ndNUkOheqMdl3qIrk624ohY/Qa8weqGZwvQh9 CuelJJPHLXuXL4ZzWPwvU5PK1CGP+1mvW9GV20BUilzwj1La8YUydIISC7SKSYN79u+S kQ3UQC3yDEy1oOkK/dJdkW0tSNs/17XciA3E396j1ON4CCMnzbXrTy0Nvb+Tk3z0KkMQ yt9tv4foW42vddyBHhEO2fPZG+LwgsraTTMp2LOwvLYPfXHNLxGxnE/PPH+yUIROXgHf Pw7rwZ0m8+km0xPivQlMtWs3O9G+AhUMEC1fAuJpE8fF4019KL2f9ly9rpS8sz/0+nFk UeSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=m7OpRdxUBC/ox/YnPiQqQeukhD6ryQi0+yXVdK+eRGw=; b=ngxp7Q5z9vD35nUqmlGlmc/oxGRmo6AWLr74fkqH6hY6Tdz8CXB1tQpORjb97XNEAt XRB9m2w7UDdLX0vsCppkXYaLm+BQ3atTHXOXyQsyA13eT1Cy8UVPmMKrv4gS3F8C9rkW TZWz4FtVlVoZS2ZLN/csGomCNs6ji0ixA3TtKUxsxSnaMcfY0MaoOSKENWfkJERkz8b2 WxFLfWax7I8iPZ6FVaSWNoLxVs2uEqO0BLrxDr1A7llAAtWEVfkXe712ArCxYNuZ6fv6 4SquF9Iz9ZTOy4gQpkIgIlw666lQKmr3butM/NAMnPPD7isQRgaGKXMRJNiNJN+TOH9j S3yA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VGctb+Zl; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g23-v6si648430pgb.150.2018.10.23.12.07.32; Tue, 23 Oct 2018 12:07:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VGctb+Zl; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728918AbeJXDcL (ORCPT + 5 others); Tue, 23 Oct 2018 23:32:11 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:45624 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728426AbeJXDcL (ORCPT ); Tue, 23 Oct 2018 23:32:11 -0400 Received: by mail-pl1-f193.google.com with SMTP id o19-v6so1054240pll.12 for ; Tue, 23 Oct 2018 12:07:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m7OpRdxUBC/ox/YnPiQqQeukhD6ryQi0+yXVdK+eRGw=; b=VGctb+ZleozBkR1WBbOyfJB8zCoOXO9QMkWtKnIHRpvdsw1eWxqJvdjeYDUdq36GLH 66K6BT4uMw7TkiLumL3eNCgAKU0/pczN8c/H26supEyX8xZzl0NcozjWJhpRgbFVSVp9 hraC5LCvsOC2olGw5Z7qt6ge+KDY2/ves3n0k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m7OpRdxUBC/ox/YnPiQqQeukhD6ryQi0+yXVdK+eRGw=; b=OihMBeDZazCt42dKJFwo4EHCdbXtgkqtIJW3+4z93W1HVLzmGmNDK+omKvNdPc+bQ7 hkVhwu5/9FNB/CaFhak4OAJfPYCcjdSTnpujZcm3ZCmOJEeEtcnARC/+TljAqPs4Z41E VmdgbC5TgtBU1N4WUJCApHH4isyzXcJayzYFxM0KRCUZtf5I0L5EKraaLba9LU/Gx/Be BL2egtsTllItxyNliefD+MbdB2UnCCcXPx7/QsZTNdgRrn+mB+sqF2ti7a4ZSj4phUCd iNWgFq750QZgvAKINUHUwsrA2f7PhtylRDVD0wj6eiUyYZKWArz37ASTONdvmpWdTpDk wO+A== X-Gm-Message-State: ABuFfohGq4ZgJIkNT4RU2mdG6sFyrhk55Id4+g1fSeae0E2DZD0lp+LL a+KY4hYCcivGR68r20q+OGYk X-Received: by 2002:a17:902:187:: with SMTP id b7-v6mr49880442plb.150.1540321650544; Tue, 23 Oct 2018 12:07:30 -0700 (PDT) Received: from localhost.localdomain ([2405:204:744c:7bc5:17c:5f65:76c4:d542]) by smtp.gmail.com with ESMTPSA id v189-v6sm4897075pfb.54.2018.10.23.12.07.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Oct 2018 12:07:29 -0700 (PDT) From: Manivannan Sadhasivam To: xuwei5@hisilicon.com, linus.walleij@linaro.org, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/5] arm64: dts: hisilicon: hi3670: Add UART nodes Date: Wed, 24 Oct 2018 00:36:53 +0530 Message-Id: <20181023190655.12004-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181023190655.12004-1-manivannan.sadhasivam@linaro.org> References: <20181023190655.12004-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add UART nodes for HiSilicon HI3670 SoC and also relevant pinmux/pinconf entries. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 ++++++++ .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 157 ++++++++++++++++++ 2 files changed, 229 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index b99f5e0fe577..a5bd6d80b226 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -187,6 +187,76 @@ #clock-cells = <1>; }; + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + + uart5: serial@fdf05000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf05000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + status = "disabled"; + }; + uart6: serial@fff32000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfff32000 0x0 0x1000>; @@ -194,6 +264,8 @@ clocks = <&crg_ctrl HI3670_CLK_UART6>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index 64fb9a3bd707..67bb52d43619 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -20,6 +20,47 @@ pinctrl-single,function-mask = <0x7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 82 0>; + + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0x054 MUX_M2 /* UART0_RXD */ + 0x058 MUX_M2 /* UART0_TXD */ + >; + }; + + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0x700 MUX_M2 /* UART2_CTS_N */ + 0x704 MUX_M2 /* UART2_RTS_N */ + 0x708 MUX_M2 /* UART2_RXD */ + 0x70c MUX_M2 /* UART2_TXD */ + >; + }; + + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x064 MUX_M1 /* UART3_CTS_N */ + 0x068 MUX_M1 /* UART3_RTS_N */ + 0x06c MUX_M1 /* UART3_RXD */ + 0x070 MUX_M1 /* UART3_TXD */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x074 MUX_M1 /* UART4_CTS_N */ + 0x078 MUX_M1 /* UART4_RTS_N */ + 0x07c MUX_M1 /* UART4_RXD */ + 0x080 MUX_M1 /* UART4_TXD */ + >; + }; + + uart6_pmx_func: uart6_pmx_func { + pinctrl-single,pins = < + 0x05c MUX_M1 /* UART6_RXD */ + 0x060 MUX_M1 /* UART6_TXD */ + >; + }; }; pmx2: pinmux@e896c800 { @@ -27,6 +68,122 @@ reg = <0x0 0xe896c800 0x0 0x72c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* UART0_RXD */ + 0x05c 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x700 0x0 /* UART2_CTS_N */ + 0x704 0x0 /* UART2_RTS_N */ + 0x708 0x0 /* UART2_RXD */ + 0x70c 0x0 /* UART2_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x068 0x0 /* UART3_CTS_N */ + 0x06c 0x0 /* UART3_RTS_N */ + 0x070 0x0 /* UART3_RXD */ + 0x074 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x078 0x0 /* UART4_CTS_N */ + 0x07c 0x0 /* UART4_RTS_N */ + 0x080 0x0 /* UART4_RXD */ + 0x084 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x060 0x0 /* UART6_RXD */ + 0x064 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; }; pmx5: pinmux@fc182000 { From patchwork Tue Oct 23 19:06:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 149470 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1081388ljp; Tue, 23 Oct 2018 12:07:43 -0700 (PDT) X-Google-Smtp-Source: ACcGV63TkxZEwrz6lnkY1IqJHeO5bk4t9jws5gAbos/4PeP+wuTxaXkb4YcidnjzENP7dIuq7SOf X-Received: by 2002:a62:ca4d:: with SMTP id n74-v6mr50031177pfg.10.1540321663547; Tue, 23 Oct 2018 12:07:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540321663; cv=none; d=google.com; s=arc-20160816; b=w07v593xYFzbAP4VtFShPIfrBLl44Z6Wr6rS7R7vZpyvY9QDnoQjmxPuTnB7LJVr6B 8rv58r4fN+vvH4zGdLNQ5UCQf2WxvRPFvQf2VgdePnbn3ylqVAZDIkdf54DX+00K6NUO d2fwGhvMn1mND6K4wjBVOhDuvsRMLMt9ah505qVeJfaxWACEzV79PbkfJp5dI6JxkIgm lS+ulrW+0igsA08VN775Oqseu+D27cDYGElLvu6qmXNOrh0eGuVkU0OueACpS3kD8HBy t59l2fKVVAb/UxvGyabqosYpji6Vm4c5KjcYG+MKcHZrD65ix4/w4XCpYruMJxu4yiHw +a8Q== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id c4-v6si2107012pgn.309.2018.10.23.12.07.43; Tue, 23 Oct 2018 12:07:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dmi16/wj"; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729005AbeJXDcW (ORCPT + 5 others); Tue, 23 Oct 2018 23:32:22 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35162 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728788AbeJXDcW (ORCPT ); Tue, 23 Oct 2018 23:32:22 -0400 Received: by mail-pg1-f196.google.com with SMTP id 32-v6so1106398pgu.2 for ; Tue, 23 Oct 2018 12:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ekCHjoKA6CAi10Zv1PCEdpufcwUFeObbP8nppV00v2U=; b=dmi16/wj60Hy7MnhgVDxUhg+fuecyIA1aJ9h/Gv0B7n3JYWhnlPHuTMRwqDcQAJ7x/ ok3v/O6R4lW7FYg5+ybSAgDbLAC5UuXE9SOvX0ivO1U7jxAh/RE1b0LRAVTQxtYGE80P B5LtdiU8Qw6jhq0chTrcJeqcilppR0iGy5VHE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ekCHjoKA6CAi10Zv1PCEdpufcwUFeObbP8nppV00v2U=; b=qk4LJyHFXPZMu49XP4teqgBXXuplLiiuLZ4wrUxyWHisjpPdhtsKX3UtF9hQiVvY2N avuvdIPmesF4XWhLgBLH8x33QFS14MF3Heq7EHcg3kAYUHeACJeun44cJGB5+QK/RSSE E6TRoV2e9+QXrTBlTrqQPcx1jUw+qbdxeUArdXMs/oELiN/yqhvivWCZQOdecuou3gls IO48d62UJAv91/5e8DgxaKIAkeO0EczhaXhCc3jNYT0kAY84Z+ouAA7Jd6dofNd9CCjm 90MyeFZTLAW3BQBkcUATP3Kgs4/QhogTzp7Bw+l6cN2QlfWRCHVzFevXKzUw88M0P/rI RiTQ== X-Gm-Message-State: ABuFfog1cxphhBKEBD5J6FegGSQHFgbRJjMSyCX+pIgiydzvoz51cDo6 GoJ9EgjsBSlHIrPvf98uZH23wWReIg== X-Received: by 2002:a62:fc13:: with SMTP id e19-v6mr51474755pfh.101.1540321661098; Tue, 23 Oct 2018 12:07:41 -0700 (PDT) Received: from localhost.localdomain ([2405:204:744c:7bc5:17c:5f65:76c4:d542]) by smtp.gmail.com with ESMTPSA id v189-v6sm4897075pfb.54.2018.10.23.12.07.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Oct 2018 12:07:40 -0700 (PDT) From: Manivannan Sadhasivam To: xuwei5@hisilicon.com, linus.walleij@linaro.org, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/5] arm64: dts: hisilicon: hikey970: Add GPIO line names Date: Wed, 24 Oct 2018 00:36:55 +0530 Message-Id: <20181023190655.12004-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181023190655.12004-1-manivannan.sadhasivam@linaro.org> References: <20181023190655.12004-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add GPIO line names for HiSilicon HiKey970 board based on HI3670 SoC. The Line names are derived from "hikey970-schematics.pdf" document and named in conjunction with 96Boards CE Specification v1.0. Signed-off-by: Manivannan Sadhasivam --- .../boot/dts/hisilicon/hi3670-hikey970.dts | 317 ++++++++++++++++++ 1 file changed, 317 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index fc851a3177e7..c9775b66629f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -37,6 +37,323 @@ }; }; +/* + * Legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * "" = no idea, schematic doesn't say, could be + * unrouted (not connected to any external pin) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from "hikey970-schematics.pdf" from HiSilicon. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART2. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ +&gpio0 { + /* GPIO_000-GPIO_007 */ + gpio-line-names = + "", + "TP901", /* TEST_MODE connected to TP901 */ + "", + "GPIO_003_USB_HUB_RESET_N", + "NC", + "[AP_GPS_REF_CLK]", + "[I2C3_SCL]", + "[I2C3_SDA]"; +}; + +&gpio1 { + /* GPIO_008-GPIO_015 */ + gpio-line-names = + "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */ + "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */ + "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */ + "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */ + "[USER_LED5]", + "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */ + "[USER_LED3]", + "[USER_LED4]"; +}; + +&gpio2 { + /* GPIO_016-GPIO_023 */ + gpio-line-names = + "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */ + "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ + "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ + "GPIO_019_BT_ACTIVE", + "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ + "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ + "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ + "[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */ +}; + +&gpio3 { + /* GPIO_024-GPIO_031 */ + gpio-line-names = + "GPIO_024_WIFI_ACTIVE", + "GPIO_025_PERST_M.2", + "[I2C4_SCL]", + "[I2C4_SDA]", + "NC", + "GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */ + "[USER_LED1]", + "GPIO-L"; /* LSEC pin 34: GPIO_031 */ +}; + +&gpio4 { + /* GPIO_032-GPIO_039 */ + gpio-line-names = + "GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */ + "GPIO_033_PMU1_EN", + "GPIO_034_USBSW_SEL", + /* + * These two pins should be used for SD(IO) data according + * to the 96boards specification but seems to be repurposed + * for UART 0. They are however named according to the spec. + */ + "[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */ + "[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */ + "[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */ + "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ + "[SOC_GPS_UART3_CTS_N]"; /* TP2304 */ +}; + +&gpio5 { + /* GPIO_040-GPIO_047 */ + gpio-line-names = + "[SOC_GPS_UART3_RTS_N]", /* TP2302 */ + "[SOC_GPS_UART3_RXD]", /* TP2303 */ + "[SOC_GPS_UART3_TXD]", /* TP2305 */ + "[SOC_BT_UART4_CTS_N]", + "[SOC_BT_UART4_RTS_N]", + "[SOC_BT_UART4_RXD]", + "[SOC_BT_UART4_TXD]", + "NC"; +}; + +&gpio6 { + /* GPIO_048-GPIO_055 */ + gpio-line-names = + "NC", + "GPIO_049_USER_LED6", + "GPIO_050_CAN_RST", + "GPIO_051_WIFI_EN", + "GPIO-D", /* LSEC pin 26 */ + "GPIO-J", /* LSEC pin 32 */ + "GPIO_054_BT_EN", + "[GPIO_055_SEL]"; +}; + +&gpio7 { + /* GPIO_056-GPIO_063 */ + gpio-line-names = + "[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio8 { + /* GPIO_064-GPIO_071 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio9 { + /* GPIO_072-GPIO_079 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio10 { + /* GPIO_080-GPIO_087 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio11 { + /* GPIO_088-GPIO_095 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio12 { + /* GPIO_096-GPIO_103 */ + gpio-line-names = "NC", "", "", "", "", "", "", ""; +}; + +&gpio13 { + /* GPIO_104-GPIO_111 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio14 { + /* GPIO_112-GPIO_119 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio15 { + /* GPIO_120-GPIO_127 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio16 { + /* GPIO_128-GPIO_135 */ + gpio-line-names = + "[WL_SDIO_CLK]", + "[WL_SDIO_CMD]", + "[WL_SDIO_DATA0]", + "[WL_SDIO_DATA1]", + "[WL_SDIO_DATA2]", + "[WL_SDIO_DATA3]", + "[ETH_ISOLATE]", + "NC"; +}; + +&gpio17 { + /* GPIO_136-GPIO_143 */ + gpio-line-names = + "[MINI1CLK_EN]", "NC", "", "", "", "", "", ""; +}; + +&gpio18 { + /* GPIO_144-GPIO_151 */ + gpio-line-names = + "[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */ + "[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */ + "[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */ + "[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */ + "[POWER_INT_N]", + "[CDMA_GPS_SYNC]", + "GPIO_150_PEX_INTA", + "GPIO_151_CAN_INT"; +}; + +&gpio19 { + /* GPIO_152-GPIO_159 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio20 { + /* GPIO_160-GPIO_167 */ + gpio-line-names = + "[SD_CLK]", + "[SD_CMD]", + "[SD_DATA0]", + "[SD_DATA1]", + "[SD_DATA2]", + "[SD_DATA3]", + "GPIO_166_ETHCLK_EN", + "GPIO_167_USER_LED2"; +}; + +&gpio21 { + /* GPIO_168-GPIO_175 */ + gpio-line-names = + "GPIO_168_GPS_EN", + "GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */ + "GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */ + "GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */ + "", "", "", "", ""; +}; + +&gpio22 { + /* GPIO_176-GPIO_183 */ + gpio-line-names = + "[PMU_PWR_HOLD]", + "GPIO_177_WL_WAKEUP_AP", + "[JTAG_TCK]", + "[JTAG_TMS]", + "[JTAG_TDI]", + "[JTAG_TMS]", + "GPIO_182_FATAL_ERR", + "NC"; +}; + +&gpio23 { + /* GPIO_184-GPIO_191 */ + gpio-line-names = + "GPIO_184_JTAG_SEL", + "GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */ + "[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */ + "[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */ + "[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */ + "[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */ + "[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */ + "[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */ +}; + +&gpio24 { + /* GPIO_192-GPIO_199 */ + gpio-line-names = + "[SD_LED]", + "NC", + "[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */ + "[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */ + "[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */ + "[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */ + "", + "[I2S2_DO]"; +}; + +&gpio25 { + /* GPIO_200-GPIO_207 */ + gpio-line-names = + "[I2S2_XCLK]", + "[I2S2_XFS]", + "GPIO_202_PERST_ETH", + "GPIO_203_PWRON_DET", + "GPIO_204_PMU1_IRQ_N", + "GPIO_205_SD_DET", + "GPIO_206_GPS_MOTION_INT", + "GPIO_207_HDMI_SEL"; +}; + +&gpio26 { + /* GPIO_208-GPIO_215 */ + gpio-line-names = + "GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */ + "GPIO_209_VBUS_TYPEC", + "NC", + "NC", + "NC", + "[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */ + "[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */ + "[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */ +}; + +&gpio27 { + /* GPIO_216-GPIO_223 */ + gpio-line-names = + "[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */ + "GPIO_217_HDMI_PD", + "GPIO_218_GPS_WAKEUP_AP", + "GPIO_219_M.2CLK_EN", + "GPIO_220_PERST_MINI", + "GPIO_221_CC_INT", + "[PCIE_CLKREQ_L]", + "NC"; +}; + +&gpio28 { + /* GPIO_224-GPIO_231 */ + gpio-line-names = + "[PMU0_INT]", + "[SPMI_DATA]", + "[SPMI_CLK]", + "[CAN_SPI_CLK]", + "[CAN_SPI_DI]", + "[CAN_SPI_DO]", + "[CAN_SPI_CS]", + "GPIO_231_HDMI_INT"; +}; + &uart0 { /* On High speed expansion header */ label = "HS-UART0";