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Tue, 14 Sep 2021 05:58:03 -0700 Envelope-to: git@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com Received: from [10.140.6.39] (port=36978 helo=xhdsgoud40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mQ80f-0002I2-Q0; Tue, 14 Sep 2021 05:58:02 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Shubhrajyoti Datta Subject: [PATCH v13 1/5] dt-bindings: add documentation of xilinx clocking wizard Date: Tue, 14 Sep 2021 18:27:41 +0530 Message-ID: <5abe09974e95f127784b9eb5b8764e099e4a1b2d.1631623906.git.shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cb874f2d-e4a0-435f-d99b-08d9777f51a4 X-MS-TrafficTypeDiagnostic: BY5PR02MB6962: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:439; 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Signed-off-by: Shubhrajyoti Datta Reviewed-by: Rob Herring --- .../bindings/clock/xlnx,clocking-wizard.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 000000000000..634b7b964606 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + enum: + - xlnx,clocking-wizard + - xlnx,clocking-wizard-v5.2 + - xlnx,clocking-wizard-v6.0 + + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. Higher the speed grade faster is the FPGA device. + + xlnx,nr-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + description: + Number of outputs. + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - xlnx,speed-grade + - xlnx,nr-outputs + +additionalProperties: false + +examples: + - | + clock-controller@b0000000 { + compatible = "xlnx,clocking-wizard"; + reg = <0xb0000000 0x10000>; + #clock-cells = <1>; + xlnx,speed-grade = <1>; + xlnx,nr-outputs = <6>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + }; +... 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Tue, 14 Sep 2021 05:58:05 -0700 Envelope-to: git@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com Received: from [10.140.6.39] (port=36978 helo=xhdsgoud40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mQ80i-0002I2-Ko; Tue, 14 Sep 2021 05:58:05 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Shubhrajyoti Datta Subject: [PATCH v13 2/5] clk: clocking-wizard: Add the clockwizard to clk directory Date: Tue, 14 Sep 2021 18:27:42 +0530 Message-ID: <3059a0f043c8f92e4ca35980c89d5864acc20513.1631623906.git.shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e41c25b6-c5fa-43d2-afdf-08d9777f5758 X-MS-TrafficTypeDiagnostic: MW4PR02MB7188: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3173; 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And delete the driver from the staging as it is in drivers/clk. Signed-off-by: Shubhrajyoti Datta --- drivers/clk/Kconfig | 9 ++++++ drivers/clk/Makefile | 1 + .../clk-xlnx-clock-wizard.c | 3 +- drivers/staging/Kconfig | 2 -- drivers/staging/Makefile | 1 - drivers/staging/clocking-wizard/Kconfig | 10 ------- drivers/staging/clocking-wizard/Makefile | 2 -- drivers/staging/clocking-wizard/TODO | 13 -------- .../staging/clocking-wizard/dt-binding.txt | 30 ------------------- 9 files changed, 12 insertions(+), 59 deletions(-) rename drivers/{staging/clocking-wizard => clk}/clk-xlnx-clock-wizard.c (99%) delete mode 100644 drivers/staging/clocking-wizard/Kconfig delete mode 100644 drivers/staging/clocking-wizard/Makefile delete mode 100644 drivers/staging/clocking-wizard/TODO delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c5b3dc97396a..3e0bf794ee09 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -390,6 +390,15 @@ config COMMON_CLK_K210 help Support for the Canaan Kendryte K210 RISC-V SoC clocks. +config COMMON_CLK_XLNX_CLKWZRD + tristate "Xilinx Clocking Wizard" + depends on COMMON_CLK && OF + help + Support for the Xilinx Clocking Wizard IP core clock generator. + Adds support for clocking wizard and compatible. + This driver supports the Xilinx clocking wizard programmable clock + synthesizer. The number of output is configurable in the design. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e42312121e51..e7abf6665423 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o # please keep this section sorted lexicographically by directory path name obj-y += actions/ diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c similarity index 99% rename from drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c rename to drivers/clk/clk-xlnx-clock-wizard.c index 39367712ef54..ec377f0d569b 100644 --- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -2,9 +2,10 @@ /* * Xilinx 'Clocking Wizard' driver * - * Copyright (C) 2013 - 2014 Xilinx + * Copyright (C) 2013 - 2021 Xilinx * * Sören Brinkmann + * */ #include diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index e03627ad4460..7d0f49f9a847 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -72,8 +72,6 @@ source "drivers/staging/gs_fpgaboot/Kconfig" source "drivers/staging/unisys/Kconfig" -source "drivers/staging/clocking-wizard/Kconfig" - source "drivers/staging/fbtft/Kconfig" source "drivers/staging/most/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index c7f8d8d8dd11..9498bc973d4e 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_LTE_GDM724X) += gdm724x/ obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/ obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/ obj-$(CONFIG_UNISYSSPAR) += unisys/ -obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ obj-$(CONFIG_FB_TFT) += fbtft/ obj-$(CONFIG_MOST) += most/ obj-$(CONFIG_KS7010) += ks7010/ diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig deleted file mode 100644 index 2324b5d73788..000000000000 --- a/drivers/staging/clocking-wizard/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Xilinx Clocking Wizard Driver -# - -config COMMON_CLK_XLNX_CLKWZRD - tristate "Xilinx Clocking Wizard" - depends on COMMON_CLK && OF && HAS_IOMEM - help - Support for the Xilinx Clocking Wizard IP core clock generator. diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile deleted file mode 100644 index b1f915224d96..000000000000 --- a/drivers/staging/clocking-wizard/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO deleted file mode 100644 index c7e1dc58dfba..000000000000 --- a/drivers/staging/clocking-wizard/TODO +++ /dev/null @@ -1,13 +0,0 @@ -TODO: - - support for fractional multiplier - - support for fractional divider (output 0 only) - - support for set_rate() operations (may benefit from Stephen Boyd's - refactoring of the clk primitives: - https://lore.kernel.org/lkml/1409957256-23729-1-git-send-email-sboyd@codeaurora.org) - - review arithmetic - - overflow after multiplication? - - maximize accuracy before divisions - -Patches to: - Greg Kroah-Hartman - Sören Brinkmann diff --git a/drivers/staging/clocking-wizard/dt-binding.txt b/drivers/staging/clocking-wizard/dt-binding.txt deleted file mode 100644 index efb67ff9f76c..000000000000 --- a/drivers/staging/clocking-wizard/dt-binding.txt +++ /dev/null @@ -1,30 +0,0 @@ -Binding for Xilinx Clocking Wizard IP Core - -This binding uses the common clock binding[1]. Details about the devices can be -found in the product guide[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Clocking Wizard Product Guide -https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf - -Required properties: - - compatible: Must be 'xlnx,clocking-wizard' - - reg: Base and size of the cores register space - - clocks: Handle to input clock - - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' - - clock-output-names: Names for the output clocks - -Optional properties: - - speed-grade: Speed grade of the device (valid values are 1..3) - -Example: - clock-generator@40040000 { - reg = <0x40040000 0x1000>; - compatible = "xlnx,clocking-wizard"; - speed-grade = <1>; - clock-names = "clk_in1", "s_axi_aclk"; - clocks = <&clkc 15>, <&clkc 15>; - clock-output-names = "clk_out0", "clk_out1", "clk_out2", - "clk_out3", "clk_out4", "clk_out5", - "clk_out6", "clk_out7"; - }; From patchwork Tue Sep 14 12:57:43 2021 Content-Type: text/plain; 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Tue, 14 Sep 2021 05:58:08 -0700 Envelope-to: git@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com Received: from [10.140.6.39] (port=36978 helo=xhdsgoud40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mQ80l-0002I2-DH; Tue, 14 Sep 2021 05:58:07 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Shubhrajyoti Datta Subject: [PATCH v13 3/5] clk: clocking-wizard: Rename nr-outputs to xlnx, nr-outputs Date: Tue, 14 Sep 2021 18:27:43 +0530 Message-ID: <9945464e90fa29c2008af182c87d055de8ac88fa.1631623906.git.shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 66575bed-eb2b-4baf-f12a-08d9777f54fc X-MS-TrafficTypeDiagnostic: CH0PR02MB7866: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:475; 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Signed-off-by: Shubhrajyoti Datta --- drivers/clk/clk-xlnx-clock-wizard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index ec377f0d569b..1e0818eb0435 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -480,7 +480,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) goto err_disable_clk; } - ret = of_property_read_u32(np, "nr-outputs", &nr_outputs); + ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); if (ret || nr_outputs > WZRD_NUM_OUTPUTS) { ret = -EINVAL; goto err_disable_clk; From patchwork Tue Sep 14 12:57:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shubhrajyoti Datta X-Patchwork-Id: 511098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87A56C433EF for ; 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Tue, 14 Sep 2021 05:58:10 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Shubhrajyoti Datta Subject: [PATCH v13 4/5] clk: clocking-wizard: Fix the reconfig for 5.2 Date: Tue, 14 Sep 2021 18:27:44 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c9f4076d-6117-4fbb-e924-08d9777f558e X-MS-TrafficTypeDiagnostic: SN6PR02MB4399: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:883; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rWvBkireDBBehzMD3rIS/jH1TCGT8869a6oHE2+ASuYR2Z3+ubK2vOFj8Y5/I6rBtyFjS1nmskE1XQhhPcG/LFsnmH0hX7+vJPs6eqOcwQZYbiqTPscqt6OhhI1EKVrf9epkJWJBr6oFtAEJ24wo7wpTPGZi75fHoP8Iiw/UqDEK2ENgh5gFCd0g7tNZ7K4oIyA49y9vwXedT2ojJFxomPiDh1cLKV3P8WH7cJYjvnWPUqTX2n8AYW6UyCII4Dt3GqvbrZZH3jDpLZ3S0CbVePaKdsM1AcXhrM4F0IC256PSH612vEp+csvefppqEkaUP79ZornXZDHYLy3lTgisQQLe7lRqGpRreVq4lym8wfSesi304EsCl2Chz86JNDop4XnGfb31PNCHsrSU0ii4J0+4cliRG+lSBPdvjA47l0zFmlhelzWx3DOOcawpnwBxAUTAkppMciIHhdPVD2ADwzWX+r2l+kcHdoxrjnf2fG2vPb6FTm/DmDzWPn+MacNYhxuIvP8E80NfHuyhiKRSD0P3ssWZojoRJNHVOkn1bzREtDvE8N+xZYpzBFfMrrwaNzxeF2fzRL6k0kCwtFOquaMlLIgfSc1M7ClMXdbu2K5OkFBmpf1KSms6KoDpLJ92n+AOW6e/0GbDMIwt2BeopTnCb6AxGsAU6zQfOe+wv2nbTLgzNeHFn19MNz6Hm7hkImSA/OQP8xh3TzCW0ekMVu9fQP6s/0Hb/38GaDauekw= X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(346002)(136003)(376002)(396003)(39860400002)(36840700001)(46966006)(83380400001)(5660300002)(2906002)(9786002)(478600001)(6666004)(336012)(426003)(8936002)(70586007)(356005)(107886003)(82310400003)(6916009)(316002)(82740400003)(8676002)(26005)(186003)(36906005)(7636003)(47076005)(7696005)(54906003)(36756003)(70206006)(2616005)(36860700001)(4326008)(44832011)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 12:58:22.8797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9f4076d-6117-4fbb-e924-08d9777f558e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0050.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4399 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 5.2 the reconfig is triggered by writing 7 followed by 2 to the reconfig reg. Add the same. Also 6.0 is backward compatible so it should be fine. Signed-off-by: Shubhrajyoti Datta --- drivers/clk/clk-xlnx-clock-wizard.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 1e0818eb0435..61c40e06e381 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -44,6 +44,8 @@ #define WZRD_DR_INIT_REG_OFFSET 0x25C #define WZRD_DR_DIV_TO_PHASE_OFFSET 4 #define WZRD_DR_BEGIN_DYNA_RECONF 0x03 +#define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07 +#define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02 #define WZRD_USEC_POLL 10 #define WZRD_TIMEOUT_POLL 1000 @@ -165,7 +167,9 @@ static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, goto err_reconfig; /* Initiate reconfiguration */ - writel(WZRD_DR_BEGIN_DYNA_RECONF, + writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, + divider->base + WZRD_DR_INIT_REG_OFFSET); + writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, divider->base + WZRD_DR_INIT_REG_OFFSET); /* Check status register */ @@ -224,7 +228,7 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); void __iomem *div_addr = divider->base + divider->offset; - rate_div = ((parent_rate * 1000) / rate); + rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate); clockout0_div = rate_div / 1000; pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); @@ -246,7 +250,9 @@ static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, return err; /* Initiate reconfiguration */ - writel(WZRD_DR_BEGIN_DYNA_RECONF, + writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, + divider->base + WZRD_DR_INIT_REG_OFFSET); + writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, divider->base + WZRD_DR_INIT_REG_OFFSET); /* Check status register */ From patchwork Tue Sep 14 12:57:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shubhrajyoti Datta X-Patchwork-Id: 511097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8672EC433F5 for ; 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Tue, 14 Sep 2021 05:58:18 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Shubhrajyoti Datta Subject: [PATCH v13 5/5] clk: clocking-wizard: Update the compatible Date: Tue, 14 Sep 2021 18:27:45 +0530 Message-ID: <0ab0e49385d7f7a1cece9bb3ba2c23944d5dbc67.1631623906.git.shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b662a00-8d8e-4102-c861-08d9777f5b17 X-MS-TrafficTypeDiagnostic: DM6PR02MB4889: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G5XRlHCmCg49LfsyOzgGMQllEOYUdr4CM7WfISXOxHAlVt8eyfEoRLnggv2YZH1JYDE+jgihNCm90cd9nt1Mpet2gk98pv+Yoa13VHjpvKMf8uNmBuX7Zhbm09V5m+PZUG1NWzZivCRuyyfa8T+VPZUj2/xs++Lbk+GmnvNFytTTb+v0ckqJi9EDQe7apbpi4vZwSAxKG+2AkIpKHeR92GCGw/PtB5QmAf7DyrYPUaT7O9LzILL8FLNxb/oUsivLwAgfgcBAEl1MLg3BTXlk20BZq/Xw22z3Zg0jph2u1SI+KKsHUsOMeac+JMWwc+QF+6CrbpkP+qPuO9gS2MgWXhJB/xx4gxr5O39eL960q19pNw0eciWN3GTaQ3IfydB9A/+phv1HFIsTuuh4XRVl8bIbLuUnBw7nMcLD8Ngq3nBidRE9LrAj3FSSDQ2TxnITjXbjxuLEsiXKq46b4XWwAbhSA/T7oMLad5FnEkHY2GKHihFCqxKYMYD9XUOb1b4K3xlFaQY3RSvA4CaoMEtEdMYNIcWp1mmimZrr3s5xvMcoFUL+lzrLigugJBezxspoUeCQAreiod3Y7JGI+k1nSTJj26LMiGZ1qYCqW2hSUspnXJnmW31P/3iapaId6P7M67D17H7tN0IRBREny9+yy9/CYLZLjkZLaZ+7sVV8Wj0V7oqaVZetYKjtGs48voS79WvI1tUIyt/5c2VKUotsXYcqtXnaumUn5sdSGS/2crA= X-Forefront-Antispam-Report: CIP:149.199.62.198; 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MODULE_DEVICE_TABLE(of, clk_wzrd_ids);