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[209.51.188.17]) by mx.google.com with ESMTPS id l12si1207593vsv.46.2021.09.16.08.38.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:38:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ioJ7RRMH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtSm-0004E9-JS for patch@linaro.org; Thu, 16 Sep 2021 11:38:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLQ-0001E6-13 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:36 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:34466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLK-0002Mb-Cj for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:35 -0400 Received: by mail-pf1-x435.google.com with SMTP id g14so6302947pfm.1 for ; Thu, 16 Sep 2021 08:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Za07j0Y47GbP3hPdPAHTpHPNXYMHqLxdsq6WQb/v+yc=; b=ioJ7RRMH6AO6+XGdcojFGv1YpcJ4RMSjhwTxOgvN38Rh/EoEqamaq0c1WNAxCggl17 XfhAI65DeHT3DXEZnlweEIMYuvi1IAH8oDNKDZDNRgZFo3a7KaTjUG46Mz8grj5vJ45k C9Tg/+lMH7eVchcATpkByEZwxaXvIXYz4sUr6KDZsKtcp8q8n00SmP3aayIN0tnOeOIw 25eXy3On6oubLPdl984Zu8jpIiEaR73grZZo5bEkYzq+JTbkyo56itYpv+5qGdCUaPhk SSt9bj1JX7m7+om0ThhOC8lO41SB4sySdU09TLtTZvCME5EMXZ09+CWLwyuSRPacBKug wuww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Za07j0Y47GbP3hPdPAHTpHPNXYMHqLxdsq6WQb/v+yc=; b=6ktCX+k0AlDWBoQtEtbZJ2ofMl6idy+e8eEF9E5sHimZ1jEWj5BbzaRVjicn/+/wY4 k04V7xrfnEJ+MIbiV3PITF4IepEqJmjybsEL9bO6GArM3FBp18tX75Y6qBZCbr94Xgi0 FKErOXQoldg64g/yxgyEFr+aey8pYyFnivyC4dg0iwqjwSQ1WNnc0rSKyqUqxqVK/FNp wanuV/aQBCLidcJTbDZ+Z+im/8S0WtCk0Faah8y+7LvvCfv4MCpwJ7Rao8/YRWBsT+Lp DLvEMxDqiXWVoCu5gm5tE7xrEVfNkM3XIdC9+JMuJsJP+fu3bqqSAuFnfO/7GdhGOebW MC4A== X-Gm-Message-State: AOAM532q8NIXO795aGEe1LQuUxM4E0UnyQgcqFjKEc0ossygMDnX1jhY x6KwU4f4KZJISOKvZ1UHsw9UrLYE0Sszrg== X-Received: by 2002:a63:6e03:: with SMTP id j3mr5470403pgc.465.1631806227007; Thu, 16 Sep 2021 08:30:27 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/35] include/exec: Move cpu_signal_handler declaration Date: Thu, 16 Sep 2021 08:29:51 -0700 Message-Id: <20210916153025.1944763-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 13 +++++++++++++ target/alpha/cpu.h | 6 ------ target/arm/cpu.h | 7 ------- target/avr/cpu.h | 2 -- target/cris/cpu.h | 8 -------- target/hexagon/cpu.h | 3 --- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 7 ------- target/m68k/cpu.h | 8 -------- target/microblaze/cpu.h | 7 ------- target/mips/cpu.h | 3 --- target/mips/internal.h | 2 -- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 7 ------- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 4 ---- target/s390x/cpu.h | 7 ------- target/sh4/cpu.h | 3 --- target/sparc/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 13 insertions(+), 89 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5d1b6d80fb..9d5987ba04 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, } return addr; } + +/** + * cpu_signal_handler + * @signum: host signal number + * @pinfo: host siginfo_t + * @puc: host ucontext_t + * + * To be called from the SIGBUS and SIGSEGV signal handler to inform the + * virtual cpu of exceptions. Returns true if the signal was handled by + * the virtual CPU. + */ +int cpu_signal_handler(int signum, void *pinfo, void *puc); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 4e993bd15b..ce9ec32199 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); #define cpu_list alpha_cpu_list -#define cpu_signal_handler cpu_alpha_signal_handler typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; @@ -440,11 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_alpha_signal_handler(int host_signum, void *pinfo, - void *puc); bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 09d9027734..751141915d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env) return env->aarch64; } -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_arm_signal_handler(int host_signum, void *pinfo, - void *puc); - /** * pmu_op_start/finish * @env: CPUARMState @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU -#define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list /* ARM has the following "translation regimes" (as the ARM ARM calls them): diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 93e3faa0a9..dceacf3cd7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature) } #define cpu_list avr_cpu_list -#define cpu_signal_handler cpu_avr_signal_handler #define cpu_mmu_index avr_cpu_mmu_index static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); void avr_cpu_list(void); int cpu_avr_exec(CPUState *cpu); -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index be021899ae..6603565f83 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_cris_signal_handler(int host_signum, void *pinfo, - void *puc); - void cris_initialize_tcg(void); void cris_initialize_crisv10_tcg(void); @@ -250,8 +244,6 @@ enum { #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU -#define cpu_signal_handler cpu_cris_signal_handler - /* MMU modes definitions */ #define MMU_USER_IDX 1 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2855dd3881..f7d043865b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -129,9 +129,6 @@ typedef struct HexagonCPU { #include "cpu_bits.h" -#define cpu_signal_handler cpu_hexagon_signal_handler -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); - static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7854675b90..d3cb7a279f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -319,9 +319,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } void cpu_hppa_change_prot_id(CPUHPPAState *env); #endif -#define cpu_signal_handler cpu_hppa_signal_handler - -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7dd664791a..c2954c71ea 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_x86_signal_handler(int host_signum, void *pinfo, - void *puc); - /* cpu.c */ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3); @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif -#define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list /* MMU modes definitions */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 550eb028b6..a3423729ef 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_m68k_signal_handler(int host_signum, void *pinfo, - void *puc); uint32_t cpu_m68k_get_ccr(CPUM68KState *env); void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); @@ -563,7 +556,6 @@ enum { #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU -#define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list /* MMU modes definitions */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 40401c33b7..13ed3cd4dd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) } void mb_tcg_init(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_mb_signal_handler(int host_signum, void *pinfo, - void *puc); #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU -#define cpu_signal_handler cpu_mb_signal_handler - /* MMU modes definitions */ #define MMU_NOMMU_IDX 0 #define MMU_KERNEL_IDX 1 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1dfe69c6c0..56b1cbd091 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1193,7 +1193,6 @@ struct MIPSCPU { void mips_cpu_list(void); -#define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); @@ -1277,8 +1276,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); - #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU diff --git a/target/mips/internal.h b/target/mips/internal.h index eecdd10116..daddb05fd4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; #endif /* !CONFIG_USER_ONLY */ -#define cpu_signal_handler cpu_mips_signal_handler - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc71..88a511209c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,7 +193,6 @@ struct Nios2CPU { void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU #define cpu_gen_code cpu_nios2_gen_code -#define cpu_signal_handler cpu_nios2_signal_handler #define CPU_SAVE_VERSION 1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index be6df81a81..187a4a114e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -320,11 +320,9 @@ void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list -#define cpu_signal_handler cpu_openrisc_signal_handler #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 362e7c4c5c..01d3773bc7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU -#define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list /* MMU modes definitions */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e735e53e26..465142616a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); -#define cpu_signal_handler riscv_cpu_signal_handler #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); void riscv_translate_init(void); -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index faa3606f52..4ac71aec37 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void rx_translate_init(void); -int cpu_rx_signal_handler(int host_signum, void *pinfo, - void *puc); - void rx_cpu_list(void); void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); -#define cpu_signal_handler cpu_rx_signal_handler #define cpu_list rx_cpu_list #include "exec/cpu-all.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b26ae8fff2..3153d053e9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); -#define cpu_signal_handler cpu_s390x_signal_handler - - /* interrupt.c */ #define RA_IGNORED 0 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 017a770214..56f7c32df9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); void sh4_translate_init(void); -int cpu_sh4_signal_handler(int host_signum, void *pinfo, - void *puc); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env); #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU -#define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list /* MMU modes definitions */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ff8ae73002..6b40d02237 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, int mmu_idx); #endif #endif -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU -#define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list /* MMU modes definitions */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f..c461387e71 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); void tricore_cpu_list(void); -#define cpu_signal_handler cpu_tricore_signal_handler #define cpu_list tricore_cpu_list static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index cbb720e7cc..646965f379 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -#define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); qemu_irq *xtensa_get_extints(CPUXtensaState *env); qemu_irq xtensa_get_runstall(CPUXtensaState *env); -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); void xtensa_cpu_list(void); void xtensa_sync_window_from_phys(CPUXtensaState *env); void xtensa_sync_phys_from_window(CPUXtensaState *env); From patchwork Thu Sep 16 15:29:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512941 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1325523jao; Thu, 16 Sep 2021 08:34:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmXVVLoOU+62RRHdRrSbx2+rNlp3PQgpD/0nsaJs1dt88yzz8bu1RoiBKiU54ouBLZjufF X-Received: by 2002:a05:620a:4404:: with SMTP id v4mr5748029qkp.344.1631806498687; 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If we don't ensure we go back * to sleep in the halted state we won't cleanly * start-up when the vCPU is enabled. * * cpu->halted should ensure we sleep in wait_io_event */ g_assert(cpu->halted); break; qemu_wait_io_event() is sysemu-specific, so we can restrict the cpu_handle_halt() call in cpu_exec() to system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 75dbc1e4e3..5fd1ed3422 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -588,8 +588,9 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, static inline bool cpu_handle_halt(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY if (cpu->halted) { -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) +#if defined(TARGET_I386) if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { X86CPU *x86_cpu = X86_CPU(cpu); qemu_mutex_lock_iothread(); @@ -597,13 +598,14 @@ static inline bool cpu_handle_halt(CPUState *cpu) cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); qemu_mutex_unlock_iothread(); } -#endif +#endif /* TARGET_I386 */ if (!cpu_has_work(cpu)) { return true; } cpu->halted = 0; } +#endif /* !CONFIG_USER_ONLY */ return false; } From patchwork Thu Sep 16 15:29:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512944 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1327552jao; Thu, 16 Sep 2021 08:37:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwNlziXXndAyB4XSdQuFX2BTjRN6IUOjtfNH08cxnB9uqKKTTqD7LvwmTduy7IVLwa+V0YH X-Received: by 2002:ac8:5941:: with SMTP id 1mr5535404qtz.1.1631806631939; Thu, 16 Sep 2021 08:37:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806631; cv=none; d=google.com; s=arc-20160816; b=O4LaRRSReS8akSXEWW3P4EA/lKJn5/7mP9gsvfXVILzYLVEx9IUhgdeIcbVfovEBEh 75bEdEEQ3D3T/HKobAokrQmH8Rhhg3+lTr34PeNe4ICj1GKNMxwVErYKcoWqrb4JV5Ni KGVeD24jbINhINL3j6YCodiPx8lnH8RpXy5NWf/BTbv73GsNzUz7KS6NtA8pnuoDp1Pz 9qRsjkudYMm+PT+WoYUZ839/7dgHEfY8HYSYpP8TAaUC2OhCEZipkGpr2l0RIBv0XRI9 pFFrHZc8rP4cq0Syg7Oiy7Zr9DIL8nDkd4B2TmbL+jSevGygLvhiiUkUSY+Fe/OhmSIh pMlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/b65paiPCJASFJfCtunYkpNY6XJIYqckezX/cCSvcrY=; b=OQ9JNE1b4hHAz0OFf38hj+bUtlHz4LCzDt2+nBu19MZop6lJFcoSPXBmwPHJf48Xhw NKfwcLpVJMBWHlZw5BKHb6Gx4vPHJr9iBhc8eJpCOyINtY7wllSer8SBjNcxgdmzBz/3 NSI2l90ZED6ldDqoVhpV3rsnZY8rrPPe2F6+g8BekCCrigo2SmFZYeyJstwNDL+zKA3w dRL4Gvd6XlorVSD9IyoGWoJyXqwaQXse3saYXvJSBVw9RmKsAZPPbVTw1bwcpm9XwM25 2tXKcGc7XHVdmewfEfvWPgMjfFtdDge+H5rNjFaF+GCjTuJfur+6nTbDt3JjUlnEkFFP JZ8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eQCOAoqW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-3-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bc864564ce..2bd563e221 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -538,6 +538,22 @@ enum CPUDumpFlags { void cpu_dump_state(CPUState *cpu, FILE *f, int flags); #ifndef CONFIG_USER_ONLY +/** + * cpu_has_work: + * @cpu: The vCPU to check. + * + * Checks whether the CPU has work to do. + * + * Returns: %true if the CPU has work, %false otherwise. + */ +static inline bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + g_assert(cc->has_work); + return cc->has_work(cpu); +} + /** * cpu_get_phys_page_attrs_debug: * @cpu: The CPU to obtain the physical page address for. @@ -636,22 +652,6 @@ CPUState *cpu_create(const char *typename); */ const char *parse_cpu_option(const char *cpu_option); -/** - * cpu_has_work: - * @cpu: The vCPU to check. - * - * Checks whether the CPU has work to do. - * - * Returns: %true if the CPU has work, %false otherwise. - */ -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - - g_assert(cc->has_work); - return cc->has_work(cpu); -} - /** * qemu_cpu_is_self: * @cpu: The vCPU to check against. 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[209.51.188.17]) by mx.google.com with ESMTPS id z13si1769832qtv.346.2021.09.16.08.40.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:40:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cdUGAF2M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56826 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtUZ-0000I2-KA for patch@linaro.org; Thu, 16 Sep 2021 11:40:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLR-0001IM-IL for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:37 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:53169) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLK-0002N6-W3 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:37 -0400 Received: by mail-pj1-x102f.google.com with SMTP id v19so4815288pjh.2 for ; Thu, 16 Sep 2021 08:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VtxRpJ0CcK/sAEcE4Sv89p9y9iZvEmtHp37kJ5kh0xo=; b=cdUGAF2M5jMcbbKPmfEWnLrP/wNrAn1m6sjWJ1qT1HIjZi9uBpwSCq4AMoK+j47A6F 7zD54D0SljmKQfUjR6VyZMkE8NmvIvHSrMc54Y2f6dvvbRW9Kt84neEDIWkzczDHOr0Q 5emcudIeCY5igtl601Fg9Qjdk9G7RQxavm9RECRItP/KgMYha+bqm91eZkq81k/FAlBp 2bt8LCFeGrvPGXWtKRTGw3pL1LJPJ9nZx5qovruHYboqoCwlH81Rf9INFzXHnByjKjXh iMR4xkxPFmNFeT9yBNrEmgyCe8BmrmVRsEQoT5oEpG/FW311WDaB3txsAFcjkW1RgWKO Iwlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VtxRpJ0CcK/sAEcE4Sv89p9y9iZvEmtHp37kJ5kh0xo=; b=zF9Fdb6HAvhKAmIQkVK7wQdN8xtga+tywJrBAoXZwBlYpbvBZyfq/VVvGkLVuxIezj r1epyfgtFz4rhSALi2KmIC1uTpGiWBrbvaSIi2+C6Z9SNAWGOpjk7X+0QaC3ZX8sloZF 0go+UNibO4XI2sb039DZ5MYEQC+LcYwi+RR+8+ZKclUzefVfvhOPN1W9c5l8DDO9UMwL cahh3PC+UwU50CPRYfXpyBuaLTs0diptR0LnSB/bLM+1dvJxMOBumlusi14rpR77Rcud 4x4aG+6WFCHhs3LFUkfYMAWvcuPX4NlK2ir0wQnpwE/47oOuqz4+ZTw/PaE2leXGdtqU 4z0Q== X-Gm-Message-State: AOAM533lIGnDsr7taCG5Rf2YzYB9B/yI+rLZfNW6l2XGaz6jrZIUJ0vG aGG7QqVoiPFxetaimBgkfSkFb6OMBg1wmA== X-Received: by 2002:a17:90a:d596:: with SMTP id v22mr15731489pju.51.1631806228967; Thu, 16 Sep 2021 08:30:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/35] hw/core: Un-inline cpu_has_work() Date: Thu, 16 Sep 2021 08:29:54 -0700 Message-Id: <20210916153025.1944763-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé We want to make cpu_has_work() per-accelerator. Only declare its prototype and move its definition to softmmu/cpus.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-4-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 +------- softmmu/cpus.c | 8 ++++++++ 2 files changed, 9 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2bd563e221..e2dd171a13 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -546,13 +546,7 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags); * * Returns: %true if the CPU has work, %false otherwise. */ -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - - g_assert(cc->has_work); - return cc->has_work(cpu); -} +bool cpu_has_work(CPUState *cpu); /** * cpu_get_phys_page_attrs_debug: diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 071085f840..7e2cb2c571 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -251,6 +251,14 @@ void cpu_interrupt(CPUState *cpu, int mask) } } +bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + g_assert(cc->has_work); + return cc->has_work(cpu); +} + static int do_vm_stop(RunState state, bool send_stop) { int ret = 0; From patchwork Thu Sep 16 15:29:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512942 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1326694jao; Thu, 16 Sep 2021 08:36:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzt/+dwPc/NfMJt2EVQNx+o4e6F3c7f86WGgcI/usnnajRx56ffhxH26kOiEuydAZZJqbOV X-Received: by 2002:a05:620a:789:: with SMTP id 9mr5703293qka.400.1631806571305; Thu, 16 Sep 2021 08:36:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806571; cv=none; d=google.com; s=arc-20160816; b=AOW02lD0jIUwzU97oDAjCgAz+EWAGlk0fH6Ym+2euWKlCBejlISypIwI3lfOxC2J3m aoadX6/OQXmBgbr6SsWNG1gDVEmwzlduj0sgiqRncInuLh1YN+mrqFNpEpUvPspg+zor g3X3CKJTI1j2Q6wyBwW3IpbGJicYIiab5neKZ5L1tPKE/WQUnnaL5HPj5MkmvkkyZURt 95pXKQfLouE9MCtYAaWcoOWTi7qhIwBrTuz10Ui/Wkgy4jP7LA816RZXvplYw04yCJka U2utATI0RK9aOV4XnK+jgwt38+k6Xs1y6Ec/eZ0WWAI7X84ZJGuGwNyma0XhwHVX/XLe qk1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kZ2VcPtLko9Bov3EWMO38HipWq5pDjJDr/5HXHOEyEY=; b=icDMZYbUYwzoa+cknGOXBzdmMAdXF+lGm+XfmClzgugh+2d+mQf8UuGEyahdOyY4/O rZVWAHMwYxgNvoBSlouBlf2ERReA1FMLAe8LpyijuH4EGlD/aESGXEndI4344b1rgeXW ZjIFUCXi86HgBf5l+rusOpTilU1gN6ftL9qdY+2aseGOlloDpnckxdHXja20FufwN5FR v5/l3uhjyVy1dTiM2O/R7nFWw2XnxV5+eWxI40aVS7IFgLy7TGmaWzPBhe0dz8Hsx3mI Sqk//IobzW4aPpjNlJZLpImTGklus3fw2jVBQa4p4y+jlxNSAIiPhsbcmHafzCvk9xrF NaUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="U/kmVse9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Eventually call it from cpu_has_work(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-5-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/sysemu/accel-ops.h | 5 +++++ softmmu/cpus.c | 3 +++ 2 files changed, 8 insertions(+) -- 2.25.1 diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 032f6979d7..de83f095f2 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -31,6 +31,11 @@ struct AccelOpsClass { void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ void (*kick_vcpu_thread)(CPUState *cpu); + /** + * @has_work: Callback for checking if there is work to do. + */ + bool (*has_work)(CPUState *cpu); + void (*synchronize_post_reset)(CPUState *cpu); void (*synchronize_post_init)(CPUState *cpu); void (*synchronize_state)(CPUState *cpu); diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 7e2cb2c571..2a61dfd628 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -255,6 +255,9 @@ bool cpu_has_work(CPUState *cpu) { CPUClass *cc = CPU_GET_CLASS(cpu); + if (cpus_accel->has_work) { + return cpus_accel->has_work(cpu); + } g_assert(cc->has_work); return cc->has_work(cpu); } From patchwork Thu Sep 16 15:29:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512945 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1328129jao; Thu, 16 Sep 2021 08:37:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzyNlqIxAdHwhY6DvBS0u4j+rtfhhSREnOQpu6oKA+le2Ss69Qvzx0X25m3sT1CjVQ76RjF X-Received: by 2002:a05:6130:325:: with SMTP id ay37mr591836uab.88.1631806665645; Thu, 16 Sep 2021 08:37:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806665; cv=none; d=google.com; s=arc-20160816; b=nS+kXUuJm1wmt7V5/pAigeJ5kMq1b2RMF3/ZIOvNxlw95kqycRpjzJtxg5UvArva9W fuxxbjugc17OfA3uHS7YL/mIrrvIJhUfUAgn0W91BWJwGu8TA0VTDZKGpxs0ZSRkymeT KCodLRs+VWbvIYdNARapBWCdzVhsHw8Xbevafl8n0QyDoe32wIJFIueMzmjq/UHqvP5h xr7zos+AsR8vTudgV2dbmtdkrjVg9/K8VIgpSmCBO9V/ngjgh3eUQN7TFsQIxcHZ9N/7 MQmQze+V/+2ObsCFB8RyltcsFPacYUoq2oFnPW5a5G3MefacvxjA30nVAxAjCoArv49+ BmHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OAb8lar0gsn2p9u8wn1vUp6jj9gu5rLadFKsG/mZhGI=; b=FfQxFfSF0Z+2dN5w2dWoluZY3r97dJwxyV6GESr0D24LcNmo8Ky8T0F33XEVRdpyi8 oA94EKAz+saP6CNHnMpIHuR51SJe8UQTwbooZZysBdbIuCPz+/vPqvpNjVEWB3sf+2Sw LE7hq+0tR72QbmzChLdoSx1KOlmVQydMx9lj7rTafpOPP1w0oD5MeCKHnEd894iMIs1E 3BSKiMpfk4ikigvnQf1HcVWWt4+wUfgMedeImT/73LGr97i2bdl78BFTWga+b924eh9N oYFMuFe8V9HR3ryD9bYpMMhc2bf0YZdtNOPWV4MfVuW+l0cCd2U3A5YoaJ8HFaJViuK1 Zihg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCf6s4eR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l14si1590567uar.158.2021.09.16.08.37.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:37:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iCf6s4eR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtSL-0002nW-3u for patch@linaro.org; Thu, 16 Sep 2021 11:37:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLQ-0001F0-C6 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:36 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:41830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLM-0002PL-N3 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:36 -0400 Received: by mail-pl1-x62f.google.com with SMTP id v2so4089174plp.8 for ; Thu, 16 Sep 2021 08:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OAb8lar0gsn2p9u8wn1vUp6jj9gu5rLadFKsG/mZhGI=; b=iCf6s4eRJxBD75pQDp5vtzub8JQjh60bfdnsaGVpJK7PcJdEUQTLvFi/DRrqeCJEil gS61h9B+cCwm+NPCf/XAo6Tw1dU8Hph2STqVGRWJIAckocH7YhUUE5xovXgwi4KHY6s0 rgVBDUUZqErL+Ep1Drji3w52L53FGhnjjJgqHvxqaMJo802wYypk97n+ck6ChhnujcmD cXzt8/n+ifZokIvO5cjXgdJCUhb0nruc6gLMNegT/3+nc6ooAvvlClTgsKH8PE7Wkgkl 1qHeJkpiKpuw4YzU8XXr4SW9vOzm4NqvFAl54ruFQQfiMmykOYpW1iBR9l4bQTRx9pnl d8xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OAb8lar0gsn2p9u8wn1vUp6jj9gu5rLadFKsG/mZhGI=; b=CzGo15JYpzbQvQQ7EXdgbWjHKXAQJpTFIwWGMO4+uoQuv+M3y5wNdjuelm4MvKTdu7 OqgSnQUnBAIiXqANhKdGyKr+bZGfMJ502xVElbhkb1d+b61lFwc7yKkMRgsRwypXi0Pp YhtXrM8AaUuT4yJbfJ6o7vTNSRTLvJyP+QGye0wppMQLRfuLQF1EYGYSkfeNsSnYN39g rZNH6sDYG6X9alRlTiMxjNDEV7gMicDEkZUlcBejmfzh+AUYaQjjNgz/M6R2GDvmxOjw D/28x4Yoj2nNjuIgsrdYe4wLHy1Pcxiaftdzic6Mg7S40gDq40WHAVA3+riREuiT02JY G3KQ== X-Gm-Message-State: AOAM531leo+zbGwVGTtk5rtLJ9NXx2ASab5TK6msR44Si/u5Zqx7X5iS XtBM+sW39k50ezYnde/q7TEkLUwTHrM96Q== X-Received: by 2002:a17:90a:1950:: with SMTP id 16mr6530482pjh.126.1631806230214; Thu, 16 Sep 2021 08:30:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/35] accel/kvm: Implement AccelOpsClass::has_work() Date: Thu, 16 Sep 2021 08:29:56 -0700 Message-Id: <20210916153025.1944763-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Implement KVM has_work() handler in AccelOpsClass and remove it from cpu_thread_is_idle() since cpu_has_work() is already called. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-6-f4bug@amsat.org> Signed-off-by: Richard Henderson --- accel/kvm/kvm-accel-ops.c | 6 ++++++ softmmu/cpus.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 7516c67a3f..6f4d5df3a0 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -74,6 +74,11 @@ static void kvm_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } +static bool kvm_cpu_has_work(CPUState *cpu) +{ + return kvm_halt_in_kernel(); +} + static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); @@ -83,6 +88,7 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = kvm_cpu_synchronize_post_init; ops->synchronize_state = kvm_cpu_synchronize_state; ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; + ops->has_work = kvm_cpu_has_work; } static const TypeInfo kvm_accel_ops_type = { diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 2a61dfd628..3db7bd4eb4 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -90,7 +90,7 @@ bool cpu_thread_is_idle(CPUState *cpu) return true; } if (!cpu->halted || cpu_has_work(cpu) || - kvm_halt_in_kernel() || whpx_apic_in_platform()) { + whpx_apic_in_platform()) { return false; } return true; From patchwork Thu Sep 16 15:29:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512953 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1332467jao; Thu, 16 Sep 2021 08:43:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz49ekKMzvB9kpv/SAv/HaxNDyVlZes4cTX26a88fOE2szUzxdvAjZKxOEP6G44y9kyaz3f X-Received: by 2002:a37:809:: with SMTP id 9mr5535968qki.318.1631806986873; Thu, 16 Sep 2021 08:43:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806986; cv=none; d=google.com; s=arc-20160816; b=bL6k4mtT2YNgm1WsWMeaSALDfLY0bH0vIXQoMqQlhHAt869wzuzd6UX0IMMOc8kj2L aMy5zKz/qSbTtbJ9xRTd0FudzjPHEYxsCyQwMCu7IQzkmGeSJ+/snE9Igwxe1t2vlafL 0zqvpYP07+vb+pQkWVihUl4K7FDqISHSNFzVx6ZQkcP7J3yCJOw6NsjrBrqU5MuDSpMF gSELGvzlcoQydh+2B/7KQzmddKiGWG41LHhvStS6rFhnq1M7FGIiKe0xxlLWE9AWJjjS ON1+nJpEnsZDOHQ1KCHc2/3iBpWBwk1PFmDbEDvDaiAC89BI1puFs2FzNMtXQZJauajH n7Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1ujtoHmWANpUUSk4HPJATTFV4O1b/xtgCUsvKjJvcGw=; b=mNf1DJwdLYoYpXnjJ95dfsdyPlYxdmhzrQ6sirXzu8HRNTDCIGImZ773GmsFl+Tim1 EM/grNsjOqBCXltcTdlBYd8BHYrmLKRMvK8wvlGvd0u0AhGP0FKplh1PXHSTmaVakzQX zmjzcJNoN0CDQKvmVEw8LamLnR6D12VQ3yoC98NixuEYNoak3i+Tsn7GRTrR0GkehiSP aSA7g85Ijf8UGHIOYWTz6TQryLflQVzxoRJ71OV0BX5Mtil8ns4mGxU1p6qSaCqzn9/O t0vjdCNxUO4WhgkvSmEi/6zDxLtwYGoKjNQ3mEPT1KgMZ0MtCMyR3XqJHZN/yQyfAS8x Wvkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d2H+8Hhr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-7-f4bug@amsat.org> Signed-off-by: Richard Henderson --- softmmu/cpus.c | 4 +--- target/i386/whpx/whpx-accel-ops.c | 6 ++++++ 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 3db7bd4eb4..6bce52ce56 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -41,7 +41,6 @@ #include "sysemu/replay.h" #include "sysemu/runstate.h" #include "sysemu/cpu-timers.h" -#include "sysemu/whpx.h" #include "hw/boards.h" #include "hw/hw.h" #include "trace.h" @@ -89,8 +88,7 @@ bool cpu_thread_is_idle(CPUState *cpu) if (cpu_is_stopped(cpu)) { return true; } - if (!cpu->halted || cpu_has_work(cpu) || - whpx_apic_in_platform()) { + if (!cpu->halted || cpu_has_work(cpu)) { return false; } return true; diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-accel-ops.c index 6bc47c5309..1f9c6d52c2 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -83,6 +83,11 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) } } +static bool whpx_cpu_has_work(CPUState *cpu) +{ + return whpx_apic_in_platform(); +} + static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); @@ -94,6 +99,7 @@ static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = whpx_cpu_synchronize_post_init; ops->synchronize_state = whpx_cpu_synchronize_state; ops->synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm; + ops->has_work = whpx_cpu_has_work; } static const TypeInfo whpx_accel_ops_type = { From patchwork Thu Sep 16 15:29:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512939 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1323718jao; Thu, 16 Sep 2021 08:32:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCXivmrYOqyIun+33rNFRJa8RlIKokkGjDUDcyLf3vswH2l4JhsozTUiTBCfueD0XNLDKY X-Received: by 2002:ac8:744e:: with SMTP id h14mr5654243qtr.252.1631806361534; Thu, 16 Sep 2021 08:32:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806361; cv=none; d=google.com; s=arc-20160816; b=d7wc0gWmOLkYTilKexvp05ODTaSqP/LnQPob5H37oVlK+t0Uy07yPgUSjCe8ZMphLH 54j7oAiTezarUHkaI1qjPZF4BM5D/VMgO/21UD8AMo25U+9pfDDK1prTT3ODLwzmyLAB mV/Nh3XJTO5HNH+CaEz6f/CHRnQwjL2+titaGO1oPf7GEuSU5N+1b1xGWCR4V3ABW8o2 JQ+4WX5ZNVbmJ3498csiNLs+P+NCRgwiC0S5magjtL876/y+xPtgMszPC+rzIDDkiifK MvFw1t1qo3nuU0Ap5DvEVFsv36nXhIIAvTD/ROIgUGaUYK4daR503Gyn7iO7XnhBb0MT jkTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+2Hxp80Fi+o3vSY5VLA0rrEE2x+zxZah+yk4DEWnBqQ=; b=g3zkZFC+mtNYNsQ7QDXO4huWMYw36RYMkz0zc9opl332dpDenajbcbrLNMi/Gyqp5Q kOBV+j7BVJI9NdLneH7iupjUsoD7aXYTHwSdIvAixbK/qspyp5rM3cvky6Ll/25heZIQ vqQ3hDll2LSdC2AzKG57UARnJmAN75bd/zUVWIgGusgSapxueXaZ01APCep2FtJqf94q /J++337dFzKG4QM54mzOMKUPjIEU1UhxUx9gi5Pi3IL4wIjwtwqUqKHKDppdsSI897Gc 9v+SaRdRsAbn46jxz6PUIe/xL/H4iUIIpdFYJTRwrgwlX0qaCFsLp/fYe62joxEW7X6j 1/Hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="n/bBt6Fq"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-8-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 4 ++++ accel/tcg/tcg-accel-ops.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 55123cb4d2..4a4c4053e3 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -66,6 +66,10 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU + /** + * @has_work: Callback for checking if there is work to do. + */ + bool (*has_work)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 1a8e8390bd..ed4ebe735f 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,6 +32,7 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" +#include "hw/core/tcg-cpu-ops.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" @@ -73,6 +74,16 @@ int tcg_cpus_exec(CPUState *cpu) return ret; } +static bool tcg_cpu_has_work(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (!cc->tcg_ops->has_work) { + return false; + } + return cc->tcg_ops->has_work(cpu); +} + /* mask must never be zero, except for A20 change call */ void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -108,6 +119,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) ops->kick_vcpu_thread = rr_kick_vcpu_thread; ops->handle_interrupt = tcg_handle_interrupt; } + ops->has_work = tcg_cpu_has_work; } static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) From patchwork Thu Sep 16 15:29:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512950 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1331209jao; Thu, 16 Sep 2021 08:41:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDIPMTB76f0GH2dBvXMKcV+RnQY7Q5sKW6Zh+wJHpL9l/aIEqxDLiJYI6EA54KOcjZIbz+ X-Received: by 2002:a05:6102:2004:: with SMTP id p4mr4644606vsr.27.1631806887719; Thu, 16 Sep 2021 08:41:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806887; cv=none; d=google.com; s=arc-20160816; b=qo7Yq/SBdtNJpsuMCLb+B1vHz/lg6pFG3KNVCfbRDuErgMt2BiE9Qy0y0bKRLSwjaf vEm4eyawt9Ep5JST1X4Wovvod83RWHt9MLZsqnAwDlWGUpyVsFXXvWsd8PmcZADtR/Zd ir60rJ6aMINS7ukh8aT0nxLb2i3pUHIAgb92XkI+SQYV5zYqPd+qF7fMo7UPFRqSjBO6 G+LEVc+U8wug9xx9c8nlGM2EvHNOKiyOhaEYnRvq+bTkJvFBvHI+8quFtAN0VbtFIrSG 5UV324vuspdqlysjjyFTRcGipGpNcYJSOdwOABPZ0FJi8k/SP+ITajyLtc5Ad0Tr61J5 27KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v+sL6u8bXsTKjedcptTkC5TsAqmI7f7iPpsRjw30zQg=; b=HWLiw3uTuEJJ9GObg4mKw3g+4WfhvJKZeqEMyftuHEEO0smEXYcFRbL+9HurZWS0D7 vk7v3iQ+BwbbbUr/BmkDyKd1axJ9UwcKz4Sr68VWVAoEbkyeykJtXXyOf5yKmzMICI0M Kyxzgvz3TzABT4RxO+6JitHwgoU88u+qdtPB46ewT+s6KA5DQMWvpc2DyR+zLf+0mvV1 coEuMzY0xICarvEoRRw7pfZkNLlgymKDjIMmQPC4rd0fdBFY1lqzFOAdlxMZWS96ZPy+ 9Cxrro1Pi5rH/xZXK8m8TJzjN7cDcAJUg4rpOLQzl+Ii0eoCNHRgZG3grojYjEBXMKQp DnAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QE+qMyCS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-9-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 93e16a2ffb..1ca601cac5 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -33,6 +33,7 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +#if !defined(CONFIG_USER_ONLY) static bool alpha_cpu_has_work(CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. @@ -47,6 +48,7 @@ static bool alpha_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_SMP | CPU_INTERRUPT_MCHK); } +#endif /* !CONFIG_USER_ONLY */ static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -221,6 +223,7 @@ static const struct TCGCPUOps alpha_tcg_ops = { .tlb_fill = alpha_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = alpha_cpu_has_work, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, @@ -238,7 +241,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); cc->class_by_name = alpha_cpu_class_by_name; - cc->has_work = alpha_cpu_has_work; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512955 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1333051jao; Thu, 16 Sep 2021 08:43:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwint0nt7qmmFdsPWhqtB2QSMCyBFOw/ihPpu29ocKEufwbzkwocZBagr3Y084Fq2nkW7vZ X-Received: by 2002:a05:620a:79b:: with SMTP id 27mr5644361qka.248.1631807032049; Thu, 16 Sep 2021 08:43:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807032; cv=none; d=google.com; s=arc-20160816; b=Me5bDTdsguGModLfHAPgKmSjuOxpTIZMZCr/HtpzfXZn4GG4pwC5UgDHQchVr1P68W it0LrQKwkdumZSp1H5KQSP5mFEBQcPd1ravHIYmU2ZWjcfYGU1Kxu7htvlLJUwc8WFUW 1nbNHvd7JhZMPXlc+LfJW1QAIazbgYkZUvjI5dRTfCUuYOq7np2JaxHVtKGAqznwC7QL TO0OBaFJg/85nHvYZ3UxU4t7eh/XievHcZn+Foe49vMOPDyNVULV5vHWK1k5LEEvkbdA KKVHHr4pSzCukcldNc/vk8PuN6jFgYl7zxxd7HPPKBhDQDwcgK/krf5Evidv8qDAy/Cd Akag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gP5Ac48Ygfft0H1EsMdA6mk0u3/jlbxiZGs/HX9oV80=; b=tl2TpZM3StjOQPUBh+G/RcT+mop5hHyILsCoFM2xadyPL3IwOlOBO6xvanBexvZhA0 BPB6RuCP1ZfyXetzaRlzrgQbrGfPkVziTgfFQZD8U3aNtQh+Oqk9VAfUIdJWTZavPppS q1+B3tgtXJwgbhLcDFnmkzCGfNSd1eJ4n69HZQwIinBJ3tAy9tMeFbe+4UYRK2KQvhyu hVhD3ImOb9XCezvUuun9u/sO8pVJtfBkXyc1ghewYleuZPRkYWGp5m/kpMwGT7bEYDAr 1SIALJVTBIrus6ktyNm0caSoZUuaB3AtMrU9SCG+tNK6h+hWSLgpaY1XsVGnMDHzTK2E AQpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=reRTrn4Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-10-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ba0741b20e..e11aa625a5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -73,8 +73,8 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, env->regs[15] = tb->pc; } } -#endif /* CONFIG_TCG */ +#ifndef CONFIG_USER_ONLY static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); @@ -85,6 +85,9 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_EXITTB); } +#endif /* !CONFIG_USER_ONLY */ + +#endif /* CONFIG_TCG */ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) @@ -2017,6 +2020,7 @@ static const struct TCGCPUOps arm_tcg_ops = { .debug_excp_handler = arm_debug_excp_handler, #if !defined(CONFIG_USER_ONLY) + .has_work = arm_cpu_has_work, .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, @@ -2041,7 +2045,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; - cc->has_work = arm_cpu_has_work; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->gdb_read_register = arm_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512958 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1335505jao; Thu, 16 Sep 2021 08:46:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZ1IL3T5ZVOoDAMba11XJoiFC/qjokLchgs/CcbSCBMEAqGXMKTzRzxeyc9BiydL0aKKHZ X-Received: by 2002:ac8:18d:: with SMTP id x13mr5556019qtf.301.1631807201713; Thu, 16 Sep 2021 08:46:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807201; cv=none; d=google.com; s=arc-20160816; b=o46NI9Gp2nUI0ibGY6a56enjyPvMlSZ0xpZt1yJUZHKaXuS4Cqm5ywo4Ff88gOrnNc NxyYK1cfNTFwnK8O7OIujS2xRf41kvaO3tIWn7U1ugsO20KZ5ciRiqgVhAWVHR73Xgf6 bFRpDxKb4NGjq2wyODOyAS9DW71XGmaZquRcF2kG3pP7EyqqtxLwLl5xTLm2I4k6Taw4 nRA3HilOheQNj10Q6DQRtDzBboAd8r+4FWGsvNvqS37mJ96yztfQ6X3UMMGQJXhZuiNv Rlg7wnL57GIO/Ltgc85t2jWxdkWnFQWQ2hcSHevICEFN/z6fWAQvYhKi1t09SJ0kJ47Z Plhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dwPWLEp4Zz1Osmk2eBXqla8Z9DrCfYKS2P2ajgRsNfc=; b=O94jdoD54K56+OqJjI8vlgX1PXVKfCI3zkh9WAtEw0sK0NuEXbfnNSnYNJ1fJxKgEq kAEewr+/BkHdOFGr06GYzvHk/wr8Rm5kJT9Xkyksbzl0GwxUboWgKeUy5rqCsFbZ9/rV wmQkhG1a4PB+o8YlHT8LzTH3kpc3PbiyRyeEhaMCz9UjO7u6+mIikZKfgabK2eJQAL1C EnPoGam62KnOMyj/TsvDipsoV92M2D9fboePtxuJbfImsnhSuwJMB2xmS2vclNl5Js9s JdEIu8b6HUGnHwmrDEgBGaGYdsCGu+Ex9aAswnXYTHKe3q1NBA7JjyLjEvmMdFHqDEL1 yQ3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="N7/sGb/h"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-11-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d70e34dd5..6d51f91ca2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -195,6 +195,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { static const struct TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, .synchronize_from_tb = avr_cpu_synchronize_from_tb, + .has_work = avr_cpu_has_work, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .tlb_fill = avr_cpu_tlb_fill, .do_interrupt = avr_cpu_do_interrupt, @@ -211,7 +212,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = avr_cpu_class_by_name; - cc->has_work = avr_cpu_has_work; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; cc->memory_rw_debug = avr_cpu_memory_rw_debug; From patchwork Thu Sep 16 15:30:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512963 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1338174jao; Thu, 16 Sep 2021 08:50:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxv+y5rOLY/4e8pfHuQLuxYoZquoGr95ofbK/88zSGmCoU66yO1e2DfTaxM8JvOzPRrUT12 X-Received: by 2002:a05:620a:4ed:: with SMTP id b13mr5866891qkh.26.1631807404209; Thu, 16 Sep 2021 08:50:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807404; cv=none; d=google.com; s=arc-20160816; b=Mfq+9vC0hIu/SPOHJJCnQOYNnpWqX4XDU8lI5qcKbiDU4v8rwJiD+4Rwz8UC/ZYswL Dc3IMJU9RpDu5PCcV6Onj/mzcli2JcI17bVrdt1QHajK9i7e/6Z/tTE6qqpgxsmHJ5NN JHdyByu/8QeQ65Kj5My4ie5+wZLuIg0Hd8JZJ0oqu+1BZ45aOqR8N9Pn0s/nuS1sulOW kA2cq6lrrV/LeiwrViA6HzhTAsxByYKzN+9rbTzwjvfFjPxXyvlNDn2oGp68+FNB/5Hy S8dm61lkgE7CfGqLl8YuVgTLoeNSO0sWMDh+zidYrKFo1cBUsWp4QQVSO5s2PckyJNrY TXuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M/fz3nm2YLKytQPDTi7ONHRlfHiXRDVxp1klTgoeiA4=; b=vMJUYLVhZJzaRI9ywkc6TGO6d0opPqA7ZC6FsGam2ZRp3Wb4YDT5oYVfIXNml2uV/G svjolh8TzX44sCOOPGKQzUk8K2XCxU2NhKPPkuVzJ6Aqy1X8Xo91Ardq1C1xrB3EGusH uhn94uDG5BpFm8oEFx5IxCisb6kIOejQvg3w5IlCOgDjmq+zuurp7/BKkjBUqA3l5HGy lY4TRoWe7xHLFMT8AGetSUh7pc+xQGJRaotht9oGtJN+YZzjGaeHtEtu0WfAohmSgZ9d xZcm33WX+dloijBEd/8m8RstKVgzUbiFTRg9a9p5GBm5BjJNY5s5MWgZAJV1fpJqb5Nx a8Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RCzKU9Ey; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-12-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/cris/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5b..b9f30ba58f 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -35,10 +35,12 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +#if !defined(CONFIG_USER_ONLY) static bool cris_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +#endif /* !CONFIG_USER_ONLY */ static void cris_cpu_reset(DeviceState *dev) { @@ -208,6 +210,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = { .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = cris_cpu_has_work, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -294,7 +297,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); cc->class_by_name = cris_cpu_class_by_name; - cc->has_work = cris_cpu_has_work; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512959 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1336186jao; Thu, 16 Sep 2021 08:47:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHANbKuCbXnz6TMSPsKYD+Fizdxswz50yKADChHNwDpIvJJ8MQYvQcSzLiC3iP4Q8eY89l X-Received: by 2002:ac8:4149:: with SMTP id e9mr5517341qtm.106.1631807257550; Thu, 16 Sep 2021 08:47:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807257; cv=none; d=google.com; s=arc-20160816; b=b+yWAnGXCpQtYqMBiriOUPQXyt3UeVrR9oixTTcw3Y4hDylMBU/aCCDZplyIxtXW16 mDRFEBL9sWa34LnhKHZjuBknp6K9gbbsV58FlNczrYAWdq66z1uSFmkiMNTb4mLCubRb 39lOGdndLKd+q/ImWg9f+aXnw6AYrv1EEFvRMGW91p9m6y2YlF+GumhruCVzKXVJTzmf kckETwGsp6x/4jpHHygxKU+U3NUQA9yQyvRn8l3IrFBNSQwW97kMJrCPxSXdil+em60R 6tJ/iwVfD3kli4cym9LG2uI/Dqw0qNDW+JHrX5JT1dm4jwEhCP5SbLRkTWGKzBPrqMqC NVAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jAI1XCWGYN+pfAsCZFTEnAEoAetKy0IcJx6ab0+wDcg=; b=0yEmQPkUlvXl/d1GvlkLZYLWQ5Rm/3CTJn4JA6h5VhvhZLJ8VIUplIT1KVYBjJ/gvZ 5pBg5IkZiZL+qSydGzMSLZdEQGSfIUgiPQujCPWxopQPa73dPNqIrI2uTVWSMC01uXEJ py12Xv8vDy52G0/UwoluepokmjAdf8HUURl/GUBysg9jk8uPX5PKWjYk251pSO3INPzX CkNhQueaLbKyx1htFEl5lgF3Wl9ba9SjIjhXTtcIhrR+Fnj5aSFdI0W5uA8rbgyTOXbD XBHTEudos+TJIVMeR2ATS7LqJ9pMSkRe/pNwFCNFazbynC7DR3twU2LEnsHhcfbpiyU2 Bmag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TBdmkxtq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m19si1923387qtk.426.2021.09.16.08.47.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:47:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TBdmkxtq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtbs-00059M-Pz for patch@linaro.org; Thu, 16 Sep 2021 11:47:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLV-0001Ni-Oj for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:41 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:42516) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLQ-0002Sr-Qb for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:41 -0400 Received: by mail-pl1-x631.google.com with SMTP id n4so4081699plh.9 for ; Thu, 16 Sep 2021 08:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jAI1XCWGYN+pfAsCZFTEnAEoAetKy0IcJx6ab0+wDcg=; b=TBdmkxtq2CIedgYBkpubctNylv4K0FRXEIb4ZxzRTzQKYTi0ngXTmpFYUGCYF2SgND lZ6pf0mdlihvz+Ui2y9nFtkCcYL/IoAlkm94/n2ZcRHnoVMFD1aiBcPy53RnHzvPgmay z1i7WzW4yfNvFxIyx4qmBdL6CpqV55O83Qzr4Pa5VrsTkz7vLnm0eyLuuIrFX/3X5Frr 2UgCYZFhs99GyAEE1PEnVSe9YaEiumcitP3hOfmne0eb46tJVbSOoRDAwMYfS6okmDwL hyK0gsa+2KF1flFx81DTd2tEK3kemS6Ft6cRpPuUiLnRg/w27jFtVumM3UfiL/eQ7WBU dE+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jAI1XCWGYN+pfAsCZFTEnAEoAetKy0IcJx6ab0+wDcg=; b=LANVUyiVtxCXeIo8a7OIsY7JFAjfMNBo46m/miq5hylJnPlvSWpz3FeDTKxK4QlLby Dpb44+cy4xjXPGy3BrBuA6nDCiP1AEZK5+8BtKLu9NafGXwUH/fb9ZTzDBjXhHWiuXVy inCfJYzv6Mw/h1ENPRXfQHe1BLK2r8VMd92p2CV27Dzb6cS7BRavJAqRYUWCRXh2QIBX oL+d6RRan8d+wElmd1YeZSk717WLn0gKIVkV9rtHqdGuIcGVyVI6DJpE8dRPgUEA6V30 +VnMCLLng66E4UYkjF3b4tZigkmcrNnQKKdW1/ZVAwbzQu2JxPLxlUESP/8mA76N0VL6 02gA== X-Gm-Message-State: AOAM531IgZkJGDCfHNIWrPvpAfqHblSNexhhzYi6d3dwWgDoqRspvr9o JDbkcQVGD7aqb/XPSnsJapiUIKS/AfUJKg== X-Received: by 2002:a17:90a:e7cd:: with SMTP id kb13mr5262807pjb.52.1631806235338; Thu, 16 Sep 2021 08:30:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/35] target/hexagon: Remove unused has_work() handler Date: Thu, 16 Sep 2021 08:30:03 -0700 Message-Id: <20210916153025.1944763-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé has_work() is sysemu specific, and Hexagon target only provides a linux-user implementation. Remove the unused hexagon_cpu_has_work(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-13-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/hexagon/cpu.c | 6 ------ 1 file changed, 6 deletions(-) -- 2.25.1 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3338365c16..aa01974807 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -189,11 +189,6 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs, env->gpr[HEX_REG_PC] = tb->pc; } -static bool hexagon_cpu_has_work(CPUState *cs) -{ - return true; -} - void restore_state_to_opc(CPUHexagonState *env, TranslationBlock *tb, target_ulong *data) { @@ -287,7 +282,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset); cc->class_by_name = hexagon_cpu_class_by_name; - cc->has_work = hexagon_cpu_has_work; cc->dump_state = hexagon_dump_state; cc->set_pc = hexagon_cpu_set_pc; cc->gdb_read_register = hexagon_gdb_read_register; From patchwork Thu Sep 16 15:30:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512948 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1329282jao; Thu, 16 Sep 2021 08:39:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzDHCdwDoffi/leSSoPGs+wZ4sISrqHY/lYPGDTK/ZmbQU4ItJDCGD4GwiMN9lTAcdiI3ZU X-Received: by 2002:a67:1087:: with SMTP id 129mr4310832vsq.60.1631806749822; Thu, 16 Sep 2021 08:39:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806749; cv=none; d=google.com; s=arc-20160816; b=PUTtMCwEBywfPkiS8mYSGZ+AmJ/JElSdwavBgIcbfHsK8AKFfMW4TAE7JKjUyX0xlZ ALXGT077ENklHkSFzVMt4vvS+bv3zBr4kPy5wNVBgTuurHfeEZcP2qyj8DbYoLdWhfdN 8JWaZsJZOx5USJjoBr6yt9cIGR2s/LPxObU6pcuJnQWWedUDrEl3QyC5u/7h6uqMb2HR Tp/TfGeA0FDzCWL+sjlq1WzOjWGeG/rMJ1hqva0TM4XfckKhczm+Ul5pcKvR246Hrw4B iO4YIkP81zQ8RC0eQIVo8wtvxHes+52Ax3/uF+jmMDUOtB8p8DPesFatZyNQ9czUrZLp DS4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ePy6aN6lFva1+oLoEnr79Yb8aPoSMIJ8GBwpmOsa/Yg=; b=V2z2oVJ7JRGfsXjXI7zBWH75/CRI9f6vTtwQIaVl8coaCRYkD0ZVE/7F4HNuhZwbwt R/JbQEm5/G01X2YGzvMDBnXwicvxuYmPmcL+QneCJsJF+hbUHWLmqHt/aTeUH2LD5zKj JQQm1bBm2SBy3UmLy768YUyOLk4GWnac47+EOI1yuOWwxQYusGBe7XnnDtBN+0q0ttPL 3l1R8BS64Yqfb2rX5eIxtgzxbYCWGp0XuV0ykScmbUP07yh1H7ZV3avr7mZY/fVUEz/M u5q9EXFvizUTU4sYZumzgHIxBE3XhXSgJbZ8r9sOCXRX+mZR3UvMfUof1WvrjDEbAMBu GFUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zM61HbEk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-14-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e8edd189bf..be940ae224 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -60,10 +60,12 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, cpu->env.psw_n = (tb->flags & PSW_N) != 0; } +#if !defined(CONFIG_USER_ONLY) static bool hppa_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; } +#endif /* !CONFIG_USER_ONLY */ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { @@ -147,6 +149,7 @@ static const struct TCGCPUOps hppa_tcg_ops = { .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = hppa_cpu_has_work, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, @@ -163,7 +166,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); cc->class_by_name = hppa_cpu_class_by_name; - cc->has_work = hppa_cpu_has_work; cc->dump_state = hppa_cpu_dump_state; cc->set_pc = hppa_cpu_set_pc; cc->gdb_read_register = hppa_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512962 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1337556jao; Thu, 16 Sep 2021 08:49:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxf3zLLJ3DrKsMjMU4lS/DgX2a2zO56rfEHb0zRKApZ4jwu2skTxQa7j6hcoCVCF+09fmqs X-Received: by 2002:a0c:8064:: with SMTP id 91mr6116592qva.66.1631807359613; Thu, 16 Sep 2021 08:49:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807359; cv=none; d=google.com; s=arc-20160816; b=dfb8o7gNEb0LcxmAYmbCXrG7Jqze/kQi0njUFWaXbf5P9qvEBsYm4fLlcmPwLdQI/r yXElA9Pe4kyNMARE5BukOwspYBewrgUPlsuPrpIDVAzLD0DLcQ4+b6TJ1Pk/qFbOmI7z ailI/EgKTQWoapV8obKSchn/hGNobCHpmlUG/mLKItYa1l6qjQEslTPEY0sBgg6Siui2 rh0MKz76mmYggtEkHsMqd7L7N0pXbJMW2ig64rX3ymyETKcC4FT5gKKSsHSL2rLfrjNz eW7ZUUxgJFnDApnvz7wrzUG1RPkgNCnG4okgv4uQAHl6eTJlacA8uYRGcRrz4yNGLXgj Ecew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lXET+xYBNc1lxlyCwf5bn3A4DBRHEif1uqzxMzBFnFs=; b=k4aQZT6JU4xlFPEa0wZGxOVEVSALilm6NEWz3U1AW2UaTda0GUEiZoh+v5ADB6DiaL tOrISylY2LGpUY14VIfaW4ZZpYJ12AZTPgFGVkxfgzzOKVrSKJI/RS0gSJ0d+q40hnt6 347YIjY6lhJbTY0uVXU2Ovbyi/o2UiAqQPuI/+E5JKxv8gv5EFjqfzHJCYvunpVi1BZ+ LtOodeSeOIxYqVAQvag6g/90Bo8lfAfbUngmkS36q5UszS67szEMSgTl+kMAqZNahp7F lX6XFFgEaneHKPin5mxZVy2e7Ea4VLbElltMqH5VRkYiArveD3d3QoR2B9rj5fhc4Acy 0EEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q2M6igR1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-15-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/i386/cpu.c | 6 ------ target/i386/tcg/tcg-cpu.c | 8 +++++++- 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6b029f1bdf..36a1c5f3fd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6554,11 +6554,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) return 0; } -static bool x86_cpu_has_work(CPUState *cs) -{ - return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu = X86_CPU(cs); @@ -6763,7 +6758,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->class_by_name = x86_cpu_class_by_name; cc->parse_features = x86_cpu_parse_featurestr; - cc->has_work = x86_cpu_has_work; cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->gdb_read_register = x86_cpu_gdb_read_register; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3ecfae34cb..aef050d089 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -55,6 +55,11 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, } #ifndef CONFIG_USER_ONLY +static bool x86_cpu_has_work(CPUState *cs) +{ + return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; +} + static bool x86_debug_check_breakpoint(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); @@ -63,7 +68,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) /* RF disables all architectural breakpoints. */ return !(env->eflags & RF_MASK); } -#endif +#endif /* CONFIG_USER_ONLY */ #include "hw/core/tcg-cpu-ops.h" @@ -76,6 +81,7 @@ static const struct TCGCPUOps x86_tcg_ops = { #ifdef CONFIG_USER_ONLY .fake_user_interrupt = x86_cpu_do_interrupt, #else + .has_work = x86_cpu_has_work, .do_interrupt = x86_cpu_do_interrupt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler, From patchwork Thu Sep 16 15:30:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512966 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1341228jao; Thu, 16 Sep 2021 08:53:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyXpDKBcNoe/omXTZCZbdMPB2TQzs0Qe6hmZ/pndbGEgwmXJIPe0G3Z39k6kGdQtiSpj5Io X-Received: by 2002:ac8:568f:: with SMTP id h15mr252735qta.318.1631807628427; Thu, 16 Sep 2021 08:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807628; cv=none; d=google.com; s=arc-20160816; b=a94pUYGrIt4YEIHtSS1zx/ptuW/gAr4M4yo5D9hY8I9TNkVzkQscqyWrg6AuVPs7cZ RQbPO/dai3kYfCu+obqqGYIc8TBdUC+4Ca6mQAjlquzWNhFQ5fdDj5tjMqsDFiluD8Sj u+B1JlC3jDYkxZdI/M7noXCBOJkkUWtf6xc68x4dBwCQtU1DRVWqjKRaNJ7hLGZjFA7w wO1BYpBkHW59k3cFCCNNJPAZuWAUSXmsqYuz68HLykP+z8wLYT4ss6hqbsIQMl55m3i+ C4Eckh8hk30qL5frSD2Bvg45nuZ2LnMN19MlI2YmZIu0e1FaLvV62cq5MKLN+11ZBDY0 SX/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LMAaN3fIk1+CGVDUh2TqRwq0ThOKp39rivwNuMj/4tA=; b=Q9NiAlvq5IDTlxJ/xFLHB1hfRXBHc0QLGyVOqIo/Hb0BQouTsgcCScUyxJbCZrdtva CgtWEMN388ptXFU1JwrtnraT7n0vj1C3cg0LvlMMfgoyIzim4+stnF2cSMaW5ErGHcoz fQUn2Wa+dLBcSF24eYGvndvIV+cXtdOp/gmgpmFBcmfKaiSpp0APnGPEdPZ7qL1va6JF rFlSwNWsAHp4hzfMZdozrxXNtkmzqigD6Ch8hY1G9mqjxW6ScNbgyJZDzCdFr3FszntO 7dNvonu1EHnjYhvnvme9VtAhPKZdDpvjiq69vSS/DQJv13gZgWUjtjJ4AkWEY8RmPkXf D/BQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RAa9NDJM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-16-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 66d22d1189..ad5d26b5c9 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -31,10 +31,12 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +#if !defined(CONFIG_USER_ONLY) static bool m68k_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; } +#endif /* !CONFIG_USER_ONLY */ static void m68k_set_feature(CPUM68KState *env, int feature) { @@ -518,6 +520,7 @@ static const struct TCGCPUOps m68k_tcg_ops = { .tlb_fill = m68k_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = m68k_cpu_has_work, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, @@ -535,7 +538,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); cc->class_by_name = m68k_cpu_class_by_name; - cc->has_work = m68k_cpu_has_work; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512947 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1328994jao; Thu, 16 Sep 2021 08:38:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFkNI7P+MO0y1svPozzU51okSAdqmf+Hu/n1tuyqX9t5Y1/E8cOtj+kKf/HSEMhhNcK0+1 X-Received: by 2002:a05:6102:34b:: with SMTP id e11mr4568465vsa.22.1631806726782; Thu, 16 Sep 2021 08:38:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806726; cv=none; d=google.com; s=arc-20160816; b=nwdMCXo014uApY8TuoJGNVEmrdUCjr4LK4dj0TMMFhgwjrLXYR5bN3GuClhxYMmUWJ CJaoJmTw6i9Hp7IAPJhvtu9wyRU/lemG4lobQbRD+ZXiLilXzBAsJMFwhDz2byreEmPF prGihX1a1Q7msx1y0lkAzTNW6baPTDQ/51pvZcM0+bbg0lH88Rp4ykDeR0xZFjgyA4OM R0zkDoMFnj6kOsUHdUGjYB/cyD2qmFPlRWxUL3UHiVDpwgsQPBK2XUOyBOOoI+8Wxxyw 2/RNNL8oRTUhZ1y243LuGTsJLN3KPw0vJbGAu4uUFB+YsQlRQvqsS0IZ7LEU+zlEPV7p QP8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=B7rWuZpn/SMFqm/jKpkO+UpJH/x3OABwCOd9KRMVg2I=; b=k6gofVgSzXoNxWLZAbWpjB3zHUa7QjXmp3uF0xkuMfc+y/4yiAbx4Rj3GbIiryo/s2 rUB1mmmQTdAyPjNGn2RcCcVY9Zrr5SpeiUD+zEc0X54voFOLNSTX/euqShjxEBX2fRzh 2mIfT1SnszJqrpGsFEm4yLEd6adoBliONprRw3GBe5jsa43WLGPVE5lBBOiTJebvypsm 2qccVNPLJVCmp5dMwKDGbCxs/xjwCAKM9+Cy61VHv0/PIvGFb6rWtI8H9tkBCqflTL9U D6J1rdTZ6uRsSDWY6d2hbOJ+t0NbVB7BvSTOukgazANfSuE3JUgp+LQdZ01C4b0JdQzY khkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SJc92Y7D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-17-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/microblaze/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925..36e6e54048 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -92,12 +92,13 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } +#ifndef CONFIG_USER_ONLY + static bool mb_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -#ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { MicroBlazeCPU *cpu = opaque; @@ -142,7 +143,7 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) cpu_reset_interrupt(cs, type); } } -#endif +#endif /* !CONFIG_USER_ONLY */ static void mb_cpu_reset(DeviceState *dev) { @@ -368,6 +369,7 @@ static const struct TCGCPUOps mb_tcg_ops = { .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = mb_cpu_has_work, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, @@ -386,8 +388,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; - cc->has_work = mb_cpu_has_work; - cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512952 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1332025jao; Thu, 16 Sep 2021 08:42:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxAvHXWt9XmToLALK+0ofE8Ma/+ZUtQ/Q3iC6pLRDM7pFe6fOAhCJFhjDauZfF3WM0CK7os X-Received: by 2002:ac8:6bd0:: with SMTP id b16mr5779472qtt.375.1631806951483; Thu, 16 Sep 2021 08:42:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806951; cv=none; d=google.com; s=arc-20160816; b=gIschVtSKQEC1hYuaLbwKXqf0RU5VbjpYLCgfJswc46y3Z/FUi1qKNgE9dCuLk6y19 fv02gVHMTEfShO5R1PrelhNn51ZAr31ZGVnGp5+8cTMAZOd/9q1E1FOLN+ZPxBrD+t7p q06q+OAy4TVODacxOMeVUTdPzaguGvJEOzgNKdYp8ylx4OktuE+y46a06NL4re3d4UK+ BOK6Y3ERrQ6cPQQkSXb9XLe8bkFo5Ly5RaM6JVD7UQycHSqISl+cerA3d6lcx0kCn0I0 B2wo3G2qAE4MSJXjWCubXpZAaCLLundJ5KsKuTEKm1aBv6XiqvU7x68a8M7fqAOFEk9u a5Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lL5fiNGlIY2Cx7URLhUqVO158bdYKQAqHd9ebRpcjXE=; b=pkToCkWZ/9IpFtf/fmmkpBRUUYErZT8AsbrqkEMuZS2tYDhJuDTXV9XQLT3xIGFH1w wguScU5IItA8Q0TCd3QWQfvPzy/Inae+/gNUuQVTmjSpGushEA5LPIGX1v/0zq7YoWVb N1XfDgFCwaCwCRI/ciV/5p4uVjLUsfxryB9OocHfyy4qd6NMnvWM9OiwTzvHumRp1QsB hPWdZJLmL9u9Fl9QrYvHopWWh9cIoQj3jWiOc6tv1zP6Fxz7rK6PdBKyiH354O4tJmjC 3MdpqXeTJ6uPx4+icREHbqlv8larloPcjEJ8fJpz3dhYUXGNOqr77Hvptvawhb228z7a UEEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I482VBxo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-18-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/mips/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e..3639c03f8e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -128,6 +128,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_env_set_pc(&cpu->env, value); } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -172,6 +173,7 @@ static bool mips_cpu_has_work(CPUState *cs) } return has_work; } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #include "cpu-defs.c.inc" @@ -542,6 +544,7 @@ static const struct TCGCPUOps mips_tcg_ops = { .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .has_work = mips_cpu_has_work, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, @@ -563,7 +566,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, mips_cpu_properties); cc->class_by_name = mips_cpu_class_by_name; - cc->has_work = mips_cpu_has_work; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->gdb_read_register = mips_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512943 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1327027jao; Thu, 16 Sep 2021 08:36:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyn5a1DnViyAfveN2uR5WajbYGjM2mMzRugBN2GKfma5QIo2QjlfwGG/RhlZH/7OJRhh420 X-Received: by 2002:a37:90b:: with SMTP id 11mr5601548qkj.419.1631806593991; Thu, 16 Sep 2021 08:36:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806593; cv=none; d=google.com; s=arc-20160816; b=kh90rtTK/f8ae12KEg0k+kv4OBouNhXLwJpZNbj3WwKIYPFYRUU6fmyoYgVDS0cVpT +C2GbiEKUStIfu3H6Z51kUBUjuLiQnm6HhfjYd8VjMLVYLhMmn5g0yniBSrYUrl2ULqh 0PqATuqVjPohVDLfH3Ao8aWLg2lOycYHO1B5UDSZwFLE4HVAgk6FilANd0jR/QTTV1tp LxQosOGvkyiczpg655Q+BiPTQK9YYp/pOqhh6lMyzsQMsYH6eKsSGx5TBFZFmLZB3PIr cUGdm2MphdCanmuUYgywCHwte5Gon7IACkm5Xa2m3KuUuXEECbLBMS26FLZxzvLTC+FM 7Kww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zQBj6R6mNHBuNIdCp6TRGb9J98g6c/du643Q8y+hiXM=; b=PTX7o+5HfTaEL4THfQTc6v64kP4wFz6AAgrMGVyCIG59w1VlaoBGs53KeUtqDj92lc 4Qhu6skybJeuYUEGoSJUKNFZjCYLMagokgs9xhCgAqABZG3xET3ylo1zG+PLkkc7/sQA Gzb67+mh8ll+jhHKmLFVWEZ6tOs5xO604PEaNyIEzTlr4ljiAb26domnNoE0uZL8+QJt 8djWAn9Z7bkIIGCw+YKAN4YhAO8zEQV1GKYB5LgCeEKTooxVg6Phiszh+7xMFwQfIoLL AIMXMxi1+xFVRDCqY5sR1iotSdLsNi+oDTGwT6/X6kwCf74iD8xOId8ktdqquGs6/G8d aPdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LfnWUeN+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-19-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 947bb09bc1..9938d7c291 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -34,10 +34,12 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) env->regs[R_PC] = value; } +#if !defined(CONFIG_USER_ONLY) static bool nios2_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +#endif /* !CONFIG_USER_ONLY */ static void nios2_cpu_reset(DeviceState *dev) { @@ -223,6 +225,7 @@ static const struct TCGCPUOps nios2_tcg_ops = { .tlb_fill = nios2_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = nios2_cpu_has_work, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, @@ -241,7 +244,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; - cc->has_work = nios2_cpu_has_work; cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info; From patchwork Thu Sep 16 15:30:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512957 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1334096jao; Thu, 16 Sep 2021 08:45:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFRCUUS7qRnLg+CyPxcyZrjNd165XQD1iY0azrit3O7WQdLVuV5flnlNJoCip4ac0nTfic X-Received: by 2002:a05:6214:3e1:: with SMTP id cf1mr6023180qvb.43.1631807102628; Thu, 16 Sep 2021 08:45:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807102; cv=none; d=google.com; s=arc-20160816; b=IgwsvXELTY1EgrYTapEKHJYKixYykPTOr3UHN6y7/pPoakX8nRQc4vZW3CBdvQI6bw xawsm4Qu2h0RwdefPlZHGsR2uNYAXB8v6WrgeMtHp+koseBtXItrPYXKdxtpuCnHmvJC /zPnK7mMOIzCvkbJYo1CUAkZer2XD+6YJEuRHF5TYpjQxM6schqFgbdhbT5q1vk3giqi 1s8Y/KkG5POeK5qLgoa5fLNhXkhxT7MX75yU8k8Wg8OnGedqS7Mc4RU61IdtNF8oEUpA +FO9VpLwVLzyySaJw+cYXPXXWZ4GbU6IBJT5QBe3gCGpzpe/zFeAnYkcaGRjXoglwMHm cMZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r/Nt2deQEM4uyDo8RGvA8xthDggEvZqmw8YagLLQ3b4=; b=sIr1uPVz95umwZ959/O7HTcaJjfzagEubXdExHtBmUdB+7M81UvMQpsEIjyGmhhO84 qdlxUXgKuOXdqqU5efzHgtT98TpCI8FJcJHagHT7Pzybp38wloWsIgrO2RmWjTweVrs8 U4SWHutFp5mMRr+1nvPgp1PbqtRO1fXFeBMjJC/kcORV/uXVddNPXJ4RLXxLs/ROK6ZU K13+wUBZ0GM1BZ41XYmrndhhRFMLbJHsOyh0Qnbdg8Xjae4QlR9/P2q1yijLlb8D2q3M DXhqGbam9ycZ34XCfWEpnIOTUpwNlrC2P7h9GbUYzr3P1dCo4ZPG/bfZj0+EVlrXOMdp UGwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lv7yyag9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a18si1848737qtg.207.2021.09.16.08.45.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:45:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lv7yyag9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtZN-0001eB-Uy for patch@linaro.org; Thu, 16 Sep 2021 11:45:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLi-0001Xr-Ou for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:55 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:44854) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLW-0002Yv-6P for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:51 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d18so4069185pll.11 for ; Thu, 16 Sep 2021 08:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r/Nt2deQEM4uyDo8RGvA8xthDggEvZqmw8YagLLQ3b4=; b=Lv7yyag9vyK2KwngmY71nt8wdxIxgWbE6/azJy29oWMPBqczh34W4989gx77LkvhwV RFdnfgjt/Qnu1NBvk8l77/I2/EU6YkZedrxPg5z3sH0LxPHOCTllQeBcVaxXTY6q5llB zIHz6WNhaBPCy0H+6EAfRUKT/YyCSFy+fsZfKdXfu+EuajaD90aOatyteMyA6LNAhyk3 3g83/jm5WQHY1aYbRBmgbUkQLiOu7MheXfnsMcakmKnQv8x18+XaxBhVIcfeT45YA8yh dh5j1PEmJImqMYSOegDd94cgxrTirRowX8hb70P7P70wdNIupr+fUbi+8bDFKbr/zLIs o0og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r/Nt2deQEM4uyDo8RGvA8xthDggEvZqmw8YagLLQ3b4=; b=XmvWTkJA7h/RNaBo6fOSkImqDns6aGPpx+9zxyENU9deQaLPY9rJlltpyjrJdZLUpb IDWELT/GswzjrSWW8vv79KPGRF2GdKlfAl1EDrIX0TCwB78MYKaxmX4ScFv9SxcKccre ZH5oQ2sL8HV885RKkTu0vm05tnNCwyrVypKHg9YQQBYRnpuO0nhtjjPQa6oDv0S6jylP +klHOtHwRJZPNNgQLm/vseeOGB8IZTlCEtvhgDN7RdJF63/NfJAMMzlR29j2rB3XB44L 8UuQz7DAzoNnFo0SxS50i+MqTxjsRs9g62fQVktieMEf1c8I3EogNRMhUNa17KTHRdqM De0w== X-Gm-Message-State: AOAM531RH+ECFdFZgznbXvx4Nstsl9WtKLFJBx7ZMuWHXrss/7RX/D9y k1xIB6QIarrxeZRtiarEtM/fThZEPSXwMw== X-Received: by 2002:a17:90a:301:: with SMTP id 1mr6762410pje.65.1631806240255; Thu, 16 Sep 2021 08:30:40 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/35] target/openrisc: Restrict has_work() handler to sysemu Date: Thu, 16 Sep 2021 08:30:10 -0700 Message-Id: <20210916153025.1944763-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Restrict has_work() to sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-20-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f..3c368a1bde 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -30,11 +30,13 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.dflag = 0; } +#if !defined(CONFIG_USER_ONLY) static bool openrisc_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER); } +#endif /* !CONFIG_USER_ONLY */ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -189,6 +191,7 @@ static const struct TCGCPUOps openrisc_tcg_ops = { .tlb_fill = openrisc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = openrisc_cpu_has_work, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -205,7 +208,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); cc->class_by_name = openrisc_cpu_class_by_name; - cc->has_work = openrisc_cpu_has_work; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512951 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1331638jao; Thu, 16 Sep 2021 08:41:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwixQP96ignTE+T99muHs7act8yoOOXs31WSl1CU7hCA7zYleIdVuOM1wAsXsqQUmoWteTr X-Received: by 2002:a05:620a:941:: with SMTP id w1mr5528355qkw.434.1631806918218; Thu, 16 Sep 2021 08:41:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631806918; cv=none; d=google.com; s=arc-20160816; b=rALHdAsKu7hzVqqH+M+8yxU5G0keaGMIZbj3Dh9Zmyf77E19y0YYSjJiepX82Jf10R WcC0R1u4mOL906CUOcZaT8UnJZ1oth6hgiRAoOvIvhWchm9lRKK2479BZQhtyXyUpuCn VRbfG8rblqkxBIfEfztosizUgccO5CMSf5xNBriyTjv4iICmHWS22zTEsO5lnzcNVXOm J4alAv7DxjEMdSm3d96Vu9wjHdOBBdJ17dk3O26lu8OW2NGDYZyZx4me9/lgukTbC/cw XD6FNhBGf6dX+BBYW2E2F1OJ01yssQByO1wT6HddDQjxTol7O/2wDAxyaXbxUHCKpePD zvfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=R7BRXEWvxWUGmwl0JiVhEapCxr/L2l4nPcG0jEXDrDU=; b=Y7LzcosRdwrtad2rYtpRpS/I6zCWo5j7q3IJ3t9kbXWHl9aVyIU6lsVvHOdi2IvTSi Lw/G9eBVT39HBq9EGAKAxZ2qO4p+eJhxlCUQYRvHM76BuV8gqBcZoCdBp3pLQKAbnLeA G89aYEPq4BeOAPS47x/zBdV6TF9En5LCj7LtwuWaTEB9WcqWHm8VOr4f9RMl2LUGnIr7 iHJBqzXfEpNOUZB22b8tIq3Xsi5f8W6a4tEg5cU0+PnokwOd7JqLRmNu4wtONrDYwMfm teW2zU6PEJR5nhB2nCK4Iq9txhksD4gk5cbL7EKkq4SHT2m6wC7cTCrFfl1EbkoYijBW r4Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ILll7l8l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jv8si2029694qvb.131.2021.09.16.08.41.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:41:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ILll7l8l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtWP-0002t4-Jj for patch@linaro.org; Thu, 16 Sep 2021 11:41:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLk-0001Zm-4H for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:56 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:43605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLY-0002ZA-KX for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:52 -0400 Received: by mail-pg1-x52b.google.com with SMTP id r2so6474600pgl.10 for ; Thu, 16 Sep 2021 08:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R7BRXEWvxWUGmwl0JiVhEapCxr/L2l4nPcG0jEXDrDU=; b=ILll7l8l0832sU+IQQE1ndDm8dBYqmgusQUSdgvvgUDz5ki8ZB7TJsWR5HPt31ui8T AvYJNHWCVd5kLue2i4eRO42HM3INtoCD3M+zhpkmLmL6m14x2ygQinOnHJvVIOWhsVPb WoFws7GR5okAfQwGKK0xsDcW9nC7K6rRx64f87tpsRlAaR4uYpd0MH2i+bRGjeI/7g2h pSpUOleUYN+kcECFskq2+j9/2EZ2aheNRoElkBOnLnOY97Isjl5acNywblHtiHzvkekC VtpehcmkL6shfh5SiDhdsltMV7HwWY0nWwDWHdkOOHkMgtPxgGdcnC+Kul8fmaovlnUA ATSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R7BRXEWvxWUGmwl0JiVhEapCxr/L2l4nPcG0jEXDrDU=; b=vH0yFVBUj1Rd1Ug+IjYF6bhp8GzsS7PBoZKLyzZubeZZ1WhBgw4Id/xF6mRdjrd/mA po3WuIdiPgvQI7KvpDbxK/pAMfDP0/1j56RJdJfQiDWcTBF2h/ZCWBBTyf8Bll1oIopE lvpFVuc8aLrUZVMXjH+4HSOV2Mfm08KlPsbXJQd3RkPx1f1T2MfHQY4mpmYUI4XhRXE7 IOSTtYFO5XpxjkpHdK7Ci6sy2RgKdHA/wqmERHXocYubl/6ZxRooUikqdgLuRYrhTHC6 5a738ceo3wjz5h9uqr4vFWiy7/+V26h9e/LQSPhiJqF11vCNoYGYaz+JImTG1H1intgS t81g== X-Gm-Message-State: AOAM531uu3rkDreWK3MHgHkHrad86gigelnGW80AMWjCb0E0ogsW409X leRh9bDlRIHRaqFW5leX2p+rCspFk6B/JA== X-Received: by 2002:a05:6a00:c83:b0:43e:d99:7e1e with SMTP id a3-20020a056a000c8300b0043e0d997e1emr5791538pfv.43.1631806241083; Thu, 16 Sep 2021 08:30:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/35] target/ppc: Introduce PowerPCCPUClass::has_work() Date: Thu, 16 Sep 2021 08:30:11 -0700 Message-Id: <20210916153025.1944763-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is a const structure, so to avoid creating multiple versions of the same structure, simply changing the has_work() handler, introduce yet another indirection with a has_work() handler in PowerPCCPUClass, and ppc_cpu_has_work() method which dispatch to it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-21-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/ppc/cpu-qom.h | 1 + target/ppc/cpu_init.c | 23 ++++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 5800fa324e..3611011250 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -188,6 +188,7 @@ struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; + bool (*has_work)(CPUState *cpu); #ifndef CONFIG_USER_ONLY unsigned int gdb_num_sprs; const char *gdb_spr_xml; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6aad01d1d3..2f7d262b17 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7621,7 +7621,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); dc->fw_name = "PowerPC,POWER7"; dc->desc = "POWER7"; @@ -7630,7 +7629,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER7; + pcc->has_work = cpu_has_work_POWER7; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7789,7 +7788,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); dc->fw_name = "PowerPC,POWER8"; dc->desc = "POWER8"; @@ -7798,7 +7796,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER8; + pcc->has_work = cpu_has_work_POWER8; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8003,7 +8001,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); dc->fw_name = "PowerPC,POWER9"; dc->desc = "POWER9"; @@ -8013,7 +8010,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER9; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER9; + pcc->has_work = cpu_has_work_POWER9; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8212,7 +8209,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); dc->fw_name = "PowerPC,POWER10"; dc->desc = "POWER10"; @@ -8223,7 +8219,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER10; pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER10; + pcc->has_work = cpu_has_work_POWER10; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8790,7 +8786,7 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip = value; } -static bool ppc_cpu_has_work(CPUState *cs) +static bool cpu_has_work_default(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; @@ -8798,6 +8794,14 @@ static bool ppc_cpu_has_work(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } +static bool ppc_cpu_has_work(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + + return pcc->has_work(cs); +} + static void ppc_cpu_reset(DeviceState *dev) { CPUState *s = CPU(dev); @@ -9037,6 +9041,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match = ppc_pvr_match_default; + pcc->has_work = cpu_has_work_default; device_class_set_props(dc, ppc_cpu_properties); device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); From patchwork Thu Sep 16 15:30:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512968 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1343786jao; Thu, 16 Sep 2021 08:57:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeABbtFwHcNJFlkzG/tpr2GtBLBt9rlUw4LDRJPVCcvbjq1WVRDBqtbddorLTRWjTDmtmt X-Received: by 2002:a05:622a:254:: with SMTP id c20mr5779447qtx.213.1631807841600; Thu, 16 Sep 2021 08:57:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807841; cv=none; d=google.com; s=arc-20160816; b=WDaAZ0nQm6USslTbXPWMDu8juzq39xdUxfwiMl1D2bBvgKdMcsFAwJzmsd5POIExbh ffS1XarV6bNyuo4Mo5t6EDUWUXcSUgSqqMFwSHaJYkl3j305FB41wRhzN0fhDDtjrOFq OU26yjo7SNIcz7GY4ENh4gwjRYzSwbORmNgmyygvUfz1MKMkf6M+O9acLPcXkNBsMTHM cqUH2PkGxTgY/vRf4RDqmPnX1rZJpi5ny7ZysEj//ydRfdhcso2TSw2zlvQaJ9ZAkD0u clf9yQX0tpH6lgaUdFMhvIIsVtbmr1mx+mqb42MvcaM6wjSlB7V6mSd9maIPBFUDftTq xCWQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id c23si1899847qtm.49.2021.09.16.08.57.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:57:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bh+BfcQq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtlI-0005Mf-W9 for patch@linaro.org; Thu, 16 Sep 2021 11:57:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLk-0001Zx-5E for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:56 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:40485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLZ-0002aH-64 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:55 -0400 Received: by mail-pg1-x535.google.com with SMTP id h3so6480194pgb.7 for ; Thu, 16 Sep 2021 08:30:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0hwaVqaKz38vUrAyliZJndyCYKt8BX36m2eIR+cLHnk=; b=Bh+BfcQq7JMQ+SKJJIV9o8dB5G4ujbjrjS9DGUWawwU3tBrXLjVHXk5M2zfLRN4Y6H ugyxQ83hOg9Ule7vywlkgv+JNkeZT4XKs9L+xDKVc8eVnluaMehliyzCJ0DnIl6rDny/ TrTncUxsihBTb+KzIdtsVWVXzeM6aMPxCkVX1alLaA8JqKTQnfl86S9V2sqvtCHCcgPx Jp1IcgowzH2XDZdZbjfJn6Y0HFChuVcEmyMCgsz203nJkgMqpBozISweijoJ4nNGFs3A uR7HVgTnTF80qo53G5It7zQwBcUMkTwIuUq5FwjFt+1h59lVUPHN4eaCpp2TWGtaLJMQ 1Lpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0hwaVqaKz38vUrAyliZJndyCYKt8BX36m2eIR+cLHnk=; b=QqrTe2PCE8HdfupkpZNnJMWSDXr9veS77r0G29HWDalGPIOhYIPGlSe7k6MIBSIpNO WWao3CybI9CtE3qy6sO3861gQ1Zhf5H3D5RT0yma2/2eF1klCVABKWOxrOyMSW1H+KAg qyYOqvAoIEE9xHFdhVMdNS8Jyv2M4+O8/d5X6qbb1fsHDwfmWmxwyR96mQOigVaFKqDR 1XxABW/aXYXOIMIB6uf30vt37tew5QU8Ii+iW2KY3CUBmv4lb/9PnYSz1jF7lam+wz+A z5ziYPVpWf5R2eX7/n/JhZlinF0sk07ntW2I8im6/bhqkVgXVCtYjt6HrRMNRxvqzWPw s/kg== X-Gm-Message-State: AOAM532QFi7jpatXcR063ZQyhPUF2e7uvBFnkAEXxMcCxw8beHfc3iwb e7OrDr2+xr2w7jxYpf5VHpIGMEPIMf+YYQ== X-Received: by 2002:a63:cc01:: with SMTP id x1mr5453611pgf.304.1631806241880; Thu, 16 Sep 2021 08:30:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/35] target/ppc: Restrict has_work() handlers to sysemu and TCG Date: Thu, 16 Sep 2021 08:30:12 -0700 Message-Id: <20210916153025.1944763-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work() - SysemuCPUOps::has_work() implementation - to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-22-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/ppc/cpu-qom.h | 4 +++- target/ppc/cpu_init.c | 24 ++++++++++++++++++------ 2 files changed, 21 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 3611011250..ff2bafcde6 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -188,8 +188,10 @@ struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; - bool (*has_work)(CPUState *cpu); #ifndef CONFIG_USER_ONLY +#ifdef CONFIG_TCG + bool (*has_work)(CPUState *cpu); +#endif /* CONFIG_TCG */ unsigned int gdb_num_sprs; const char *gdb_spr_xml; #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 2f7d262b17..5c134adeea 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7583,6 +7583,7 @@ static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) return false; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER7(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -7616,6 +7617,7 @@ static bool cpu_has_work_POWER7(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) { @@ -7629,7 +7631,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; - pcc->has_work = cpu_has_work_POWER7; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7672,6 +7673,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) + pcc->has_work = cpu_has_work_POWER7; pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits = 32; #endif @@ -7742,6 +7744,7 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) return false; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER8(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -7783,6 +7786,7 @@ static bool cpu_has_work_POWER8(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { @@ -7796,7 +7800,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; - pcc->has_work = cpu_has_work_POWER8; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7846,6 +7849,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) + pcc->has_work = cpu_has_work_POWER8; pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->lrg_decr_bits = 32; pcc->n_host_threads = 8; @@ -7939,6 +7943,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) return false; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER9(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -7996,6 +8001,7 @@ static bool cpu_has_work_POWER9(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) { @@ -8010,7 +8016,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER9; pcc->check_pow = check_pow_nocheck; - pcc->has_work = cpu_has_work_POWER9; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8059,6 +8064,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) + pcc->has_work = cpu_has_work_POWER9; /* segment page size remain the same */ pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->radix_page_info = &POWER9_radix_page_info; @@ -8147,6 +8153,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) return false; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_POWER10(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -8204,6 +8211,7 @@ static bool cpu_has_work_POWER10(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) { @@ -8219,7 +8227,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER10; pcc->check_pow = check_pow_nocheck; - pcc->has_work = cpu_has_work_POWER10; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8271,6 +8278,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) + pcc->has_work = cpu_has_work_POWER10; /* segment page size remain the same */ pcc->hash64_opts = &ppc_hash64_opts_POWER7; pcc->radix_page_info = &POWER10_radix_page_info; @@ -8786,6 +8794,7 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.nip = value; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cpu_has_work_default(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -8801,6 +8810,7 @@ static bool ppc_cpu_has_work(CPUState *cs) return pcc->has_work(cs); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ static void ppc_cpu_reset(DeviceState *dev) { @@ -9021,6 +9031,7 @@ static const struct TCGCPUOps ppc_tcg_ops = { .tlb_fill = ppc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = ppc_cpu_has_work, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, @@ -9041,13 +9052,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match = ppc_pvr_match_default; - pcc->has_work = cpu_has_work_default; device_class_set_props(dc, ppc_cpu_properties); device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); cc->class_by_name = ppc_cpu_class_by_name; - cc->has_work = ppc_cpu_has_work; cc->dump_state = ppc_cpu_dump_state; cc->set_pc = ppc_cpu_set_pc; cc->gdb_read_register = ppc_cpu_gdb_read_register; @@ -9078,6 +9087,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #ifdef CONFIG_TCG cc->tcg_ops = &ppc_tcg_ops; +#ifndef CONFIG_USER_ONLY + pcc->has_work = cpu_has_work_default; +#endif #endif /* CONFIG_TCG */ } From patchwork Thu Sep 16 15:30:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512961 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1337139jao; Thu, 16 Sep 2021 08:48:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyerYLJntIvVYluTQKMKJoNn/6eeaNU39ekOpRHvUZr4zvHkwUEManBPDgScAZDArDbNNID X-Received: by 2002:a05:622a:181d:: with SMTP id t29mr5711771qtc.309.1631807330675; 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[209.51.188.17]) by mx.google.com with ESMTPS id v26si1828332qtf.242.2021.09.16.08.48.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:48:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mg7GdO2m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtd4-0007YM-66 for patch@linaro.org; Thu, 16 Sep 2021 11:48:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLk-0001ZL-1i for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:56 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:38893) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLZ-0002ah-5w for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:54 -0400 Received: by mail-pg1-x529.google.com with SMTP id w8so6486197pgf.5 for ; Thu, 16 Sep 2021 08:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/h2t7iFSfX1gtAhd6k9niCF0SPBIUY92gpdkPQq/Z1o=; b=mg7GdO2mmqVUEKzB3EjE3GpHETqpdw2XOG/GbE0Uf97+m+thauE9rFCdz0GmesGa90 Bf1tRYa+LEukgfX6cYiFOdKD1XKlxIdz8oAeOmKx3HOpmvfCDbwL8ITkTSytASehnQUl JEN7Np7MWw0mSBg3ts2BGf/YE7GQUykEMQtKzK9KQ5S8wwJFiljXkS9VKW34UvUTWrDB V2h6Q37eqoKchknJo3Bb7e+XvtC29DObbw/wVVnJk/ArbVL671IYAwaEhVHCy80wsDxj NIHOBPQThiz0o1omMOgu1bQCdEaaXTP/XQfI1etYNbMUHSgPtWl7+kowcFBJDvV1TVev 8Zpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/h2t7iFSfX1gtAhd6k9niCF0SPBIUY92gpdkPQq/Z1o=; b=bX+in59FThVNwtSBkcfnQJQMhXpmyGmBIGebj/pvr4dCm3fBS1mGq9usfFBX+3T1fZ irOX2+/R+DFw856Ar4ad0POFc5inG/wx24DRSjPuOTwOASik/XzWHqhsT2GjDi9GyM8z hD1GBXP6OzThpca2asLPm6yNP4EqYPk7wJ4J+BumhcdDrAKRPMNlvYto5RY+qXJcXKUz 6P66+bkM5DARufrIIyyZeK1lXL3Fj7mrAWp5TPUaVQ/RKXRwtbe3o89+9HRX+pFkqk1n XOJCVtSGvIRvTU5hfmNW2bJZKeB9rhOew0MwmHQWQFJsUw5AGzVnmRiXdYf4ZNZ+EMWt JQJw== X-Gm-Message-State: AOAM531fNmD4KhiTtOUYoVZ/sa7eQTEEDVCEdbRPNJo40Gx1YCek+y9D eZDeon0Z1z8JqU6KECTWXZrWixE5ZjEZeA== X-Received: by 2002:a63:f817:: with SMTP id n23mr5442467pgh.250.1631806242490; Thu, 16 Sep 2021 08:30:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/35] target/riscv: Restrict has_work() handler to sysemu and TCG Date: Thu, 16 Sep 2021 08:30:13 -0700 Message-Id: <20210916153025.1944763-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-23-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13575c1408..abb555a8bd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -335,9 +335,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, env->pc = tb->pc; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; /* @@ -345,10 +345,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * mode and delegation registers, but respect individual enables */ return (env->mip & env->mie) != 0; -#else - return true; -#endif } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) @@ -647,6 +645,7 @@ static const struct TCGCPUOps riscv_tcg_ops = { .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = riscv_cpu_has_work, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, @@ -666,7 +665,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->gdb_read_register = riscv_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512956 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1333653jao; Thu, 16 Sep 2021 08:44:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4ysqH8pkdtsg8vWKt244jUs7QnLV0WWHUgkGvauh9ldX1jqbDl/bEHs344zMOSzVPi3Qo X-Received: by 2002:ac8:5710:: with SMTP id 16mr5570953qtw.395.1631807073548; Thu, 16 Sep 2021 08:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807073; cv=none; d=google.com; s=arc-20160816; b=OClfO9YXYUX3shL/5aK6bWRj+tx1nbB0PYiIVhk82zlOY+d8Lohk21Q8N/Gl8jBQCO z4tvqMz15ZklUNHTuBMJz3IjXN8b8PhOmltqEjKtoh2I/EbOyqMWDOhBuV1UN2/CBO9n VKfSJRoaDdpyS586qse4O2BlShlo4g/VJFKnJzzHwg8kH7tm8Q6i2NCR/n0hDFgIOOza gTl13f9zazc37WfQwgA7VzLSxhvGY0aGHxDpBOtxhJ2oCWkeSLZz44vY6J+w5VAeb/CF yk3Bony7xV7wjvN/6t7+A5s2liE+1fFhf/g6jCE1SjYwyAq9dw49GS/w1ii/XiT2L/n6 cwMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=54hnQT1IlwQI1vqo01dQd8XkfxGimuQYo48f9SWydvk=; b=mhKpJCxriGbdnsFTNDyv1az76dlrkpMUxR3mwz88UgbYtjEixy+V6AZWk2ctadJF+5 KSMH8HSp+cpvM0/wr54/korFwgtZnyXLcx7TopV0Us3/CMiLj2vLTCXQk4pTENOVXhbY fH3SlJ0JpXRWRmPqunpFPu0+IS63fpi2cbshR69CGbrJXld+YiNJcI26v2cuRV9rfhW2 Oj6jhgKc2qLGZ++JUw5fd5Ywn+Q+PPKfnRwRqsrj/EKQsCn9ebCbwQPuBXFnf+zweeC0 f5WgnIRU8nZrhFF4YTApfkauGJKzBPz3jlO/674ejcqYgFGW/2oMyUBjn5KNL2S/NJEB SkyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hjrgstxn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-24-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/rx/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 25a4aa2976..ac6b40b271 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -41,11 +41,13 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, cpu->env.pc = tb->pc; } +#if !defined(CONFIG_USER_ONLY) static bool rx_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } +#endif /* !CONFIG_USER_ONLY */ static void rx_cpu_reset(DeviceState *dev) { @@ -189,6 +191,7 @@ static const struct TCGCPUOps rx_tcg_ops = { .tlb_fill = rx_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = rx_cpu_has_work, .cpu_exec_interrupt = rx_cpu_exec_interrupt, .do_interrupt = rx_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -206,7 +209,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) &rcc->parent_reset); cc->class_by_name = rx_cpu_class_by_name; - cc->has_work = rx_cpu_has_work; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; From patchwork Thu Sep 16 15:30:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512960 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1336621jao; Thu, 16 Sep 2021 08:48:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwA7/knP5h1mX+ylFoADGt2ip4Rn87Su6hdqjwghvxcjb6jX/8t1+MMJfb+dVT8KrmcnpeK X-Received: by 2002:a05:620a:799:: with SMTP id 25mr5772107qka.119.1631807291856; Thu, 16 Sep 2021 08:48:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807291; cv=none; d=google.com; s=arc-20160816; b=hQgOFYeMA6V5yIauNvn6OJK+MRyjtTeWEuXXDwHt6aNiyg5y3F0DXe6PAaF21allxX +wrJh8uSwwEmUVE8WQAzbURzQ1D0xAcojw3WyZvUYLWMfAy60eyhHFEsW6vWMte5EIhj wT0dc6x/d73kF73zoJ6ASIMP2MPKmE+U+MbsU3GkFmhtt7pvVZfTM1dUr3SmZ1yai/AP H1JTpUBm8+GnOwxIdjoNcBOofXuMYLfqFMIw8bULHvT/Or7VPI/IVXMZcJFYg+h/D+7H zPXFYXcm0N3AATv3rfhxb4DxIEfZnHUjBPKH6dlXOpWqn8E8mbndoAXOkpB7ga39IsJ6 tkAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yqnQxPNNPW3cXaX5Uop3j/apP2OYNx8szUJcSd+WiRU=; b=QZTGoeRmA1LULLjoVwhhDtDG3EzEifhv032SMEb7L8Iu6H9voyO2xe+0mDP7yITbjr ExQWaxc0vRRMQg9SfHRom4bQcNZBTHRI6NDsfNK0jcE1miFtw7ReFmNeqfreP57afabL X6iapEZnYGUiDArRF35Pd/4R0wMyXQS+Rui0sUmedY6cVzNYB35BuHdqtpA0WxhzARjI 3dhtBcLwoSn2xDLSni8MIgeZu3fV+pe5zXuYPzrkRZ6oRCGtdwl870kKZqabm92m3Qae JmoEJbqjYxyFru5MVst4KVQZ/9b8OHbj9WWUTeYlMCg4WD2GMMI5LBi9Uwii1OGatsce JFJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HdaTNicb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-25-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b7b05f1d3..df8ade9021 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -88,6 +88,7 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr = value; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool s390_cpu_has_work(CPUState *cs) { S390CPU *cpu = S390_CPU(cs); @@ -104,6 +105,7 @@ static bool s390_cpu_has_work(CPUState *cs) return s390_cpu_has_int(cpu); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ /* S390CPUClass::reset() */ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) @@ -269,6 +271,7 @@ static const struct TCGCPUOps s390_tcg_ops = { .tlb_fill = s390_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .has_work = s390_cpu_has_work, .cpu_exec_interrupt = s390_cpu_exec_interrupt, .do_interrupt = s390_cpu_do_interrupt, .debug_excp_handler = s390x_cpu_debug_excp_handler, @@ -292,7 +295,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) scc->reset = s390_cpu_reset; cc->class_by_name = s390_cpu_class_by_name, - cc->has_work = s390_cpu_has_work; cc->dump_state = s390_cpu_dump_state; cc->set_pc = s390_cpu_set_pc; cc->gdb_read_register = s390_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512970 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1345569jao; Thu, 16 Sep 2021 08:59:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJysst3LV/xzwfeWkDAuL+3kYLR/eE+FriqnfjE3UzJaqgIODIQONJf1OZ7U7g+PClK/+Rvp X-Received: by 2002:ac8:7959:: with SMTP id r25mr51382qtt.29.1631807971486; Thu, 16 Sep 2021 08:59:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807971; cv=none; d=google.com; s=arc-20160816; b=hv8Jnjl+e4saQyK0K3U7nPCIEDUupd0IsaQ3Zjm1vElp9uIl7Usy4nT11jFcVWU/++ BncteUVRjC/43yXmnRusbDI3aAkw5CyqbwYhrR3KM9R6O3uisXgsp1ip0zIAA6cVSt/K RztYX0E49cpvfNT+rIMKP7PiRFXmFl6X1Q5et+e0jrRE87hxZwj6wC3FvMBDpkiG78jk iMNa0qUNs7e0gEwJd6D8hG1Oor1LJ973Httsx403gqUWsYv5jTH3E1bYhcB6uR7MWSlO O7HXOTnkzMcx3g7apV+gaHUG8Hrubr3aoETLfe5mg+tNFMCuCAGfEiM2jhOFmWy221EB lERg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RwS32umeuTKtPdFMznfukznJpzAEayn9YEvDSjPds5w=; b=GiHnM6xH0GdMBeUPCIiKF7MIQDkSEIrfnDMNmYtbjAMrs7amdbuShw7jEYJclBsR8e lFeqBOocS+iANcszox396YvNZMr4DLvk2i01MeufSM8udh92Ta38m1G7hDo7+H269/Bu dbcZQt+gSFvFq8qTJ/Wx1eY2Ucd5jBKA+4sdezZG0Cb5DZheu1geB+qZTDkgK17vK3Vr BFKct7nmGJErnB0kMzp0p197yse0IUinMmIbEQMGTls7IO4R00+bSQxoZzaGZjVadqpg 13EparuTBOy1jaLCtJub8aGtbELnoxoO39VxAJiequzXBZjhYTYrvlsuEf8loVEsAqec qdEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ttN/Vs2F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-26-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/sh4/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2047742d03..fb2116dc52 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -58,13 +58,14 @@ static bool superh_io_recompile_replay_branch(CPUState *cs, } return false; } -#endif static bool superh_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; } +#endif /* !CONFIG_USER_ONLY */ + static void superh_cpu_reset(DeviceState *dev) { CPUState *s = CPU(dev); @@ -239,6 +240,7 @@ static const struct TCGCPUOps superh_tcg_ops = { .tlb_fill = superh_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = superh_cpu_has_work, .cpu_exec_interrupt = superh_cpu_exec_interrupt, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, @@ -258,7 +260,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); cc->class_by_name = superh_cpu_class_by_name; - cc->has_work = superh_cpu_has_work; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->gdb_read_register = superh_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512978 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1354929jao; Thu, 16 Sep 2021 09:08:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwikVLTlop6Wtjbat3HoO261teBi3uL4Tx7NLYiuGGn3/2lYlyemks9q5y745qdC0RDmc3i X-Received: by 2002:a05:6512:23a5:: with SMTP id c37mr4656778lfv.321.1631808519242; Thu, 16 Sep 2021 09:08:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631808519; cv=none; d=google.com; s=arc-20160816; b=cDCLNYlOAPgyw0TvV8+82u1Nf5Wm1hpvEufgj51jAO9dYRhjHziIffetixog+uIMCt yijOAysStDEyVLR9knz5e1Bd41zYrABiK4hbB7L8CkbZL8/x0r3xmAFzCTvwGDB/+6RD mENMBtTgZHyUIvcZ7WKxm9JfL9sr3ZF6F8eKPyVot4ML3vlSGspdQTqooDLNo+20THB1 hZhuOE90zN6AfEXJwAYHKCw4b7Vl5AZIWawtxJxYRxQ3an0cJvsp3wBnV5ArFmSKVbcj IsSdx0dQjbuQshPdlkYERRsYvcpJDx2eRj3s7AGcpcgTPMzO9gi4SK5OD1HDL9FaG4ys tUMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fsDKJ9HWSGf+3RAOS+lcZoApkaAa44EIIs8LfeqvPUs=; b=dzfu02oLzqeebn30DzMLXTL7JOe/TnwZmN00gC3wMdGEYj7DnyhSRlcdzVLFOjUI5c icW2EqC42QzIAcaSYvZUIN269G0yMY00tk0Tc1H6ELzew3igjmzTokkRKB8ZeNVLzjz8 m+1Wep7PSm0YPqNwCxEJsF8TyDjqV77BMg9MICw1uZODHTQZ6h1aW1dTrvulOQyHVSt3 1gVMkEKWjTTsuSNUonuuBfARbzCDQds4d6BzyhiXCRZocqyeIo+AuFp931GVnp9fX8f+ ZjeQfFpUZh1DtNRSXl6NSXdmMyH61JAjx3BdE98wZPDjkdPwR7wAUdFOXrGp8lcRbOXF QS6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A8o4gkh2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove the CONFIG_TCG definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-27-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 2 -- 1 file changed, 2 deletions(-) -- 2.25.1 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 5a8a4ce750..e83e305aa9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -859,7 +859,6 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { }; #endif -#ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" static const struct TCGCPUOps sparc_tcg_ops = { @@ -874,7 +873,6 @@ static const struct TCGCPUOps sparc_tcg_ops = { .do_unaligned_access = sparc_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; -#endif /* CONFIG_TCG */ static void sparc_cpu_class_init(ObjectClass *oc, void *data) { From patchwork Thu Sep 16 15:30:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512965 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1340726jao; Thu, 16 Sep 2021 08:53:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyCgB1jezc/VDxAeo2MRB0p2vbztTl9STthtrZSbnUPFXang7PRlHbERtw+af+UWiH+MV1T X-Received: by 2002:ac8:570f:: with SMTP id 15mr5794584qtw.335.1631807590351; Thu, 16 Sep 2021 08:53:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807590; cv=none; d=google.com; s=arc-20160816; b=p5+o0rMpYR7sRptvGVGaKJcic7p7HEw/egXosEytHP6INu4rp+XoGp/tz4XGLjynup bn+8Ezmi3NXmcuE5dMFhWLTpaoP9c7RRrNdyKMLErnkU6DjmJuy/yGxQY6D8Vl0NN+5s iazp5PNWK3a/CjxCSS/bpLvARUygq2WFteHgwFNqdJLdQq3KEoDuCDjy3qZnO2Coiqtp /0KcFutNd3t+v0c2zVlYHMLjKyCVen5J4zt7JFjWPcNqWkfwuVZLwHak9IsKpTouGIE1 edWflaF4FGR/3Az2+AyR+gO3q2ZdApH4DyO/7UprqdpIUNh92FKz4+BSC9viYKNhKzVK 9B7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J6Fp0tDii68JisdtRr/m4W+R/ln8amHARXVC+ekHe9o=; b=NakHkXD15Bd5phh1Cwecw7tU3TOTcegfZdyI1TxjvB3SOHGhtNeXibmV1wImMZ0OG5 jlOdpBFAViyyTmVLsY5jZLvQvNMF7lU2VQASpQHG2H8nBHF4vELtDy6wD3jiT8NQkHQ4 MgQaWeWbX0aC9s8Jc0gVe4KSncfWiHnaxWSqhzUBkm06jRJ+ksvYbIEwH/VOB12iSBr0 h5gPD71tHmAk9iVYzWO6ywN5DKwOl6xKd8taI+TSJIWQXPYVA6HUULFOQ5BKUgCJwMzC N9FAY3AxG2yiAvoO1ho13cZZayju8hH6FJJdqGWKLfyvV9g3gqI152yzeywr0pLV6P+6 IKHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WTvC0Zu1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-28-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e83e305aa9..4a63ed1264 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -702,6 +702,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc = tb->cs_base; } +#if !defined(CONFIG_USER_ONLY) static bool sparc_cpu_has_work(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); @@ -710,6 +711,7 @@ static bool sparc_cpu_has_work(CPUState *cs) return (cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(env); } +#endif /* !CONFIG_USER_ONLY */ static char *sparc_cpu_type_name(const char *cpu_model) { @@ -867,6 +869,7 @@ static const struct TCGCPUOps sparc_tcg_ops = { .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = sparc_cpu_has_work, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, @@ -888,7 +891,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; - cc->has_work = sparc_cpu_has_work; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug; From patchwork Thu Sep 16 15:30:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512972 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1349768jao; Thu, 16 Sep 2021 09:03:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3+5nSMZOPyAzOj6+jFBnH2WGRxi01fdZ6imXx+dkHgVML+mNgwgN665HLb7Sw5GHXoCM8 X-Received: by 2002:ac8:5b04:: with SMTP id m4mr5835128qtw.344.1631808231289; Thu, 16 Sep 2021 09:03:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631808231; cv=none; d=google.com; s=arc-20160816; b=M613NrCHN5/mQ4TDqxM1RjzU2OWej62EOJuQmo7fkZ7mW7gv8qZRgsStoZo7Nmuv3Q jQEyRZI0OOtVhtKErlJtB2Ptg3lHSs+wqLEQW7DXLc//nZ6GZ5fNEPhXMifAjDOzDt7h 5PkDilBw7pLROzo7YeFg4cdHXFx8wgZjSW9wDSZEe44xI4rzr4nBjHIjGvdQ/dDq75Vf pFFd5ZBiikrN/CpTHrdcqTZrLl+NHtnTjVpUWKQkOMiLnV+q5OD9YNrPD/BLP90dkCu/ h5u+QErkO3T0DhtUhZ8ErwWMkaJOLFdElIWMwZuus/NPF36tfKDUBKqRAy4jjHQXjyZg XRnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+b0ulkNTfnCVlv+G/yTL5zdVouYmE4FD5mdoMaQi2iI=; b=fK2lVkpRiy6ebD9Ko6AtjMXXqz7n107DlhgPS/vmz7WTLY1DUeMnigZkS4xMGHv8XZ kegpQJOGbMNYQtdzNcBY8278zcdBDFHQnZQSrk0EzFCf5aHyZoyzIRg+1+RFgyxTpLtl YF3ex8Dmij+iwdbt1qCXKI38jmzHcNgYebqIAHZbBUQ1iKsiw+3GxkhuTmv3Ho+Otw80 1J8oam516QWo6VsP5QvAucABGFxg7L/d1vPVC9GeNEAf3XlQRnY57qHIfUzqqTqgsU8M 8ObVvFAWR0v7tqOHqrwj+xr1SbkAlMMMgTbVVO7iOX0IgCrZ9B3UWokIXKD6qwsANNCK eUEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nEfCprHO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-29-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/tricore/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f0..419fa624bd 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -62,10 +62,12 @@ static void tricore_cpu_reset(DeviceState *dev) cpu_state_reset(env); } +#if !defined(CONFIG_USER_ONLY) static bool tricore_cpu_has_work(CPUState *cs) { return true; } +#endif /* !CONFIG_USER_ONLY */ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) { @@ -154,6 +156,9 @@ static const struct TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .tlb_fill = tricore_cpu_tlb_fill, +#if !defined(CONFIG_USER_ONLY) + .has_work = tricore_cpu_has_work, +#endif }; static void tricore_cpu_class_init(ObjectClass *c, void *data) @@ -167,7 +172,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name = tricore_cpu_class_by_name; - cc->has_work = tricore_cpu_has_work; cc->gdb_read_register = tricore_cpu_gdb_read_register; cc->gdb_write_register = tricore_cpu_gdb_write_register; From patchwork Thu Sep 16 15:30:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512981 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1359338jao; Thu, 16 Sep 2021 09:13:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwqUQh+sILLqYe9rWdsz7LQEttrZcdieBkOmPwMH0jxe5udpj2+Dy8bkLu8uGkJ3LXq328R X-Received: by 2002:ac8:7245:: with SMTP id l5mr5706707qtp.206.1631808784955; Thu, 16 Sep 2021 09:13:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631808784; cv=none; d=google.com; s=arc-20160816; b=u7cyEkVmMpf+LWP6TIVnJScyAuyItDOuPgPbjweIyy4LaxemGQZSmoPnt2VE/5/wyb i9Fnr5R2tpDeMMDJfJn4O8oxuAK0cFwiO25f3CRoCEinMxJTxugX34/LavyFD9GG9Cyj 9ezF1RnsvplqqrYpekbKz6wE/A/VcV81cwbZ8Uo7PuP2yM3oJIWtdPegIIEXCyMWUDLD 9yQwLG9ZYseNYaKR/497QrCMtb0OFPJBe9ssRcDP30kXTjrqIMT5NT30T0TWPbW7vX6y r8WWRbRvn7I7NSE6MTsACLsF4YQSlJ1JQ+tg+r4auLqjaAZTehoeUw3mzMbvtxt6ZWXd WI4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lh58yC+MNXGB83pjMDOt8lSKa0ARivzdvFCovau9CGE=; b=LRB3gXixGVA4BXws8McP/gpX46UtRLhFRY4JF6c0WkEt1q0Ie344ixa1bNM3+FvL1I 4jeyQKJooUrK9Fx9tKdKaT7+vv1xtDeyusGo2hh5j9/dU4yZIZ8ngFT3nRtn1X7RtHUM pEhAcIc7VRR6x1HjK2WxUP16LShqbk2zCkERkHqoMNd0ZkIxcmEWdzXpWkbeZRW6UTja zwuirtrhOewTDWgzVUd6gBPb4ilgCxAMfhfdRb9X9wRAJi0Hs1ZwM4o/xm/3iB1rvkx9 frbGRhCAdzZvV8WyZQLqyo7NH+P++46TU8fATEfw0wrEgzbDnrtIKuOdm3golqLcFfNP PP4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="mK2Jb/xK"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210912172731.789788-30-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/xtensa/cpu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cbd03595..5cb19a8881 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -43,18 +43,17 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +#ifndef CONFIG_USER_ONLY + static bool xtensa_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY XtensaCPU *cpu = XTENSA_CPU(cs); return !cpu->env.runstall && cpu->env.pending_irq_level; -#else - return true; -#endif } -#ifdef CONFIG_USER_ONLY +#else /* CONFIG_USER_ONLY*/ + static bool abi_call0; void xtensa_set_abi_call0(void) @@ -66,7 +65,8 @@ bool xtensa_abi_call0(void) { return abi_call0; } -#endif + +#endif /* CONFIG_USER_ONLY */ static void xtensa_cpu_reset(DeviceState *dev) { @@ -196,6 +196,7 @@ static const struct TCGCPUOps xtensa_tcg_ops = { .debug_excp_handler = xtensa_breakpoint_handler, #ifndef CONFIG_USER_ONLY + .has_work = xtensa_cpu_has_work, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, @@ -215,7 +216,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); cc->class_by_name = xtensa_cpu_class_by_name; - cc->has_work = xtensa_cpu_has_work; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; cc->gdb_read_register = xtensa_cpu_gdb_read_register; From patchwork Thu Sep 16 15:30:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512971 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1349121jao; Thu, 16 Sep 2021 09:03:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTLoTbySG4qag5U0SWClzWiO/c4Kh+IiZRwb5gleaqQOF/89CYtGywMlyV+kVafRlD167O X-Received: by 2002:a05:622a:1a24:: with SMTP id f36mr5780612qtb.294.1631808192070; Thu, 16 Sep 2021 09:03:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631808192; cv=none; d=google.com; s=arc-20160816; b=WRY4eVrjKejLnridSKXuXfIHQMlyCoH8l9BhBijOuGkrdrGLQQkbgeQd+z1KfAzMfl dYL6skl2kKjz4uxba2Gl87rV/koJxx1z5/bxP55t2lRcInOa2P38MIVZ40VHJrXbJLfQ Na2a6PO8D0xLSmmGKwyUd6CIORg4xMzya17cjhpI+ZaLHVRC+tnm/CIMWjbfXBteLm3x 5dSNnruwu06B2OJ/hGe75F5NN967P10OIrij4xCl2u9JTOVuvjgDLJyxP3b4w9seMGCI wSG+Lx65Rc6qLzm8wQyCJUiI08FWfMPkb+lt2YmPOzyoQemHQoqzpJs+hbELafe4GCgB SbDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pv5WSTG+D7D0H6LWYGDgFu80+f0Xh3zAIIrMYFZZVwg=; b=jQrnmjF6dpqtYDa8y4Ir2si+B9W63hdZHoitYWRN+91jBTR6a8RirR7FxtIK7w9qBl 8ZQXjoAWvuMikevjbXyT0zkFZlhP7/VR4mV++0YesYMfkUIwcAEobwicUfLbhnSv8jSi EsgcdGs32yJx6e98P+SwxetrTpGcIDRu+aWGv0Q/FcExpHyenIqwsfhrzwkOFDCOvO5m y0Bi7Kwt8En8jhxVb08ucga4AEWmVStJrkwk68Jcz+fiFhwiGk4EsEFGM8l3wqOT6B2g Lv6paG3rr80vE7STG2ypYH84zX6IwZxg65zFX9K5Ob2EcTFerP4iKvK959gx2CR0IBKf Giag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uVnnWtrE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Explicit it for the QTest / HAX / HVF / NVMM / Xen accelerators and remove cpu_common_has_work(). Since there are no more implementations of SysemuCPUOps::has_work, remove it along with the assertion in cpu_has_work(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Paul Durrant Message-Id: <20210912172731.789788-31-f4bug@amsat.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- accel/hvf/hvf-accel-ops.c | 6 ++++++ accel/qtest/qtest.c | 6 ++++++ accel/xen/xen-all.c | 6 ++++++ hw/core/cpu-common.c | 6 ------ softmmu/cpus.c | 9 ++------- target/i386/hax/hax-accel-ops.c | 6 ++++++ target/i386/nvmm/nvmm-accel-ops.c | 6 ++++++ 8 files changed, 32 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e2dd171a13..c64709b898 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,7 +89,6 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @has_work: Callback for checking if there is work to do. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @get_arch_id: Callback for getting architecture-dependent CPU ID. @@ -132,7 +131,6 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); int reset_dump_flags; - bool (*has_work)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index d1691be989..53c427ee42 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -446,6 +446,11 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } +static bool hvf_cpu_has_work(CPUState *cpu) +{ + return false; +} + static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); @@ -456,6 +461,7 @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = hvf_cpu_synchronize_post_init; ops->synchronize_state = hvf_cpu_synchronize_state; ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm; + ops->has_work = hvf_cpu_has_work; }; static const TypeInfo hvf_accel_ops_type = { .name = ACCEL_OPS_NAME("hvf"), diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index 7e6b8110d5..eb5a17cef1 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -47,12 +47,18 @@ static const TypeInfo qtest_accel_type = { }; module_obj(TYPE_QTEST_ACCEL); +static bool qtest_cpu_has_work(CPUState *cpu) +{ + return false; +} + static void qtest_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); ops->create_vcpu_thread = dummy_start_vcpu_thread; ops->get_virtual_clock = qtest_get_virtual_clock; + ops->has_work = qtest_cpu_has_work; }; static const TypeInfo qtest_accel_ops_type = { diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 69aa7d018b..fe5a37fa2e 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -215,11 +215,17 @@ static const TypeInfo xen_accel_type = { .class_init = xen_accel_class_init, }; +static bool xen_cpu_has_work(CPUState *cpu) +{ + return false; +} + static void xen_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); ops->create_vcpu_thread = dummy_start_vcpu_thread; + ops->has_work = xen_cpu_has_work; } static const TypeInfo xen_accel_ops_type = { diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64604..5ed1ccdfdd 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -143,11 +143,6 @@ static void cpu_common_reset(DeviceState *dev) } } -static bool cpu_common_has_work(CPUState *cs) -{ - return false; -} - ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) { CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); @@ -279,7 +274,6 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->parse_features = cpu_common_parse_features; k->get_arch_id = cpu_common_get_arch_id; - k->has_work = cpu_common_has_work; k->gdb_read_register = cpu_common_gdb_read_register; k->gdb_write_register = cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 6bce52ce56..e6dad2243c 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -251,13 +251,8 @@ void cpu_interrupt(CPUState *cpu, int mask) bool cpu_has_work(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cpus_accel->has_work) { - return cpus_accel->has_work(cpu); - } - g_assert(cc->has_work); - return cc->has_work(cpu); + g_assert(cpus_accel->has_work); + return cpus_accel->has_work(cpu); } static int do_vm_stop(RunState state, bool send_stop) diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-ops.c index 136630e9b2..5407ba17ea 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -74,6 +74,11 @@ static void hax_start_vcpu_thread(CPUState *cpu) #endif } +static bool hax_cpu_has_work(CPUState *cpu) +{ + return false; +} + static void hax_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); @@ -85,6 +90,7 @@ static void hax_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = hax_cpu_synchronize_post_init; ops->synchronize_state = hax_cpu_synchronize_state; ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm; + ops->has_work = hax_cpu_has_work; } static const TypeInfo hax_accel_ops_type = { diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-accel-ops.c index f788f75289..36296f79ff 100644 --- a/target/i386/nvmm/nvmm-accel-ops.c +++ b/target/i386/nvmm/nvmm-accel-ops.c @@ -83,6 +83,11 @@ static void nvmm_kick_vcpu_thread(CPUState *cpu) cpus_kick_thread(cpu); } +static bool nvmm_cpu_has_work(CPUState *cpu) +{ + return false; +} + static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); @@ -94,6 +99,7 @@ static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = nvmm_cpu_synchronize_post_init; ops->synchronize_state = nvmm_cpu_synchronize_state; ops->synchronize_pre_loadvm = nvmm_cpu_synchronize_pre_loadvm; + ops->has_work = nvmm_cpu_has_work; } static const TypeInfo nvmm_accel_ops_type = { From patchwork Thu Sep 16 15:30:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512969 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1345320jao; Thu, 16 Sep 2021 08:59:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJztavzn6vQriPhFF+J2G/CxGcEYTswsSJAQ4kF1MpEWJ2IDsBIycOGToqy8elKBbfGYOhhg X-Received: by 2002:a37:6697:: with SMTP id a145mr5631201qkc.5.1631807952828; Thu, 16 Sep 2021 08:59:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807952; cv=none; d=google.com; s=arc-20160816; b=J5cTDFjtZPU3tyu0D48hZgLvhilG5soM0zhsU3VkA9Z5YlXlJr7e4pqSYIUZ4Lb8EE 9Hizd++Y8WAMNgvGAkIzuXkRuokvj3EhGnn6d4oP+3nEs9f0hbjMrYF4D+J+3i1UI/jL dn6gVU/jnuNOFC6mozMK3oPl1zMHpDgDFx8JxDjlfdNwr10JBT5OBEXIOVWqWfmgR+iL vBg88DrQni2r6Pom53M6vuVwf7fFHgpN2t5MQ6XM8cA64pCrY3HSbRjBhJLO/l8f9iHg +iFhvIlhlRkd31syx7CB/Rcb3bxHXPHsSwRWGV5RtZThHBkbbF4XcchhshtD+jDdcwTW FdAA== ARC-Message-Signature: i=1; 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Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 76 ++++++++++++++------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bf0eb84e2d..320795a637 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -187,7 +187,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, #endif -static inline bool is_p2m1(tcg_target_long val) +static bool is_p2m1(tcg_target_long val) { return val && ((val + 1) & val) == 0; } @@ -361,8 +361,8 @@ typedef enum { /* * Type reg */ -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rs, TCGReg rt) +static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rs, TCGReg rt) { int32_t inst; @@ -376,8 +376,8 @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, /* * Type immediate */ -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs, TCGArg imm) +static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, + TCGReg rt, TCGReg rs, TCGArg imm) { int32_t inst; @@ -391,8 +391,8 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, /* * Type bitfield */ -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, - TCGReg rs, int msb, int lsb) +static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, + TCGReg rs, int msb, int lsb) { int32_t inst; @@ -404,8 +404,8 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, tcg_out32(s, inst); } -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, - MIPSInsn oph, TCGReg rt, TCGReg rs, +static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, + MIPSInsn oph, TCGReg rt, TCGReg rs, int msb, int lsb) { if (lsb >= 32) { @@ -422,8 +422,7 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, /* * Type branch */ -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs) +static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) { tcg_out_opc_imm(s, opc, rt, rs, 0); } @@ -431,8 +430,8 @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, /* * Type sa */ -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rt, TCGArg sa) { int32_t inst; @@ -479,28 +478,27 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) return true; } -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, 0); } -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); } -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); } -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret != arg) { @@ -612,27 +610,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) } } -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); - } -} - -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); - } -} - -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); @@ -656,8 +634,8 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, tcg_out_opc_imm(s, opc, data, addr, lo); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_LD; if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { @@ -666,8 +644,8 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_SD; if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { @@ -676,8 +654,8 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { if (val == 0) { tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); @@ -1637,9 +1615,9 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, } } -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; From patchwork Thu Sep 16 15:30:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512967 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1343206jao; Thu, 16 Sep 2021 08:56:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzbktx180mJvVrEJCF3G+gOfdb1tUr+PuyBHBMHBdbMLFvEoNJcqpBmGQArLGHSsCGsJHXa X-Received: by 2002:a37:6147:: with SMTP id v68mr3117075qkb.154.1631807789828; Thu, 16 Sep 2021 08:56:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807789; 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[209.51.188.17]) by mx.google.com with ESMTPS id s5si2162137qkp.36.2021.09.16.08.56.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 08:56:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TZpfsdUU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtkT-0004FH-AI for patch@linaro.org; Thu, 16 Sep 2021 11:56:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtLn-0001lW-Ia for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:59 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:42619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLf-0002eM-10 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:30:59 -0400 Received: by mail-pf1-x430.google.com with SMTP id q23so4149690pfs.9 for ; Thu, 16 Sep 2021 08:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=boBYT/QiHeueJZHokksNQvqeAcOMVEQaXWz4csao3Kg=; b=TZpfsdUUSIg1OPfVjhAs+xnvlBPhlHTRlz0aqyDT+4B2+bpIcVg09ZIkUdOC9MWLdR LelQdWAK1nojTOzs7Z2FrQzo/cYJWXSF+YQgBvrdjuGzdb2CNN9T7D4oiMly0myFtBK+ ytGSerNPIOEW34H4cRNSMLCkIdhS2VKt3ijNqvkLWTD+3DuYvUWUlHSHW7GCqLynbTlv eQ/jb3FCsflgGP4r8IVuYmgnqTiftv+BFBQK4+n+46Gq8l5DqBvLZ+mkrVYV9EQyUrsO C8RSiAJPE1TtVFvlvTOw3nsbXquOuU9gi8rcUueTxtvsmxlPMhQN7moyDdYk/NG4mwl9 AubQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=boBYT/QiHeueJZHokksNQvqeAcOMVEQaXWz4csao3Kg=; b=GZMX12+dVrTxZHc0sVhsqKYBeymPyZ1hL9tJbt1xm2RZ5mt+ID+kDNnTScpG7S9Wnz XzoLknexO3De/171i9xub2/RVpV35bML2WSE4WzwopVhDRJOCounX18NpLxcVv53OnsH 1eEEEKm3anZtKHSikOWeyhKNmelPK0+XJVrJJLUoGjhpJDg1wv6ERmYfhW16PaDvtbFW A8fTF+KOKehVCwYE63E8KsenK/RUiYTHKlYgm+EEa3RhONezVdtJreFJp7oTfxNGvYIu 7fUGlNv3YbL/d6XRHICMX/GgPk2la54+8T9hxgBtPwlIb8gDgBjofuFypdAg26g7sPnN XhIg== X-Gm-Message-State: AOAM530qKY3gTVO14n50Q55VbcJ4xIsDCVvkEPhFNxZFBHVQ6e6I+/7K U7ow7bQTYQMILymM1ZTAtZc80uj6BUVrrg== X-Received: by 2002:a63:c10b:: with SMTP id w11mr5553924pgf.228.1631806249237; Thu, 16 Sep 2021 08:30:49 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 33/35] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Date: Thu, 16 Sep 2021 08:30:23 -0700 Message-Id: <20210916153025.1944763-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 320795a637..3a40af8799 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -573,8 +573,10 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { - bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); - tcg_debug_assert(ok); + if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); + } } static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) From patchwork Thu Sep 16 15:30:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512964 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1339418jao; Thu, 16 Sep 2021 08:51:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzj1YBMfe44n7LrJX7o3986geZ5QMU/iQsRiXLJEx6rbNzt2Ma0IyRjfXnGCYXJC8BIIgyt X-Received: by 2002:ac8:410f:: with SMTP id q15mr5521316qtl.299.1631807483588; Thu, 16 Sep 2021 08:51:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631807483; cv=none; d=google.com; s=arc-20160816; b=tGrWLGL5IO5G1sWtNzSvRRCMFPj7Og6muSHNVYtLC9J/HWmPJ4JWw726MBapjmKS7s w39WcYYIth05eXBRtQFJLGeY50x+oFiAKeV0t9rYx/5nyPJDHnJJWTrx/hTNVSIL0YY+ /vANMrvkuzYuDCSpNAat2Ap1djatlSGhYGb4EtRsT+wQQ7Kf+P4+fUgIyB4oh74uX3Pr pZcqaok30d7TL15PmsmqtXpNGI7+TDFOlAOqysima9KTYWTOa9qnjM0gcuZStacXRvV1 NsefopGCi2CgXo2AHNE4EziOL8kgTaZsssx5boGDMv3yLXsTYfvRLQFcVWoBjReqW3D9 X5pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sx9OxIFdY4NzqELX94oh/fd9umRX24uKGyg1w/4NOWY=; b=cyhw34mRkxe6dlftsQ8TrXG+VBwI+204mZK/mu0J1DAKAXOLDDknfNRoRV11fjoPUg gOf5qSlv/2H/OouKrsf5O1gkKaex4fO3wbzdgOBI45AFoqDSac9h/h1cxwGk2vH3c5Nd K/8rtoiGgE2F4fTh85zLMou/ZIID13HfRniQs9ZbxO0FwdqHmbjJantBMAdYPIfFt2MD HFoszlbHzL128aSHZvE9uTvmCKiHvKx2QXhvXCctZeCUM7nOD1+pnTWO1bWJF+QR0NFQ uK6GpGA480Kw8Abt+X0/GuUxI/Qz/pNy62EG55jwVh6YswuGo4TMPQTFCEodgttn0FqF AY8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Chb+4yuw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 12 +++++------- tcg/mips/tcg-target.c.inc | 23 +++++------------------ 2 files changed, 10 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 3a62055f04..c366fdf74b 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,11 +39,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 -/* - * We have a 256MB branch region, but leave room to make sure the - * main executable is also within that region. - */ -#define MAX_CODE_GEN_BUFFER_SIZE (128 * MiB) +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) typedef enum { TCG_REG_ZERO = 0, @@ -136,7 +132,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -207,7 +203,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) + QEMU_ERROR("code path is reachable"); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3a40af8799..41ffa28394 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1654,17 +1654,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - /* Avoid clobbering the address during retranslation. */ - tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); - } else { - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } + /* indirect jump method */ + tcg_debug_assert(s->tb_jmp_insn_offset == 0); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); tcg_out_nop(s); set_jmp_reset_offset(s, a0); break; @@ -2538,13 +2532,6 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) -{ - qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_rx, jmp_rw, 4); -} - typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; From patchwork Thu Sep 16 15:30:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 512979 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1355462jao; Thu, 16 Sep 2021 09:09:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBNpl0bZ1xp3iR3MNlwxNxQ7vhgRZh0ySYTUcPzoLbuQuRuhztAN9P5Z1Gc7G0r8O+w4Zp X-Received: by 2002:a05:6512:ba5:: with SMTP id b37mr4563227lfv.355.1631808549561; Thu, 16 Sep 2021 09:09:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631808549; cv=none; d=google.com; s=arc-20160816; b=cbW0744DHqiYba0c73r2wAtozUhuaOgpDMtXKEANPytxpljxP9oJGnOAFP/H/ypqj3 ylakFM+v5KyNqUXlT3DiuoP2G3SXFgscDc5VOoph/56hsmUmesp6cBvan+8kifmnevUj sfr/W3ObFLs6wvD6AdruuV85HxWrW47tvE4YRHRQKovao9v5L3GjKSmj1tPjWUWB20U3 nWyafrz22yreF7Rn1kEfOpUX9Lm063VeCIT1LnTtnWDoTXLectYhacAOvs+r15Z2m3ZB xnwePCQnu6EWBp+HJgRe5UA75UYu/2wf8cjWxTwvMiHoQzUZ29ywAI7S1RvJASDhm95c e/MQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zxXZyIG+Pw01TAIshh/v24ac5SJa+rYMBmTa7I6pYe8=; b=pnCarKVBJKJdb8cPCICFU2IVF7kwbDjytAL/gMeoX+4nypkWGYdl5R++af10QxT+f1 18HksVHWcwgLO05ebr8x//aM5dn+JjmFTS3wk4ygozufKDoQ0M9clObpIRgaWWQkZrmM JemttAGC63Ys5aTn6luGkgPxxyJfE4ix5Id/uJ5/YZsDe4NDiztOkKlySB1+aC4lE0k4 DHBgxmuqWyCZhzxG741cZ1NWDPwFyV/SLv62cCAF/XNqj08jgfLR0QRq5+I+UVhs3xVQ 8bBHKMrRJ4fdYsi+s/oB+iq0odNRREed4uJrkm9VJfa7ut87ef5lHJ2gaK1ACCrUzHp2 Idaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i3qy1MUF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b14si4440381ljo.212.2021.09.16.09.09.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Sep 2021 09:09:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i3qy1MUF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQtwi-0006NN-A4 for patch@linaro.org; Thu, 16 Sep 2021 12:09:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQtM5-00029T-UH for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:31:19 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:38894) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQtLj-0002gF-G6 for qemu-devel@nongnu.org; Thu, 16 Sep 2021 11:31:14 -0400 Received: by mail-pg1-x529.google.com with SMTP id w8so6486608pgf.5 for ; Thu, 16 Sep 2021 08:30:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zxXZyIG+Pw01TAIshh/v24ac5SJa+rYMBmTa7I6pYe8=; b=i3qy1MUF7NrohW/phU3qwMsmnhqBGpAQOZditdLxgWX/87KuQvGf4+gkmcaRKOI/Tf rlLPYQIGFNDGtqePfAomKnMQxIPtjdQXolV8UHXhrPDGkIOa1kbKyEVR59zATPHuxwFt bolX28j/6PQkvolQ6zYB/m4Ltx4Lf7/uiR3dTYMk6J1SrWs3+iNDr6zHCNDZVsJqGlNU zJKmXsIJQuDZNZw09ZfDySV/R7T7yvcdrvrKO0a70IgH+cZkR2bxs8EdW9M3CLsZRmoC JWAyJJ4Qis+wNy8sc76BGbY8mYU+MUDHMcytssbRhZhAVXNji/sfXkSHf5SomUPqiTQ5 madg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zxXZyIG+Pw01TAIshh/v24ac5SJa+rYMBmTa7I6pYe8=; b=8ERAok5lL4nR9t7ZF/5sXH3+5I63teLvMqfkYEZuyFCjFLi1J9Iy1ybxDwbVE1N/uq RZuq49tSl7Mc2cyBBO8S6QklgXbT3Uqc1VQ3+mPqrj/EQjtLmo1lYz0IGtbvfsOXIkvg TueiNZufT382rS/ngaAoArrr5gPDs33u2QX0Jwtmon6QhQ7TsWC0jZFaUzWVUn8L41+2 3L886sYlZdOU76834puCo0yJkllqQGG/HZHpgra27BpP89VHrl2hQ1prS+RA3dig5OmL s1WnFxOYpgXr3pjbr6x2H2dBGFe5j3IQsy/EsikWZDZQA+ZnynjO6E5uI+zSmFGk1k9o /s5w== X-Gm-Message-State: AOAM531wH6NkUtwx+J0EURGEcWfBQODXho8/byS/R0NQC4WZHFjO/FHK pgu5Cmqq0bCDNUUBVNmB7PWawi6ER9ehcg== X-Received: by 2002:a63:150e:: with SMTP id v14mr5507189pgl.126.1631806250492; Thu, 16 Sep 2021 08:30:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 35/35] tcg/mips: Drop special alignment for code_gen_buffer Date: Thu, 16 Sep 2021 08:30:25 -0700 Message-Id: <20210916153025.1944763-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/region.c | 91 ---------------------------------------------------- 1 file changed, 91 deletions(-) -- 2.25.1 diff --git a/tcg/region.c b/tcg/region.c index e64c3ea230..9cc30d4922 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -467,38 +467,6 @@ static size_t tcg_n_regions(size_t tb_size, unsigned max_cpus) (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) -#ifdef __mips__ -/* - * In order to use J and JAL within the code_gen_buffer, we require - * that the buffer not cross a 256MB boundary. - */ -static inline bool cross_256mb(void *addr, size_t size) -{ - return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & ~0x0ffffffful; -} - -/* - * We weren't able to allocate a buffer without crossing that boundary, - * so make do with the larger portion of the buffer that doesn't cross. - * Returns the new base and size of the buffer in *obuf and *osize. - */ -static inline void split_cross_256mb(void **obuf, size_t *osize, - void *buf1, size_t size1) -{ - void *buf2 = (void *)(((uintptr_t)buf1 + size1) & ~0x0ffffffful); - size_t size2 = buf1 + size1 - buf2; - - size1 = buf2 - buf1; - if (size1 < size2) { - size1 = size2; - buf1 = buf2; - } - - *obuf = buf1; - *osize = size1; -} -#endif - #ifdef USE_STATIC_CODE_GEN_BUFFER static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); @@ -526,12 +494,6 @@ static int alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) size = QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); } -#ifdef __mips__ - if (cross_256mb(buf, size)) { - split_cross_256mb(&buf, &size, buf, size); - } -#endif - region.start_aligned = buf; region.total_size = size; @@ -573,39 +535,6 @@ static int alloc_code_gen_buffer_anon(size_t size, int prot, return -1; } -#ifdef __mips__ - if (cross_256mb(buf, size)) { - /* - * Try again, with the original still mapped, to avoid re-acquiring - * the same 256mb crossing. - */ - size_t size2; - void *buf2 = mmap(NULL, size, prot, flags, -1, 0); - switch ((int)(buf2 != MAP_FAILED)) { - case 1: - if (!cross_256mb(buf2, size)) { - /* Success! Use the new buffer. */ - munmap(buf, size); - break; - } - /* Failure. Work with what we had. */ - munmap(buf2, size); - /* fallthru */ - default: - /* Split the original buffer. Free the smaller half. */ - split_cross_256mb(&buf2, &size2, buf, size); - if (buf == buf2) { - munmap(buf + size2, size - size2); - } else { - munmap(buf, size - size2); - } - size = size2; - break; - } - buf = buf2; - } -#endif - region.start_aligned = buf; region.total_size = size; return prot; @@ -620,35 +549,15 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) void *buf_rw = NULL, *buf_rx = MAP_FAILED; int fd = -1; -#ifdef __mips__ - /* Find space for the RX mapping, vs the 256MiB regions. */ - if (alloc_code_gen_buffer_anon(size, PROT_NONE, - MAP_PRIVATE | MAP_ANONYMOUS | - MAP_NORESERVE, errp) < 0) { - return false; - } - /* The size of the mapping may have been adjusted. */ - buf_rx = region.start_aligned; - size = region.total_size; -#endif - buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); if (buf_rw == NULL) { goto fail; } -#ifdef __mips__ - void *tmp = mmap(buf_rx, size, PROT_READ | PROT_EXEC, - MAP_SHARED | MAP_FIXED, fd, 0); - if (tmp != buf_rx) { - goto fail_rx; - } -#else buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); if (buf_rx == MAP_FAILED) { goto fail_rx; } -#endif close(fd); region.start_aligned = buf_rw;