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Fri, 17 Sep 2021 02:46:19 -0400 (EDT) From: Mathew McBride To: u-boot@lists.denx.de Cc: Mathew McBride Subject: [PATCH 1/4] rtc: rx8025: drop non-DM support Date: Fri, 17 Sep 2021 06:46:01 +0000 Message-Id: <20210917064604.3912-2-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210917064604.3912-1-matt@traverse.com.au> References: <20210917064604.3912-1-matt@traverse.com.au> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean A search of the tree showed there is only one user of this driver (soon to be two) - board/socrates The second user will be the Traverse Ten64 board. Both these boards have DM_RTC. Signed-off-by: Mathew McBride --- drivers/rtc/Kconfig | 1 + drivers/rtc/rx8025.c | 80 +++----------------------------------------- 2 files changed, 6 insertions(+), 75 deletions(-) -- 2.30.1 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index b6692e62df..71777cdd05 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -136,6 +136,7 @@ config RTC_RX8010SJ config RTC_RX8025 bool "Enable RX8025 driver" + depends on DM_RTC help Support for Epson RX8025 Real Time Clock devices. diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index e717dcbbfe..36e5b0122c 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -24,22 +24,6 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#endif - -#ifdef CONFIG_DM_RTC -#define DEV_TYPE struct udevice -#else -/* Local udevice */ -struct ludevice { - u8 chip; -}; - -#define DEV_TYPE struct ludevice - -#endif - /* * RTC register addresses */ @@ -74,39 +58,22 @@ struct ludevice { * address in a first cycle that is terminated by * a STOP condition. The chips needs a 'restart' * sequence (start sequence without a prior stop). - * This driver has been written for a 4xx board. - * U-Boot's 4xx i2c driver is currently not capable - * to generate such cycles to some work arounds - * are used. */ -/* static uchar rtc_read (uchar reg); */ -#ifdef CONFIG_DM_RTC -/* - * on mpc85xx based board with DM and offset len 1 - * accessing rtc works fine. May we can drop this ? - */ #define rtc_read(reg) buf[(reg) & 0xf] -#else -#define rtc_read(reg) buf[((reg) + 1) & 0xf] -#endif -static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val); +static int rtc_write(struct udevice *dev, uchar reg, uchar val); /* * Get the current time from the RTC */ -static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) +static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp) { int rel = 0; uchar sec, min, hour, mday, wday, mon, year, ctl2; uchar buf[16]; -#ifdef CONFIG_DM_RTC if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { -#else - if (i2c_read(dev->chip, 0, 0, buf, 16)) { -#endif printf("Error reading from RTC\n"); return -EIO; } @@ -165,7 +132,7 @@ static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) /* * Set the RTC */ -static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) +static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp) { DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, @@ -201,16 +168,12 @@ static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) /* * Reset the RTC */ -static int rx8025_rtc_reset(DEV_TYPE *dev) +static int rx8025_rtc_reset(struct udevice *dev) { uchar buf[16]; uchar ctl2; -#ifdef CONFIG_DM_RTC if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { -#else - if (i2c_read(dev->chip, 0, 0, buf, 16)) { -#endif printf("Error reading from RTC\n"); return -EIO; } @@ -225,17 +188,13 @@ static int rx8025_rtc_reset(DEV_TYPE *dev) /* * Helper functions */ -static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) +static int rtc_write(struct udevice *dev, uchar reg, uchar val) { uchar buf[2]; buf[0] = reg << 4; buf[1] = val; -#ifdef CONFIG_DM_RTC if (dm_i2c_write(dev, 0, buf, 2)) { -#else - if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) { -#endif printf("Error writing to RTC\n"); return -EIO; } @@ -243,7 +202,6 @@ static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) return 0; } -#ifdef CONFIG_DM_RTC static int rx8025_probe(struct udevice *dev) { uchar buf[16]; @@ -276,31 +234,3 @@ U_BOOT_DRIVER(rx8010sj_rtc) = { .of_match = rx8025_rtc_ids, .ops = &rx8025_rtc_ops, }; -#else -int rtc_get(struct rtc_time *tm) -{ - struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, - }; - - return rx8025_rtc_get(&dev, tm); -} - -int rtc_set(struct rtc_time *tm) -{ - struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, - }; - - return rx8025_rtc_set(&dev, tm); -} - -void rtc_reset(void) -{ - struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, - }; - - rx8025_rtc_reset(&dev); -} -#endif From patchwork Fri Sep 17 06:46:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathew McBride X-Patchwork-Id: 514166 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1943958jao; Thu, 16 Sep 2021 23:46:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz1m6vhc1B3XpxgWJTmNtfzXn/bZFiGj9F3dZgMIgoSdGxoORtueq0tbj9+xRdPMvUszwtk X-Received: by 2002:a05:6402:b23:: with SMTP id bo3mr10981600edb.145.1631861209472; Thu, 16 Sep 2021 23:46:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631861209; cv=none; d=google.com; s=arc-20160816; b=zeRdLhK5npP4LAeu7EBFySHuJHkykgoIurrmjtzFYofPSD1XsmVTS9L+6gON4g1LBR 8PbKgmWHsL1sOd5gyX0b4JvmL/Lg5lao6OyV/MeOLg0cWQ1SYv44JLyCcedpcHa91uEA CbYe3h6QauLtDfzgytGesZBnJDulbdfVOk4QCiTA7TdbtAVjTUtaidbJS/K+RzQW9sDY v+ywJEJAmsJ0Nx9woT3qKAivBtKbYmoMZWiUegZt6KqCzHY1pbkyG7ERtTD34rop4FkG BhxuqIBBUNQJHgAOjwfLQMvCCbrA3GWRtAIQvjd79V6G59UdhJLxTo/SgRB0iPVdqgRn depw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dkim-signature; bh=PftpGZ1DIluCKzJ+A1TQr8FM3E85+uKOb93uJ99eiPM=; b=GY1Dul1TniJ796X4sz5B7SleBMl0RB+4OSvMcr1nAgAlDfqg1e+yneniOsHM45cEgW iQO/U3K/RuOY1jbKRicATj+lxI2jkUayo0B8peSA3f8ymdW4URFabDOHwFjCH7RzlRu6 +3iKm40ayds193dgp02wZ1iuaeVks5g8BjKwCFI1tLTQxh0qQS204OUW2Y4QQjgELLEL r7FN4JPPxogthRY1dk4VQWxQBO62h9VM1/bPC9vidE2VhXPx31tZN3BkzHLWafciAPt3 KPxS3PlGVSTKgkIi5AaJToUjDpKZjxrNTSbnjD3Cj5F8AqtM3NnlTkwspIDFt3ZtFfdd 2e2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@traverse.com.au header.s=fm1 header.b="C3sBY/Qi"; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=bUrW26vv; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Date: Fri, 17 Sep 2021 06:46:02 +0000 Message-Id: <20210917064604.3912-3-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210917064604.3912-1-matt@traverse.com.au> References: <20210917064604.3912-1-matt@traverse.com.au> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The RX8035 is a newer model from EPSON which is very similar in operation to the RX8025. The changes mirror similar ones that will be in Linux 5.15: https://lore.kernel.org/all/20210709044518.28769-2-matt@traverse.com.au/ The UBOOT_DRIVER ID has also been corrected, previously it declared itself as rx8010sj_rtc which is a different driver. Signed-off-by: Mathew McBride --- drivers/rtc/rx8025.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) -- 2.30.1 diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 36e5b0122c..09bf365f63 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -24,6 +24,11 @@ #endif /*---------------------------------------------------------------------*/ +enum rx_model { + model_rx_8025, + model_rx_8035, +}; + /* * RTC register addresses */ @@ -64,6 +69,20 @@ static int rtc_write(struct udevice *dev, uchar reg, uchar val); +static int rx8025_is_osc_stopped(enum rx_model model, int ctrl2) +{ + int xstp = ctrl2 & RTC_CTL2_BIT_XST; + /* XSTP bit has different polarity on RX-8025 vs RX-8035. + * RX-8025: 0 == oscillator stopped + * RX-8035: 1 == oscillator stopped + */ + + if (model == model_rx_8025) + xstp = !xstp; + + return xstp; +} + /* * Get the current time from the RTC */ @@ -101,8 +120,7 @@ static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp) printf("RTC: voltage drop detected\n"); rel = -1; } - - if (!(ctl2 & RTC_CTL2_BIT_XST)) { + if (rx8025_is_osc_stopped(dev->driver_data, ctl2)) { printf("RTC: oscillator stop detected\n"); rel = -1; } @@ -180,7 +198,11 @@ static int rx8025_rtc_reset(struct udevice *dev) ctl2 = rtc_read(RTC_CTL2_REG_ADDR); ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); - ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; + + if (dev->driver_data == model_rx_8035) + ctl2 &= ~(RTC_CTL2_BIT_XST); + else + ctl2 |= RTC_CTL2_BIT_XST; return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2); } @@ -223,11 +245,12 @@ static const struct rtc_ops rx8025_rtc_ops = { }; static const struct udevice_id rx8025_rtc_ids[] = { - { .compatible = "epson,rx8025" }, + { .compatible = "epson,rx8025", .data = model_rx_8025 }, + { .compatible = "epson,rx8035", .data = model_rx_8035 }, { } }; -U_BOOT_DRIVER(rx8010sj_rtc) = { +U_BOOT_DRIVER(rx8025_rtc) = { .name = "rx8025_rtc", .id = UCLASS_RTC, .probe = rx8025_probe, From patchwork Fri Sep 17 06:46:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathew McBride X-Patchwork-Id: 514169 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1944248jao; Thu, 16 Sep 2021 23:47:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzun3VROMPCKYLZWjaxA2wU11t+vbta2ZwWs2RaPVX5pkDKra6uCu90uuEwVVmsnvZqDkj0 X-Received: by 2002:a17:907:1b06:: with SMTP id mp6mr10169329ejc.188.1631861243769; Thu, 16 Sep 2021 23:47:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631861243; cv=none; d=google.com; s=arc-20160816; b=ojz354glQr40tX/1zcI4XrEP5JZLHiSMnrZq6DWKmth+271G/ikCNuaMdGriP3ekA5 pLD3ZBLD3oCLjdAD3IPUT8bdgIUsx+jEO9RqRYdxO97CzJ09iUWJkiZ1d5GgxoqaM1/h 8twBvOi6wdG1UDok53wZ+KnWOWq3O6rV4xLcjksTilmDLjxlxiEMs0DyIVIWRz99km1W sy4mtPYBo7iUo/a2WOsCoktXMF+qiuUw5jOuY5i4bDXsO9bo98FeNSh9/LTXw2zscUmH 7q1OYIZvQTFnYPeSHNoHS2zY0IPz0JAh650PRccHLFkI3TVu3Y9VSx3sgmQ7LXHGXGfd 7+KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dkim-signature; bh=MHQ0Dzp4J2auLnbQOKEqK7x6t858fjiad6JaGCsIRvU=; b=ho8e9djQIDhhGBdeyjapJtS+6zIc3jR9+1a0+rweHnKigY0RUa31wfQWwnsAwUSFdV 0GtZTQ+skVVz05Y7r1QfjWfmJGqXTfVI4+j3p+3Amlthvr+IrncDPWWZG2CyiYh3ts8A 6Dshw21d+PCnscMCUNHs6Qk0pGL5PhQD8wl76dyY1CwmeMZ7mgDktLnu8nT75yteDQHB KxMDUEANLx9I8cDr7YVIIwtyUIImi/5F839V0YZZ0Mym0olHqWNihIYy6z4fJF9HDkhd juaEZyJRT8PL/shC+Rt7bBIwwO3TbntHGqRxNK/buunNP/XjIisZDFtCSyr153j0/1xW 00Gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@traverse.com.au header.s=fm1 header.b=BicDGa8q; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=F1bePsuL; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Fri, 17 Sep 2021 02:46:22 -0400 (EDT) From: Mathew McBride To: u-boot@lists.denx.de Cc: Mathew McBride Subject: [PATCH 3/4] rtc: rx8025: set date in a single i2c transaction Date: Fri, 17 Sep 2021 06:46:03 +0000 Message-Id: <20210917064604.3912-4-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210917064604.3912-1-matt@traverse.com.au> References: <20210917064604.3912-1-matt@traverse.com.au> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The RX8025/RX8035 does not like having it's time registers set byte-by-byte in separate I2C transactions. >From the note at the top of the file, it appears target-dependent workarounds have been used in the past for this. Resolve this by setting the time registers in a single I2C transaction. As part of this, also ensure the '24/12' flag in the RTC is reset before writing the date (instead of after), otherwise the RX8035 will clear the seconds and minutes registers. Tested on Traverse Ten64 (NXP LS1088A) with RX8035. Signed-off-by: Mathew McBride --- drivers/rtc/rx8025.c | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) -- 2.30.1 diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 09bf365f63..9423a1bb82 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -39,6 +39,7 @@ enum rx_model { #define RTC_DATE_REG_ADDR 0x04 #define RTC_MON_REG_ADDR 0x05 #define RTC_YR_REG_ADDR 0x06 +#define RTC_OFFSET_REG_ADDR 0x07 #define RTC_CTL1_REG_ADDR 0x0e #define RTC_CTL2_REG_ADDR 0x0f @@ -152,6 +153,19 @@ static int rx8025_rtc_get(struct udevice *dev, struct rtc_time *tmp) */ static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp) { + /* To work around the read/write cycle issue mentioned + * at the top of this file, write all the time registers + * in one I2C transaction + */ + u8 write_op[8]; + + /* 2412 flag must be set before doing a RTC write, + * otherwise the seconds and minute register + * will be cleared when the flag is set + */ + if (rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412)) + return -EIO; + DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec); @@ -159,28 +173,16 @@ static int rx8025_rtc_set(struct udevice *dev, const struct rtc_time *tmp) if (tmp->tm_year < 1970 || tmp->tm_year > 2069) printf("WARNING: year should be between 1970 and 2069!\n"); - if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100))) - return -EIO; - - if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon))) - return -EIO; - - if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday))) - return -EIO; - - if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday))) - return -EIO; - - if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour))) - return -EIO; - - if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min))) - return -EIO; - - if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec))) - return -EIO; + write_op[RTC_SEC_REG_ADDR] = bin2bcd(tmp->tm_sec); + write_op[RTC_MIN_REG_ADDR] = bin2bcd(tmp->tm_min); + write_op[RTC_HR_REG_ADDR] = bin2bcd(tmp->tm_hour); + write_op[RTC_DAY_REG_ADDR] = bin2bcd(tmp->tm_wday); + write_op[RTC_DATE_REG_ADDR] = bin2bcd(tmp->tm_mday); + write_op[RTC_MON_REG_ADDR] = bin2bcd(tmp->tm_mon); + write_op[RTC_YR_REG_ADDR] = bin2bcd(tmp->tm_year % 100); + write_op[RTC_OFFSET_REG_ADDR] = 0; - return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); + return dm_i2c_write(dev, 0, &write_op[0], 8); } /* From patchwork Fri Sep 17 06:46:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathew McBride X-Patchwork-Id: 514168 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp1944151jao; Thu, 16 Sep 2021 23:47:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzyG83RbI56/8jD/JkklN/s3lBXlenOm5du5BSrln/XJF7UJceg5TJDCxtaHFu3NL0tr1za X-Received: by 2002:a17:906:3e08:: with SMTP id k8mr10865377eji.361.1631861232710; Thu, 16 Sep 2021 23:47:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631861232; cv=none; d=google.com; s=arc-20160816; b=IGK5vmB2wudLCDpv12LiF6kRXXtm7DelU0J660eUnYU0Iii233FutWmvjGdkkUv05T HNdm1+XtBNE2U8JgZQI6ysQiKhAhgWUhlBgz0hxVAN0D2NcKW2OdAO8dbT9gYJD06Aea dhx+5bGx4/iZgnii7HHAC3/V4EbiebzKy7c8V9fMQm7m8cGF2lBCoK81FYVTBmBivKnA A4xuKfGiHlfsCzOuwt+asOYQubrKy8i3ebIaXAdcC7NyzSstIAxtS0ayPcpuI5ZkB8Ji w2gs9SzMBuCAAD+Xwm1IWCqfr8BJz9NW/wj3mCm00GpRiSTKq2D3vFzQB3RgXdnLGufc N13Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dkim-signature; bh=UAEbbsKet/6CYBIq5uiss9Eit2a/lURi01Xr9XCB06A=; b=VqrsVbQ0WjdFpsU516cqAfwqkOxcqqT3XC7lWd8yUN+0rMkw+IIIr56FQNS+morkEW gELcSRus/BqB2XnOP8WDmif/60Aq9mJJuWwM0CSwbWvIHmZSkzFfet1kN0wjW1gha9Ub EvAANSbXyaRC+8OZnowa0sDJDSJaZZuQGnUbPbAfa4b/bfFtO7znhysAJpSYHp77CtGJ gMjlYwIPEF1CWT9WLj9qqPlko6LfdqK6ddT+eI9RcGpjCXsyGHUbCVeuiNKqeDlatnXb wjjOhuGOnSUr6m87uzsjXCc3g52607/KzZp1c1bAS/slZM+nKsxQ+cr/yl3dxg4oeCGK Yx7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@traverse.com.au header.s=fm1 header.b=pfxsJQ9i; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=lj0teugd; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Fri, 17 Sep 2021 02:46:23 -0400 (EDT) From: Mathew McBride To: u-boot@lists.denx.de Cc: Mathew McBride Subject: [PATCH 4/4] rtc: rx8025: revise single register write to use offset Date: Fri, 17 Sep 2021 06:46:04 +0000 Message-Id: <20210917064604.3912-5-matt@traverse.com.au> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210917064604.3912-1-matt@traverse.com.au> References: <20210917064604.3912-1-matt@traverse.com.au> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Writing of individual registers was not functioning correctly as a 0 'offset' byte under DM-managed I2C was being appended in front of register we wanted to access. Signed-off-by: Mathew McBride --- drivers/rtc/rx8025.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.30.1 diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 9423a1bb82..1394c2306a 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -214,11 +214,14 @@ static int rx8025_rtc_reset(struct udevice *dev) */ static int rtc_write(struct udevice *dev, uchar reg, uchar val) { - uchar buf[2]; - buf[0] = reg << 4; - buf[1] = val; + /* The RX8025/RX8035 uses the top 4 bits of the + * 'offset' byte as the start register address, + * and the bottom 4 bits as a 'transfer' mode setting + * (only applicable for reads) + */ + u8 offset = (reg << 4); - if (dm_i2c_write(dev, 0, buf, 2)) { + if (dm_i2c_reg_write(dev, offset, val)) { printf("Error writing to RTC\n"); return -EIO; }