From patchwork Fri Nov 2 19:08:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 150079 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2433954ljp; Fri, 2 Nov 2018 12:09:12 -0700 (PDT) X-Google-Smtp-Source: AJdET5dt8tS4aNwI0fWr4lKRX2sH8XC9iQ0bU7JMcKIzVb2fiC1essYYQNzssLZUTjbjESm6FGYk X-Received: by 2002:a17:902:2468:: with SMTP id m37-v6mr12972532plg.154.1541185752728; Fri, 02 Nov 2018 12:09:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541185752; cv=none; d=google.com; s=arc-20160816; b=DLNPTtr3yZabIpM/eBKYDEEiDPvdRUfLSvQQDq17ugrxtsnkeuDIEm6y7ae9+6dKrW 3rnR6BFKMOUssSHklDEZenhF0IM9d9rc4zP6EcOUFu0EPWg5dOYN+WCTj6Y9gVwQdds1 MLYozqiXG+8jtR7elUy49xix2IUMKAjnoVDMPKjayOu+DLZaEG9cVPff7OglWHo3JFnR 5LGgrKm7b1DVnNutxu6gJQAwobZzeHw+dFD1/2o8lt5LqLR56h50z8BYIKKZePTQAUEb jxdHrt8MDYglUBl2hSZVaa4bvc4pZVseEVHdDqwf1SGvaQQMSxlJEx4jThSxfl2SJFRW zzeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=n5rXuDaEHAkFW6LDykdQEBdeHgn9b95w5iCoVqi0Omg=; b=LUCuRGge9W3Zc/kG+jlxApg6W1lt8uQBmXhtSPtVLUaapMKxexcPdeWIY5gZa/o/cO JjLodbe+4H/p3CADUy2ylUX7LF3p+5jc5HsF+2SEnqrUuirIXkUYWWIZ+P7G3TaXAOJs f9ceVzKwveueBU4Xs1CMD1MUAC/8G+NKRSq3VTHCkNd4mk/FtOE9yP4wtDYzjRQtFklM HUAds31fPFPBgCkvc4GAmmZtwrLdkj8kNgU+6q2N3UWZBAQxk13gWDFyFQ6fGkJswmwV b1f9GdQtfl1pd94FOk54lnfObgp+Xp9WTZuZntwthQCmNKV/3xFcaU2Ol579MOJe8/AB 6uWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PsVrQgNf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z11-v6si34718316pgf.66.2018.11.02.12.09.12; Fri, 02 Nov 2018 12:09:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PsVrQgNf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726869AbeKCERa (ORCPT + 32 others); Sat, 3 Nov 2018 00:17:30 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:51798 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725728AbeKCERa (ORCPT ); Sat, 3 Nov 2018 00:17:30 -0400 Received: by mail-wm1-f66.google.com with SMTP id w7-v6so2878327wmc.1 for ; Fri, 02 Nov 2018 12:09:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n5rXuDaEHAkFW6LDykdQEBdeHgn9b95w5iCoVqi0Omg=; b=PsVrQgNfaLhnEDvTl5n5EKW2y3IWdusohE/I75tigkTc15taDY2nE/wcnS08gQ4mDK eryWgL4JvX3Ov9GDRFzpBTidlRsUaQyYLsEWhsT+rUoeEcvYQ9OipnoLmSp6DLB97w0G ywtxM/spcMzmwaxvD2l90A7XeRQ1wdC+ENnJI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n5rXuDaEHAkFW6LDykdQEBdeHgn9b95w5iCoVqi0Omg=; b=owKcetrwGV7Oenyeu216H+W9JPyCAtHOz0FftB4DgniwmcuTP+lfVzu/6YsqbWRdsZ JUobEErOtTPubKPaJCbrER69GdEoDdpqogxWQJWk8RIWS5xwQkbAk3mLUZD1kG5d43E3 kLeNbZmSYUFIbsedS6NECaxlFGe2gpMiIxYyd99WWLY0OiBGdeSa9aFG6LuwL1b3UV8+ 7VuYqAmV24kNeZ78hMoUQXntiu71uiI67R0gKBPq28kDKl9zq3ktzY73FBLaR89UaDZm KGaH7Hvk3UMTMPG0zkcQjazxOSf3exliVuYlI5YgpPwE0L4J0JZw1fZA4psI6uOL+j0o ipOA== X-Gm-Message-State: AGRZ1gI9wtCYLGuxNDzreweZDAHpmHSTfQS6H+JDeh/c4JOc4aQbmBqP sWAcMMSMFuwPluKVMc8sXpu++A== X-Received: by 2002:a1c:a905:: with SMTP id s5-v6mr154989wme.75.1541185748291; Fri, 02 Nov 2018 12:09:08 -0700 (PDT) Received: from localhost.localdomain ([80.125.186.228]) by smtp.gmail.com with ESMTPSA id s195-v6sm3899337wmd.39.2018.11.02.12.09.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Nov 2018 12:09:07 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, arnd@arndb.de, ren_guo@c-sky.com Subject: [PATCH 1/4] clocksource/drivers/c-sky: Add C-SKY SMP timer Date: Fri, 2 Nov 2018 20:08:55 +0100 Message-Id: <1541185738-8208-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren The driver is for C-SKY SMP timer. It only supports oneshot event and 32bit overflow for clocksource. Per cpu core has one timer and all timers share one clock-counter-input from the same clocksource. This use mfcr&mtcr instructions to access the regs. Signed-off-by: Guo Ren Cc: Daniel Lezcano Cc: Thomas Gleixner Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 10 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-mp-csky.c | 173 ++++++++++++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 185 insertions(+) create mode 100644 drivers/clocksource/timer-mp-csky.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a11f4ba..591c9a8 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -620,4 +620,14 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems. +config CSKY_MP_TIMER + bool "SMP Timer for the C-SKY platform" if COMPILE_TEST + depends on CSKY + select TIMER_OF + help + Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP + system. + csky,mptimer is not only used in SMP system, it also could be used + single core system. It's not a mmio reg and it use mtcr/mfcr instruction. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index db51b24..5ce82d3 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -79,3 +79,4 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o +obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o diff --git a/drivers/clocksource/timer-mp-csky.c b/drivers/clocksource/timer-mp-csky.c new file mode 100644 index 0000000..a8acc43 --- /dev/null +++ b/drivers/clocksource/timer-mp-csky.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +#define PTIM_CCVR "cr<3, 14>" +#define PTIM_CTLR "cr<0, 14>" +#define PTIM_LVR "cr<6, 14>" +#define PTIM_TSR "cr<1, 14>" + +static int csky_mptimer_irq; + +static int csky_mptimer_set_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + mtcr(PTIM_LVR, delta); + + return 0; +} + +static int csky_mptimer_shutdown(struct clock_event_device *ce) +{ + mtcr(PTIM_CTLR, 0); + + return 0; +} + +static int csky_mptimer_oneshot(struct clock_event_device *ce) +{ + mtcr(PTIM_CTLR, 1); + + return 0; +} + +static int csky_mptimer_oneshot_stopped(struct clock_event_device *ce) +{ + mtcr(PTIM_CTLR, 0); + + return 0; +} + +static DEFINE_PER_CPU(struct timer_of, csky_to) = { + .flags = TIMER_OF_CLOCK, + .clkevt = { + .rating = 300, + .features = CLOCK_EVT_FEAT_PERCPU | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = csky_mptimer_shutdown, + .set_state_oneshot = csky_mptimer_oneshot, + .set_state_oneshot_stopped = csky_mptimer_oneshot_stopped, + .set_next_event = csky_mptimer_set_next_event, + }, +}; + +static irqreturn_t csky_timer_interrupt(int irq, void *dev) +{ + struct timer_of *to = this_cpu_ptr(&csky_to); + + mtcr(PTIM_TSR, 0); + + to->clkevt.event_handler(&to->clkevt); + + return IRQ_HANDLED; +} + +/* + * clock event for percpu + */ +static int csky_mptimer_starting_cpu(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&csky_to, cpu); + + to->clkevt.cpumask = cpumask_of(cpu); + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), + 2, ULONG_MAX); + + enable_percpu_irq(csky_mptimer_irq, 0); + + return 0; +} + +static int csky_mptimer_dying_cpu(unsigned int cpu) +{ + disable_percpu_irq(csky_mptimer_irq); + + return 0; +} + +/* + * clock source + */ +static u64 sched_clock_read(void) +{ + return (u64)mfcr(PTIM_CCVR); +} + +static u64 clksrc_read(struct clocksource *c) +{ + return (u64)mfcr(PTIM_CCVR); +} + +struct clocksource csky_clocksource = { + .name = "csky", + .rating = 400, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .read = clksrc_read, +}; + +static int __init csky_mptimer_init(struct device_node *np) +{ + int ret, cpu, cpu_rollback; + struct timer_of *to = NULL; + + /* + * Csky_mptimer is designed for C-SKY SMP multi-processors and + * every core has it's own private irq and regs for clkevt and + * clksrc. + * + * The regs is accessed by cpu instruction: mfcr/mtcr instead of + * mmio map style. So we needn't mmio-address in dts, but we still + * need to give clk and irq number. + * + * We use private irq for the mptimer and irq number is the same + * for every core. So we use request_percpu_irq() in timer_of_init. + */ + csky_mptimer_irq = irq_of_parse_and_map(np, 0); + if (csky_mptimer_irq <= 0) + return -EINVAL; + + ret = request_percpu_irq(csky_mptimer_irq, csky_timer_interrupt, + "csky_mp_timer", &csky_to); + if (ret) + return -EINVAL; + + for_each_possible_cpu(cpu) { + to = per_cpu_ptr(&csky_to, cpu); + ret = timer_of_init(np, to); + if (ret) + goto rollback; + } + + clocksource_register_hz(&csky_clocksource, timer_of_rate(to)); + sched_clock_register(sched_clock_read, 32, timer_of_rate(to)); + + ret = cpuhp_setup_state(CPUHP_AP_CSKY_TIMER_STARTING, + "clockevents/csky/timer:starting", + csky_mptimer_starting_cpu, + csky_mptimer_dying_cpu); + if (ret) + return -EINVAL; + + return 0; + +rollback: + for_each_possible_cpu(cpu_rollback) { + if (cpu_rollback == cpu) + break; + + to = per_cpu_ptr(&csky_to, cpu_rollback); + timer_of_cleanup(to); + } + return -EINVAL; +} +TIMER_OF_DECLARE(csky_mptimer, "csky,mptimer", csky_mptimer_init); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index caf40ad..e0cd2ba 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -126,6 +126,7 @@ enum cpuhp_state { CPUHP_AP_MIPS_GIC_TIMER_STARTING, CPUHP_AP_ARC_TIMER_STARTING, CPUHP_AP_RISCV_TIMER_STARTING, + CPUHP_AP_CSKY_TIMER_STARTING, CPUHP_AP_KVM_STARTING, CPUHP_AP_KVM_ARM_VGIC_INIT_STARTING, CPUHP_AP_KVM_ARM_VGIC_STARTING, From patchwork Fri Nov 2 19:08:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 150080 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2433990ljp; Fri, 2 Nov 2018 12:09:15 -0700 (PDT) X-Google-Smtp-Source: AJdET5etdHuQ6xY1s/vEm0m62cW7/BR5MCWaROp/LEfD1r7xUhzYV20waz5sAUJsvowigsjAT99M X-Received: by 2002:a62:6b41:: with SMTP id g62-v6mr12841516pfc.106.1541185755224; Fri, 02 Nov 2018 12:09:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541185755; cv=none; d=google.com; s=arc-20160816; b=okcg8CQOlTShRY+utVO8SFzo90ypg2UImCQXhYUvjJFAAOF7JaSWGc7fShRyCbj2Or txsurqNNcBKGqD5nM6ugPr/xVQQrCKwcRVzAuJlcr7B/SKTNj+9ewL5FXfSCeXXSzA32 EnlLm+GLm+AYCY1pj8CJp2ndi76XhNtaDuqr7j3b+lQ/BIFE0jQ96KLyzpxc4/01CtmL yDNOXCK2YuyX5VV8D489VDicShA2ngm7suz1oqncVeV0hArJWQOITyAWFhcyHi2+Gpwp 0Ge8l1VUul+Gp2vWzKVs5Bnsu9RZBr7dfeeMlI1L+cy/dmwTGX/oRm6Kelq+YlT5/nfu ztQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=AYhygTC2wYv/caLmoYMF60fvpB/eiIKLPujtWer++2M=; b=FLG2L3701eHFgMQQehKkAxJ1AoRcp2Cg59o/mdajfroVlyX2PPfwxnxbz7wIPJREts nSZfEvGuH49pqoWiTLoT+dOjxapzuGySKRjz+8De76YESjEX5d9ZiRFOO5jA3U4rRGjv a1JOWTXI5Hazf4BvevPzy2w28CAPEd0OCDY63bkvlUPUN2EYs99JS9TlGTeiL0RGxh18 fPoL62Ddh8RxRuckD7IrqT1jfDZ3Ttg9DIi0G7tWzNZBXXrHbfo68hx86SVbcKgSFLEJ 6noYvbwu2TdGx62kodYrtnjrwk3jHARh93lo04SbpyitX+DTI28YGM0SZUdfCg1X55bu CO3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kYEmU2t9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Guo Ren Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/csky,mptimer.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/csky,mptimer.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt b/Documentation/devicetree/bindings/timer/csky,mptimer.txt new file mode 100644 index 0000000..15cfec0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,mptimer.txt @@ -0,0 +1,42 @@ +============================ +C-SKY Multi-processors Timer +============================ + +C-SKY multi-processors timer is designed for C-SKY SMP system and the +regs is accessed by cpu co-processor 4 registers with mtcr/mfcr. + + - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. + - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. + - PTIM_CCVR "cr<3, 14>" Current counter value reg. + - PTIM_LVR "cr<6, 14>" Window value reg to triger next event. + +============================== +timer node bindings definition +============================== + + Description: Describes SMP timer + + PROPERTIES + + - compatible + Usage: required + Value type: + Definition: must be "csky,mptimer" + - clocks + Usage: required + Value type: + Definition: must be input clk node + - interrupts + Usage: required + Value type: + Definition: must be timer irq num defined by soc + +Examples: +--------- + + timer: timer { + compatible = "csky,mptimer"; + clocks = <&dummy_apb_clk>; + interrupts = <16>; + interrupt-parent = <&intc>; + }; From patchwork Fri Nov 2 19:08:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 150081 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2434049ljp; Fri, 2 Nov 2018 12:09:18 -0700 (PDT) X-Google-Smtp-Source: AJdET5eMYxAY8AVlGVtZnrSINizvAZVJto7xqxBqmIFsKVjDtU4f4oYkkWYGiX3IzH+9HiV12Paq X-Received: by 2002:a17:902:3381:: with SMTP id b1-v6mr12711344plc.323.1541185758290; Fri, 02 Nov 2018 12:09:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541185758; cv=none; d=google.com; s=arc-20160816; b=STkcdQ4tmcNtQgv8vWrLaONLH2hxcr9NPT/p82aoL0tHtOpqd6a39iweL3QBjHSNIl jdoBe33iLCMmiQprvwAY7PLVF9cTQ4ePjuvhQgh0rk2PL9R8O9twFA3giekhK6+g998U UsqyYV0gNRFaeTiSEk/RCjuunpABqPrzKwvhx85NNdlfPKZyE3C+AtRO4RdGuCzBxCed QZFAS7yJ+t5vGgp/1siPi68YHU6nZebz9GRC38lzTaKw4Jq38iEK2HQMOq+mzwuPdw9q kw752xLuCrx0fjkt8cq1pfw8djvCM7nuOuDeyB0WrhwuHRXIAga3JmgzN17QPLPx3Fkh Oo5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=DTGYor+aDoY+YYD6WunsmjKGozWWt6wj8+L/EBCu/QY=; b=Hxm+5chsId35enrFX3bGVww/AqPnGwPRZv0Nllctd+1O9yjYQbSqeJ8M2tTGm9k4ei 7Et2S6GV1VgJH25Gl+eowy86K2Nr9wVNz92CAMifLlWh7J0wjDut+SLYt0Pc40VCX9WY YPVf6ltj9LEZ3Y7LpEbbs0uVA3w3QoevtF0t+axjJ3LPRUq7nFeEi460wqnyMMzXfKl5 9HPb5k1JjRJuolk2KRZnh4SGK0p6EKpZBf63b1vzoMv4r4h4kll2HXLAfGigQI9Bh6Ga j7YttWnU6Pt9+xESLKGQdQiac8IDNsyNH6SHBmKOyMH65IYWAoTYwtQP3N52zYyI97f8 92jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JdZeDslg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z72-v6si37649549pgz.323.2018.11.02.12.09.18; Fri, 02 Nov 2018 12:09:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JdZeDslg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728390AbeKCERf (ORCPT + 32 others); Sat, 3 Nov 2018 00:17:35 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:37142 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726926AbeKCERd (ORCPT ); Sat, 3 Nov 2018 00:17:33 -0400 Received: by mail-wr1-f66.google.com with SMTP id z3-v6so3032521wru.4 for ; Fri, 02 Nov 2018 12:09:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DTGYor+aDoY+YYD6WunsmjKGozWWt6wj8+L/EBCu/QY=; b=JdZeDslg1NcvtvSbCV5f/2STVqO82V6hl3mZLUxfXdZPyuT7kkpoW/WD2xtsyAk5Pz f1w6kcWdYaUdyURUlZupD/Y0JA7D7SGXdh4HDLdCoTY8zcciRELOxdjlHGwPNscy3k1a eCgbrcyg0F1WhthAEYpWajLNXijaBgtwH5aKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DTGYor+aDoY+YYD6WunsmjKGozWWt6wj8+L/EBCu/QY=; b=Nl5YMvIX/0x6qzv+g+dOzhkexO7FPlH51vt/IzLbLxnTvK9s18j6o7ruwn1z1ky7Ih IUxXJrgIWj7XJZeAec2IMDCQ67CQ6156V7qEywSSMMOpVyMDbW3ueSd36FMrSiZf3msc zsGeAJtBLtzLbLuUYg8+w4BoU6lDeRSMJIGpfJS5L+woI/PqTUNeuCX1IYouAkNOQJiJ 5kqXsYRIt1dtu0gAutvlK+0TEb3ywJ36UALTVzFkDA/tHs/fL22fYM7FicAMssfUSNTd OnEd3CIt/P4ieh74bw0jDxWQGmHORif4or4SierlB+dsPYPHFf3SjlVnj67xrK+xoyo2 Nj7A== X-Gm-Message-State: AGRZ1gJAjduDM5Zx7UCaWe+OOatQpp55TwU0zXDycbNdbcP3LfqTe/UR ymphYLSmWLnieTNjFSA4ewwaO+JFDr4= X-Received: by 2002:adf:ecc5:: with SMTP id s5-v6mr1726370wro.208.1541185751317; Fri, 02 Nov 2018 12:09:11 -0700 (PDT) Received: from localhost.localdomain ([80.125.186.228]) by smtp.gmail.com with ESMTPSA id s195-v6sm3899337wmd.39.2018.11.02.12.09.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Nov 2018 12:09:10 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, arnd@arndb.de, ren_guo@c-sky.com Subject: [PATCH 3/4] clocksource/drivers/c-sky: Add gx6605s SOC system timer Date: Fri, 2 Nov 2018 20:08:57 +0100 Message-Id: <1541185738-8208-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541185738-8208-1-git-send-email-daniel.lezcano@linaro.org> References: <1541185738-8208-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren The driver is for gx6605s SOC system timer and there are two same timers in gx6605s. We use one for clkevt and another one for clksrc. The timer is mmio map to access, so we need give mmio address in dts. The counter at 0x0 offset is clock event. The counter at 0x40 offset is clock source. Signed-off-by: Guo Ren Cc: Daniel Lezcano Cc: Thomas Gleixner Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 154 ++++++++++++++++++++++++++++++++++++ 3 files changed, 163 insertions(+) create mode 100644 drivers/clocksource/timer-gx6605s.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 591c9a8..55c77e4 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -630,4 +630,12 @@ config CSKY_MP_TIMER csky,mptimer is not only used in SMP system, it also could be used single core system. It's not a mmio reg and it use mtcr/mfcr instruction. +config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" if COMPILE_TEST + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s SOC's timer. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5ce82d3..9196331 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -80,3 +80,4 @@ obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o +obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o diff --git a/drivers/clocksource/timer-gx6605s.c b/drivers/clocksource/timer-gx6605s.c new file mode 100644 index 0000000..80d0939 --- /dev/null +++ b/drivers/clocksource/timer-gx6605s.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include +#include +#include + +#include "timer-of.h" + +#define CLKSRC_OFFSET 0x40 + +#define TIMER_STATUS 0x00 +#define TIMER_VALUE 0x04 +#define TIMER_CONTRL 0x10 +#define TIMER_CONFIG 0x20 +#define TIMER_DIV 0x24 +#define TIMER_INI 0x28 + +#define GX6605S_STATUS_CLR BIT(0) +#define GX6605S_CONTRL_RST BIT(0) +#define GX6605S_CONTRL_START BIT(1) +#define GX6605S_CONFIG_EN BIT(0) +#define GX6605S_CONFIG_IRQ_EN BIT(1) + +static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev) +{ + struct clock_event_device *ce = dev; + void __iomem *base = timer_of_base(to_timer_of(ce)); + + writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); + + ce->event_handler(ce); + + return IRQ_HANDLED; +} + +static int gx6605s_timer_set_oneshot(struct clock_event_device *ce) +{ + void __iomem *base = timer_of_base(to_timer_of(ce)); + + /* reset and stop counter */ + writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); + + /* enable with irq and start */ + writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, + base + TIMER_CONFIG); + + return 0; +} + +static int gx6605s_timer_set_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + void __iomem *base = timer_of_base(to_timer_of(ce)); + + /* use reset to pause timer */ + writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); + + /* config next timeout value */ + writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); + writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); + + return 0; +} + +static int gx6605s_timer_shutdown(struct clock_event_device *ce) +{ + void __iomem *base = timer_of_base(to_timer_of(ce)); + + writel_relaxed(0, base + TIMER_CONTRL); + writel_relaxed(0, base + TIMER_CONFIG); + + return 0; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + .clkevt = { + .rating = 300, + .features = CLOCK_EVT_FEAT_DYNIRQ | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = gx6605s_timer_shutdown, + .set_state_oneshot = gx6605s_timer_set_oneshot, + .set_next_event = gx6605s_timer_set_next_event, + .cpumask = cpu_possible_mask, + }, + .of_irq = { + .handler = gx6605s_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static u64 notrace gx6605s_sched_clock_read(void) +{ + void __iomem *base; + + base = timer_of_base(&to) + CLKSRC_OFFSET; + + return (u64)readl_relaxed(base + TIMER_VALUE); +} + +static void gx6605s_clkevt_init(void __iomem *base) +{ + writel_relaxed(0, base + TIMER_DIV); + writel_relaxed(0, base + TIMER_CONFIG); + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2, + ULONG_MAX); +} + +static int gx6605s_clksrc_init(void __iomem *base) +{ + writel_relaxed(0, base + TIMER_DIV); + writel_relaxed(0, base + TIMER_INI); + + writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); + + writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG); + + writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); + + sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to)); + + return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s", + timer_of_rate(&to), 200, 32, clocksource_mmio_readl_up); +} + +static int __init gx6605s_timer_init(struct device_node *np) +{ + int ret; + + /* + * The timer driver is for nationalchip gx6605s SOC and there are two + * same timer in gx6605s. We use one for clkevt and another for clksrc. + * + * The timer is mmio map to access, so we need give mmio address in dts. + * + * It provides a 32bit countup timer and interrupt will be caused by + * count-overflow. + * So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg. + * + * The counter at 0x0 offset is clock event. + * The counter at 0x40 offset is clock source. + * They are the same in hardware, just different used by driver. + */ + ret = timer_of_init(np, &to); + if (ret) + return ret; + + gx6605s_clkevt_init(timer_of_base(&to)); + + return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET); +} +TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init); From patchwork Fri Nov 2 19:08:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 150082 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2434087ljp; Fri, 2 Nov 2018 12:09:20 -0700 (PDT) X-Google-Smtp-Source: AJdET5eM34PmYSI/XV8QH7puO3wUNQl0Ift3ogVYbrKF/INNit1HidMtbVerQaZFGThUS1kzOtTa X-Received: by 2002:a17:902:1ea:: with SMTP id b97-v6mr13126430plb.152.1541185760183; Fri, 02 Nov 2018 12:09:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541185760; cv=none; d=google.com; s=arc-20160816; b=cMkE144KSpGLdN6OIUUHrjlTHh1zNM/f1600tF+qLP443rLP/5b/O4H8hDjTgkRhoR le38hIwg99YaXXkjk9nBk4B/q7fsHQ4Im3sco4VPWZ5QY1b6SMai+C6Ha3fRsM6fo2OX q+HYFwTz6GvJP+oMSB/W9D+7xmi4GHzvN0E7Lmg1wa48wfaJXpe2Fle+cOWlQ2mSNQLg v4YHk90bCAtbf+z610PLO7Xp2UYq71t/zZc6rsEu4h2MNpTU4uNPjEwhGYIiku/CeQKU zVrfottpV71NQr56EF6nE+AUDen1pnVmmSN+eacoHzUzcFlwAi3ompiEEGrIufasUy2/ oOLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Cs/HdsgXrRlb81nkVaefoI3h8zuKKKj/56RKUVVtQxY=; b=CW5+Nb3Q27DRGVmQltyYYr2+BWDCbDl22VnZazHHCIftXmmqLVB/Jm3UBcf7p4jqcB g5LWSXGaxKPKrUpuTv6t+mNbbYAqLij6GWUn51uPyzuwgTFv80w8lqGTz1CK8rOD80uW 4H58TOSb9bG3+sSMEglpA67s+KtQcuXfYUe4iCdLGxdBZIHKIDqCPwR0MEXqVgj/GjME mvs0Heh/agMZswHRol3xsKVS2TmeB17Wq9t58P/eMYlHs40uG6ew7Y0vZ/5sQECgJS8L yJGjqkZXM2ynu7rGUOfrKm72T6nnoMFVsEJILZsLOdrOw0ltBq/cAyJWp+2uM901RHrL prVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RGdtU/gD"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x11-v6si17477353pgp.592.2018.11.02.12.09.19; Fri, 02 Nov 2018 12:09:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RGdtU/gD"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728540AbeKCERg (ORCPT + 32 others); Sat, 3 Nov 2018 00:17:36 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33710 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726051AbeKCERf (ORCPT ); Sat, 3 Nov 2018 00:17:35 -0400 Received: by mail-wm1-f65.google.com with SMTP id f19-v6so1837283wmb.0 for ; Fri, 02 Nov 2018 12:09:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cs/HdsgXrRlb81nkVaefoI3h8zuKKKj/56RKUVVtQxY=; b=RGdtU/gDTXeH0/chT7ehctiXFFGrPalMWu1QBCdTU0yCFeBGarEi9G6CC3koHGZCdb lDZwpPgYmXvoWeAi0PzVtjMlxmEFQRCEtBUrTmMDXXor0gUqWMFV8aL2qVP1XvEn9P9N EG/ocwbCPVNQVyrXftndTAesZZkK/Hr9amPyU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cs/HdsgXrRlb81nkVaefoI3h8zuKKKj/56RKUVVtQxY=; b=Dirij63xR1hAkbBZ5MQG4y+uw9qts9HcdDPWNtb8DJUp73asYsOObwV/ZI+9mwMphu O7p6Kh5+Xf2NISy7I63RLqTQS7yNMRWwYoRtHIg6gkoyuKGQTYyCeTs1T4YAj3PyrnZe lU14gzvHBIHzFwnMn3PyMAtgYw2mFnQXWy/ErK3S7XGV4r+SVM2RT7geqj/m3gLC4kL4 4KoG51uSzI0v+Yyxo5dqD5CHw6hi30EZIHGu9pOYw4W+Ddvs4CmLMitD5ykJaVwm+4tu K6Al+/KPzEQxOiAe48/f1k5tUMzGteTL9B7NDj+o9Cgg1jXcpRnAHTstdco7ZI+Il/QI A26Q== X-Gm-Message-State: AGRZ1gKE39dkEgUwoSeuBipB1gQqCkEJ00j2mpfReiJkBvXrbByEy3gL DIUJTYHeIVcBBoY7U10lLgii3q5ok6o= X-Received: by 2002:a1c:f60f:: with SMTP id w15-v6mr162627wmc.101.1541185752982; Fri, 02 Nov 2018 12:09:12 -0700 (PDT) Received: from localhost.localdomain ([80.125.186.228]) by smtp.gmail.com with ESMTPSA id s195-v6sm3899337wmd.39.2018.11.02.12.09.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Nov 2018 12:09:11 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, arnd@arndb.de, ren_guo@c-sky.com Subject: [PATCH 4/4] dt-bindings: timer: gx6605s SOC timer Date: Fri, 2 Nov 2018 20:08:58 +0100 Message-Id: <1541185738-8208-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541185738-8208-1-git-send-email-daniel.lezcano@linaro.org> References: <1541185738-8208-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren Dt-bindings doc for gx6605s SOC's system timer. Signed-off-by: Guo Ren Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../bindings/timer/csky,gx6605s-timer.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt new file mode 100644 index 0000000..6b04344 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt @@ -0,0 +1,42 @@ +================= +gx6605s SOC Timer +================= + +The timer is used in gx6605s soc as system timer and the driver +contain clk event and clk source. + +============================== +timer node bindings definition +============================== + + Description: Describes gx6605s SOC timer + + PROPERTIES + + - compatible + Usage: required + Value type: + Definition: must be "csky,gx6605s-timer" + - reg + Usage: required + Value type: + Definition: in soc from cpu view + - clocks + Usage: required + Value type: phandle + clock specifier cells + Definition: must be input clk node + - interrupt + Usage: required + Value type: + Definition: must be timer irq num defined by soc + +Examples: +--------- + + timer0: timer@20a000 { + compatible = "csky,gx6605s-timer"; + reg = <0x0020a000 0x400>; + clocks = <&dummy_apb_clk>; + interrupts = <10>; + interrupt-parent = <&intc>; + };