From patchwork Thu Sep 30 15:11:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514904 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp268176jam; Thu, 30 Sep 2021 08:18:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsLQmZX7/cV2KIkHsPuNmoy9ctRx9qWZ9igFEtMExmWUKyHgOfvpUgTenKbSHDSEpGGfEj X-Received: by 2002:a2e:98c3:: with SMTP id s3mr6783284ljj.430.1633015111225; Thu, 30 Sep 2021 08:18:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015111; cv=none; d=google.com; s=arc-20160816; b=QMI9Vwv0Rr81vQimreTSK/ESV70PtIdyGLJwcYkTueJV/hnlKH23NeKzzPMHPKtDiT GNTeY7NJ3oussADPjR2458AI49BwjJdSFuWr7oFKux+qdzj8Ycieg/Aq8YJY1qiWEMKh b/fgr9h5ENWSJyBxhDRt8UDVG5iZiHHTrxcgcThBGfjugVuAf/dlwpPZToraeUVPKatB WhMYgX3vyyRhdF36R/B6Puwb4TxGGSzAwRd/eIz975coDqMXroXcQ1ahRlXBuAFqqEj0 8cHdTbNGvvYPMbWN/N7hSgEBa85RbUnG3T3OTMk8nmtaUua4Og6YkJTgdgC4zfG9xgCL Y8Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GM2JxCRaBytatr1OYZoPy0AOg6Otwsdfxo/5ZWRKoz0=; b=MGLnpdzVmt328xaVUYJWCzfKpfB21oVWjfQkKCVUi8mgeOFBx/wtsX2DCbvqrC3fX4 m5X/v/GenLe8yPjPQIRg2zhQfF46zMTt8WMWHWZQqRhTzf1b0TSkCPl5HGQDFHfP08yw 2ymjiFWip602DWi68d0aqpXsFTOAUwFU4y1rKUOSbibOkZ2Yp9zwd7H4+6gJ85C4CWwS Z0c4HJ+nC4D+oFbBNJsUMMYJeE0nHmDzd39rXnXPsgyuZw5FgtvYSYrCUmRvjvZykwJm zvpMrgp3SR5Zn5t564aJr24V0EWcuiei4sL8b+xQpLjTANFCcsCPgXpEpbDEgrIWKxUm sI2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xY/HKGGf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s2si3623920edy.8.2021.09.30.08.18.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:18:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xY/HKGGf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxpO-0007KJ-6I for patch@linaro.org; Thu, 30 Sep 2021 11:18:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjE-0008WS-Nj for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:10 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjC-0003sq-BZ for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:08 -0400 Received: by mail-wr1-x434.google.com with SMTP id w29so10651914wra.8 for ; Thu, 30 Sep 2021 08:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GM2JxCRaBytatr1OYZoPy0AOg6Otwsdfxo/5ZWRKoz0=; b=xY/HKGGf3T8nrKMXw3W5mRRRmX0Uiv3gxCZrDe9nsDaNkrI1ppe6Wdlh1BY1BmILRF gOtnWss4MZUquj7CMtC3W/1YXd5zFNbXZSAdNHhLutlUMiX19xgs5QEXnETSviuQYDXX L5Y2GIRE8A1hccOrtvOtSmC/YUVlNrvsFRNFSquFcn1vj1LbRQ409TL6yygTK8YJ9mf7 3dd3ZCx6yuGyYu719uYmTZXTLYASJHXyyitLVHE569x+7MFHHsUTQwrlTg46Tbjh9SHI RFkmEhO82EW9COgMEjcHJN90EyH1zDTm4Bo30UsPMctVwuQv0gTq5bq11XSM0y/hOLdV VkeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GM2JxCRaBytatr1OYZoPy0AOg6Otwsdfxo/5ZWRKoz0=; b=O8c7nXw5q5PXGtIQvqyGi4EuL0zeVEAcUnjPcwY+XjS23NAK0cROhFFqddm1UdFuJ/ vOUl5yPCOru/IwGvm5BaWtMUVbOgXu06SdUpqse81lm2ouTV0k8sMYA7h5ekRTcs8dnJ 016CyK9etmxtMbhYbEqvOHaAVduFgLqcgfj9Uq6APXxi8WseZhEY4YejHcRpyiqaQz7M L8Y3bISNY93fo3Zrq9yHQCw78/8ZJe+TB/24KW1hDhAlmdwnNiuQbFXLxlD/3mV5sec5 vZA21yoR9JeG/Wxv21YunueqE0DMJV9zrbWZAhEJ+1gtbDrJoGn8twSy/itRQoucEP67 gPPw== X-Gm-Message-State: AOAM532tDVpvV5my4Rd6+JL/7ua/G8SZrqCibkI17qMoaCAju0YPZbTX KOGN+FDaoqkPVelmCw7ZX857cTIb2Mw9UA== X-Received: by 2002:adf:fe89:: with SMTP id l9mr6867795wrr.0.1633014724350; Thu, 30 Sep 2021 08:12:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit Date: Thu, 30 Sep 2021 16:11:40 +0100 Message-Id: <20210930151201.9407-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization. However, today we are configuring QEMU to use HVC as PSCI conduit. That means HVC calls get trapped into QEMU instead of the guest's own emulated CPU and thus break the guest's ability to execute virtualization. Fix this by moving to SMC as conduit, freeing up HYP completely to the VM. Signed-off-by: Alexander Graf Message-id: 20210920203931.66527-1-agraf@csgraf.de Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip") Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/arm/allwinner-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 27f10701453..f9b7ed18711 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -237,7 +237,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) /* Provide Power State Coordination Interface */ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", - QEMU_PSCI_CONDUIT_HVC); + QEMU_PSCI_CONDUIT_SMC); /* Disable secondary CPUs */ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", From patchwork Thu Sep 30 15:11:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514906 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp270723jam; Thu, 30 Sep 2021 08:20:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyE6k+cJgsltbBQonfh6khmYe5+gjb1g8al9jVRjLDqEeZPPSqPt0sqcFDaY0KxFgWVaMji X-Received: by 2002:a5d:56cf:: with SMTP id m15mr6795377wrw.240.1633015256783; Thu, 30 Sep 2021 08:20:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015256; cv=none; d=google.com; s=arc-20160816; b=M8RoOppBPUdxGU9vkcVERO+6PL3lLy82PN0q0cGSIcwTmTVbS+4f8zyQCS4mEE0CEj k34Hw8fgPdQnb16pmBpTLN2xqgF5sIbxShuij2OX0cfYjVioRm8s3oCSt7osh+qZtrxi RjGjptCGDWKX79O73FzdK2ywmo1QzwtlyfgnTjfYEpLuhCBcCWRa3P8zb9BwQZf+G2H3 nMFVqpuGjrnJPL8V0daoIMdH6T4woo9XsYmw6Ltoxe9W6sMzB64c47GzIEGdgUTP3Qg7 jz2PoZU+YDQQqmcSmNCnN8pRmEmwLLrdXUKZ32O3111gCOc3S0YhLyUL44L8C8ydi29D PlVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0GE2AGcFHy79W+XlJkL7M8hbutjaw0ssS0YKptIt1WQ=; b=gaftq/1mGaQLEPqxIzP/+RzuJIn92TNZWg24atYeQb2qUjzkw11YSEfDhIiPsUmBK8 JeCTVaE2Mh9nqviz4ev2rYIaj8zUo3O5SAT7uicHnooKxXobcZflYwbUpLVc44kG+s4h lqrBt1iyVEP+h8psL4uCdn+yRlHt/Y3SPcR7VNRbEpn3u3MEsW4EADmcrJCvbf73PdSK iotLnhm/eGo1OU7XaVyml/4MJxxesP0fYQbsEUbr2Y5kvYv1aIVNNGBjS7bsid8/dkeX q6fiTazbHwjDRHV0qdMncbp8Nuldt95dbTiM8YIlANbpPGtqL3xpO+g+76Czn3Tq92Zy 2W8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=byq43GK5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m12si5054146wmg.232.2021.09.30.08.20.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:20:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=byq43GK5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxrj-0003Gm-Ky for patch@linaro.org; Thu, 30 Sep 2021 11:20:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjE-0008WT-TQ for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:10 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjC-0003tR-CG for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:08 -0400 Received: by mail-wr1-x42d.google.com with SMTP id t8so10711990wri.1 for ; Thu, 30 Sep 2021 08:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0GE2AGcFHy79W+XlJkL7M8hbutjaw0ssS0YKptIt1WQ=; b=byq43GK5WXv51v9fdv3pVuZScJxE6hi+pEh5wM12U+r8+pUn+VQMRxvWD8VtY6pyYl VD1Vf/JAuml3wEMfS7kKOH8w2q7Gyd1uusGeHHpQNshroQzMaa9Qjk+zlW4FptvioASA g/VcJVnN2ZGU+8itKrNaLC7rP9kDS3EpucUcUuXzt5b0nC7Acag/9rZiYbcX5bi4NX+R ps6Yex2HLD5feQ1uTzrxuSqws0L2Fk3FPACI6CBPzvNsBNC+cgfoHMIgJrSLC9jOnm6O Gd+mD46tHenUnITO9wj6qT6geUkWLJ3gcHLqAEAJDnK1SRNtjFiZUdpo9fLW1cVXHze1 cAcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0GE2AGcFHy79W+XlJkL7M8hbutjaw0ssS0YKptIt1WQ=; b=J6j9FZk3D9xqjUGFbF+RarrBZV5+lD/cSYhRcrpt6Do8Ks4TKqLTVIZPIoSR4Qha4Q clkQzwwx9PkEuQ2n2rqIpaLsCODlaoarFROD6ycCdkD4VpjGcY1Ecl6XqH2KL/zG7Tru jEuQgppJtQwYgVCJHEsJlPZ1PMql8sS9b6uLDeCD2lEeWCaD3ZAkIRp03iiZoZ9NCD1E GSkPs0UJsjrydWgHEjbLzVUb46RApdDwDQWitwB2CGYYL9nlpckDtBowXFdDhHmRkxR5 IAH9edpLVZo6dX2RiFK4Q2ZSpUSgVm0dxe2Fjk2IEDz05i/I6c47roMsCTdyMZOyBSrn cfDQ== X-Gm-Message-State: AOAM531VPmlBUZWAAthHOTTzmLoBzgz0EcyTpeJqa0zenX3oeq019uJ3 8eHK0JC0l6AgePRQHcaLGPYFuQ+gDYNMmw== X-Received: by 2002:adf:d1c9:: with SMTP id b9mr6990510wrd.426.1633014724921; Thu, 30 Sep 2021 08:12:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2 Date: Thu, 30 Sep 2021 16:11:41 +0100 Message-Id: <20210930151201.9407-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf The SMCCC 1.3 spec section 5.2 says The Unknown SMC Function Identifier is a sign-extended value of (-1) that is returned in the R0, W0 or X0 registers. An implementation must return this error code when it receives: * An SMC or HVC call with an unknown Function Identifier * An SMC or HVC call for a removed Function Identifier * An SMC64/HVC64 call from AArch32 state To comply with these statements, let's always return -1 when we encounter an unknown HVC or SMC call. Signed-off-by: Alexander Graf Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/psci.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-) -- 2.20.1 diff --git a/target/arm/psci.c b/target/arm/psci.c index 6709e280133..b279c0b9a45 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -27,15 +27,13 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { - /* Return true if the r0/x0 value indicates a PSCI call and - * the exception type matches the configured PSCI conduit. This is - * called before the SMC/HVC instruction is executed, to decide whether - * we should treat it as a PSCI call or with the architecturally + /* + * Return true if the exception type matches the configured PSCI conduit. + * This is called before the SMC/HVC instruction is executed, to decide + * whether we should treat it as a PSCI call or with the architecturally * defined behaviour for an SMC or HVC (which might be UNDEF or trap * to EL2 or to EL3). */ - CPUARMState *env = &cpu->env; - uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; switch (excp_type) { case EXCP_HVC: @@ -52,27 +50,7 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) return false; } - switch (param) { - case QEMU_PSCI_0_2_FN_PSCI_VERSION: - case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: - case QEMU_PSCI_0_2_FN_AFFINITY_INFO: - case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: - case QEMU_PSCI_0_2_FN_SYSTEM_RESET: - case QEMU_PSCI_0_2_FN_SYSTEM_OFF: - case QEMU_PSCI_0_1_FN_CPU_ON: - case QEMU_PSCI_0_2_FN_CPU_ON: - case QEMU_PSCI_0_2_FN64_CPU_ON: - case QEMU_PSCI_0_1_FN_CPU_OFF: - case QEMU_PSCI_0_2_FN_CPU_OFF: - case QEMU_PSCI_0_1_FN_CPU_SUSPEND: - case QEMU_PSCI_0_2_FN_CPU_SUSPEND: - case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: - case QEMU_PSCI_0_1_FN_MIGRATE: - case QEMU_PSCI_0_2_FN_MIGRATE: - return true; - default: - return false; - } + return true; } void arm_handle_psci_call(ARMCPU *cpu) @@ -194,10 +172,9 @@ void arm_handle_psci_call(ARMCPU *cpu) break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: + default: ret = QEMU_PSCI_RET_NOT_SUPPORTED; break; - default: - g_assert_not_reached(); } err: From patchwork Thu Sep 30 15:11:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514908 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp271564jam; Thu, 30 Sep 2021 08:21:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAG8lBxlapFYBtbp9MLAxgRdB3IfAGWFAj7QBsUjd9wFWnKLf7nPc3q1atggCA+jAQMjcn X-Received: by 2002:a05:6000:1562:: with SMTP id 2mr6945677wrz.36.1633015304969; Thu, 30 Sep 2021 08:21:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015304; cv=none; d=google.com; s=arc-20160816; b=UG7GDNajCP9XYB8Re+we09schQnL5CLmENbc/v4tyfSrJixGu6T/5SA8Jz4SzSGAT2 ADRy1DCT0v9yVTab1C7n6XZDt8iUiBqFcZdWSdqrGCMXWFkU8Q+FNvdwowmIflnCQSBe sKp0ikiXd6uYUhjmSQGaHGb1Lgd34qMgBJZ0bdcTT0jx9tnTD4A1TzdQeRxa0oAikB8J cAyOPssQHzQkGFkRaNkhzwuoY6OEmLIyc4H8zuUMdHCG3VEfaQ124Bc1IVfG30sw5XNU FEpp1p3F3QEYIx/ihLoq5AKP7Co3nrJVyrvQi20ccww19BnPU37lpPVmbuuClQ1dsCWe wsFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3b/eUZ85vtp5+DMkKCRt0b139ytnYD7QsgZ5MnN9SgA=; b=p3djfvWxaIl81l42FZ/4bx5g34+fNU6DVyAQBu25/zbUmcbscrFHp0t6QYWtlxjvFF jqu6dA3vx0n0x7FSBACYFz45cvTQE9f+FmGeFnMHJxwh2eWNuzdk3m4VgnTPizgMzIUC 6tXBTty+3Co/2TWIBNQeBrUrnrMY+/2eMDz6uD2PFqsWlScX1JG82daNLXgJss2OpFBL m+oPwxnMMCE2zdl+WaqsoP0Epn81i/JSUuTWkilUX03qD8czGV5fJqUAkuAwkyJx+mZe UoEImW1UchxMiRvvLw6Kz3tfuKF8vJDdt9FEYB77zSAQjBzSUK9a3HyzAmuZsyV49DFD phPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GypI5LuN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o18si3353232wrx.508.2021.09.30.08.21.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:21:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GypI5LuN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxsV-0004Zj-OR for patch@linaro.org; Thu, 30 Sep 2021 11:21:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjJ-0000BD-FN for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:13 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41900) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjD-0003uB-W3 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:13 -0400 Received: by mail-wr1-x434.google.com with SMTP id w29so10652055wra.8 for ; Thu, 30 Sep 2021 08:12:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3b/eUZ85vtp5+DMkKCRt0b139ytnYD7QsgZ5MnN9SgA=; b=GypI5LuND+faUdTmPS6UFzJLL9QfzdVKg/RSHZ5j1N056oaNNI6e9FsO4uPGblO/o7 0+1mzHWxrBjNL9CjEmwO5s/PNZyMs0+Nm2XEq1rE/rT5OZRK74GWQrLnWFEiDXiRnsu9 jd11r/1t7gNC6ZDKkilcaByj27DtJ94mkDApTl8fNzrgMS1HF3E//edj78+ULcvII+vL uawVVJNsXbqiBL64pnEkMHc9Az1ZQ1wRCGEfPAh/6doqW4854inVJ2QQI8T/OJ8LhM52 GnRiCyTN8GRcmIeAPl13EqwUvG++lQA6gN2o5ewTvnF+WCOP9pbpr61h106DeDw/RzXf PbZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3b/eUZ85vtp5+DMkKCRt0b139ytnYD7QsgZ5MnN9SgA=; b=NJdjGRE2y9SN/YYZL+D02P5IOFBt4HGqt7rQV+GC4eK9lkxXY6fyvWAUNBHFHYucqL yfRgaxRQ3FrCUF+gIh6H1gHZLL0ozVQCuGbv5rZbW3Tikf0E5ilhqRiaJhnz3/ObQZka S3Loo2tlCO8YzY+TCePT4J0fQgTMCoysIlXSSoDNyc5L/ZonkUwypbugt0TbaT1kUxI/ WpbPnree4uzO73BvI2b8jujlt5WyV38Zb+W9QtKSBkALBKMo3qq5oKNpJHqhL0jW3zl0 PNUfNQFvKIO9LT1+evWBmoT3tUmnXjEigZOoQ4nTcgNx85qaIahjaDKlp22dNLfwxdBz ACEQ== X-Gm-Message-State: AOAM531ACFtkfb0pT2qv1nPL51t0F/ucupJ1syXHw/j6UGk8umYXT3Xo S3YOf0ghJuFALaaaEbn+wcAhdoTBqsyVNA== X-Received: by 2002:a05:6000:1567:: with SMTP id 7mr6928761wrz.84.1633014725974; Thu, 30 Sep 2021 08:12:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM Date: Thu, 30 Sep 2021 16:11:42 +0100 Message-Id: <20210930151201.9407-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho This introduces the QOM for Xilinx eFuse, an one-time field-programmable storage bit array. The actual mmio interface to the array varies by device families and will be provided in different change-sets. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/nvram/xlnx-efuse.h | 132 ++++++++++++++++ hw/nvram/xlnx-efuse-crc.c | 119 +++++++++++++++ hw/nvram/xlnx-efuse.c | 280 ++++++++++++++++++++++++++++++++++ hw/nvram/Kconfig | 7 + hw/nvram/meson.build | 2 + 5 files changed, 540 insertions(+) create mode 100644 include/hw/nvram/xlnx-efuse.h create mode 100644 hw/nvram/xlnx-efuse-crc.c create mode 100644 hw/nvram/xlnx-efuse.c -- 2.20.1 diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h new file mode 100644 index 00000000000..58414e468b5 --- /dev/null +++ b/include/hw/nvram/xlnx-efuse.h @@ -0,0 +1,132 @@ +/* + * QEMU model of the Xilinx eFuse core + * + * Copyright (c) 2015 Xilinx Inc. + * + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef XLNX_EFUSE_H +#define XLNX_EFUSE_H + +#include "sysemu/block-backend.h" +#include "hw/qdev-core.h" + +#define TYPE_XLNX_EFUSE "xlnx,efuse" +OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE); + +struct XlnxEFuse { + DeviceState parent_obj; + BlockBackend *blk; + bool blk_ro; + uint32_t *fuse32; + + DeviceState *dev; + + bool init_tbits; + + uint8_t efuse_nr; + uint32_t efuse_size; + + uint32_t *ro_bits; + uint32_t ro_bits_cnt; +}; + +/** + * xlnx_efuse_calc_crc: + * @data: an array of 32-bit words for which the CRC should be computed + * @u32_cnt: the array size in number of 32-bit words + * @zpads: the number of 32-bit zeros prepended to @data before computation + * + * This function is used to compute the CRC for an array of 32-bit words, + * using a Xilinx-specific data padding. + * + * Returns: the computed 32-bit CRC + */ +uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt, + unsigned zpads); + +/** + * xlnx_efuse_get_bit: + * @s: the efuse object + * @bit: the efuse bit-address to read the data + * + * Returns: the bit, 0 or 1, at @bit of object @s + */ +bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit); + +/** + * xlnx_efuse_set_bit: + * @s: the efuse object + * @bit: the efuse bit-address to be written a value of 1 + * + * Returns: true on success, false on failure + */ +bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit); + +/** + * xlnx_efuse_k256_check: + * @s: the efuse object + * @crc: the 32-bit CRC to be compared with + * @start: the efuse bit-address (which must be multiple of 32) of the + * start of a 256-bit array + * + * This function computes the CRC of a 256-bit array starting at @start + * then compares to the given @crc + * + * Returns: true of @crc == computed, false otherwise + */ +bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start); + +/** + * xlnx_efuse_tbits_check: + * @s: the efuse object + * + * This function inspects a number of efuse bits at specific addresses + * to see if they match a validation pattern. Each pattern is a group + * of 4 bits, and there are 3 groups. + * + * Returns: a 3-bit mask, where a bit of '1' means the corresponding + * group has a valid pattern. + */ +uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s); + +/** + * xlnx_efuse_get_row: + * @s: the efuse object + * @bit: the efuse bit address for which a 32-bit value is read + * + * Returns: the entire 32 bits of the efuse, starting at a bit + * address that is multiple of 32 and contains the bit at @bit + */ +static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit) +{ + if (!(s->fuse32)) { + return 0; + } else { + unsigned int row_idx = bit / 32; + + assert(row_idx < (s->efuse_size * s->efuse_nr / 32)); + return s->fuse32[row_idx]; + } +} + +#endif diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c new file mode 100644 index 00000000000..5a5cc13f39f --- /dev/null +++ b/hw/nvram/xlnx-efuse-crc.c @@ -0,0 +1,119 @@ +/* + * Xilinx eFuse/bbram CRC calculator + * + * Copyright (c) 2021 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "hw/nvram/xlnx-efuse.h" + +static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data, + uint32_t addr) +{ + /* A table for 7-bit slicing */ + static const uint32_t crc_tab[128] = { + 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8, + 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27, + 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087, + 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848, + 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936, + 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9, + 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59, + 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696, + 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54, + 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b, + 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b, + 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4, + 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a, + 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45, + 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5, + 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a, + 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90, + 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f, + 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff, + 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330, + 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e, + 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81, + 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521, + 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee, + 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c, + 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3, + 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643, + 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c, + 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2, + 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d, + 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d, + 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052 + }; + + /* + * eFuse calculation is shown here: + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496 + * + * Each u32 word is appended a 5-bit value, for a total of 37 bits; see: + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356 + */ + uint32_t crc = prev_crc; + const unsigned rshf = 7; + const uint32_t im = (1 << rshf) - 1; + const uint32_t rm = (1 << (32 - rshf)) - 1; + const uint32_t i2 = (1 << 2) - 1; + const uint32_t r2 = (1 << 30) - 1; + + unsigned j; + uint32_t i, r; + uint64_t w; + + w = (uint64_t)(addr) << 32; + w |= data; + + /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */ + for (j = 0; j < 5; j++) { + r = rm & (crc >> rshf); + i = im & (crc ^ w); + crc = crc_tab[i] ^ r; + + w >>= rshf; + } + + /* Feed the remaining 2 bits */ + r = r2 & (crc >> 2); + i = i2 & (crc ^ w); + crc = crc_tab[i << (rshf - 2)] ^ r; + + return crc; +} + +uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt, + unsigned zpads) +{ + uint32_t crc = 0; + unsigned index; + + for (index = zpads; index; index--) { + crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt)); + } + + for (index = u32_cnt; index; index--) { + crc = xlnx_efuse_u37_crc(crc, data[index - 1], index); + } + + return crc; +} diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c new file mode 100644 index 00000000000..ee1caab54cb --- /dev/null +++ b/hw/nvram/xlnx-efuse.c @@ -0,0 +1,280 @@ +/* + * QEMU model of the EFUSE eFuse + * + * Copyright (c) 2015 Xilinx Inc. + * + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/nvram/xlnx-efuse.h" + +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "sysemu/blockdev.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" + +#define TBIT0_OFFSET 28 +#define TBIT1_OFFSET 29 +#define TBIT2_OFFSET 30 +#define TBIT3_OFFSET 31 +#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET) +#define TBITS_MASK (0x0FU << TBIT0_OFFSET) + +bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit) +{ + bool b = s->fuse32[bit / 32] & (1 << (bit % 32)); + return b; +} + +static int efuse_bytes(XlnxEFuse *s) +{ + return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4); +} + +static int efuse_bdrv_read(XlnxEFuse *s, Error **errp) +{ + uint32_t *ram = s->fuse32; + int nr = efuse_bytes(s); + + if (!s->blk) { + return 0; + } + + s->blk_ro = !blk_supports_write_perm(s->blk); + if (!s->blk_ro) { + int rc; + + rc = blk_set_perm(s->blk, + (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE), + BLK_PERM_ALL, NULL); + if (rc) { + s->blk_ro = true; + } + } + if (s->blk_ro) { + warn_report("%s: Skip saving updates to read-only eFUSE backstore.", + blk_name(s->blk)); + } + + if (blk_pread(s->blk, 0, ram, nr) < 0) { + error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.", + blk_name(s->blk), nr); + return -1; + } + + /* Convert from little-endian backstore for each 32-bit row */ + nr /= 4; + while (nr--) { + ram[nr] = le32_to_cpu(ram[nr]); + } + + return 0; +} + +static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit) +{ + unsigned int row_offset; + uint32_t le32; + + if (!s->blk || s->blk_ro) { + return; /* Silent on read-only backend to avoid message flood */ + } + + /* Backstore is always in little-endian */ + le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit)); + + row_offset = (bit / 32) * 4; + if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) { + error_report("%s: Failed to write offset %u of eFUSE backstore.", + blk_name(s->blk), row_offset); + } +} + +static int efuse_ro_bits_cmp(const void *a, const void *b) +{ + uint32_t i = *(const uint32_t *)a; + uint32_t j = *(const uint32_t *)b; + + return (i > j) - (i < j); +} + +static void efuse_ro_bits_sort(XlnxEFuse *s) +{ + uint32_t *ary = s->ro_bits; + const uint32_t cnt = s->ro_bits_cnt; + + if (ary && cnt > 1) { + qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp); + } +} + +static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) +{ + const uint32_t *ary = s->ro_bits; + const uint32_t cnt = s->ro_bits_cnt; + + if (!ary || !cnt) { + return false; + } + + return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL; +} + +bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) +{ + if (efuse_ro_bits_find(s, bit)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: " + "Ignored setting of readonly efuse bit<%u,%u>!\n", + object_get_canonical_path(OBJECT(s)), + (bit / 32), (bit % 32)); + return false; + } + + s->fuse32[bit / 32] |= 1 << (bit % 32); + efuse_bdrv_sync(s, bit); + return true; +} + +bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start) +{ + uint32_t calc; + + /* A key always occupies multiple of whole rows */ + assert((start % 32) == 0); + + calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0); + return calc == crc; +} + +uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s) +{ + int nr; + uint32_t check = 0; + + for (nr = s->efuse_nr; nr-- > 0; ) { + int efuse_start_row_num = (s->efuse_size * nr) / 32; + uint32_t data = s->fuse32[efuse_start_row_num]; + + /* + * If the option is on, auto-init blank T-bits. + * (non-blank will still be reported as '0' in the check, e.g., + * for error-injection tests) + */ + if ((data & TBITS_MASK) == 0 && s->init_tbits) { + data |= TBITS_PATTERN; + + s->fuse32[efuse_start_row_num] = data; + efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET)); + } + + check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN); + } + + return check; +} + +static void efuse_realize(DeviceState *dev, Error **errp) +{ + XlnxEFuse *s = XLNX_EFUSE(dev); + + /* Sort readonly-list for bsearch lookup */ + efuse_ro_bits_sort(s); + + if ((s->efuse_size % 32) != 0) { + error_setg(errp, + "%s.efuse-size: %u: property value not multiple of 32.", + object_get_canonical_path(OBJECT(dev)), s->efuse_size); + return; + } + + s->fuse32 = g_malloc0(efuse_bytes(s)); + if (efuse_bdrv_read(s, errp)) { + g_free(s->fuse32); + } +} + +static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + + qdev_prop_drive.set(obj, v, name, opaque, errp); + + /* Fill initial data if backend is attached after realized */ + if (dev->realized) { + efuse_bdrv_read(XLNX_EFUSE(obj), errp); + } +} + +static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + qdev_prop_drive.get(obj, v, name, opaque, errp); +} + +static void efuse_prop_release_drive(Object *obj, const char *name, + void *opaque) +{ + qdev_prop_drive.release(obj, name, opaque); +} + +static const PropertyInfo efuse_prop_drive = { + .name = "str", + .description = "Node name or ID of a block device to use as eFUSE backend", + .realized_set_allowed = true, + .get = efuse_prop_get_drive, + .set = efuse_prop_set_drive, + .release = efuse_prop_release_drive, +}; + +static Property efuse_properties[] = { + DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *), + DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3), + DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32), + DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true), + DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits, + qdev_prop_uint32, uint32_t), + DEFINE_PROP_END_OF_LIST(), +}; + +static void efuse_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = efuse_realize; + device_class_set_props(dc, efuse_properties); +} + +static const TypeInfo efuse_info = { + .name = TYPE_XLNX_EFUSE, + .parent = TYPE_DEVICE, + .instance_size = sizeof(XlnxEFuse), + .class_init = efuse_class_init, +}; + +static void efuse_register_types(void) +{ + type_register_static(&efuse_info); +} +type_init(efuse_register_types) diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig index e872fcb1941..252251f3665 100644 --- a/hw/nvram/Kconfig +++ b/hw/nvram/Kconfig @@ -15,3 +15,10 @@ config NMC93XX_EEPROM config CHRP_NVRAM bool + +config XLNX_EFUSE_CRC + bool + +config XLNX_EFUSE + bool + select XLNX_EFUSE_CRC diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index fd2951a860f..623c94efff6 100644 --- a/hw/nvram/meson.build +++ b/hw/nvram/meson.build @@ -9,5 +9,7 @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c')) softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c')) softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c')) softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) From patchwork Thu Sep 30 15:11:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514901 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp263670jam; Thu, 30 Sep 2021 08:14:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7Cu1wfzF5TMgt8GQdUm597wivAl+/rkPa8ozZYs0ydLfKED57RfLs4/cE+VStvF2sY2uO X-Received: by 2002:a5d:4810:: with SMTP id l16mr6839402wrq.3.1633014875860; Thu, 30 Sep 2021 08:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633014875; cv=none; d=google.com; s=arc-20160816; b=x5eKfZp9wLAcUjfNkhpeMKjuUMBdGljYRxYA2SlNRWH6PK20Jnd4l54O2j0tK853R+ FYA+s7aBV4hd/6s7iLaVrcfk743GKHKYzkM+hGMlgpnYO2da3uoVBZTPSe28W4KlvVwB 6fShdchMAYwiB1xxi/6X7DbVITNVVOULlfhftvBD+r+u4VQIipEbvN5733pGE1QUgzXL vXvjlPjRblywUrqajIsi7+3LbvG/2lbzsg9c+JFwcSZGnXGbDbD+moq+L0Ihp/Iv0ZCz jw1TaTSkM6hqZt88DBYuqmg8OAgcIJNlU+LZxcKo2kTuD0gXNAHpKxc2HmPkKRSODlyK r1kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=V8eWYncZxRi/zWeXUkirF5LyMh8AtlDHHnrSmwtX22E=; b=cfHQfRl4OAjpVLQe11q5STt7v7AdYqtBjArNBe6EVOXW9FfCjqszk9V8Uv4ViUNxCZ yK9GL7de4wryKRMn0/57tfCQHv6nZ8lpY9Ijc61F9XDk/U2IaZiBAw/MXEyGUcYGMwes 1UyZqZiRQaieTUTWpO+mmPfUcUlKY6pYfsOiKH5Tt3IetRRhyabw5tSSs9EskX2HF9iE IMG6jx6EdvAQX9YitYTNtmUwx9dsJhFP+TZjlHIoa4lXFXI/heEfXN6zVT3QVTtalGe8 5w4ySrCZ001ShYQcXeVMmGkBYVIZuJU1nCc8xUkLMXiAAthqODmjb/953IxvTdNuL6MS nVyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oK/nHH3g"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o8si4984049wri.397.2021.09.30.08.14.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:14:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oK/nHH3g"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54176 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxla-0001S0-Im for patch@linaro.org; Thu, 30 Sep 2021 11:14:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjJ-0000Aj-Cg for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:13 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:36357) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjF-0003vp-A1 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:12 -0400 Received: by mail-wr1-x433.google.com with SMTP id h15so9052483wrc.3 for ; Thu, 30 Sep 2021 08:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V8eWYncZxRi/zWeXUkirF5LyMh8AtlDHHnrSmwtX22E=; b=oK/nHH3goqYNgHQHohSHEZOoYy69AxkJcqo2bmmwIKM4NNInaJDfmOYoTEVcgjnT1e i4q882owe85hsNytXkHmSG+Ag99ChykJ82r/y3XOj4SkhqrRLvcQnaigJZfeKxdUR3mn YZd+0n40Kv6DL5OLHAgH0z6z7THMGggtYLo7mR0XcZNMXMiFMi/g800oPEtyHL/PYcr4 oizIOP5gn3lQwTfK8vRU47W7sRuP9YzAUdP4xNxquIsQhUVzoxBh6fWuyfW9YUYt7jGl aLzru8ZS44DkqT0pwoBtXYZcj4U7XtUfPzSJEZ5ZbNMFd+zjSaGybFA1txvKLQyWajg/ hhOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V8eWYncZxRi/zWeXUkirF5LyMh8AtlDHHnrSmwtX22E=; b=rQfh0E7c28HyJtrhPwcVrpWtiPpUbCFDolOIS8AAbabqA2HVMDdEN/v72PcSAvixDw vWygB+E62J/rVHAQt9kZuP67g8gadNqnMCPAHybTRI0UEzX97jXg3DorEDU1FkZdABtX PA+UdB93WPbfFnC7rj9JOKRJTDu+x1yhFb+FrS7rAK48EX+mcYN9NamkB7lSjghJm0wX IZEnMJ+T5dFcHg5jEauJCOt78oDCBddL9wTOqLn6esSsDzIJtRdj3o5eTh4L0eoxuAxB 8LLlCKxaJN/2rb9TzaExfoAjHDM5YGM8uctrFuk/ArrI6lo/6enQYyb1i2VWwr1rpvZ5 /wEA== X-Gm-Message-State: AOAM530on/8ZWBB770qxA8bzgEpJoFGZzBq4kLlwhEfuLeyDEUv6zJ8V aX3Ha6l9z2xiW2/MoZn53IMrLhS+n8pVpg== X-Received: by 2002:adf:d1b3:: with SMTP id w19mr6904649wrc.152.1633014727306; Thu, 30 Sep 2021 08:12:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device Date: Thu, 30 Sep 2021 16:11:43 +0100 Message-Id: <20210930151201.9407-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho This implements the Xilinx Versal eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx Versal product family. This device has two separate mmio interfaces, a controller and a flatten readback. The controller provides interfaces for field-programming, configuration, control, and status. The flatten readback is a cache to provide a byte-accessible read-only interface to efficiently read efuse array. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/nvram/xlnx-versal-efuse.h | 68 +++ hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++ hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++ hw/nvram/Kconfig | 4 + hw/nvram/meson.build | 3 + 5 files changed, 972 insertions(+) create mode 100644 include/hw/nvram/xlnx-versal-efuse.h create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c -- 2.20.1 diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h new file mode 100644 index 00000000000..a873dc5cb01 --- /dev/null +++ b/include/hw/nvram/xlnx-versal-efuse.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef XLNX_VERSAL_EFUSE_H +#define XLNX_VERSAL_EFUSE_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/nvram/xlnx-efuse.h" + +#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1) + +#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse" +#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache" + +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL); +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE); + +struct XlnxVersalEFuseCtrl { + SysBusDevice parent_obj; + qemu_irq irq_efuse_imr; + + XlnxEFuse *efuse; + + void *extra_pg0_lock_spec; /* Opaque property */ + uint32_t extra_pg0_lock_n16; + + uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; + RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; +}; + +struct XlnxVersalEFuseCache { + SysBusDevice parent_obj; + MemoryRegion iomem; + + XlnxEFuse *efuse; +}; + +/** + * xlnx_versal_efuse_read_row: + * @s: the efuse object + * @bit: the bit-address within the 32-bit row to be read + * @denied: if non-NULL, to receive true if the row is write-only + * + * Returns: the 32-bit word containing address @bit; 0 if @denies is true + */ +uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied); + +#endif diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c new file mode 100644 index 00000000000..eaec64d785e --- /dev/null +++ b/hw/nvram/xlnx-versal-efuse-cache.c @@ -0,0 +1,114 @@ +/* + * QEMU model of the EFuse_Cache + * + * Copyright (c) 2017 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/nvram/xlnx-versal-efuse.h" + +#include "qemu/log.h" +#include "hw/qdev-properties.h" + +#define MR_SIZE 0xC00 + +static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size) +{ + XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque); + unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32); + unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32); + + uint64_t ret; + + assert(w0 == w1 || (w0 + 32) == w1); + + ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL); + if (w0 < w1) { + ret <<= 32; + ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL); + } + + /* If 'addr' unaligned, the guest is always assumed to be little-endian. */ + addr &= 3; + if (addr) { + ret >>= 8 * addr; + } + + return ret; +} + +static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + /* No Register Writes allowed */ + qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only", + __func__); +} + +static const MemoryRegionOps efuse_cache_ops = { + .read = efuse_cache_read, + .write = efuse_cache_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static void efuse_cache_init(Object *obj) +{ + XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s, + TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static Property efuse_cache_props[] = { + DEFINE_PROP_LINK("efuse", + XlnxVersalEFuseCache, efuse, + TYPE_XLNX_EFUSE, XlnxEFuse *), + + DEFINE_PROP_END_OF_LIST(), +}; + +static void efuse_cache_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, efuse_cache_props); +} + +static const TypeInfo efuse_cache_info = { + .name = TYPE_XLNX_VERSAL_EFUSE_CACHE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxVersalEFuseCache), + .class_init = efuse_cache_class_init, + .instance_init = efuse_cache_init, +}; + +static void efuse_cache_register_types(void) +{ + type_register_static(&efuse_cache_info); +} + +type_init(efuse_cache_register_types) diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c new file mode 100644 index 00000000000..d3623767032 --- /dev/null +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -0,0 +1,783 @@ +/* + * QEMU model of the Versal eFuse controller + * + * Copyright (c) 2020 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/nvram/xlnx-versal-efuse.h" + +#include "qemu/log.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" + +#ifndef XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG +#define XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG 0 +#endif + +REG32(WR_LOCK, 0x0) + FIELD(WR_LOCK, LOCK, 0, 16) +REG32(CFG, 0x4) + FIELD(CFG, SLVERR_ENABLE, 5, 1) + FIELD(CFG, MARGIN_RD, 2, 1) + FIELD(CFG, PGM_EN, 1, 1) +REG32(STATUS, 0x8) + FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1) + FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1) + FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1) + FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1) + FIELD(STATUS, AES_CRC_PASS, 7, 1) + FIELD(STATUS, AES_CRC_DONE, 6, 1) + FIELD(STATUS, CACHE_DONE, 5, 1) + FIELD(STATUS, CACHE_LOAD, 4, 1) + FIELD(STATUS, EFUSE_2_TBIT, 2, 1) + FIELD(STATUS, EFUSE_1_TBIT, 1, 1) + FIELD(STATUS, EFUSE_0_TBIT, 0, 1) +REG32(EFUSE_PGM_ADDR, 0xc) + FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4) + FIELD(EFUSE_PGM_ADDR, ROW, 5, 8) + FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5) +REG32(EFUSE_RD_ADDR, 0x10) + FIELD(EFUSE_RD_ADDR, PAGE, 13, 4) + FIELD(EFUSE_RD_ADDR, ROW, 5, 8) +REG32(EFUSE_RD_DATA, 0x14) +REG32(TPGM, 0x18) + FIELD(TPGM, VALUE, 0, 16) +REG32(TRD, 0x1c) + FIELD(TRD, VALUE, 0, 8) +REG32(TSU_H_PS, 0x20) + FIELD(TSU_H_PS, VALUE, 0, 8) +REG32(TSU_H_PS_CS, 0x24) + FIELD(TSU_H_PS_CS, VALUE, 0, 8) +REG32(TRDM, 0x28) + FIELD(TRDM, VALUE, 0, 8) +REG32(TSU_H_CS, 0x2c) + FIELD(TSU_H_CS, VALUE, 0, 8) +REG32(EFUSE_ISR, 0x30) + FIELD(EFUSE_ISR, APB_SLVERR, 31, 1) + FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1) + FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1) + FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1) + FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1) + FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1) + FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1) + FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1) + FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1) + FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1) + FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1) + FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1) + FIELD(EFUSE_ISR, RD_ERROR, 3, 1) + FIELD(EFUSE_ISR, RD_DONE, 2, 1) + FIELD(EFUSE_ISR, PGM_ERROR, 1, 1) + FIELD(EFUSE_ISR, PGM_DONE, 0, 1) +REG32(EFUSE_IMR, 0x34) + FIELD(EFUSE_IMR, APB_SLVERR, 31, 1) + FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1) + FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1) + FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1) + FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1) + FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1) + FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1) + FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1) + FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1) + FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1) + FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1) + FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1) + FIELD(EFUSE_IMR, RD_ERROR, 3, 1) + FIELD(EFUSE_IMR, RD_DONE, 2, 1) + FIELD(EFUSE_IMR, PGM_ERROR, 1, 1) + FIELD(EFUSE_IMR, PGM_DONE, 0, 1) +REG32(EFUSE_IER, 0x38) + FIELD(EFUSE_IER, APB_SLVERR, 31, 1) + FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1) + FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1) + FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1) + FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1) + FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1) + FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1) + FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1) + FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1) + FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1) + FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1) + FIELD(EFUSE_IER, CACHE_ERROR, 4, 1) + FIELD(EFUSE_IER, RD_ERROR, 3, 1) + FIELD(EFUSE_IER, RD_DONE, 2, 1) + FIELD(EFUSE_IER, PGM_ERROR, 1, 1) + FIELD(EFUSE_IER, PGM_DONE, 0, 1) +REG32(EFUSE_IDR, 0x3c) + FIELD(EFUSE_IDR, APB_SLVERR, 31, 1) + FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1) + FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1) + FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1) + FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1) + FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1) + FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1) + FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1) + FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1) + FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1) + FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1) + FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1) + FIELD(EFUSE_IDR, RD_ERROR, 3, 1) + FIELD(EFUSE_IDR, RD_DONE, 2, 1) + FIELD(EFUSE_IDR, PGM_ERROR, 1, 1) + FIELD(EFUSE_IDR, PGM_DONE, 0, 1) +REG32(EFUSE_CACHE_LOAD, 0x40) + FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1) +REG32(EFUSE_PGM_LOCK, 0x44) + FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1) +REG32(EFUSE_AES_CRC, 0x48) +REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c) +REG32(EFUSE_AES_USR_KEY1_CRC, 0x50) +REG32(EFUSE_PD, 0x54) +REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60) +REG32(EFUSE_TEST_CTRL, 0x100) + +#define R_MAX (R_EFUSE_TEST_CTRL + 1) + +#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D) + +/* + * eFuse layout references: + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h + */ +#define BIT_POS_OF(A_) \ + ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \ + R_EFUSE_PGM_ADDR_COLUMN_MASK))) + +#define BIT_POS(R_, C_) \ + ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \ + & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \ + | \ + (R_EFUSE_PGM_ADDR_COLUMN_MASK \ + & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT)))) + +#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28)) + +#define EFUSE_ANCHOR_ROW (0) +#define EFUSE_ANCHOR_3_COL (27) +#define EFUSE_ANCHOR_1_COL (1) + +#define EFUSE_AES_KEY_START BIT_POS(12, 0) +#define EFUSE_AES_KEY_END BIT_POS(19, 31) +#define EFUSE_USER_KEY_0_START BIT_POS(20, 0) +#define EFUSE_USER_KEY_0_END BIT_POS(27, 31) +#define EFUSE_USER_KEY_1_START BIT_POS(28, 0) +#define EFUSE_USER_KEY_1_END BIT_POS(35, 31) + +#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START +#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END + +#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31) +#define EFUSE_PPK0_WR_LK BIT_POS(43, 6) +#define EFUSE_PPK1_WR_LK BIT_POS(43, 7) +#define EFUSE_PPK2_WR_LK BIT_POS(43, 8) +#define EFUSE_AES_WR_LK BIT_POS(43, 11) +#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13) +#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15) +#define EFUSE_PUF_SYN_LK BIT_POS(43, 16) +#define EFUSE_DNA_WR_LK BIT_POS(43, 27) +#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28) + +#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0) +#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31) + +#define EFUSE_PUF_PAGE (2) +#define EFUSE_PUF_SYN_START BIT_POS(129, 0) +#define EFUSE_PUF_SYN_END BIT_POS(255, 27) + +#define EFUSE_KEY_CRC_LK_ROW (43) +#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10)) +#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12) +#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14) + +/* + * A handy macro to return value of an array element, + * or a specific default if given index is out of bound. + */ +#define ARRAY_GET(A_, I_, D_) \ + ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_)) + +QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs)); + +typedef struct XlnxEFuseLkSpec { + uint16_t row; + uint16_t lk_bit; +} XlnxEFuseLkSpec; + +static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s) +{ + bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR]; + qemu_set_irq(s->irq_efuse_imr, pending); +} + +static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + efuse_imr_update_irq(s); +} + +static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + uint32_t val = val64; + + s->regs[R_EFUSE_IMR] &= ~val; + efuse_imr_update_irq(s); + return 0; +} + +static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + uint32_t val = val64; + + s->regs[R_EFUSE_IMR] |= val; + efuse_imr_update_irq(s); + return 0; +} + +static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s) +{ + uint32_t check = xlnx_efuse_tbits_check(s->efuse); + uint32_t val = s->regs[R_STATUS]; + + val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0))); + val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1))); + val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2))); + + s->regs[R_STATUS] = val; +} + +static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s) +{ + unsigned page; + + if (!s->efuse || !s->efuse->init_tbits) { + return; + } + + for (page = 0; page < s->efuse->efuse_nr; page++) { + uint32_t row = 0, bit; + + row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page); + row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW); + + bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL); + if (!xlnx_efuse_get_bit(s->efuse, bit)) { + xlnx_efuse_set_bit(s->efuse, bit); + } + + bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL); + if (!xlnx_efuse_get_bit(s->efuse, bit)) { + xlnx_efuse_set_bit(s->efuse, bit); + } + } +} + +static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc, + uint32_t pass_mask, uint32_t done_mask, + unsigned first, uint32_t lk_mask) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + uint32_t r, lk_bits; + + /* + * To start, assume both DONE and PASS, and clear PASS by xor + * if CRC-check fails or CRC-check disabled by lock fuse. + */ + r = s->regs[R_STATUS] | done_mask | pass_mask; + + lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask; + if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) { + pass_mask = 0; + } + + s->regs[R_STATUS] = r ^ pass_mask; +} + +static void efuse_data_sync(XlnxVersalEFuseCtrl *s) +{ + efuse_status_tbits_sync(s); +} + +static int efuse_lk_spec_cmp(const void *a, const void *b) +{ + uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row; + uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row; + + return (r1 > r2) - (r1 < r2); +} + +static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s) +{ + XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec; + const uint32_t n8 = s->extra_pg0_lock_n16 * 2; + const uint32_t sz = sizeof(ary[0]); + const uint32_t cnt = n8 / sz; + + if (ary && cnt) { + qsort(ary, cnt, sz, efuse_lk_spec_cmp); + } +} + +static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row) +{ + const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec; + const uint32_t n8 = s->extra_pg0_lock_n16 * 2; + const uint32_t sz = sizeof(ary[0]); + const uint32_t cnt = n8 / sz; + const XlnxEFuseLkSpec *item = NULL; + + if (ary && cnt) { + XlnxEFuseLkSpec k = { .row = row, }; + + item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp); + } + + return item ? item->lk_bit : 0; +} + +static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit) +{ + /* Hard-coded locks */ + static const uint16_t pg0_hard_lock[] = { + [4] = EFUSE_GLITCH_DET_WR_LK, + [37] = EFUSE_BOOT_ENV_WR_LK, + + [8 ... 11] = EFUSE_DNA_WR_LK, + [12 ... 19] = EFUSE_AES_WR_LK, + [20 ... 27] = EFUSE_USER_KEY_0_WR_LK, + [28 ... 35] = EFUSE_USER_KEY_1_WR_LK, + [64 ... 71] = EFUSE_PPK0_WR_LK, + [72 ... 79] = EFUSE_PPK1_WR_LK, + [80 ... 87] = EFUSE_PPK2_WR_LK, + }; + + uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW); + uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0); + + return lk_bit ? lk_bit : efuse_lk_spec_find(s, row); +} + +static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit) +{ + + unsigned int lock = 1; + + /* Global lock */ + if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { + goto ret_lock; + } + + /* Row lock */ + switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) { + case 0: + if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) && + bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) { + goto ret_lock; + } + + lock = efuse_bit_locked(s, bit); + break; + case EFUSE_PUF_PAGE: + if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) { + lock = 0; + goto ret_lock; + } + + lock = EFUSE_PUF_SYN_LK; + break; + default: + lock = 0; + goto ret_lock; + } + + /* Row lock by an efuse bit */ + if (lock) { + lock = xlnx_efuse_get_bit(s->efuse, lock); + } + + ret_lock: + return lock != 0; +} + +static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + unsigned bit = val64; + bool ok = false; + + /* Always zero out PGM_ADDR because it is write-only */ + s->regs[R_EFUSE_PGM_ADDR] = 0; + + /* + * Indicate error if bit is write-protected (or read-only + * as guarded by efuse_set_bit()). + * + * Keep it simple by not modeling program timing. + * + * Note: model must NEVER clear the PGM_ERROR bit; it is + * up to guest to do so (or by reset). + */ + if (efuse_pgm_locked(s, bit)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Denied setting of efuse<%u, %u, %u>\n", + object_get_canonical_path(OBJECT(s)), + FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE), + FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW), + FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN)); + } else if (xlnx_efuse_set_bit(s->efuse, bit)) { + ok = true; + if (EFUSE_TBIT_POS(bit)) { + efuse_status_tbits_sync(s); + } + } + + if (!ok) { + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); + } + + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); + efuse_imr_update_irq(s); +} + +static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + unsigned bit = val64; + bool denied; + + /* Always zero out RD_ADDR because it is write-only */ + s->regs[R_EFUSE_RD_ADDR] = 0; + + /* + * Indicate error if row is read-blocked. + * + * Note: model must NEVER clear the RD_ERROR bit; it is + * up to guest to do so (or by reset). + */ + s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse, + bit, &denied); + if (denied) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Denied reading of efuse<%u, %u>\n", + object_get_canonical_path(OBJECT(s)), + FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE), + FIELD_EX32(bit, EFUSE_RD_ADDR, ROW)); + + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); + } + + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); + efuse_imr_update_irq(s); + return; +} + +static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + + if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) { + efuse_data_sync(s); + + ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); + efuse_imr_update_irq(s); + } + + return 0; +} + +static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); + + /* Ignore all other bits */ + val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK); + + /* Once the bit is written 1, only reset will clear it to 0 */ + val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK); + + return val64; +} + +static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64) +{ + efuse_key_crc_check(reg, val64, + R_STATUS_AES_CRC_PASS_MASK, + R_STATUS_AES_CRC_DONE_MASK, + EFUSE_AES_KEY_START, + EFUSE_AES_KEY_CRC_LK_MASK); +} + +static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64) +{ + efuse_key_crc_check(reg, val64, + R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK, + R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK, + EFUSE_USER_KEY_0_START, + EFUSE_USER_KEY_0_CRC_LK_MASK); +} + +static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64) +{ + efuse_key_crc_check(reg, val64, + R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK, + R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK, + EFUSE_USER_KEY_1_START, + EFUSE_USER_KEY_1_CRC_LK_MASK); +} + +static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val) +{ + return val != R_WR_LOCK_UNLOCK_PASSCODE; +} + +static const RegisterAccessInfo efuse_ctrl_regs_info[] = { + { .name = "WR_LOCK", .addr = A_WR_LOCK, + .reset = 0x1, + .pre_write = efuse_wr_lock_prew, + },{ .name = "CFG", .addr = A_CFG, + .rsvd = 0x9, + },{ .name = "STATUS", .addr = A_STATUS, + .rsvd = 0x8, + .ro = 0xfff, + },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR, + .post_write = efuse_pgm_addr_postw, + },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR, + .rsvd = 0x1f, + .post_write = efuse_rd_addr_postw, + },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA, + .ro = 0xffffffff, + },{ .name = "TPGM", .addr = A_TPGM, + },{ .name = "TRD", .addr = A_TRD, + .reset = 0x19, + },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS, + .reset = 0xff, + },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS, + .reset = 0x11, + },{ .name = "TRDM", .addr = A_TRDM, + .reset = 0x3a, + },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS, + .reset = 0x16, + },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR, + .rsvd = 0x7fff8000, + .w1c = 0x80007fff, + .post_write = efuse_isr_postw, + },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR, + .reset = 0x80007fff, + .rsvd = 0x7fff8000, + .ro = 0xffffffff, + },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER, + .rsvd = 0x7fff8000, + .pre_write = efuse_ier_prew, + },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR, + .rsvd = 0x7fff8000, + .pre_write = efuse_idr_prew, + },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD, + .pre_write = efuse_cache_load_prew, + },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK, + .pre_write = efuse_pgm_lock_prew, + },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC, + .post_write = efuse_aes_crc_postw, + },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC, + .post_write = efuse_aes_u0_crc_postw, + },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC, + .post_write = efuse_aes_u1_crc_postw, + },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD, + .ro = 0xfffffffe, + },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP, + },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL, + .reset = 0x8, + } +}; + +static void efuse_ctrl_reg_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + RegisterInfoArray *reg_array = opaque; + XlnxVersalEFuseCtrl *s; + Object *dev; + + assert(reg_array != NULL); + + dev = reg_array->mem.owner; + assert(dev); + + s = XLNX_VERSAL_EFUSE_CTRL(dev); + + if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s[reg_0x%02lx]: Attempt to write locked register.\n", + object_get_canonical_path(OBJECT(s)), (long)addr); + } else { + register_write_memory(opaque, addr, data, size); + } +} + +static void efuse_ctrl_register_reset(RegisterInfo *reg) +{ + if (!reg->data || !reg->access) { + return; + } + + /* Reset must not trigger some registers' writers */ + switch (reg->access->addr) { + case A_EFUSE_AES_CRC: + case A_EFUSE_AES_USR_KEY0_CRC: + case A_EFUSE_AES_USR_KEY1_CRC: + *(uint32_t *)reg->data = reg->access->reset; + return; + } + + register_reset(reg); +} + +static void efuse_ctrl_reset(DeviceState *dev) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + efuse_ctrl_register_reset(&s->regs_info[i]); + } + + efuse_anchor_bits_check(s); + efuse_data_sync(s); + efuse_imr_update_irq(s); +} + +static const MemoryRegionOps efuse_ctrl_ops = { + .read = register_read_memory, + .write = efuse_ctrl_reg_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void efuse_ctrl_realize(DeviceState *dev, Error **errp) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev); + const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2; + + if (!s->efuse) { + error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE", + object_get_canonical_path(OBJECT(dev))); + return; + } + + /* Sort property-defined pgm-locks for bsearch lookup */ + if ((s->extra_pg0_lock_n16 % lks_sz) != 0) { + error_setg(errp, + "%s.pg0-lock: array property item-count not multiple of %u", + object_get_canonical_path(OBJECT(dev)), lks_sz); + return; + } + + efuse_lk_spec_sort(s); +} + +static void efuse_ctrl_init(Object *obj) +{ + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + reg_array = + register_init_block32(DEVICE(obj), efuse_ctrl_regs_info, + ARRAY_SIZE(efuse_ctrl_regs_info), + s->regs_info, s->regs, + &efuse_ctrl_ops, + XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG, + R_MAX * 4); + + sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_irq(sbd, &s->irq_efuse_imr); +} + +static const VMStateDescription vmstate_efuse_ctrl = { + .name = TYPE_XLNX_VERSAL_EFUSE_CTRL, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static Property efuse_ctrl_props[] = { + DEFINE_PROP_LINK("efuse", + XlnxVersalEFuseCtrl, efuse, + TYPE_XLNX_EFUSE, XlnxEFuse *), + DEFINE_PROP_ARRAY("pg0-lock", + XlnxVersalEFuseCtrl, extra_pg0_lock_n16, + extra_pg0_lock_spec, qdev_prop_uint16, uint16_t), + + DEFINE_PROP_END_OF_LIST(), +}; + +static void efuse_ctrl_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = efuse_ctrl_reset; + dc->realize = efuse_ctrl_realize; + dc->vmsd = &vmstate_efuse_ctrl; + device_class_set_props(dc, efuse_ctrl_props); +} + +static const TypeInfo efuse_ctrl_info = { + .name = TYPE_XLNX_VERSAL_EFUSE_CTRL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxVersalEFuseCtrl), + .class_init = efuse_ctrl_class_init, + .instance_init = efuse_ctrl_init, +}; + +static void efuse_ctrl_register_types(void) +{ + type_register_static(&efuse_ctrl_info); +} + +type_init(efuse_ctrl_register_types) + +/* + * Retrieve a row, with unreadable bits returned as 0. + */ +uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *efuse, + uint32_t bit, bool *denied) +{ + bool dummy; + + if (!denied) { + denied = &dummy; + } + + if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) { + *denied = true; + return 0; + } + + *denied = false; + return xlnx_efuse_get_row(efuse, bit); +} diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig index 252251f3665..6c2bb5afe3b 100644 --- a/hw/nvram/Kconfig +++ b/hw/nvram/Kconfig @@ -22,3 +22,7 @@ config XLNX_EFUSE_CRC config XLNX_EFUSE bool select XLNX_EFUSE_CRC + +config XLNX_EFUSE_VERSAL + bool + select XLNX_EFUSE diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index 623c94efff6..62352ad8ecc 100644 --- a/hw/nvram/meson.build +++ b/hw/nvram/meson.build @@ -11,5 +11,8 @@ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c')) softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c')) softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c')) softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files( + 'xlnx-versal-efuse-cache.c', + 'xlnx-versal-efuse-ctrl.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) From patchwork Thu Sep 30 15:11:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514899 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp263077jam; Thu, 30 Sep 2021 08:13:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkTL9YsbQ37Z9dRy9EbFs6bUKeGhUfSqTewmL4hoqNevNKQyqWQxtaFX6IBwubrQHAzcnQ X-Received: by 2002:a05:6000:1546:: with SMTP id 6mr6801740wry.305.1633014839300; Thu, 30 Sep 2021 08:13:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633014839; cv=none; d=google.com; s=arc-20160816; b=hPpY7dXD7Riqf8k2jxSG5hB9d6nreXdlzo9Tp1NYwm9UPjA9A3CLfxTQE/rJJQh/w4 6hxfzL7mOMKzn2PTq4QUgAu8gQWamFjRkxr5+tPjNBl0zKiCxxyV6CfEfrXXy30harla QV0W4atAcNxaQpI+MgqquWx+csrk7+1Bada8vv942KZPw8txFpYI+BnUgiwG942m3W2q s/+pjE5BIGn07ndwjvKBg1hZUBgxrHCZRJADSjhSbqJhxfWxZ/bupYge7QZgt/L/E4Xt f3v/2nNG15naVlHH5l0ypnBzaMDqPD3G9sa2Fe8HDi9cklKCScvhyoPJihsk8tUn9O8U GxXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l41ejspVWX81CNfODL+puu6Y17ESCpUt8k0smDDjmWo=; b=HmU62gRJXGKw2Ze0Z96A+lloi+yxsu5PBWlOU5hz0ev0LkfJQR/9mnlZ8d+Nruveyu tfrHfpqzCWsv8DXZthO/8ZndXyzi7bfIFcO4HmD0zMsJvncOI4py3Trkb2reDQM8fQ64 tQkojuWpNU0U1CrdChK1MXwss1yQWgSNx+D9r89R3uzqOw+hTP+1PPGlNfRZLLaDsbth OPEmfQHAPJeK6w48sbRIxofH2jXMpvjd264DKxaSZofaSjyp+mjFVz1HlTnB3DSSl52z 3LpcjjorjhFFGiM+L5agK9ntETwFzOD3YP6gPN2t4995TkQJQmLHyJ8xubai8OGorUUX CZCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pxeF6QoD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s18si3622363wri.159.2021.09.30.08.13.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:13:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pxeF6QoD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxl0-0000Gv-3h for patch@linaro.org; Thu, 30 Sep 2021 11:13:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjL-0000Ed-N5 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:36354) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjG-0003xF-CV for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:13 -0400 Received: by mail-wr1-x42f.google.com with SMTP id h15so9052610wrc.3 for ; Thu, 30 Sep 2021 08:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=l41ejspVWX81CNfODL+puu6Y17ESCpUt8k0smDDjmWo=; b=pxeF6QoDtoacjYBg1XTzneqamdIVJBco1lpG+YpwXBmUxMhO6z2xOxzPf7Ecc9lGTN RBbs/eQMWszevR/bCbnzA6ejOPgglHwlISTT0ToWOhvNAFTVUMSO/juJ/Z67MkJjKggv jfvE8sjy6np98hupLOMCFRNXQEbTXXGx6Yx4Go7NBVuDd4XejI9KL1hBdvKusN2B71oN YygyAxlF0nX1TwDzX+3hLQGH7pcpPtchF07JGj7mh04uMLffy4PcplmZ+utCeUqr+OiU p64lAEmg92wkAgNBS7oWawQZEc16glOKUbwJIb5zwABgaBZLIqu8zZ11oOH9SQpyH1K4 /OnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l41ejspVWX81CNfODL+puu6Y17ESCpUt8k0smDDjmWo=; b=fxK3Mgjfb/5EwxdsELemlPy9b0yja9vckTV4CD3YO8eY39mYr1ocpFdEHr+I/8W+6e ZJfs9B6m4AMdSdttDyxaqIfNfSQgs6619PFswTCrUc6KmP1gKh1YinPdRRhS7OP94njQ BBYluXXi2vMjR1CRMbPePNVNyAw5NFzs2cybkaDWdhxvKVnDdub+rAxMbSWSvUf1JrN4 Mf7K2FF+bAbHKkExkAFSHc7/zmXvSPMJadJwc0rf/luV7TFBltTUK0VtVePORKnPIzVp n9hX2UjUpBD4kHLhqvX09jtXGKklpP7badWG8nFr9OqFgSQBQsbtm7hJusZz1mWxptD1 rAug== X-Gm-Message-State: AOAM532K/8aVIyf+hnuU8C/2g+WGIjJ1xr16rRncCffvbNDuCLCChiwy Ia3DRT7R6NNbkqNIhx8dMGakFSQ3Bx3WEA== X-Received: by 2002:a5d:4a4e:: with SMTP id v14mr6832915wrs.271.1633014728759; Thu, 30 Sep 2021 08:12:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP eFuse device Date: Thu, 30 Sep 2021 16:11:44 +0100 Message-Id: <20210930151201.9407-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho This implements the Xilinx ZynqMP eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx ZynqMP product family. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++ hw/nvram/xlnx-zynqmp-efuse.c | 855 +++++++++++++++++++++++++++ hw/nvram/Kconfig | 4 + hw/nvram/meson.build | 2 + 4 files changed, 905 insertions(+) create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c -- 2.20.1 diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h new file mode 100644 index 00000000000..6b051ec4f15 --- /dev/null +++ b/include/hw/nvram/xlnx-zynqmp-efuse.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2021 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef XLNX_ZYNQMP_EFUSE_H +#define XLNX_ZYNQMP_EFUSE_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/nvram/xlnx-efuse.h" + +#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1) + +#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse" +OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE); + +struct XlnxZynqMPEFuse { + SysBusDevice parent_obj; + qemu_irq irq; + + XlnxEFuse *efuse; + uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX]; + RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX]; +}; + +#endif diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c new file mode 100644 index 00000000000..1f87dbf988d --- /dev/null +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -0,0 +1,855 @@ +/* + * QEMU model of the ZynqMP eFuse + * + * Copyright (c) 2015 Xilinx Inc. + * + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/nvram/xlnx-zynqmp-efuse.h" + +#include "qemu/log.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" + +#ifndef ZYNQMP_EFUSE_ERR_DEBUG +#define ZYNQMP_EFUSE_ERR_DEBUG 0 +#endif + +REG32(WR_LOCK, 0x0) + FIELD(WR_LOCK, LOCK, 0, 16) +REG32(CFG, 0x4) + FIELD(CFG, SLVERR_ENABLE, 5, 1) + FIELD(CFG, MARGIN_RD, 2, 2) + FIELD(CFG, PGM_EN, 1, 1) + FIELD(CFG, EFUSE_CLK_SEL, 0, 1) +REG32(STATUS, 0x8) + FIELD(STATUS, AES_CRC_PASS, 7, 1) + FIELD(STATUS, AES_CRC_DONE, 6, 1) + FIELD(STATUS, CACHE_DONE, 5, 1) + FIELD(STATUS, CACHE_LOAD, 4, 1) + FIELD(STATUS, EFUSE_3_TBIT, 2, 1) + FIELD(STATUS, EFUSE_2_TBIT, 1, 1) + FIELD(STATUS, EFUSE_0_TBIT, 0, 1) +REG32(EFUSE_PGM_ADDR, 0xc) + FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2) + FIELD(EFUSE_PGM_ADDR, ROW, 5, 6) + FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5) +REG32(EFUSE_RD_ADDR, 0x10) + FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2) + FIELD(EFUSE_RD_ADDR, ROW, 5, 6) +REG32(EFUSE_RD_DATA, 0x14) +REG32(TPGM, 0x18) + FIELD(TPGM, VALUE, 0, 16) +REG32(TRD, 0x1c) + FIELD(TRD, VALUE, 0, 8) +REG32(TSU_H_PS, 0x20) + FIELD(TSU_H_PS, VALUE, 0, 8) +REG32(TSU_H_PS_CS, 0x24) + FIELD(TSU_H_PS_CS, VALUE, 0, 8) +REG32(TSU_H_CS, 0x2c) + FIELD(TSU_H_CS, VALUE, 0, 4) +REG32(EFUSE_ISR, 0x30) + FIELD(EFUSE_ISR, APB_SLVERR, 31, 1) + FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1) + FIELD(EFUSE_ISR, RD_ERROR, 3, 1) + FIELD(EFUSE_ISR, RD_DONE, 2, 1) + FIELD(EFUSE_ISR, PGM_ERROR, 1, 1) + FIELD(EFUSE_ISR, PGM_DONE, 0, 1) +REG32(EFUSE_IMR, 0x34) + FIELD(EFUSE_IMR, APB_SLVERR, 31, 1) + FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1) + FIELD(EFUSE_IMR, RD_ERROR, 3, 1) + FIELD(EFUSE_IMR, RD_DONE, 2, 1) + FIELD(EFUSE_IMR, PGM_ERROR, 1, 1) + FIELD(EFUSE_IMR, PGM_DONE, 0, 1) +REG32(EFUSE_IER, 0x38) + FIELD(EFUSE_IER, APB_SLVERR, 31, 1) + FIELD(EFUSE_IER, CACHE_ERROR, 4, 1) + FIELD(EFUSE_IER, RD_ERROR, 3, 1) + FIELD(EFUSE_IER, RD_DONE, 2, 1) + FIELD(EFUSE_IER, PGM_ERROR, 1, 1) + FIELD(EFUSE_IER, PGM_DONE, 0, 1) +REG32(EFUSE_IDR, 0x3c) + FIELD(EFUSE_IDR, APB_SLVERR, 31, 1) + FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1) + FIELD(EFUSE_IDR, RD_ERROR, 3, 1) + FIELD(EFUSE_IDR, RD_DONE, 2, 1) + FIELD(EFUSE_IDR, PGM_ERROR, 1, 1) + FIELD(EFUSE_IDR, PGM_DONE, 0, 1) +REG32(EFUSE_CACHE_LOAD, 0x40) + FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1) +REG32(EFUSE_PGM_LOCK, 0x44) + FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1) +REG32(EFUSE_AES_CRC, 0x48) +REG32(EFUSE_TBITS_PRGRMG_EN, 0x100) + FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1) +REG32(DNA_0, 0x100c) +REG32(DNA_1, 0x1010) +REG32(DNA_2, 0x1014) +REG32(IPDISABLE, 0x1018) + FIELD(IPDISABLE, VCU_DIS, 8, 1) + FIELD(IPDISABLE, GPU_DIS, 5, 1) + FIELD(IPDISABLE, APU3_DIS, 3, 1) + FIELD(IPDISABLE, APU2_DIS, 2, 1) + FIELD(IPDISABLE, APU1_DIS, 1, 1) + FIELD(IPDISABLE, APU0_DIS, 0, 1) +REG32(SYSOSC_CTRL, 0x101c) + FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1) +REG32(USER_0, 0x1020) +REG32(USER_1, 0x1024) +REG32(USER_2, 0x1028) +REG32(USER_3, 0x102c) +REG32(USER_4, 0x1030) +REG32(USER_5, 0x1034) +REG32(USER_6, 0x1038) +REG32(USER_7, 0x103c) +REG32(MISC_USER_CTRL, 0x1040) + FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1) + FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1) + FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1) + FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1) +REG32(ROM_RSVD, 0x1044) + FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3) +REG32(PUF_CHASH, 0x1050) +REG32(PUF_MISC, 0x1054) + FIELD(PUF_MISC, REGISTER_DIS, 31, 1) + FIELD(PUF_MISC, SYN_WRLK, 30, 1) + FIELD(PUF_MISC, SYN_INVLD, 29, 1) + FIELD(PUF_MISC, TEST2_DIS, 28, 1) + FIELD(PUF_MISC, UNUSED27, 27, 1) + FIELD(PUF_MISC, UNUSED26, 26, 1) + FIELD(PUF_MISC, UNUSED25, 25, 1) + FIELD(PUF_MISC, UNUSED24, 24, 1) + FIELD(PUF_MISC, AUX, 0, 24) +REG32(SEC_CTRL, 0x1058) + FIELD(SEC_CTRL, PPK1_INVLD, 30, 2) + FIELD(SEC_CTRL, PPK1_WRLK, 29, 1) + FIELD(SEC_CTRL, PPK0_INVLD, 27, 2) + FIELD(SEC_CTRL, PPK0_WRLK, 26, 1) + FIELD(SEC_CTRL, RSA_EN, 11, 15) + FIELD(SEC_CTRL, SEC_LOCK, 10, 1) + FIELD(SEC_CTRL, PROG_GATE_2, 9, 1) + FIELD(SEC_CTRL, PROG_GATE_1, 8, 1) + FIELD(SEC_CTRL, PROG_GATE_0, 7, 1) + FIELD(SEC_CTRL, DFT_DIS, 6, 1) + FIELD(SEC_CTRL, JTAG_DIS, 5, 1) + FIELD(SEC_CTRL, ERROR_DIS, 4, 1) + FIELD(SEC_CTRL, BBRAM_DIS, 3, 1) + FIELD(SEC_CTRL, ENC_ONLY, 2, 1) + FIELD(SEC_CTRL, AES_WRLK, 1, 1) + FIELD(SEC_CTRL, AES_RDLK, 0, 1) +REG32(SPK_ID, 0x105c) +REG32(PPK0_0, 0x10a0) +REG32(PPK0_1, 0x10a4) +REG32(PPK0_2, 0x10a8) +REG32(PPK0_3, 0x10ac) +REG32(PPK0_4, 0x10b0) +REG32(PPK0_5, 0x10b4) +REG32(PPK0_6, 0x10b8) +REG32(PPK0_7, 0x10bc) +REG32(PPK0_8, 0x10c0) +REG32(PPK0_9, 0x10c4) +REG32(PPK0_10, 0x10c8) +REG32(PPK0_11, 0x10cc) +REG32(PPK1_0, 0x10d0) +REG32(PPK1_1, 0x10d4) +REG32(PPK1_2, 0x10d8) +REG32(PPK1_3, 0x10dc) +REG32(PPK1_4, 0x10e0) +REG32(PPK1_5, 0x10e4) +REG32(PPK1_6, 0x10e8) +REG32(PPK1_7, 0x10ec) +REG32(PPK1_8, 0x10f0) +REG32(PPK1_9, 0x10f4) +REG32(PPK1_10, 0x10f8) +REG32(PPK1_11, 0x10fc) + +#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN) +#define R_MAX (R_PPK1_11 + 1) + +/* #define EFUSE_XOSC 26 */ + +/* + * eFUSE layout references: + * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13 + */ +#define EFUSE_AES_RDLK BIT_POS(22, 0) +#define EFUSE_AES_WRLK BIT_POS(22, 1) +#define EFUSE_ENC_ONLY BIT_POS(22, 2) +#define EFUSE_BBRAM_DIS BIT_POS(22, 3) +#define EFUSE_ERROR_DIS BIT_POS(22, 4) +#define EFUSE_JTAG_DIS BIT_POS(22, 5) +#define EFUSE_DFT_DIS BIT_POS(22, 6) +#define EFUSE_PROG_GATE_0 BIT_POS(22, 7) +#define EFUSE_PROG_GATE_1 BIT_POS(22, 7) +#define EFUSE_PROG_GATE_2 BIT_POS(22, 9) +#define EFUSE_SEC_LOCK BIT_POS(22, 10) +#define EFUSE_RSA_EN BIT_POS(22, 11) +#define EFUSE_RSA_EN14 BIT_POS(22, 25) +#define EFUSE_PPK0_WRLK BIT_POS(22, 26) +#define EFUSE_PPK0_INVLD BIT_POS(22, 27) +#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28) +#define EFUSE_PPK1_WRLK BIT_POS(22, 29) +#define EFUSE_PPK1_INVLD BIT_POS(22, 30) +#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31) + +/* Areas. */ +#define EFUSE_TRIM_START BIT_POS(1, 0) +#define EFUSE_TRIM_END BIT_POS(1, 30) +#define EFUSE_DNA_START BIT_POS(3, 0) +#define EFUSE_DNA_END BIT_POS(5, 31) +#define EFUSE_AES_START BIT_POS(24, 0) +#define EFUSE_AES_END BIT_POS(31, 31) +#define EFUSE_ROM_START BIT_POS(17, 0) +#define EFUSE_ROM_END BIT_POS(17, 31) +#define EFUSE_IPDIS_START BIT_POS(6, 0) +#define EFUSE_IPDIS_END BIT_POS(6, 31) +#define EFUSE_USER_START BIT_POS(8, 0) +#define EFUSE_USER_END BIT_POS(15, 31) +#define EFUSE_BISR_START BIT_POS(32, 0) +#define EFUSE_BISR_END BIT_POS(39, 31) + +#define EFUSE_USER_CTRL_START BIT_POS(16, 0) +#define EFUSE_USER_CTRL_END BIT_POS(16, 16) +#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17)) + +#define EFUSE_PUF_CHASH_START BIT_POS(20, 0) +#define EFUSE_PUF_CHASH_END BIT_POS(20, 31) +#define EFUSE_PUF_MISC_START BIT_POS(21, 0) +#define EFUSE_PUF_MISC_END BIT_POS(21, 31) +#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30) + +#define EFUSE_SPK_START BIT_POS(23, 0) +#define EFUSE_SPK_END BIT_POS(23, 31) + +#define EFUSE_PPK0_START BIT_POS(40, 0) +#define EFUSE_PPK0_END BIT_POS(51, 31) +#define EFUSE_PPK1_START BIT_POS(52, 0) +#define EFUSE_PPK1_END BIT_POS(63, 31) + +#define EFUSE_CACHE_FLD(s, reg, field) \ + ARRAY_FIELD_DP32((s)->regs, reg, field, \ + (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \ + >> (EFUSE_ ## field % 32))) + +#define EFUSE_CACHE_BIT(s, reg, field) \ + ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \ + EFUSE_ ## field)) + +#define FBIT_UNKNOWN (~0) + +QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs)); + +static void update_tbit_status(XlnxZynqMPEFuse *s) +{ + unsigned int check = xlnx_efuse_tbits_check(s->efuse); + uint32_t val = s->regs[R_STATUS]; + + val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0))); + val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1))); + val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2))); + + s->regs[R_STATUS] = val; +} + +/* Update the u32 array from efuse bits. Slow but simple approach. */ +static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start, + unsigned int f_start, unsigned int f_end, + unsigned int f_written) +{ + uint32_t *u32 = &s->regs[r_start]; + unsigned int fbit, wbits = 0, u32_off = 0; + + /* Avoid working on bits that are not relevant. */ + if (f_written != FBIT_UNKNOWN + && (f_written < f_start || f_written > f_end)) { + return; + } + + for (fbit = f_start; fbit <= f_end; fbit++, wbits++) { + if (wbits == 32) { + /* Update the key offset. */ + u32_off += 1; + wbits = 0; + } + u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits; + } +} + +/* + * Keep the syncs in bit order so we can bail out for the + * slower ones. + */ +static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit) +{ + EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK); + EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK); + EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY); + EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS); + EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS); + EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS); + EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS); + EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0); + EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1); + EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2); + EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK); + EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK); + EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK); + + EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN); + EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD); + EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD); + + /* Update the tbits. */ + update_tbit_status(s); + + /* Sync the various areas. */ + s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse, + EFUSE_USER_CTRL_START) + & EFUSE_USER_CTRL_MASK; + s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START); + s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START); + + cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit); + + if (bit < EFUSE_AES_START) { + return; + } + + cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit); + cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit); + cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit); + cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit); + cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit); + cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit); +} + +static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s) +{ + bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR]; + qemu_set_irq(s->irq, pending); +} + +static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + zynqmp_efuse_update_irq(s); +} + +static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + uint32_t val = val64; + + s->regs[R_EFUSE_IMR] |= val; + zynqmp_efuse_update_irq(s); + return 0; +} + +static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + uint32_t val = val64; + + s->regs[R_EFUSE_IMR] &= ~val; + zynqmp_efuse_update_irq(s); + return 0; +} + +static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + unsigned bit = val64; + unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE); + bool puf_prot = false; + const char *errmsg = NULL; + + /* Allow only valid array, and adjust for skipped array 1 */ + switch (page) { + case 0: + break; + case 2 ... 3: + bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1); + puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK); + break; + default: + errmsg = "Invalid address"; + goto pgm_done; + } + + if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) { + errmsg = "Array write-locked"; + goto pgm_done; + } + + if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { + errmsg = "Array pgm-disabled"; + goto pgm_done; + } + + if (puf_prot) { + errmsg = "PUF_HD-store write-locked"; + goto pgm_done; + } + + if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK) + && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) { + errmsg = "AES key-store Write-locked"; + goto pgm_done; + } + + if (!xlnx_efuse_set_bit(s->efuse, bit)) { + errmsg = "Write failed"; + } + + pgm_done: + if (!errmsg) { + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0); + } else { + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); + qemu_log_mask(LOG_GUEST_ERROR, + "%s - eFuse write error: %s; addr=0x%x\n", + object_get_canonical_path(OBJECT(s)), + errmsg, (unsigned)val64); + } + + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); + zynqmp_efuse_update_irq(s); +} + +static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + + /* + * Grant reads only to allowed bits; reference sources: + * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow() + * 2/ UG1085, v2.0, table 12-13 + * (note: enumerates the masks as per described in + * references to avoid mental translation). + */ +#define COL_MASK(L_, H_) \ + ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_)))) + + static const uint32_t ary0_col_mask[] = { + /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */ + [0] = COL_MASK(28, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */ + [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31), + [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31), + [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31), + [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */ + [16] = COL_MASK(0, 7) | COL_MASK(10, 16), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */ + [17] = COL_MASK(0, 2), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */ + [20] = COL_MASK(0, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */ + [21] = COL_MASK(0, 23) | COL_MASK(29, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */ + [22] = COL_MASK(0, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */ + [23] = COL_MASK(0, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */ + [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31), + [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31), + [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31), + [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31), + [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31), + [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31), + + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */ + [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31), + [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31), + [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31), + [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31), + [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31), + [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31), + }; + + uint32_t col_mask = COL_MASK(0, 31); +#undef COL_MASK + + uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR]; + uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE); + uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW); + + switch (efuse_ary) { + case 0: /* Various */ + if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) { + goto denied; + } + + col_mask = ary0_col_mask[efuse_row]; + if (!col_mask) { + goto denied; + } + break; + case 2: /* PUF helper data, adjust for skipped array 1 */ + case 3: + val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1); + break; + default: + goto denied; + } + + s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask; + + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0); + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); + zynqmp_efuse_update_irq(s); + return; + + denied: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Denied efuse read from array %u, row %u\n", + object_get_canonical_path(OBJECT(s)), + efuse_ary, efuse_row); + + s->regs[R_EFUSE_RD_DATA] = 0; + + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0); + zynqmp_efuse_update_irq(s); +} + +static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + bool ok; + + ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START); + + ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0)); + ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1); + + s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */ +} + +static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg, + uint64_t valu64) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); + + if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) { + zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN); + ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); + zynqmp_efuse_update_irq(s); + } + + return 0; +} + +static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val) +{ + return val == 0xDF0D ? 0 : 1; +} + +static RegisterAccessInfo zynqmp_efuse_regs_info[] = { + { .name = "WR_LOCK", .addr = A_WR_LOCK, + .reset = 0x1, + .pre_write = zynqmp_efuse_wr_lock_prew, + },{ .name = "CFG", .addr = A_CFG, + },{ .name = "STATUS", .addr = A_STATUS, + .rsvd = 0x8, + .ro = 0xff, + },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR, + .post_write = zynqmp_efuse_pgm_addr_postw + },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR, + .rsvd = 0x1f, + .post_write = zynqmp_efuse_rd_addr_postw, + },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA, + .ro = 0xffffffff, + },{ .name = "TPGM", .addr = A_TPGM, + },{ .name = "TRD", .addr = A_TRD, + .reset = 0x1b, + },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS, + .reset = 0xff, + },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS, + .reset = 0xb, + },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS, + .reset = 0x7, + },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR, + .rsvd = 0x7fffffe0, + .w1c = 0x8000001f, + .post_write = zynqmp_efuse_isr_postw, + },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR, + .reset = 0x8000001f, + .rsvd = 0x7fffffe0, + .ro = 0xffffffff, + },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER, + .rsvd = 0x7fffffe0, + .pre_write = zynqmp_efuse_ier_prew, + },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR, + .rsvd = 0x7fffffe0, + .pre_write = zynqmp_efuse_idr_prew, + },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD, + .pre_write = zynqmp_efuse_cache_load_prew, + },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK, + },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC, + .post_write = zynqmp_efuse_aes_crc_postw, + },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN, + .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK, + },{ .name = "DNA_0", .addr = A_DNA_0, + .ro = 0xffffffff, + },{ .name = "DNA_1", .addr = A_DNA_1, + .ro = 0xffffffff, + },{ .name = "DNA_2", .addr = A_DNA_2, + .ro = 0xffffffff, + },{ .name = "IPDISABLE", .addr = A_IPDISABLE, + .ro = 0xffffffff, + },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL, + .ro = 0xffffffff, + },{ .name = "USER_0", .addr = A_USER_0, + .ro = 0xffffffff, + },{ .name = "USER_1", .addr = A_USER_1, + .ro = 0xffffffff, + },{ .name = "USER_2", .addr = A_USER_2, + .ro = 0xffffffff, + },{ .name = "USER_3", .addr = A_USER_3, + .ro = 0xffffffff, + },{ .name = "USER_4", .addr = A_USER_4, + .ro = 0xffffffff, + },{ .name = "USER_5", .addr = A_USER_5, + .ro = 0xffffffff, + },{ .name = "USER_6", .addr = A_USER_6, + .ro = 0xffffffff, + },{ .name = "USER_7", .addr = A_USER_7, + .ro = 0xffffffff, + },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL, + .ro = 0xffffffff, + },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD, + .ro = 0xffffffff, + },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH, + .ro = 0xffffffff, + },{ .name = "PUF_MISC", .addr = A_PUF_MISC, + .ro = 0xffffffff, + },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL, + .ro = 0xffffffff, + },{ .name = "SPK_ID", .addr = A_SPK_ID, + .ro = 0xffffffff, + },{ .name = "PPK0_0", .addr = A_PPK0_0, + .ro = 0xffffffff, + },{ .name = "PPK0_1", .addr = A_PPK0_1, + .ro = 0xffffffff, + },{ .name = "PPK0_2", .addr = A_PPK0_2, + .ro = 0xffffffff, + },{ .name = "PPK0_3", .addr = A_PPK0_3, + .ro = 0xffffffff, + },{ .name = "PPK0_4", .addr = A_PPK0_4, + .ro = 0xffffffff, + },{ .name = "PPK0_5", .addr = A_PPK0_5, + .ro = 0xffffffff, + },{ .name = "PPK0_6", .addr = A_PPK0_6, + .ro = 0xffffffff, + },{ .name = "PPK0_7", .addr = A_PPK0_7, + .ro = 0xffffffff, + },{ .name = "PPK0_8", .addr = A_PPK0_8, + .ro = 0xffffffff, + },{ .name = "PPK0_9", .addr = A_PPK0_9, + .ro = 0xffffffff, + },{ .name = "PPK0_10", .addr = A_PPK0_10, + .ro = 0xffffffff, + },{ .name = "PPK0_11", .addr = A_PPK0_11, + .ro = 0xffffffff, + },{ .name = "PPK1_0", .addr = A_PPK1_0, + .ro = 0xffffffff, + },{ .name = "PPK1_1", .addr = A_PPK1_1, + .ro = 0xffffffff, + },{ .name = "PPK1_2", .addr = A_PPK1_2, + .ro = 0xffffffff, + },{ .name = "PPK1_3", .addr = A_PPK1_3, + .ro = 0xffffffff, + },{ .name = "PPK1_4", .addr = A_PPK1_4, + .ro = 0xffffffff, + },{ .name = "PPK1_5", .addr = A_PPK1_5, + .ro = 0xffffffff, + },{ .name = "PPK1_6", .addr = A_PPK1_6, + .ro = 0xffffffff, + },{ .name = "PPK1_7", .addr = A_PPK1_7, + .ro = 0xffffffff, + },{ .name = "PPK1_8", .addr = A_PPK1_8, + .ro = 0xffffffff, + },{ .name = "PPK1_9", .addr = A_PPK1_9, + .ro = 0xffffffff, + },{ .name = "PPK1_10", .addr = A_PPK1_10, + .ro = 0xffffffff, + },{ .name = "PPK1_11", .addr = A_PPK1_11, + .ro = 0xffffffff, + } +}; + +static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + RegisterInfoArray *reg_array = opaque; + XlnxZynqMPEFuse *s; + Object *dev; + + assert(reg_array != NULL); + + dev = reg_array->mem.owner; + assert(dev); + + s = XLNX_ZYNQMP_EFUSE(dev); + + if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s[reg_0x%02lx]: Attempt to write locked register.\n", + object_get_canonical_path(OBJECT(s)), (long)addr); + } else { + register_write_memory(opaque, addr, data, size); + } +} + +static const MemoryRegionOps zynqmp_efuse_ops = { + .read = register_read_memory, + .write = zynqmp_efuse_reg_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void zynqmp_efuse_register_reset(RegisterInfo *reg) +{ + if (!reg->data || !reg->access) { + return; + } + + /* Reset must not trigger some registers' writers */ + switch (reg->access->addr) { + case A_EFUSE_AES_CRC: + *(uint32_t *)reg->data = reg->access->reset; + return; + } + + register_reset(reg); +} + +static void zynqmp_efuse_reset(DeviceState *dev) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + zynqmp_efuse_register_reset(&s->regs_info[i]); + } + + zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN); + ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); + zynqmp_efuse_update_irq(s); +} + +static void zynqmp_efuse_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev); + + if (!s->efuse) { + error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE", + object_get_canonical_path(OBJECT(dev))); + return; + } + + s->efuse->dev = dev; +} + +static void zynqmp_efuse_init(Object *obj) +{ + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + reg_array = + register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info, + ARRAY_SIZE(zynqmp_efuse_regs_info), + s->regs_info, s->regs, + &zynqmp_efuse_ops, + ZYNQMP_EFUSE_ERR_DEBUG, + R_MAX * 4); + + sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_irq(sbd, &s->irq); +} + +static const VMStateDescription vmstate_efuse = { + .name = TYPE_XLNX_ZYNQMP_EFUSE, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static Property zynqmp_efuse_props[] = { + DEFINE_PROP_LINK("efuse", + XlnxZynqMPEFuse, efuse, + TYPE_XLNX_EFUSE, XlnxEFuse *), + + DEFINE_PROP_END_OF_LIST(), +}; + +static void zynqmp_efuse_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = zynqmp_efuse_reset; + dc->realize = zynqmp_efuse_realize; + dc->vmsd = &vmstate_efuse; + device_class_set_props(dc, zynqmp_efuse_props); +} + + +static const TypeInfo efuse_info = { + .name = TYPE_XLNX_ZYNQMP_EFUSE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPEFuse), + .class_init = zynqmp_efuse_class_init, + .instance_init = zynqmp_efuse_init, +}; + +static void efuse_register_types(void) +{ + type_register_static(&efuse_info); +} + +type_init(efuse_register_types) diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig index 6c2bb5afe3b..3059c5dae03 100644 --- a/hw/nvram/Kconfig +++ b/hw/nvram/Kconfig @@ -26,3 +26,7 @@ config XLNX_EFUSE config XLNX_EFUSE_VERSAL bool select XLNX_EFUSE + +config XLNX_EFUSE_ZYNQMP + bool + select XLNX_EFUSE diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index 62352ad8ecc..6dc54d98734 100644 --- a/hw/nvram/meson.build +++ b/hw/nvram/meson.build @@ -14,5 +14,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c')) softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files( 'xlnx-versal-efuse-cache.c', 'xlnx-versal-efuse-ctrl.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files( + 'xlnx-zynqmp-efuse.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) From patchwork Thu Sep 30 15:11:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514912 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp277087jam; Thu, 30 Sep 2021 08:27:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqTag1ev2mKc2BNc/BdJG2FuYIKuoYeXSBWP4jlqyY/Xg/wxcY+uSMojTCp8mTH/v8veXV X-Received: by 2002:a1c:8056:: with SMTP id b83mr871840wmd.87.1633015636043; Thu, 30 Sep 2021 08:27:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015636; cv=none; d=google.com; s=arc-20160816; b=t9yTSI6UAQWzEG2Hmfcae7Yng+7k8T4Vc2E2VM3MU2l60NvEJYzXJ+/RG1coX/2QkF OVcv1fDZfO9Zu7cdvf79XaDoWaaQaaNN5SeSvI3IAmwUeDS/m7jdn6k+u3K3trUYd4vU ezIlQamGI8S8Uu+O3m2KOVPqoie8Paoycia8e46v8kQ+/sPBSlf7Mr2vO1pUTdBcPBZQ lfxUFNZRp1S4y1O8xaNNLyIyYa/EjTasR/Ya5k1afgMPogPBcE+nUXxSvZgFFsEl5f2L cUP3ufvRjTSUOf2g08tzqO1BXPON2RitNTYsoQANfDeInliMqLuwwXxK1RwG2dt+pVbu reRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XLebwh8ygRsd0Pf9EoW0+q/5vT4Ko+x+7OO6En4P6kU=; b=ejZpyswRPQruEG+3R9OKVcf5HSRbsG6XOxdgih5Tns9+cADhUflxG5RBBWxxlvYTZi 69i4Kf9yudT3Qdu3yy8wt+vj7RYmwa5BPKy/3ctvktVO3E0GZhFqGfIZjtUUXLFUaMmw SMSLC4BVEae0qqm668MRmXtCPcvHgZAA8EsioCUODnTnBdl3GsS3rSuZKiRkoWKI3RXh i/Ickjru3uO1aTVIvuujvc3929PM41AqcutkyZUE+DwIr0Dd5HuHJuW3FCNEmQEVMpfK nc/f5D1YwW0d/l3A5nnnGSd5N0FIRkZ45g8W3nmyrPI5N9EDfYe5xlWtFuJasr7Vl11V V4lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OBfgKPxo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m14si3810931wmq.46.2021.09.30.08.27.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:27:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OBfgKPxo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxxq-0004sO-R7 for patch@linaro.org; Thu, 30 Sep 2021 11:27:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjN-0000FP-KM for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:36358) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjH-0003xt-3b for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:16 -0400 Received: by mail-wr1-x433.google.com with SMTP id h15so9052681wrc.3 for ; Thu, 30 Sep 2021 08:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XLebwh8ygRsd0Pf9EoW0+q/5vT4Ko+x+7OO6En4P6kU=; b=OBfgKPxoepN8Ur58uq0IwGQzi/UtFGNMFzSAdjebrbPUiDr/qRHveYxCbsHqbdL9rH Zzh1qVdhDS+xAglnhhZiqB0TSK4ixPvD1djY3TpwwmjadhJJ9VoPXHUTytusbE/9v+JQ z5plU3VBWatkJox0AUONCrXkFCvJDr+eahJqmbNCZmYYEOlSwx10qJVaoSWkicLx+jpa YSuDTFIrQrJdJsVHGFIcgRZ3IaVld+AGLtX0WYjiNKXd4+0Ne2l1EGRqVTGXwxqdd57H 99eY1CO2V+dAiqEcFh/DkVZL5c2hcWKwHVHO9FOkC2nBCP1FKQxqvLmoZpXzZsZkvgVt hkdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XLebwh8ygRsd0Pf9EoW0+q/5vT4Ko+x+7OO6En4P6kU=; b=LdFkHJua30vQYmF5w3/ukw278Uy5rCGfLr5dQQtsHh1CXk1tbRg9BHY/hRsl1JYKxU tT/cQ7ivnalY82a5ETyAITiLFTmu0hzTQMrZ9t//gRqtn7lqD2nW9+haEgIQydYtrKm/ LcqWj7vnuYEOJc1nxdhE5d3Us/kc2wni6JBTb/r0kselr52QjbVGt4m79d1KMWbgItLT oqOak9h0PeyM3mlJTsS9e3VxAazCiYHX8gMaf+adhwZgm4jR4/IcBRldzeBVOurW8Kvd tgAVPUrAw6Er0/HgDNfxHgpAgC+59EXq4YsebxnptzLETImL1yMRzqVF+NS84mX0o6GL /xFg== X-Gm-Message-State: AOAM530bcFGfdZuFMyKSNkR45U6dEdXhcFoUoebHxePMfwlT5vIJDd7/ zdeUzvFXpS7JVO04fHZx8EVgCXx1Ekt7jw== X-Received: by 2002:adf:f481:: with SMTP id l1mr6702236wro.411.1633014729707; Thu, 30 Sep 2021 08:12:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram Date: Thu, 30 Sep 2021 16:11:45 +0100 Message-Id: <20210930151201.9407-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho This device is present in Versal and ZynqMP product families to store a 256-bit encryption key. Co-authored-by: Edgar E. Iglesias Co-authored-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Sai Pavan Boddu Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/nvram/xlnx-bbram.h | 54 ++++ hw/nvram/xlnx-bbram.c | 545 ++++++++++++++++++++++++++++++++++ hw/nvram/Kconfig | 4 + hw/nvram/meson.build | 1 + 4 files changed, 604 insertions(+) create mode 100644 include/hw/nvram/xlnx-bbram.h create mode 100644 hw/nvram/xlnx-bbram.c -- 2.20.1 diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h new file mode 100644 index 00000000000..87d59ef3c0c --- /dev/null +++ b/include/hw/nvram/xlnx-bbram.h @@ -0,0 +1,54 @@ +/* + * QEMU model of the Xilinx BBRAM Battery Backed RAM + * + * Copyright (c) 2015-2021 Xilinx Inc. + * + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef XLNX_BBRAM_H +#define XLNX_BBRAM_H + +#include "sysemu/block-backend.h" +#include "hw/qdev-core.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "hw/register.h" + +#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1) + +#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM); + +struct XlnxBBRam { + SysBusDevice parent_obj; + qemu_irq irq_bbram; + + BlockBackend *blk; + + uint32_t crc_zpads; + bool bbram8_wo; + bool blk_ro; + + uint32_t regs[RMAX_XLNX_BBRAM]; + RegisterInfo regs_info[RMAX_XLNX_BBRAM]; +}; + +#endif diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c new file mode 100644 index 00000000000..b70828e5bf1 --- /dev/null +++ b/hw/nvram/xlnx-bbram.c @@ -0,0 +1,545 @@ +/* + * QEMU model of the Xilinx BBRAM Battery Backed RAM + * + * Copyright (c) 2014-2021 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/nvram/xlnx-bbram.h" + +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "sysemu/blockdev.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "hw/nvram/xlnx-efuse.h" + +#ifndef XLNX_BBRAM_ERR_DEBUG +#define XLNX_BBRAM_ERR_DEBUG 0 +#endif + +REG32(BBRAM_STATUS, 0x0) + FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1) + FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1) + FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1) + FIELD(BBRAM_STATUS, PGM_MODE, 0, 1) +REG32(BBRAM_CTRL, 0x4) + FIELD(BBRAM_CTRL, ZEROIZE, 0, 1) +REG32(PGM_MODE, 0x8) +REG32(BBRAM_AES_CRC, 0xc) +REG32(BBRAM_0, 0x10) +REG32(BBRAM_1, 0x14) +REG32(BBRAM_2, 0x18) +REG32(BBRAM_3, 0x1c) +REG32(BBRAM_4, 0x20) +REG32(BBRAM_5, 0x24) +REG32(BBRAM_6, 0x28) +REG32(BBRAM_7, 0x2c) +REG32(BBRAM_8, 0x30) +REG32(BBRAM_SLVERR, 0x34) + FIELD(BBRAM_SLVERR, ENABLE, 0, 1) +REG32(BBRAM_ISR, 0x38) + FIELD(BBRAM_ISR, APB_SLVERR, 0, 1) +REG32(BBRAM_IMR, 0x3c) + FIELD(BBRAM_IMR, APB_SLVERR, 0, 1) +REG32(BBRAM_IER, 0x40) + FIELD(BBRAM_IER, APB_SLVERR, 0, 1) +REG32(BBRAM_IDR, 0x44) + FIELD(BBRAM_IDR, APB_SLVERR, 0, 1) +REG32(BBRAM_MSW_LOCK, 0x4c) + FIELD(BBRAM_MSW_LOCK, VAL, 0, 1) + +#define R_MAX (R_BBRAM_MSW_LOCK + 1) + +#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0) + +#define BBRAM_PGM_MAGIC 0x757bdf0d + +QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs)); + +static bool bbram_msw_locked(XlnxBBRam *s) +{ + return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0; +} + +static bool bbram_pgm_enabled(XlnxBBRam *s) +{ + return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0; +} + +static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail) +{ + Error *errp; + + error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.", + blk_name(s->blk), detail); + error_report("%s", error_get_pretty(errp)); + error_free(errp); + + g_free(detail); +} + +static void bbram_bdrv_read(XlnxBBRam *s, Error **errp) +{ + uint32_t *ram = &s->regs[R_BBRAM_0]; + int nr = RAM_MAX; + + if (!s->blk) { + return; + } + + s->blk_ro = !blk_supports_write_perm(s->blk); + if (!s->blk_ro) { + int rc; + + rc = blk_set_perm(s->blk, + (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE), + BLK_PERM_ALL, NULL); + if (rc) { + s->blk_ro = true; + } + } + if (s->blk_ro) { + warn_report("%s: Skip saving updates to read-only BBRAM backstore.", + blk_name(s->blk)); + } + + if (blk_pread(s->blk, 0, ram, nr) < 0) { + error_setg(errp, + "%s: Failed to read %u bytes from BBRAM backstore.", + blk_name(s->blk), nr); + return; + } + + /* Convert from little-endian backstore for each 32-bit word */ + nr /= 4; + while (nr--) { + ram[nr] = le32_to_cpu(ram[nr]); + } +} + +static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr) +{ + uint32_t le32; + unsigned offset; + int rc; + + assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8); + + /* Backstore is always in little-endian */ + le32 = cpu_to_le32(s->regs[hwaddr / 4]); + + /* Update zeroized flag */ + if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) { + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0); + } + + if (!s->blk || s->blk_ro) { + return; + } + + offset = hwaddr - A_BBRAM_0; + rc = blk_pwrite(s->blk, offset, &le32, 4, 0); + if (rc < 0) { + bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset)); + } +} + +static void bbram_bdrv_zero(XlnxBBRam *s) +{ + int rc; + + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1); + + if (!s->blk || s->blk_ro) { + return; + } + + rc = blk_make_zero(s->blk, 0); + if (rc < 0) { + bbram_bdrv_error(s, rc, g_strdup("zeroizing")); + } + + /* Restore bbram8 if it is non-zero */ + if (s->regs[R_BBRAM_8]) { + bbram_bdrv_sync(s, A_BBRAM_8); + } +} + +static void bbram_zeroize(XlnxBBRam *s) +{ + int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */ + + memset(&s->regs[R_BBRAM_0], 0, nr); + bbram_bdrv_zero(s); +} + +static void bbram_update_irq(XlnxBBRam *s) +{ + bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR]; + + qemu_set_irq(s->irq_bbram, pending); +} + +static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + uint32_t val = val64; + + if (val & R_BBRAM_CTRL_ZEROIZE_MASK) { + bbram_zeroize(s); + /* The bit is self clearing */ + s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK; + } +} + +static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + uint32_t val = val64; + + if (val == BBRAM_PGM_MAGIC) { + bbram_zeroize(s); + + /* The status bit is cleared only by POR */ + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1); + } +} + +static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + uint32_t calc_crc; + + if (!bbram_pgm_enabled(s)) { + /* We are not in programming mode, don't do anything */ + return; + } + + /* Perform the AES integrity check */ + s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK; + + /* + * Set check status. + * + * ZynqMP BBRAM check has a zero-u32 prepended; see: + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311 + */ + calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0], + (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads); + + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS, + (s->regs[R_BBRAM_AES_CRC] == calc_crc)); +} + +static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + uint32_t original_data = *(uint32_t *) reg->data; + + if (bbram_pgm_enabled(s)) { + return val64; + } else { + /* We are not in programming mode, don't do anything */ + qemu_log_mask(LOG_GUEST_ERROR, + "Not in programming mode, dropping the write\n"); + return original_data; + } +} + +static void bbram_key_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + + bbram_bdrv_sync(s, reg->access->addr); +} + +static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val) +{ + return 0; +} + +static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + + return s->bbram8_wo ? bbram_wo_postr(reg, val) : val; +} + +static bool bbram_r8_readonly(XlnxBBRam *s) +{ + return !bbram_pgm_enabled(s) || bbram_msw_locked(s); +} + +static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + + if (bbram_r8_readonly(s)) { + val64 = *(uint32_t *)reg->data; + } + + return val64; +} + +static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + + if (!bbram_r8_readonly(s)) { + bbram_bdrv_sync(s, A_BBRAM_8); + } +} + +static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + + /* Never lock if bbram8 is wo; and, only POR can clear the lock */ + if (s->bbram8_wo) { + val64 = 0; + } else { + val64 |= s->regs[R_BBRAM_MSW_LOCK]; + } + + return val64; +} + +static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + + bbram_update_irq(s); +} + +static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + uint32_t val = val64; + + s->regs[R_BBRAM_IMR] &= ~val; + bbram_update_irq(s); + return 0; +} + +static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); + uint32_t val = val64; + + s->regs[R_BBRAM_IMR] |= val; + bbram_update_irq(s); + return 0; +} + +static RegisterAccessInfo bbram_ctrl_regs_info[] = { + { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS, + .rsvd = 0xee, + .ro = 0x3ff, + },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL, + .post_write = bbram_ctrl_postw, + },{ .name = "PGM_MODE", .addr = A_PGM_MODE, + .post_write = bbram_pgm_mode_postw, + },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC, + .post_write = bbram_aes_crc_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_0", .addr = A_BBRAM_0, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_1", .addr = A_BBRAM_1, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_2", .addr = A_BBRAM_2, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_3", .addr = A_BBRAM_3, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_4", .addr = A_BBRAM_4, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_5", .addr = A_BBRAM_5, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_6", .addr = A_BBRAM_6, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_7", .addr = A_BBRAM_7, + .pre_write = bbram_key_prew, + .post_write = bbram_key_postw, + .post_read = bbram_wo_postr, + },{ .name = "BBRAM_8", .addr = A_BBRAM_8, + .pre_write = bbram_r8_prew, + .post_write = bbram_r8_postw, + .post_read = bbram_r8_postr, + },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR, + .rsvd = ~1, + },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR, + .w1c = 0x1, + .post_write = bbram_isr_postw, + },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR, + .ro = 0x1, + },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER, + .pre_write = bbram_ier_prew, + },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR, + .pre_write = bbram_idr_prew, + },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK, + .pre_write = bbram_msw_lock_prew, + .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK, + } +}; + +static void bbram_ctrl_reset(DeviceState *dev) +{ + XlnxBBRam *s = XLNX_BBRAM(dev); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + if (i < R_BBRAM_0 || i > R_BBRAM_8) { + register_reset(&s->regs_info[i]); + } + } + + bbram_update_irq(s); +} + +static const MemoryRegionOps bbram_ctrl_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void bbram_ctrl_realize(DeviceState *dev, Error **errp) +{ + XlnxBBRam *s = XLNX_BBRAM(dev); + + if (s->crc_zpads) { + s->bbram8_wo = true; + } + + bbram_bdrv_read(s, errp); +} + +static void bbram_ctrl_init(Object *obj) +{ + XlnxBBRam *s = XLNX_BBRAM(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + reg_array = + register_init_block32(DEVICE(obj), bbram_ctrl_regs_info, + ARRAY_SIZE(bbram_ctrl_regs_info), + s->regs_info, s->regs, + &bbram_ctrl_ops, + XLNX_BBRAM_ERR_DEBUG, + R_MAX * 4); + + sysbus_init_mmio(sbd, ®_array->mem); + sysbus_init_irq(sbd, &s->irq_bbram); +} + +static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + + qdev_prop_drive.set(obj, v, name, opaque, errp); + + /* Fill initial data if backend is attached after realized */ + if (dev->realized) { + bbram_bdrv_read(XLNX_BBRAM(obj), errp); + } +} + +static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + qdev_prop_drive.get(obj, v, name, opaque, errp); +} + +static void bbram_prop_release_drive(Object *obj, const char *name, + void *opaque) +{ + qdev_prop_drive.release(obj, name, opaque); +} + +static const PropertyInfo bbram_prop_drive = { + .name = "str", + .description = "Node name or ID of a block device to use as BBRAM backend", + .realized_set_allowed = true, + .get = bbram_prop_get_drive, + .set = bbram_prop_set_drive, + .release = bbram_prop_release_drive, +}; + +static const VMStateDescription vmstate_bbram_ctrl = { + .name = TYPE_XLNX_BBRAM, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static Property bbram_ctrl_props[] = { + DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *), + DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void bbram_ctrl_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = bbram_ctrl_reset; + dc->realize = bbram_ctrl_realize; + dc->vmsd = &vmstate_bbram_ctrl; + device_class_set_props(dc, bbram_ctrl_props); +} + +static const TypeInfo bbram_ctrl_info = { + .name = TYPE_XLNX_BBRAM, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxBBRam), + .class_init = bbram_ctrl_class_init, + .instance_init = bbram_ctrl_init, +}; + +static void bbram_ctrl_register_types(void) +{ + type_register_static(&bbram_ctrl_info); +} + +type_init(bbram_ctrl_register_types) diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig index 3059c5dae03..24cfc18f8b1 100644 --- a/hw/nvram/Kconfig +++ b/hw/nvram/Kconfig @@ -30,3 +30,7 @@ config XLNX_EFUSE_VERSAL config XLNX_EFUSE_ZYNQMP bool select XLNX_EFUSE + +config XLNX_BBRAM + bool + select XLNX_EFUSE_CRC diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index 6dc54d98734..202a5466e63 100644 --- a/hw/nvram/meson.build +++ b/hw/nvram/meson.build @@ -16,5 +16,6 @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files( 'xlnx-versal-efuse-ctrl.c')) softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files( 'xlnx-zynqmp-efuse.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) From patchwork Thu Sep 30 15:11:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514909 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp274337jam; Thu, 30 Sep 2021 08:24:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwdWavU6IoXFpc8fZSPXy3ozNWLil/NI3HDyN9sr4VYq0ib8awVkScZiADUZfC08RIvmKsZ X-Received: by 2002:a05:600c:190b:: with SMTP id j11mr5949778wmq.138.1633015456266; Thu, 30 Sep 2021 08:24:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015456; cv=none; d=google.com; s=arc-20160816; b=UPH8tOoEKMnM3xaJMMFjjPHeMcA+uLdRh64EKQFfHnJ3x1XzmZFemeH/RMUjjztmT1 Ly7S9ZrwAypkko2nVzxjajXnxmrCM5N5LD2U+ZbAWvy4Qoi1gV3b6kwmSbiAQuht1icJ udPB6Vzx+exRZJ8EwR5dNJUcvAyM47gbqtMVDa6UErI5RgmYiLsfF0AQEX+1K6RER3m6 aQ+K2cRWCVXUBENrb2mzd6eVeoiAU7Mw+dW64TEcvVdppEzwIpaBfv1xUwGKelnAaUCb d8alkHl3QV4ETv8pMtSSwD4kb0GnPbILf7IrxmgB4kWp9vzJV/p74mquBZZS6AjtXvl2 xCkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BVVGQaFtY+zcuvVCpwrCcg36mAkrFaMBGiBzIwrFBNo=; b=PAhKFQF+qW8h2TwlqaQEaUIgzoO5XZzKUNUsEExTaVyod9L3az4HzL6sZoC4ery9iH iNHLlSRmRp5i874pNCvpqggDSjpiBCDlzMSX1u87MKyNVckUFFGyWp+ovEVsaXjKBQ1b MloHTis66ugy7RRx20E+pnqgd5DMAeOINx3RI+ccZETF1ro1ehATwxa3l1xdtwu41Gsj SpXMoGfCgayzcWGnujgXS8jwhN4E326zJ1w3geHTBlRb/OObGCmeWKb+LZGieSWwceMe r3C97jChFEKeTgq6n3jH77N2o+uU4wGNZXO3jk9igster2OM7jiE1R0tgwMpTtpIbLrz hUfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8W+Qqzj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g17si4813612wmq.47.2021.09.30.08.24.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:24:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8W+Qqzj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxux-0000Ps-5a for patch@linaro.org; Thu, 30 Sep 2021 11:24:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjL-0000Eg-OY for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:41904) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjH-0003yI-LP for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:14 -0400 Received: by mail-wr1-x435.google.com with SMTP id w29so10652475wra.8 for ; Thu, 30 Sep 2021 08:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BVVGQaFtY+zcuvVCpwrCcg36mAkrFaMBGiBzIwrFBNo=; b=P8W+QqzjS4Da6b12wEA7XTCl0xFS0NPxyV3aaa3VsvzRbLt9bhcUknf3jcDOfqW5ad +KsU/FBiWcRUdqq1gBqmwUQkd6JRmg+SIwlkzR3A2ogykRk8jx+rpO0c31yzIBtoY1g9 wx1y5ihg+VY5yDxgCLcaJPgLeZ6dQ7OH/1HTilSzjw6wNt5iSB5o5ht3av6wJyx18gie 5o5M6Xl+IP6ihymyiQIgzqSZyYC8iEAfqgqqdf5+xdcDLSQeJ8tzv+mX7mP24t2/L1Br NUW67bRiJUV/zYaFxESWG3DoLWGY+Y3R1RgW8aDbzoGpkoHfJDifMW6B2oCB94LmJA+r nQoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVVGQaFtY+zcuvVCpwrCcg36mAkrFaMBGiBzIwrFBNo=; b=bxmhGuDNfk3queU1dAsu6dAqPIT+TEx8CmXNi2lJqqiq2Px3h+Y0Rb/Brc5GrzFw/1 pBvn5VHLRNezrKyDlxW6y+x/ogQeOTSFIxCyM/WewoFVUuiMqBtq0feXNNWVQqJZ5ZTW BSAM2B+MKWlL4+TCNie/N4WFNIpzEg/9P1Y0FAx7XGW3gg/w+LAH3R9czngqR+4MvVRF 37pr+vbFpDX4t7J10Y+/PRda/5rVRcKBkz6DeHkFCbXyr+YXrzkMMuctsTgEd6cj3QcR cHwoICEZWoXrOx90NSei600qiscA0/idFcewe8qev7bMfGhuxEW/yYDHFRa+9tcViM7G v7Ow== X-Gm-Message-State: AOAM530fAyjLQh9z/w0R9UOuigshPhmA0vHSduNOMwcK5FfwfJbV9r+6 fZoGAwNV4GXERnfFlKfUMQtfrZSgmGkfOg== X-Received: by 2002:adf:f946:: with SMTP id q6mr6829432wrr.437.1633014730353; Thu, 30 Sep 2021 08:12:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device Date: Thu, 30 Sep 2021 16:11:46 +0100 Message-Id: <20210930151201.9407-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho Connect the support for Versal Battery-Backed RAM (BBRAM) The command argument: -drive if=pflash,index=0,... Can be used to optionally connect the bbram to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The backend storage must be a seekable binary file, and its size must be 36 bytes or larger. A file with all binary 0's is a 'blank'. Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 5 +++++ hw/arm/xlnx-versal-virt.c | 36 ++++++++++++++++++++++++++++++++++++ hw/arm/xlnx-versal.c | 18 ++++++++++++++++++ hw/arm/Kconfig | 1 + 4 files changed, 60 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 9b790517478..1cac6133383 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -24,6 +24,7 @@ #include "qom/object.h" #include "hw/usb/xlnx-usb-subsystem.h" #include "hw/misc/xlnx-versal-xramc.h" +#include "hw/nvram/xlnx-bbram.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -79,6 +80,7 @@ struct Versal { } iou; XlnxZynqMPRTC rtc; + XlnxBBRam bbram; } pmc; struct { @@ -105,6 +107,7 @@ struct Versal { #define VERSAL_GEM1_WAKE_IRQ_0 59 #define VERSAL_ADMA_IRQ_0 60 #define VERSAL_XRAM_IRQ_0 79 +#define VERSAL_BBRAM_APB_IRQ_0 121 #define VERSAL_RTC_APB_ERR_IRQ 121 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_RTC_ALARM_IRQ 142 @@ -172,6 +175,8 @@ struct Versal { #define MM_PMC_SD0 0xf1040000U #define MM_PMC_SD0_SIZE 0x10000 +#define MM_PMC_BBRAM_CTRL 0xf11f0000 +#define MM_PMC_BBRAM_CTRL_SIZE 0x00050 #define MM_PMC_CRP 0xf1260000U #define MM_PMC_CRP_SIZE 0x10000 #define MM_PMC_RTC 0xf12a0000 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 5bca360dcec..e1c5ead475a 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -356,6 +356,26 @@ static void fdt_add_rtc_node(VersalVirt *s) g_free(name); } +static void fdt_add_bbram_node(VersalVirt *s) +{ + const char compat[] = TYPE_XLNX_BBRAM; + const char interrupt_names[] = "bbram-error"; + char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL); + + qemu_fdt_add_subnode(s->fdt, name); + + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + interrupt_names, sizeof(interrupt_names)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_PMC_BBRAM_CTRL, + 2, MM_PMC_BBRAM_CTRL_SIZE); + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); + g_free(name); +} + static void fdt_nop_memory_nodes(void *fdt, Error **errp) { Error *err = NULL; @@ -510,6 +530,18 @@ static void create_virtio_regions(VersalVirt *s) } } +static void bbram_attach_drive(XlnxBBRam *dev) +{ + DriveInfo *dinfo; + BlockBackend *blk; + + dinfo = drive_get_by_index(IF_PFLASH, 0); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + if (blk) { + qdev_prop_set_drive(DEVICE(dev), "drive", blk); + } +} + static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) { BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; @@ -570,6 +602,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_usb_xhci_nodes(s); fdt_add_sd_nodes(s); fdt_add_rtc_node(s); + fdt_add_bbram_node(s); fdt_add_cpu_nodes(s, psci_conduit); fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); @@ -579,6 +612,9 @@ static void versal_virt_init(MachineState *machine) memory_region_add_subregion_overlap(get_system_memory(), 0, &s->soc.fpd.apu.mr, 0); + /* Attach bbram backend, if given */ + bbram_attach_drive(&s->soc.pmc.bbram); + /* Plugin SD cards. */ for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 547a26603a3..23451ae0126 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -314,6 +314,23 @@ static void versal_create_xrams(Versal *s, qemu_irq *pic) } } +static void versal_create_bbram(Versal *s, qemu_irq *pic) +{ + SysBusDevice *sbd; + + object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, + sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, + &error_fatal, + "crc-zpads", "0", + NULL); + sbd = SYS_BUS_DEVICE(&s->pmc.bbram); + + sysbus_realize(sbd, &error_fatal); + memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, + sysbus_mmio_get_region(sbd, 0)); + sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]); +} + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -402,6 +419,7 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_sds(s, pic); versal_create_rtc(s, pic); versal_create_xrams(s, pic); + versal_create_bbram(s, pic); versal_map_ddr(s); versal_unimp(s); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 18832abf7d1..d35ded9b241 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -381,6 +381,7 @@ config XLNX_VERSAL select XLNX_ZDMA select XLNX_ZYNQMP select OR_IRQ + select XLNX_BBRAM config NPCM7XX bool From patchwork Thu Sep 30 15:11:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514911 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp275743jam; Thu, 30 Sep 2021 08:25:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzXShKHTUiQmHYuoh9TnE9mV7LMYqaJJlnpi73RQNmG4FLIni7JFTGnT9BAeEmsKMzAIdqc X-Received: by 2002:adf:f687:: with SMTP id v7mr7079564wrp.347.1633015541138; Thu, 30 Sep 2021 08:25:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015541; cv=none; d=google.com; s=arc-20160816; b=NIGYMMk3UXn+7WIHsnGUn64Ur0y45b4GAdCyKhvs4OC0GZuBsW11NVOAWlNVgcawrj bZ3H8VnDIv5j6VbHj7Ug2xDc8rkc7GB2LnwRufIOj5P5Kpjsx+N7Fue0YH/d7Z8m7mpP bHclLMSvaJASJeb791TLc7a2DZT/XCJIbMDJspCCkzOu7JcY4hgzHohEkSoEzWQS1rNo kFc93NS/YEdzdg0rYiC9W4ouykObAkYPt1eBErrn5NFTBj2zNTM8fG3Lr53vMoHw4Rz4 AVDeXyTjDQKCEGijHUqfmXEQDWam9xP8soag28cUZO8IxPQRSEHrEpDjjIrdfPTZgTIw QB/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E3kt++M6qm+//4TVEnDCmggaulDZDKOvhIh/GerLN3c=; b=ZzS5ID1zkwjftBCi8we++feMgDOYASkPoq/0PXJ4DEAw1Sr33iKl2XpJft5AFQ6sS6 fTpAK/4ANMDRW/u3QuY1rzYSU2m9FSn40sxXb3QcbRsAKqcTr45/DKMgqqDO1V4LHOtA zSSrlkJ/14NWjyz0PwiWEygHvjbFKMOOErJsmrSEQkOfbmshvjEa204AETqMymRoYKNM WZlYsulUCJN9vR4a9k1/XPekSvkcT+DkF/1piEsIihZX4wwlHNoFVFgBu+7iJ9K/GtGt DEwilntCBzqqt8dHMg9tAYORB/7PZ/gRy6lda5yfU0fOJxCcoNNvZCcdn97qI/X50n61 y9tA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HgRZiyIU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q18si6850740wme.0.2021.09.30.08.25.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:25:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HgRZiyIU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxwJ-00037k-2Q for patch@linaro.org; Thu, 30 Sep 2021 11:25:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjL-0000Eh-PN for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:42896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjI-0003zG-SZ for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:14 -0400 Received: by mail-wm1-x335.google.com with SMTP id q127-20020a1ca785000000b0030cb71ea4d1so4627563wme.1 for ; Thu, 30 Sep 2021 08:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=E3kt++M6qm+//4TVEnDCmggaulDZDKOvhIh/GerLN3c=; b=HgRZiyIUNem9/KtZRXSK8ez7xsGMgqstfOMrD/TCKXnz7SN1yQqMywhLufvnsoupdI n/jfoUMmH5oXZG5Mt71RVGlOb65Vk2gQWCKm9k5WyiM0F/WTKmfRCWgWoQlV/f6rJ8TA d2WdFxQwbvwQZ5rV71qN8BICo6wv9zcqN+gQ7fe8nFXl0FCHQPbVZJe7h1iVxZygA6bM x41+Qdq9UPMmm8OMhexADlMnuhExeDgvnrv3GwwGghI1ZRU0XFrq2EreX62YxHd/9sQu 7dBYeq5FXCVkhW5jiKE43584DWLzCZXmEkszQT/D/Nr1k1emu4ePIjT47UPFXewlBYs7 QJVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E3kt++M6qm+//4TVEnDCmggaulDZDKOvhIh/GerLN3c=; b=b7xNpRSAlsjgrpTunjvf/RgEbuodLtLOUB5W9+89bFqJjLsapPK9oKkXRxjVc4tTdR EZz9ItLU4lXura+HS3CKNUKuJnFiyxPfSeAyX+1GUdtFB1HuHRGWaORNwYBLVRtYJOcw 8DxfVyWnr78/3CpiCcKVlqCaObmey6UgscuMoZ0eFjsRyUnM59zfVX2WdTGccnyKMAuG Mf6fKeS5cbzIv5vI1llFOae0Gi8q9yBS7CsL6iZ1KYWRhOVG8w8xrxXiNkncs8JCdcig nRc8KMVvHrzomfYrs+CkeZ60/zboougxDSFo0hIYLdcWO/3wPtL34ipqPROE6UAxUALR 7lBw== X-Gm-Message-State: AOAM532hzN3AD25uDqNcq0rtwiZUd4i9tRxKkggT44OrtN5jCEKZF30q QVAvw671D5AHEQE9qgUqw3L2GJ0y9kIlzQ== X-Received: by 2002:a05:600c:1c26:: with SMTP id j38mr16989770wms.12.1633014731371; Thu, 30 Sep 2021 08:12:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device Date: Thu, 30 Sep 2021 16:11:47 +0100 Message-Id: <20210930151201.9407-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho Connect the support for Versal eFUSE one-time field-programmable bit array. The command argument: -drive if=pflash,index=1,... Can be used to optionally connect the bit array to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The backend storage must be a seekable binary file, and its size must be 3072 bytes or larger. A file with all binary 0's is a 'blank'. Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 10 +++++++ hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++ hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + 4 files changed, 102 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 1cac6133383..895ba12c61e 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -25,6 +25,7 @@ #include "hw/usb/xlnx-usb-subsystem.h" #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" +#include "hw/nvram/xlnx-versal-efuse.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -81,6 +82,9 @@ struct Versal { XlnxZynqMPRTC rtc; XlnxBBRam bbram; + XlnxEFuse efuse; + XlnxVersalEFuseCtrl efuse_ctrl; + XlnxVersalEFuseCache efuse_cache; } pmc; struct { @@ -110,6 +114,7 @@ struct Versal { #define VERSAL_BBRAM_APB_IRQ_0 121 #define VERSAL_RTC_APB_ERR_IRQ 121 #define VERSAL_SD0_IRQ_0 126 +#define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 #define VERSAL_RTC_SECONDS_IRQ 143 @@ -177,6 +182,11 @@ struct Versal { #define MM_PMC_SD0_SIZE 0x10000 #define MM_PMC_BBRAM_CTRL 0xf11f0000 #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 +#define MM_PMC_EFUSE_CTRL 0xf1240000 +#define MM_PMC_EFUSE_CTRL_SIZE 0x00104 +#define MM_PMC_EFUSE_CACHE 0xf1250000 +#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 + #define MM_PMC_CRP 0xf1260000U #define MM_PMC_CRP_SIZE 0x10000 #define MM_PMC_RTC 0xf12a0000 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index e1c5ead475a..d2f55e29b64 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -376,6 +376,41 @@ static void fdt_add_bbram_node(VersalVirt *s) g_free(name); } +static void fdt_add_efuse_ctrl_node(VersalVirt *s) +{ + const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL; + const char interrupt_names[] = "pmc_efuse"; + char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL); + + qemu_fdt_add_subnode(s->fdt, name); + + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + interrupt_names, sizeof(interrupt_names)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_PMC_EFUSE_CTRL, + 2, MM_PMC_EFUSE_CTRL_SIZE); + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); + g_free(name); +} + +static void fdt_add_efuse_cache_node(VersalVirt *s) +{ + const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE; + char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", + MM_PMC_EFUSE_CACHE); + + qemu_fdt_add_subnode(s->fdt, name); + + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_PMC_EFUSE_CACHE, + 2, MM_PMC_EFUSE_CACHE_SIZE); + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); + g_free(name); +} + static void fdt_nop_memory_nodes(void *fdt, Error **errp) { Error *err = NULL; @@ -542,6 +577,18 @@ static void bbram_attach_drive(XlnxBBRam *dev) } } +static void efuse_attach_drive(XlnxEFuse *dev) +{ + DriveInfo *dinfo; + BlockBackend *blk; + + dinfo = drive_get_by_index(IF_PFLASH, 1); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + if (blk) { + qdev_prop_set_drive(DEVICE(dev), "drive", blk); + } +} + static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) { BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; @@ -603,6 +650,8 @@ static void versal_virt_init(MachineState *machine) fdt_add_sd_nodes(s); fdt_add_rtc_node(s); fdt_add_bbram_node(s); + fdt_add_efuse_ctrl_node(s); + fdt_add_efuse_cache_node(s); fdt_add_cpu_nodes(s, psci_conduit); fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); @@ -615,6 +664,9 @@ static void versal_virt_init(MachineState *machine) /* Attach bbram backend, if given */ bbram_attach_drive(&s->soc.pmc.bbram); + /* Attach efuse backend, if given */ + efuse_attach_drive(&s->soc.pmc.efuse); + /* Plugin SD cards. */ for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 23451ae0126..b2705b6925e 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -331,6 +331,44 @@ static void versal_create_bbram(Versal *s, qemu_irq *pic) sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]); } +static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) +{ + SysBusDevice *part = SYS_BUS_DEVICE(dev); + + object_property_set_link(OBJECT(part), "efuse", + OBJECT(&s->pmc.efuse), &error_abort); + + sysbus_realize(part, &error_abort); + memory_region_add_subregion(&s->mr_ps, base, + sysbus_mmio_get_region(part, 0)); +} + +static void versal_create_efuse(Versal *s, qemu_irq *pic) +{ + Object *bits = OBJECT(&s->pmc.efuse); + Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); + Object *cache = OBJECT(&s->pmc.efuse_cache); + + object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, + TYPE_XLNX_VERSAL_EFUSE_CTRL); + + object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, + TYPE_XLNX_VERSAL_EFUSE_CACHE); + + object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, + sizeof(s->pmc.efuse), + TYPE_XLNX_EFUSE, &error_abort, + "efuse-nr", "3", + "efuse-size", "8192", + NULL); + + qdev_realize(DEVICE(bits), NULL, &error_abort); + versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); + versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); + + sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); +} + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -420,6 +458,7 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_rtc(s, pic); versal_create_xrams(s, pic); versal_create_bbram(s, pic); + versal_create_efuse(s, pic); versal_map_ddr(s); versal_unimp(s); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d35ded9b241..2d37d29f02b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -382,6 +382,7 @@ config XLNX_VERSAL select XLNX_ZYNQMP select OR_IRQ select XLNX_BBRAM + select XLNX_EFUSE_VERSAL config NPCM7XX bool From patchwork Thu Sep 30 15:11:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514910 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp274541jam; Thu, 30 Sep 2021 08:24:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGFrb/y5ZKb+DC8qPtIEnoyEgiFQaTQDLby83eInltYt3m48NT5/lRKsQeNc4/7Ob8JXBy X-Received: by 2002:adf:f583:: with SMTP id f3mr6763836wro.116.1633015468295; Thu, 30 Sep 2021 08:24:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015468; cv=none; d=google.com; s=arc-20160816; b=KIxp0mZvzi2I7SyvROQfKcXMF7mfpqhwcCBISdImw2K2uMquwskc2g1XMcFSYYGp9O Wt6IFydW/L0bK/xBM8TFBBjAt1H5yg5ops1wBIm+bFL+APAHv/FjtKWGwiOc1TZ+VRAt 3o17EMtkjMEYH9XbYpHlg3DdDeyQBOblOZXKOlnyAoY9votWWjfa0xR1msseDmLoBBZc xYw7XPyCxKwH5UlUPfzoZGTZ4a8NKRwO51nfpma4aMYutGoyVZU5AfF5i6WY4/50IdyL j3Rcq4tGGQ99INPVd2pwsBhksAWAS0xrNNYdzy2IfdwL7+ecvaT47KEhLnFBISfvneac q90A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yjhbRCAKKYqjO4C2ZkK+yymBrVJFR30QkaOvBMx2jBI=; b=u3Ejvul0mH3xH4aL7TwIarn0Qt5flQF6VfKCkHLi8RZd82kqu7NvWatSZwSOQPD+1r 4cw4itMN77PGijdX6wsu5Xgz0q9ugTntSIe5tX+jA3V3+4yzyiMTPvQR3DWPyVTJq+qv UtGjkVOuaUEjMDfQl4mqstvZEcyOSY0wbmiuuTjReeCUw27mg8GRVy9pUbuF+HYpU8zt e2A2p6ctlCR9akXzvZmQhnKNXLAcB3co2TK4qkzWvi/HIvDkrNRkTBlNtxrul638UUvw uACpkECNWVAI7/VTZCoIc9Ob48SfOlu2xYmqaTe3oZMTYHCygqNxC6ho9p4zts+MpWx+ s1qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FXA+A754; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d2si3213153wrf.24.2021.09.30.08.24.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:24:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FXA+A754; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxv9-0000nm-6y for patch@linaro.org; Thu, 30 Sep 2021 11:24:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjQ-0000Hw-N2 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46013) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjJ-0003zL-9V for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:18 -0400 Received: by mail-wr1-x42f.google.com with SMTP id d21so10619216wra.12 for ; Thu, 30 Sep 2021 08:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yjhbRCAKKYqjO4C2ZkK+yymBrVJFR30QkaOvBMx2jBI=; b=FXA+A754pTxRs1hvFTeMlV+M5QR1LiCb4J7a2xFViwKX9z0gkCqxQ3NzizAPlXdLXL 76k7p7iS47uMqrQ88hj2+REGrzuP4zpe6aTIrxurvUqYRM7d0Qnv/ftb1UHsM24y/jNy DSsMek11O8dhRDqNSGasjZGiEHlC8X8am6E6dsky5aj8c2/S8xuGNTinLTFYeJbpUfQs YGTkD0Pziw6QV1esXNteixTwsI/Ytn8BqRFLkPp0H1iMwpH0aw7c2WR1BSydVHcVbOr5 fkWjToZKYSMq3KuUdO0qnBHPN0oDcMUYzlzuGlfUd27lDw0xhGiIbb9fVVrU41yIhuuI mtTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yjhbRCAKKYqjO4C2ZkK+yymBrVJFR30QkaOvBMx2jBI=; b=VrwGKQl2DGYrfTbyI6or9xnofy+kl+aIw+Iq8OxrpoF6H4T2ElxWRn+V2UfCK3yaL5 LukJyfrrar8I0RvXSVSwa3e7XqdkffJoE66xldFiLw4S/WCvVKTvB/PUqMJM0T/u9aqA 04gXFkCGnVBt1SNfdodTeepuobDNS4gFgUZ5VhDmam1dNHAcbHj4SaeOlJ1iWjFIXg0j ipx/vKELfDeZtDvyAOBW3WGy30ALw5JQqLOC84shD+GFUrgLd0nWX3TwBdy7jcItx4oY gn5uVufLSpc4xVzfSWnEx7xTH0qziDwzbAf2J/h0+qbkGnn5a/NoR+Vygv8uFMUumdc+ RYvA== X-Gm-Message-State: AOAM530F+eIrucJUfPVvjCV1ADBVGtqzAoy4qKl7bx3Ir0r0dEsAKLiE yqWiS76pwddSHhkfuG4kLc5gAujgQwseBQ== X-Received: by 2002:a5d:64a3:: with SMTP id m3mr6957558wrp.157.1633014732053; Thu, 30 Sep 2021 08:12:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device Date: Thu, 30 Sep 2021 16:11:48 +0100 Message-Id: <20210930151201.9407-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM) The command argument: -drive if=pflash,index=2,... Can be used to optionally connect the bbram to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The backend storage must be a seekable binary file, and its size must be 36 bytes or larger. A file with all binary 0's is a 'blank'. Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zcu102.c | 15 +++++++++++++++ hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++ hw/Kconfig | 1 + 4 files changed, 38 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c84fe15996e..067e8a5238a 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -36,6 +36,7 @@ #include "qom/object.h" #include "net/can_emu.h" #include "hw/dma/xlnx_csu_dma.h" +#include "hw/nvram/xlnx-bbram.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -100,6 +101,7 @@ struct XlnxZynqMPState { MemoryRegion *ddr_ram; MemoryRegion ddr_ram_low, ddr_ram_high; + XlnxBBRam bbram; MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 6c6cb02e861..b247c5779bf 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -98,6 +98,18 @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt) } } +static void bbram_attach_drive(XlnxBBRam *dev) +{ + DriveInfo *dinfo; + BlockBackend *blk; + + dinfo = drive_get_by_index(IF_PFLASH, 2); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + if (blk) { + qdev_prop_set_drive(DEVICE(dev), "drive", blk); + } +} + static void xlnx_zcu102_init(MachineState *machine) { XlnxZCU102 *s = ZCU102_MACHINE(machine); @@ -136,6 +148,9 @@ static void xlnx_zcu102_init(MachineState *machine) qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); + /* Attach bbram backend, if given */ + bbram_attach_drive(&s->soc.bbram); + /* Create and plug in the SD cards */ for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { BusState *bus; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 4e5a471e30b..1e8e2ddcc27 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -66,6 +66,9 @@ #define RTC_ADDR 0xffa60000 #define RTC_IRQ 26 +#define BBRAM_ADDR 0xffcd0000 +#define BBRAM_IRQ 11 + #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { @@ -226,6 +229,22 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); } +static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + + object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, + sizeof(s->bbram), TYPE_XLNX_BBRAM, + &error_fatal, + "crc-zpads", "1", + NULL); + sbd = SYS_BUS_DEVICE(&s->bbram); + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, BBRAM_ADDR); + sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -626,6 +645,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); + xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { diff --git a/hw/Kconfig b/hw/Kconfig index 8cb7664d705..b6fb6a45074 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -81,3 +81,4 @@ config XLNX_ZYNQMP select REGISTER select CAN_BUS select PTIMER + select XLNX_BBRAM From patchwork Thu Sep 30 15:11:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514903 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp267535jam; Thu, 30 Sep 2021 08:17:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzH9hl/0ljz5mXO7TfQIlw82xN3ttNb6Fg+51dIltww8n4LqmH+z0EwF29W9swNWm5MddGd X-Received: by 2002:a17:907:d87:: with SMTP id go7mr7244905ejc.46.1633015078495; Thu, 30 Sep 2021 08:17:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015078; cv=none; d=google.com; s=arc-20160816; b=EULeBrKlNWbA0zc9ZM2Epv4EA5ikhnyZraNrdtp5dN3HviQiQlgUTOrdnHBSJJelkO fYgADb/hDIhtpVPaQEC+BLRz5ZC8xX9S4fkGkeTmBMRSkGzHkLWA1HWTg0ESX24GiR6a 70RJZ12kBv9wh5ADoJ01mCu76D2HLZKgcGAxAH18r6k9K6R+EWVemEZRC5inqckufR4R 2N5fIs9K2cOP1AsZFFMDzpMHsXM+CInG5FlyHmUFur+e+Cq8cThJaYjrUZYZ51YtKlyo Kf3ZtNdAGJwo1GXDZiFVVV9WwAEJvn3Tc2OIPFtf50l7iQHtx3VCumIay2NxTqpA1Ucj k3ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dAm4kAQzPJzmjXpkBCUCwi+HBhQGyOtDz2aEIW6LGo0=; b=sFKNexAS+7O8vkgtWE6Tp70eD35TeUl6kjfuP3gz6hyi0AaBGKiJIkhaCRHRkT6nWT AyzR3mIfy4rLwYn7PnGNydKFOUX/+WG9aa5K0VmGWwQ3zmWeL9419JrWZT1ro5TSL+eO rsdV4avNr65qE6ZTqVKwsUrUZo3EA+OrRLysSjOhP8h1Y+5wK64yG1fgiF2PC1Zjx/SW +A6xamTdcMbBx0puB4lv0U3ohdTDNrRCK15Zy0AZcT4z4g/fHaixC5r/T4zRa212CXE6 IHtWgwjyXM2yaMsavHCk8kmNG7UtfgAsSfjty9CxY6/z44jypHaOQSVroHL8FDloSeTK 3h/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="OTd/l/x9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v20si3845760ejv.515.2021.09.30.08.17.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:17:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="OTd/l/x9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxor-0006U2-Ag for patch@linaro.org; Thu, 30 Sep 2021 11:17:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjN-0000Fe-Mn for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:46817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjK-000403-Sc for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: by mail-wm1-x32d.google.com with SMTP id d207-20020a1c1dd8000000b00307e2d1ec1aso4602955wmd.5 for ; Thu, 30 Sep 2021 08:12:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dAm4kAQzPJzmjXpkBCUCwi+HBhQGyOtDz2aEIW6LGo0=; b=OTd/l/x9NyjfBOr05C/pBRpSkCNmfKKI+CLekDkpuhGj/f9e09m4+54s526+HGISTx 4/Tfbi/rcsistnJHLGjPMtrqX4q7b0dVNj4vt96EEKZSwrkE/d1CEHJIu7rnsKLlhXrY 1r6hgUSbPxRqSRzRjrXbvWyk9ABSkepb4stysQpR7opWKBSn13gY1qnybG/5Kg3vXDVj jhUF8pd4tT4utTkS0r73Nv549eEUt1SWWOnUQJwl+iwCcsAL2Jyz1Tt6t+e2eOfTIeIi Jz27TmsoyF0dZBnRyo2iltwAAeL+Atbe1iNW3jdtMy4tUt3odNSJyqU7qG43kAt7fN7b virA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dAm4kAQzPJzmjXpkBCUCwi+HBhQGyOtDz2aEIW6LGo0=; b=mKB3W8NJLzihPoCp4phe73BzLWK9K0mgpfG/oduQOWuw5mRiNoN0VA4XRdx5AIZpgO hxeS+fczWLKr1dSWVE5PKRqXgi3IL3fNWe10yFDaS7o7N0kbLwzkYht0zj2xNVw+VK2R tW0sxa6/Har00QuKHIIHlnG4Wr4lFbhG9i2QGXQKHqfaBPACMm0zoKynkQLOxwx4r1Tw FknMO8jWGIpBzzLbod9+1EXOwjWFEiGoVR1ANJ2WZtVQx81zaIDbeGjvG9mPP+1fcgPJ uN1pkb6epkKlUb0ekQyN8JHE9MJzZTc89DbgJZ4a+9aQoZxYR1YQ84C7ebg798xChUa0 XJ7Q== X-Gm-Message-State: AOAM531GeDfx92CT/xlP/buo784rKvsUJOpS9HOqUQ/2CDpGI4fqwHpH /fO+jUcO33M8QtzECA3/vo2zXGTMiqnkew== X-Received: by 2002:a1c:210a:: with SMTP id h10mr5679475wmh.165.1633014732815; Thu, 30 Sep 2021 08:12:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device Date: Thu, 30 Sep 2021 16:11:49 +0100 Message-Id: <20210930151201.9407-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho Connect the support for ZynqMP eFUSE one-time field-programmable bit array. The command argument: -drive if=pflash,index=3,... Can be used to optionally connect the bit array to a backend storage, such that field-programmed values in one invocation can be made available to next invocation. The backend storage must be a seekable binary file, and its size must be 768 bytes or larger. A file with all binary 0's is a 'blank'. Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 3 +++ hw/arm/xlnx-zcu102.c | 15 +++++++++++++++ hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++ hw/Kconfig | 1 + 4 files changed, 48 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 067e8a5238a..062e637fe49 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -37,6 +37,7 @@ #include "net/can_emu.h" #include "hw/dma/xlnx_csu_dma.h" #include "hw/nvram/xlnx-bbram.h" +#include "hw/nvram/xlnx-zynqmp-efuse.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -102,6 +103,8 @@ struct XlnxZynqMPState { MemoryRegion *ddr_ram; MemoryRegion ddr_ram_low, ddr_ram_high; XlnxBBRam bbram; + XlnxEFuse efuse; + XlnxZynqMPEFuse efuse_ctrl; MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index b247c5779bf..3dc2b5e8ca4 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -110,6 +110,18 @@ static void bbram_attach_drive(XlnxBBRam *dev) } } +static void efuse_attach_drive(XlnxEFuse *dev) +{ + DriveInfo *dinfo; + BlockBackend *blk; + + dinfo = drive_get_by_index(IF_PFLASH, 3); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + if (blk) { + qdev_prop_set_drive(DEVICE(dev), "drive", blk); + } +} + static void xlnx_zcu102_init(MachineState *machine) { XlnxZCU102 *s = ZCU102_MACHINE(machine); @@ -151,6 +163,9 @@ static void xlnx_zcu102_init(MachineState *machine) /* Attach bbram backend, if given */ bbram_attach_drive(&s->soc.bbram); + /* Attach efuse backend, if given */ + efuse_attach_drive(&s->soc.efuse); + /* Create and plug in the SD cards */ for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { BusState *bus; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 1e8e2ddcc27..1c52a575aad 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -69,6 +69,9 @@ #define BBRAM_ADDR 0xffcd0000 #define BBRAM_IRQ 11 +#define EFUSE_ADDR 0xffcc0000 +#define EFUSE_IRQ 87 + #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { @@ -245,6 +248,31 @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); } +static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) +{ + Object *bits = OBJECT(&s->efuse); + Object *ctrl = OBJECT(&s->efuse_ctrl); + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, + TYPE_XLNX_ZYNQMP_EFUSE); + + object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, + sizeof(s->efuse), + TYPE_XLNX_EFUSE, &error_abort, + "efuse-nr", "3", + "efuse-size", "2048", + NULL); + + qdev_realize(DEVICE(bits), NULL, &error_abort); + object_property_set_link(ctrl, "efuse", bits, &error_abort); + + sbd = SYS_BUS_DEVICE(ctrl); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, EFUSE_ADDR); + sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -646,6 +674,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); xlnx_zynqmp_create_bbram(s, gic_spi); + xlnx_zynqmp_create_efuse(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { diff --git a/hw/Kconfig b/hw/Kconfig index b6fb6a45074..ad20cce0a95 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -82,3 +82,4 @@ config XLNX_ZYNQMP select CAN_BUS select PTIMER select XLNX_BBRAM + select XLNX_EFUSE_ZYNQMP From patchwork Thu Sep 30 15:11:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514907 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp270966jam; Thu, 30 Sep 2021 08:21:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwr2S9qALZHVnUvwA/uch8RDjjCnR3+DD53yKATJdLpcZqy1N8axtYvkCN342vjWKuMp4sr X-Received: by 2002:a05:600c:510a:: with SMTP id o10mr16460751wms.81.1633015271333; Thu, 30 Sep 2021 08:21:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015271; cv=none; d=google.com; s=arc-20160816; b=sq52+ejXP/HgZ2pHEJcZEOds1mc+zzfBJfAQjxhZPG9HB9FL5J0b5EZe3xGUBWBw3O p/G8khWHr3VEO/hnFif5wQTkloSvuA2/S6/VnKuCcgecBpx3IFa7Qy8OSLIGzPOIKID6 jQwny+rtelO5oCH33SqWDQsO1r6AViDmY/D1h4vuwyfjmlk8+geMxt+qqX9zJWGjROQt HuzxCBt3gNIf6hIs3L6aM73V1qARAlcIYn2dxipSgHyQUWQCmlBW7TV133aM4RF/309u HOQq2RTh4u3v6H1NSshMZWkaAF3HAdcNEaaqqfgicWUT/LAmKCE1lTRee36kQrX4q8rN SGUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=u3LelZdD7qPOY216rLv/itDL3Wpuq00I0pFgeV7VjOE=; b=I2/2OcPD28LnXVyjo+0ejDb0/9QHKQ0u20V8UynIPNJ6hnt5r4D3j00p/HdmPgjpmn QY2idWYo9lvEytIQEVTaJ016XmpCTz1+y512t+JWbr2/zAabsBe5yUgicQPTBg2yZosa f5mulMm7tko0NXzw6WcMfigVukya5D6BQbhA58XaYzxWnuFooPzcRDcetNMYll2mxbBF UO5olBlBSIhNuvO6GQKizufJNOT8RJ4csh7QjTfU4PFOKx4N5GOVMrdsJEblWzCcBDMg YFux+Xdq7VpHD8RiXN9PZwuW20bctuEjI3AJxu6h4Nx4pAd89xpqL+Oj2R321/TV+RW0 shvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TNopLoNt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p19si6501884wmq.197.2021.09.30.08.21.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:21:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TNopLoNt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxrx-0003pj-4j for patch@linaro.org; Thu, 30 Sep 2021 11:21:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjP-0000Hv-Ni for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:45663) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjL-00040I-EJ for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:17 -0400 Received: by mail-wm1-x32b.google.com with SMTP id b192-20020a1c1bc9000000b0030cfaf18864so4600996wmb.4 for ; Thu, 30 Sep 2021 08:12:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u3LelZdD7qPOY216rLv/itDL3Wpuq00I0pFgeV7VjOE=; b=TNopLoNtvYobasKjESWyi+Q9IbgxnfjTaFHmDOV96YsBIkHU57juV1RxzPehenrkkT A3xNP4CuIHurGsBHS2FCGBF7+k2Doo8YSS9VsfgIxnNALGsiPtjWKPOGZB/Wgld8NBsB WCsLnRTfESTiCf6gJMjOm1vO96QbATHZ2NnxExj7FcKo/D/i4Pk03aQ1nWKvtG2nlISH SspSfF4+1oQKNDJZX5obvLdGW7JqZKgKLVTXamA4ZrNSZtgbJQ33ilvcOw1TeU9dSn+c p8sgGdgfGqAGHIi5vlkE+BvRzmHx6+gZhbJkmA/svXhtfBhfG29meZ5WO5GysywzJh8v 76Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u3LelZdD7qPOY216rLv/itDL3Wpuq00I0pFgeV7VjOE=; b=omu5/KoLnNgeHhHdtEFatV6xjgVA0iBjK/2hUYFmIcuh23zC03AaVtB9dPtE/95nAx nZ0pI97DpAu5f9MbNIiBTxUcYIOMcGZpyxWyYRObcE6lnYBC5l2jvuI8HGw2Rs+mhrf/ OTg3rPs9KpGvUkiS2YTmDjsCS/MMe9Gk2MvTvgT+gh99FO8Yvvm8myPkL6XfqALkzECR O3el0Zobbwwf5bH2M6Dqfk8nTSh+DKun1aEBTn5JRvoqyVQzl/FzTHXU46Z0eCT9F0ae rwV1/Ub+5LyLbjXzn0cfTfF6RBhbkESZObom1xP/mHvHUrDO7We3gPEeGC6H2j4yRcKb oubQ== X-Gm-Message-State: AOAM533ft9bzvm2CO50dfdycEqfDPlvnRvbm1n061UBNI38vhSwYOEwL cpltRVQL2es/3z5yngYbB9f30flmFkn6Cw== X-Received: by 2002:a05:600c:4c96:: with SMTP id g22mr13835978wmp.83.1633014733387; Thu, 30 Sep 2021 08:12:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/22] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage Date: Thu, 30 Sep 2021 16:11:50 +0100 Message-Id: <20210930151201.9407-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tong Ho Add BBRAM and eFUSE usage to the Xilinx Versal Virt board document. Signed-off-by: Tong Ho Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) -- 2.20.1 diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst index 27f73500d95..92ad10d2da4 100644 --- a/docs/system/arm/xlnx-versal-virt.rst +++ b/docs/system/arm/xlnx-versal-virt.rst @@ -32,6 +32,8 @@ Implemented devices: - OCM (256KB of On Chip Memory) - XRAM (4MB of on chip Accelerator RAM) - DDR memory +- BBRAM (36 bytes of Battery-backed RAM) +- eFUSE (3072 bytes of one-time field-programmable bit array) QEMU does not yet model any other devices, including the PL and the AI Engine. @@ -175,3 +177,50 @@ Run the following at the U-Boot prompt: fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000> booti 30000000 - 20000000 +BBRAM File Backend +"""""""""""""""""" +BBRAM can have an optional file backend, which must be a seekable +binary file with a size of 36 bytes or larger. A file with all +binary 0s is a 'blank'. + +To add a file-backend for the BBRAM: + +.. code-block:: bash + + -drive if=pflash,index=0,file=versal-bbram.bin,format=raw + +To use a different index value, N, from default of 0, add: + +.. code-block:: bash + + -global xlnx,bbram-ctrl.drive-index=N + +eFUSE File Backend +"""""""""""""""""" +eFUSE can have an optional file backend, which must be a seekable +binary file with a size of 3072 bytes or larger. A file with all +binary 0s is a 'blank'. + +To add a file-backend for the eFUSE: + +.. code-block:: bash + + -drive if=pflash,index=1,file=versal-efuse.bin,format=raw + +To use a different index value, N, from default of 1, add: + +.. code-block:: bash + + -global xlnx,efuse.drive-index=N + +.. warning:: + In actual physical Versal, BBRAM and eFUSE contain sensitive data. + The QEMU device models do **not** encrypt nor obfuscate any data + when holding them in models' memory or when writing them to their + file backends. + + Thus, a file backend should be used with caution, and 'format=luks' + is highly recommended (albeit with usage complexity). + + Better yet, do not use actual product data when running guest image + on this Xilinx Versal Virt board. From patchwork Thu Sep 30 15:11:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514914 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp278748jam; Thu, 30 Sep 2021 08:29:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwxC7wU6zMZm8AVxysZjgAcjFF0b13XvKzb4ahESq+dvQTY9XpTctZf4tHpJ4XkVc6WIcZ X-Received: by 2002:ac8:7051:: with SMTP id y17mr7157224qtm.117.1633015751540; Thu, 30 Sep 2021 08:29:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015751; cv=none; d=google.com; s=arc-20160816; b=S25Mg5BkfLVXxddkMWrnbzRIeNChmtBLyzGc1GeyF/s8X+ik9mJ/UjG31K8GeEcoQN cj3C/CUqWtMe2Rcxn9jqWT5wYaQlcgzL2QQ+Q95mgFxYMQS4ZvmpELt+2POhgweSDMUS CM8qsjMEBYp9wJa6TpKaVCJehVGDHCSI99aBb1j0eiVAk8LY/CWBp+f3wPpUd4RGlu9A 4vYFXDtvgmOvZQY/u9rgA/kGazAbtOfcQM7X55QkvcN6gFHyeaxGQRcxVitshOc6Q1Et 5Cn1KsNEI9V5Nxy5hGjfh3eJQJKnXnS1FewuhWZjv7Wkt/dy8bXUqPyb4enhEfPpeYdc lBWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+7xcBw3AnVLKXJaypxFNhcX1MNAtuWFGLoGLnPrZ0nM=; b=CA2ZPM/acf3oxnhG40P/1oxmnQcwvfGBSiuYuTOcZiK9NpdwjUUqf7kO3B9YSw2KHb 2mQhYfeUdUWUIAiPMOILHoluDfo3x0wLO1noNM085S4fNKtImBg17SxS8Sp6Guhc38im C6KdpYhpLxdbPdGCjyQPI5TR3hunqP2KBPO6IbtbRxqHQDfwapJ23MQ+smaoQ6qwb8d8 XIb4pzuE0Drics2V9JH9L6I0KMaKjKIhpragmJU8A6iTpNZW9Mo81YNzB9bPU2sNESYt 65OTb+oTFC+ouZLMLqxJ7g5HCXE1bBBEAm+VjbEmgUyl32MwQhf37113XtPuVQBxbeai P1fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zSC2VNSZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j18si2542516vsf.83.2021.09.30.08.29.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:29:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zSC2VNSZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxzi-0001Jw-UB for patch@linaro.org; Thu, 30 Sep 2021 11:29:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjP-0000Hu-N0 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:46018) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjL-00041Q-FK for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:19 -0400 Received: by mail-wr1-x433.google.com with SMTP id d21so10619428wra.12 for ; Thu, 30 Sep 2021 08:12:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+7xcBw3AnVLKXJaypxFNhcX1MNAtuWFGLoGLnPrZ0nM=; b=zSC2VNSZdQvDR4Azw4+4ynOJbizWiGGfOCOBW2nKCP2hk08jwHNXnBSIYjleup6grW JvZ1Q1LhQPyy83m3I5E8j2G4Ti0XIDk+WprRMWhXQHwQ2MsfOy/iezG+Co8VJoXO2n9s ItDLLOpYfQflhIR/fwI0kBpKEYblTGapQSM/00jpgsXVDpYd1fD1dwBDZtTKP6p34MiZ c7evtzuq+HYrQjuBaq8WYmJq1sV4I3bX0XVAp4XZDhARcy3cA8IgVKKDmxaNMagm8pyS SP1adk8Vc5HxKfkEy/YVWDDTEv2mnvbhSIs46kbPJrjQzDQRWnToQTb5Npwr7ABjCH5Y ynIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+7xcBw3AnVLKXJaypxFNhcX1MNAtuWFGLoGLnPrZ0nM=; b=qhTEOt9w2P8jzUWCGMZSiUElcxUJisAdJqU1B6+/eawqYHeC9JSXKN/DpreLJGBVgm lqkTzw6XVnbn7TClJ+sKK72Ww1whId444Zn/4ymVERx4V2n3kyfwLqWtubvv0jvpdMXj k9GWaxaqoF8LDd+CnK5dd5j//A15cdKfw5LFaY403/HltDijBt4V1rf+uQUKoKPyUrZ7 J5DU678si2P8gNyOdaWGD32NsczPOsqIQS4imF6piTZ3LzGQF2t6w8KEcQsTDOVI6vL2 r0DiGRqxbTfgptxggCD3zJ0qC4lR7szrGn5LjQMNeW3CskxodyHj0zHNSzM85I8KtGgR 6CuA== X-Gm-Message-State: AOAM5326WBepGwJ839iD+50KJKT++RlWBbUGHEP2RPOUTZAu7LgO9xr/ 4fmbrv+rV99mXNGioOAHIzY0WOF1lyWbvg== X-Received: by 2002:adf:a19e:: with SMTP id u30mr4423778wru.326.1633014733952; Thu, 30 Sep 2021 08:12:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs Date: Thu, 30 Sep 2021 16:11:51 +0100 Message-Id: <20210930151201.9407-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The aarch64-linux QEMU usermode binaries can never run 32-bit code, so they do not need to include the GDB XML for it. (arm_cpu_register_gdb_regs_for_features() will not use these XML files if the CPU has ARM_FEATURE_AARCH64, so we will not advertise to gdb that we have them.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210921162901.17508-2-peter.maydell@linaro.org --- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index 4713253709f..d0c603c54ec 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,5 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml TARGET_HAS_BFLT=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index fae831558da..d3ee10c00f3 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_WORDS_BIGENDIAN=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml TARGET_HAS_BFLT=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y From patchwork Thu Sep 30 15:11:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514913 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp278239jam; Thu, 30 Sep 2021 08:28:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFyqpdBrBudaY4FX0w/T3nPR7Z5UuaMrz07aTgRJiGj+oMtS5JJ94sXK9aTUik1GKE6NLf X-Received: by 2002:a17:906:5d1:: with SMTP id t17mr7467340ejt.120.1633015711972; Thu, 30 Sep 2021 08:28:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015711; cv=none; d=google.com; s=arc-20160816; b=oZdYoQVzT9ekYnq52xSKpj97KmLwBU6UIP3Ur6FfBhw7auHgCnqMSLgYOydKTWZk1H +mbl1q+VcPivU6oqTDKKoMSXmjTclHp1ULQEY2up4XXsJyXwMQCnJbxVGjogbzmNj7qr MHB3oGUMZiNhMlOzetORBaMbErKdBMp5lQlp+kq9Glj6U+CQgpsy/C3t9QLJa0ZcieE2 tBvSRYpbWaBI1HRBhO041L8WJPn/ubUbhBx4wiCIK2nltOE1S6g2ooXua9iyk0tlAruY f+GFQ3VBhFLM2u8x4NZpIyeYRAgnTOehMjlYryktU63wIQNwqWDGMlYX3BWCIDTX/oxC HbhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fiYS5FCgMGXDlrIgAMDa81IO9f4zjGQxiSsB7/2wRaE=; b=VmUjwNLF0IPrZVb9URYodEMBqqqB1rFgrli3hW+x/pY7ToMD0dFkE51Jp/a6JOFJNc XTqW9B6ZHBwtN9rhgx1rPMFioJ+ylEEPCOeIsTx8j+nR1PUBef3RmruFt4hIW/cuOEFF su8VLOvB+Jng9lXI61YAWQsVXluoQIQnKnVAmcuFVYJRSM1gAwH58M2cjD/t167YJc0J SiwuJ48QJOJ6d7J1uj/R9GkzzPKswM37wEqnM4Tnxj2W9DF556Na9Xx8oUhcLHwfO4FA bSKti2/A3qQ5IT1IFWjkhlwJccpOyUQXjOvQwT7F1BqGGp5DNZYYvFpKggz29QcVeMWT xiwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="rZfqMY/L"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ka6si3573059ejc.26.2021.09.30.08.28.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:28:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="rZfqMY/L"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxz4-0007wO-D3 for patch@linaro.org; Thu, 30 Sep 2021 11:28:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjP-0000Hx-Pa for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:39666) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjN-000426-4T for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:18 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d26so10653518wrb.6 for ; Thu, 30 Sep 2021 08:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fiYS5FCgMGXDlrIgAMDa81IO9f4zjGQxiSsB7/2wRaE=; b=rZfqMY/Lollarl/7PGVlJsMc/jAu6+ralbtVrOWwq+WQByPMLo9pRjp5gWLgtEtEed 1u4mYmU9H6bYIRzgi/oNks/hYRDt9M8/GpujQN59TA0BacXA6MPqg+HdiIxCXwrrTPtW hGC/8agv0FfHuz0GxrLP9JSsIiorTWFMVBAFjBWPtqiz/g1RaN7ZTk7yY5zmMIUD34Vf O39qetCaGc8YluFKoN03vwya2LBVvq4F6ZSO01urRHAvml/IKy+ymoRCbmyQwgXXixzA 0wuGCCVKYAUNbGHZdiI9K61DFgOkICY94X0/lDefWkG3vw0JU9ZuyhvEg9rjmRkcmBz6 drBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fiYS5FCgMGXDlrIgAMDa81IO9f4zjGQxiSsB7/2wRaE=; b=JIfOa5uICc41IYA+0UNDewgJFMgxzlzuG4sMwXBduPuYx14NG6ewQv1kOGV10ovjmO EUT5M6yzTMZIsPBIdwyd5AOV8m225tg+auM86aIJgtjtNTGtGfGAxIQ65fRO7Bft5oFW 0yO8x4FRe1wtMMdrHtSvYTvgGf3qm6g90HFfBa5xo3Af3t5M3ncaK6ZgRH7jlQnh07LM kEVR0OaW7y6TopXI+K2mCYF4KurvapHIU0Pi6v+6MzHKraK42LkWvEIsPyM6YCQ/2UVy YltOnnCamTaSj1B4lIcOrRzIVvQykZxJutQeddboj2CZ+pe3R0X15qn7Zza6JwV8G583 8Sbg== X-Gm-Message-State: AOAM530Ywb0OEygqEwwhhr94Ow8m+8ziv/Pv1j4EVJjOOad5mZzmzq/U dtONDtj0Le3p1MVRETfGToquIGZvsTfvEA== X-Received: by 2002:a5d:4704:: with SMTP id y4mr7051047wrq.138.1633014734659; Thu, 30 Sep 2021 08:12:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/22] target/arm: Fix coding style issues in gdbstub code in helper.c Date: Thu, 30 Sep 2021 16:11:52 +0100 Message-Id: <20210930151201.9407-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're going to move this code to a different file; fix the coding style first so checkpatch doesn't complain. This includes deleting the spurious 'break' statements after returns in the vfp_gdb_get_reg() function. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210921162901.17508-3-peter.maydell@linaro.org --- target/arm/helper.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 62742214473..84bba9a2244 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -72,9 +72,12 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) } } switch (reg - nregs) { - case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break; - case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; - case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break; + case 0: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + case 1: + return gdb_get_reg32(buf, vfp_get_fpscr(env)); + case 2: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); } return 0; } @@ -98,9 +101,15 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) } } switch (reg - nregs) { - case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; - case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; - case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; + case 0: + env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); + return 4; + case 1: + vfp_set_fpscr(env, ldl_p(buf)); + return 4; + case 2: + env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); + return 4; } return 0; } @@ -119,7 +128,7 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) return gdb_get_reg32(buf, vfp_get_fpsr(env)); case 33: /* FPCR */ - return gdb_get_reg32(buf,vfp_get_fpcr(env)); + return gdb_get_reg32(buf, vfp_get_fpcr(env)); default: return 0; } From patchwork Thu Sep 30 15:11:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514915 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp281491jam; Thu, 30 Sep 2021 08:32:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw05OUJ8MBzMqyNxVnvclu2FflmSK5VADKkdn5qblDI3vVvDiSQV2hQbOj4TnvnrdsJILpd X-Received: by 2002:adf:b311:: with SMTP id j17mr6785166wrd.340.1633015924611; Thu, 30 Sep 2021 08:32:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015924; cv=none; d=google.com; s=arc-20160816; b=OKUhpcEIqTiJU4C+u/UlYhqsM8hwuzPu0GMsYYTlgMGhfEImCJLdsM0x+AkcVL94YR PISrJyI9wzrS4DrFuwMfvbPw5ojC7GTTbtYrTRepG9nUXeKnqEvPPEhnZ8ZMDq6JyTT1 0sRlO24jB8soHfKCvwhtPQuB8AJHFWnt2Syso/3lYstz0zApXUOHXNLIXyuGAEQ9w+Bo TGIQxE3BVe9Vz5HnjSmGTOdgr5hgf1bAcWLydgap0UENa1K12XE34lRpFB2ToNImx7sW bBCWs0YcEy+4apYudxTgNxU3vNFqu/dAKXj8oua3WYbbgYeGIYYkHtO6rFWOxnnZoRNX hR1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h8MNT+gke2zd6+3WRfBNIerS/9ED4qUqaYzEGl7mX60=; b=mSM320V+oxttvLyuosD3WGAJNxVR3QNO5qqLK4afRbmt99V7Lk6mxis9Q46y1I0Zoy qpFCG1qIVk0RogDtlI6Dtwyd6rE9S35Azi3EXK9ONMQNP9OMkAk9LDt53WyMO+/TZ/kq sBGFIjMq6MrYrRteRTRjeA+0JRbTQgXToFd/nBfW0T42MemuUA0D3UmuKKODrgREGqUN Xh3exzY5hGTvBI097qOspvJafH6rRQ358B7ZqY+k1Sp9vxXKbwnsIcrHgeoRISmfzvbm wZe2q/3LeZjrLML+KKvwAX08tyeMMUwJ7X8NSMd9n5Sp04ReQ1vwrPSsw4YFIHjTA6ES mVHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nqgt0M77; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a11si3332908wrt.546.2021.09.30.08.32.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:32:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nqgt0M77; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVy2V-0003ib-4D for patch@linaro.org; Thu, 30 Sep 2021 11:32:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjR-0000Ik-Hv for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35383) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjN-000430-BF for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:20 -0400 Received: by mail-wr1-x435.google.com with SMTP id v25so61333wra.2 for ; Thu, 30 Sep 2021 08:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h8MNT+gke2zd6+3WRfBNIerS/9ED4qUqaYzEGl7mX60=; b=Nqgt0M77GtGwj7g/80ObbDL6woEabD+GA8jLuisERUydPdNAKJ5zsAKAbPrQ5GdMbp YwNOeLTikH7wC1MjjRu2HX2/M/DGFdFnALUU8FOiO5e3brquYhuuN42dOOtbDHIPtf2D dJyZ2gYZk/j/YhNr1b146bVluP3mQNUlC5M459g7pgRgWEhBamNvccutb6VzFS7Lyg42 NuLrLB4i+ASTzy0TM29HJT5q04cKDoK8MvZrbiLN59UvLMizJ/NLRUF25r6Ok2tkM0Zp ZqU8dCuKA/varOW8m5gDkaHorHnsybubN96lKSRd+FUDMu6BiTQQbZGJrr67+MF79It3 51fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h8MNT+gke2zd6+3WRfBNIerS/9ED4qUqaYzEGl7mX60=; b=GAniuAuIe2fOLuIVfabw/UgGRAdMW2tJ+s6VBMC9HDES7d9HjMAcmTwggg+PuJLzWZ h2fzwcuOpeD0YcQrL+EPKy82jjLRs6chF8+JpdSxUWQyenMguIuKvvYSFpwaf9gok1NW /wPhxfMHqehWQFjvoJrrL6IpUA7eBcpSy08pn4jZQzFB9JHQlVz+pFIZcbIj5cckACrd VNgA5F2TtbAf6v8n2qhpdQKFj4qEsMWmV1oPb8Gq8/vf5U/yxeRM2Zb+dWMpWednO/uw IGkaRuZ1UsUVKRqPlK++acEYjbyp96jj5T2sLVRpjPdMSrUsZI88wfSFHtZuzQA/Rjbh x4GA== X-Gm-Message-State: AOAM533HhQI4TigByDwWtJGs95pPCZrIrNzVHBTO8xclH7WoBh/rttAc jrJ1QsnZZ4ctw6wFttTJLtr/lY60QmSgQw== X-Received: by 2002:adf:a147:: with SMTP id r7mr6161791wrr.52.1633014735522; Thu, 30 Sep 2021 08:12:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/22] target/arm: Move gdbstub related code out of helper.c Date: Thu, 30 Sep 2021 16:11:53 +0100 Message-Id: <20210930151201.9407-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently helper.c includes some code which is part of the arm target's gdbstub support. This code has a better home: in gdbstub.c and gdbstub64.c. Move it there. Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move into gdbstub64.c, this means that they're now compiled only for TARGET_AARCH64 rather than always. That is the only case when they would ever be used, but it does mean that the ifdef in arm_cpu_register_gdb_regs_for_features() needs to be adjusted to match. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210921162901.17508-4-peter.maydell@linaro.org --- target/arm/internals.h | 7 ++ target/arm/gdbstub.c | 130 ++++++++++++++++++++ target/arm/gdbstub64.c | 140 +++++++++++++++++++++ target/arm/helper.c | 271 ----------------------------------------- 4 files changed, 277 insertions(+), 271 deletions(-) -- 2.20.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 9fbb3649682..3612107ab28 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1270,4 +1270,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); } +#ifdef TARGET_AARCH64 +int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); +int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +#endif + #endif diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 826601b3415..cbf156d192f 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "exec/gdbstub.h" typedef struct RegisterSysregXmlParam { @@ -124,6 +125,98 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; + + /* VFP data registers are always little-endian. */ + if (reg < nregs) { + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); + } + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* Aliases for Q regs. */ + nregs += 16; + if (reg < nregs) { + uint64_t *q = aa32_vfp_qreg(env, reg - 32); + return gdb_get_reg128(buf, q[0], q[1]); + } + } + switch (reg - nregs) { + case 0: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + case 1: + return gdb_get_reg32(buf, vfp_get_fpscr(env)); + case 2: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); + } + return 0; +} + +static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; + + if (reg < nregs) { + *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); + return 8; + } + if (arm_feature(env, ARM_FEATURE_NEON)) { + nregs += 16; + if (reg < nregs) { + uint64_t *q = aa32_vfp_qreg(env, reg - 32); + q[0] = ldq_le_p(buf); + q[1] = ldq_le_p(buf + 8); + return 16; + } + } + switch (reg - nregs) { + case 0: + env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); + return 4; + case 1: + vfp_set_fpscr(env, ldl_p(buf)); + return 4; + case 2: + env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); + return 4; + } + return 0; +} + +/** + * arm_get/set_gdb_*: get/set a gdb register + * @env: the CPU state + * @buf: a buffer to copy to/from + * @reg: register number (offset from start of group) + * + * We return the number of bytes copied + */ + +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + const ARMCPRegInfo *ri; + uint32_t key; + + key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; + ri = get_arm_cp_reginfo(cpu->cp_regs, key); + if (ri) { + if (cpreg_field_is_64bit(ri)) { + return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + } else { + return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + } + } + return 0; +} + +static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return 0; +} + static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, ARMCPRegInfo *ri, uint32_t ri_key, int bitsize, int regnum) @@ -319,3 +412,40 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) } return NULL; } + +void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) +{ + CPUState *cs = CPU(cpu); + CPUARMState *env = &cpu->env; + + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * The lower part of each SVE register aliases to the FPU + * registers so we don't need to include both. + */ +#ifdef TARGET_AARCH64 + if (isar_feature_aa64_sve(&cpu->isar)) { + gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, + arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), + "sve-registers.xml", 0); + } else { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } +#endif + } else if (arm_feature(env, ARM_FEATURE_NEON)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 51, "arm-neon.xml", 0); + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 35, "arm-vfp3.xml", 0); + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 19, "arm-vfp.xml", 0); + } + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, + arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), + "system-registers.xml", 0); + +} diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 251539ef799..596878666d7 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -17,7 +17,9 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" +#include "internals.h" #include "exec/gdbstub.h" int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) @@ -69,3 +71,141 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* Unknown register. */ return 0; } + +int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + { + /* 128 bit FP register - quads are in LE order */ + uint64_t *q = aa64_vfp_qreg(env, reg); + return gdb_get_reg128(buf, q[1], q[0]); + } + case 32: + /* FPSR */ + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + /* FPCR */ + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + default: + return 0; + } +} + +int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + /* 128 bit FP register */ + { + uint64_t *q = aa64_vfp_qreg(env, reg); + q[0] = ldq_le_p(buf); + q[1] = ldq_le_p(buf + 8); + return 16; + } + case 32: + /* FPSR */ + vfp_set_fpsr(env, ldl_p(buf)); + return 4; + case 33: + /* FPCR */ + vfp_set_fpcr(env, ldl_p(buf)); + return 4; + default: + return 0; + } +} + +int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len = 0; + for (vq = 0; vq < cpu->sve_max_vq; vq++) { + len += gdb_get_reg128(buf, + env->vfp.zregs[reg].d[vq * 2 + 1], + env->vfp.zregs[reg].d[vq * 2]); + } + return len; + } + case 32: + return gdb_get_reg32(buf, vfp_get_fpsr(env)); + case 33: + return gdb_get_reg32(buf, vfp_get_fpcr(env)); + /* then 16 predicates and the ffr */ + case 34 ... 50: + { + int preg = reg - 34; + int vq, len = 0; + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { + len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + } + return len; + } + case 51: + { + /* + * We report in Vector Granules (VG) which is 64bit in a Z reg + * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. + */ + int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return gdb_get_reg64(buf, vq * 2); + } + default: + /* gdbstub asked for something out our range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); + break; + } + + return 0; +} + +int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + + /* The first 32 registers are the zregs */ + switch (reg) { + /* The first 32 registers are the zregs */ + case 0 ... 31: + { + int vq, len = 0; + uint64_t *p = (uint64_t *) buf; + for (vq = 0; vq < cpu->sve_max_vq; vq++) { + env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; + env->vfp.zregs[reg].d[vq * 2] = *p++; + len += 16; + } + return len; + } + case 32: + vfp_set_fpsr(env, *(uint32_t *)buf); + return 4; + case 33: + vfp_set_fpcr(env, *(uint32_t *)buf); + return 4; + case 34 ... 50: + { + int preg = reg - 34; + int vq, len = 0; + uint64_t *p = (uint64_t *) buf; + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { + env->vfp.pregs[preg].p[vq / 4] = *p++; + len += 8; + } + return len; + } + case 51: + /* cannot set vg via gdbstub */ + return 0; + default: + /* gdbstub asked for something out our range */ + break; + } + + return 0; +} diff --git a/target/arm/helper.c b/target/arm/helper.c index 84bba9a2244..9b317899a66 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12,7 +12,6 @@ #include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" @@ -54,110 +53,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, static void switch_mode(CPUARMState *env, int mode); static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); -static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) -{ - ARMCPU *cpu = env_archcpu(env); - int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; - - /* VFP data registers are always little-endian. */ - if (reg < nregs) { - return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); - } - if (arm_feature(env, ARM_FEATURE_NEON)) { - /* Aliases for Q regs. */ - nregs += 16; - if (reg < nregs) { - uint64_t *q = aa32_vfp_qreg(env, reg - 32); - return gdb_get_reg128(buf, q[0], q[1]); - } - } - switch (reg - nregs) { - case 0: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); - case 1: - return gdb_get_reg32(buf, vfp_get_fpscr(env)); - case 2: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); - } - return 0; -} - -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - ARMCPU *cpu = env_archcpu(env); - int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; - - if (reg < nregs) { - *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); - return 8; - } - if (arm_feature(env, ARM_FEATURE_NEON)) { - nregs += 16; - if (reg < nregs) { - uint64_t *q = aa32_vfp_qreg(env, reg - 32); - q[0] = ldq_le_p(buf); - q[1] = ldq_le_p(buf + 8); - return 16; - } - } - switch (reg - nregs) { - case 0: - env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); - return 4; - case 1: - vfp_set_fpscr(env, ldl_p(buf)); - return 4; - case 2: - env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); - return 4; - } - return 0; -} - -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) -{ - switch (reg) { - case 0 ... 31: - { - /* 128 bit FP register - quads are in LE order */ - uint64_t *q = aa64_vfp_qreg(env, reg); - return gdb_get_reg128(buf, q[1], q[0]); - } - case 32: - /* FPSR */ - return gdb_get_reg32(buf, vfp_get_fpsr(env)); - case 33: - /* FPCR */ - return gdb_get_reg32(buf, vfp_get_fpcr(env)); - default: - return 0; - } -} - -static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) -{ - switch (reg) { - case 0 ... 31: - /* 128 bit FP register */ - { - uint64_t *q = aa64_vfp_qreg(env, reg); - q[0] = ldq_le_p(buf); - q[1] = ldq_le_p(buf + 8); - return 16; - } - case 32: - /* FPSR */ - vfp_set_fpsr(env, ldl_p(buf)); - return 4; - case 33: - /* FPCR */ - vfp_set_fpcr(env, ldl_p(buf)); - return 4; - default: - return 0; - } -} - static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); @@ -217,134 +112,6 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } -/** - * arm_get/set_gdb_*: get/set a gdb register - * @env: the CPU state - * @buf: a buffer to copy to/from - * @reg: register number (offset from start of group) - * - * We return the number of bytes copied - */ - -static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) -{ - ARMCPU *cpu = env_archcpu(env); - const ARMCPRegInfo *ri; - uint32_t key; - - key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; - ri = get_arm_cp_reginfo(cpu->cp_regs, key); - if (ri) { - if (cpreg_field_is_64bit(ri)) { - return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); - } else { - return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); - } - } - return 0; -} - -static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) -{ - return 0; -} - -#ifdef TARGET_AARCH64 -static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) -{ - ARMCPU *cpu = env_archcpu(env); - - switch (reg) { - /* The first 32 registers are the zregs */ - case 0 ... 31: - { - int vq, len = 0; - for (vq = 0; vq < cpu->sve_max_vq; vq++) { - len += gdb_get_reg128(buf, - env->vfp.zregs[reg].d[vq * 2 + 1], - env->vfp.zregs[reg].d[vq * 2]); - } - return len; - } - case 32: - return gdb_get_reg32(buf, vfp_get_fpsr(env)); - case 33: - return gdb_get_reg32(buf, vfp_get_fpcr(env)); - /* then 16 predicates and the ffr */ - case 34 ... 50: - { - int preg = reg - 34; - int vq, len = 0; - for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { - len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); - } - return len; - } - case 51: - { - /* - * We report in Vector Granules (VG) which is 64bit in a Z reg - * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. - */ - int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; - return gdb_get_reg64(buf, vq * 2); - } - default: - /* gdbstub asked for something out our range */ - qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); - break; - } - - return 0; -} - -static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) -{ - ARMCPU *cpu = env_archcpu(env); - - /* The first 32 registers are the zregs */ - switch (reg) { - /* The first 32 registers are the zregs */ - case 0 ... 31: - { - int vq, len = 0; - uint64_t *p = (uint64_t *) buf; - for (vq = 0; vq < cpu->sve_max_vq; vq++) { - env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; - env->vfp.zregs[reg].d[vq * 2] = *p++; - len += 16; - } - return len; - } - case 32: - vfp_set_fpsr(env, *(uint32_t *)buf); - return 4; - case 33: - vfp_set_fpcr(env, *(uint32_t *)buf); - return 4; - case 34 ... 50: - { - int preg = reg - 34; - int vq, len = 0; - uint64_t *p = (uint64_t *) buf; - for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { - env->vfp.pregs[preg].p[vq / 4] = *p++; - len += 8; - } - return len; - } - case 51: - /* cannot set vg via gdbstub */ - return 0; - default: - /* gdbstub asked for something out our range */ - break; - } - - return 0; -} -#endif /* TARGET_AARCH64 */ - static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* Return true if the regdef would cause an assertion if you called @@ -8667,44 +8434,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif } -void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) -{ - CPUState *cs = CPU(cpu); - CPUARMState *env = &cpu->env; - - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* - * The lower part of each SVE register aliases to the FPU - * registers so we don't need to include both. - */ -#ifdef TARGET_AARCH64 - if (isar_feature_aa64_sve(&cpu->isar)) { - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), - "sve-registers.xml", 0); - } else -#endif - { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, - 34, "aarch64-fpu.xml", 0); - } - } else if (arm_feature(env, ARM_FEATURE_NEON)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 51, "arm-neon.xml", 0); - } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 35, "arm-vfp3.xml", 0); - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 19, "arm-vfp.xml", 0); - } - gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), - "system-registers.xml", 0); - -} - /* Sort alphabetically by type name, except for "any". */ static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) { From patchwork Thu Sep 30 15:11:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514922 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp293826jam; Thu, 30 Sep 2021 08:46:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwfQhLG8olDOaoytkD7jzFQQ4vqOa/PS2bh6Xc9BuKHyTNXORXVCf+BFYv3pqzpN43BnVnx X-Received: by 2002:adf:aac8:: with SMTP id i8mr3144205wrc.54.1633016766422; Thu, 30 Sep 2021 08:46:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016766; cv=none; d=google.com; s=arc-20160816; b=BT9WBuZxvQIjhHpbHKl/nJe1DORpzg8U6OdtGhPKLUPv3kyByWjUxxxYtJ19hyU/7Q SFBst7lVVweQ9zUro2qTQxDcZ4OPkjKWWa4e6wGb2UtnO131dJoFEtb0KnFJ6gNpbTxU nzzXZCHQsVoGvKT0nXTeLQeRbswmIi2EmenJnLFu97Eh3bazhbsW8H6RU3EhEeuDk2hH nviisxXWZy4Mve4XosX3XfVvK1961PiPb+iiCJ04oT1UmlYLH1bwrRa+XfsKqLrEeMnv RBeN7c4Wjk4MzSSP9ATx0FxJ6zAKyYcWIgKfZhIWo/KFm6jmYZNg0d/AXYzBigtdO0z2 3oaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=df3ktvzb5CG1BKifpEL1YOCm6Kq0Mca9smWBzQx/djI=; b=a3cY1iXrlqZ8Szo3I9fKJzA2yOcff/u6znUyHscfqIas2w7qeU0y6rGrR6avKg4h+1 Qz/8UnkUsTPmpu531GcabnZx3v43xG995KczfpDgb+aV56W0DCW9BI+bvz354E+KNVRi Cf+ONSDpNrCq3zti3t3kuXyUgzwsTr/PuM+nxW2A8sUYjDIRaYBfK7gHHIpIjq9oXfWj LoPqxBvHy+2T7IcmY/GYyT0I442E/MnNGECCTQCPlBWiIGcHZTAllpJyTrzkXrNdfsYr 6UcCUF3Txl/xzoCu2awlBCbgLHPTXbgPQ7+MFFpbEknoa5RsTjR8kjRCCKO/rv+C9r9T HEyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m+5chfHj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y131si3431007wmc.37.2021.09.30.08.46.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:46:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m+5chfHj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVyG5-0002wF-94 for patch@linaro.org; Thu, 30 Sep 2021 11:46:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjX-0000Oz-Cq for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:29 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:36356) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjO-000434-94 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:25 -0400 Received: by mail-wr1-x42e.google.com with SMTP id h15so9053206wrc.3 for ; Thu, 30 Sep 2021 08:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=df3ktvzb5CG1BKifpEL1YOCm6Kq0Mca9smWBzQx/djI=; b=m+5chfHjifgiTA4SIyxqWb47Bhjemz1dpscjdzzeAkbDeEMoZcwiMLiTtn+crp5Urc YP4E7zOStl4SuTFRR4itTlKgO8sWgEl0iFP3EEmwVqIsmvGKe5yMtFdaaQUW09RSbOxp 99bqFIOSSG4G9xfqGcI9TcC+hE5KXUBJDMdS2pBDDwBJ1r7cDy1SJJIaDJDz9KQsXQ96 rrTJ3nkHOT3TBwAYlGW+8/Gztn58Evn1TJwqzm/051x1UpQLjBqgJFb4oeBSMRi1Kx45 wkaWCRz+DmiqD+NF3UyRhGrwaIBOqv6AeDtrN5s4JqrXf3Y3IRY8GStEU68484nP1RC3 xFIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=df3ktvzb5CG1BKifpEL1YOCm6Kq0Mca9smWBzQx/djI=; b=zKVtSkTkkSJzJ7MglbEzMZ1FuUodSJhac4CRFLdqXHIOBduOdVYpfOCzNexiwT5+R0 zOhD9389L8bnGJi+DWoHSCfPwGxHzHPcOQRbPbUbgcnbS2AUT0dSuqUsjjnpgjYLNv8S 2tWposqFEY5maYTjHNr1gZnXglhb3x47PJubWgSPCVHs15UeYQd10vHJ8cckWrwX6rHo 8+MS9wbbhNV2YCeJk3o4070cKKAtSW9KpZooZNZpHZX8GSHu7n2QL6z0280ndF91opRU FEHWzqLdBGIIlGFnxCvHiRMlLbOGUPSKkBkEX0q+MLr8zfcMULc7mYD1gYBeHQMyLK6T RJvw== X-Gm-Message-State: AOAM530VDOpd0i27P4rf8kPqy99VDC+5yv5V01d4BtVySFrFdtJQbysO OqYYen6F9RgHc7UdWST9BHJ24D0ZBD2UrA== X-Received: by 2002:a05:6000:154f:: with SMTP id 15mr4459052wry.254.1633014736219; Thu, 30 Sep 2021 08:12:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/22] target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML Date: Thu, 30 Sep 2021 16:11:54 +0100 Message-Id: <20210930151201.9407-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently we send VFP XML which includes D0..D15 or D0..D31, plus FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its definition of this XML feature does not include FPSID or FPEXC. In particular, for M-profile cores there are no FPSID or FPEXC registers, so advertising those is wrong. Move FPSID and FPEXC into their own bit of XML which we only send for A and R profile cores. This brings our definition of the XML org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for non-Neon cores...) and means we don't claim to have FPSID and FPEXC on M-profile. (It seems unlikely to me that any gdbstub users really care about being able to look at FPEXC and FPSID; but we've supplied them to gdb for a decade and it's not hard to keep doing so.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210921162901.17508-5-peter.maydell@linaro.org --- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/arm-linux-user.mak | 2 +- configs/targets/arm-softmmu.mak | 2 +- configs/targets/armeb-linux-user.mak | 2 +- target/arm/gdbstub.c | 56 ++++++++++++++++++++-------- gdb-xml/arm-neon.xml | 2 - gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++ gdb-xml/arm-vfp.xml | 2 - gdb-xml/arm-vfp3.xml | 2 - 9 files changed, 61 insertions(+), 26 deletions(-) create mode 100644 gdb-xml/arm-vfp-sysregs.xml -- 2.20.1 diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index 7703127674e..13d40b55e6d 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_NEED_FDT=y diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak index e741ffd4d30..acecc339e38 100644 --- a/configs/targets/arm-linux-user.mak +++ b/configs/targets/arm-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=arm TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl -TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index 84a98f48186..f6c95ba07a4 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,4 +1,4 @@ TARGET_ARCH=arm TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_NEED_FDT=y diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak index 255e44e8b0a..662c73d8fbd 100644 --- a/configs/targets/armeb-linux-user.mak +++ b/configs/targets/armeb-linux-user.mak @@ -2,6 +2,6 @@ TARGET_ARCH=arm TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl TARGET_WORDS_BIGENDIAN=y -TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml +TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index cbf156d192f..e0dcb33e325 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -144,11 +144,7 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) } switch (reg - nregs) { case 0: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); - case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); - case 2: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); } return 0; } @@ -172,13 +168,31 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) } } switch (reg - nregs) { + case 0: + vfp_set_fpscr(env, ldl_p(buf)); + return 4; + } + return 0; +} + +static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + case 1: + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); + } + return 0; +} + +static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; case 1: - vfp_set_fpscr(env, ldl_p(buf)); - return 4; - case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; } @@ -434,15 +448,25 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 34, "aarch64-fpu.xml", 0); } #endif - } else if (arm_feature(env, ARM_FEATURE_NEON)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 51, "arm-neon.xml", 0); - } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 35, "arm-vfp3.xml", 0); - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 19, "arm-vfp.xml", 0); + } else { + if (arm_feature(env, ARM_FEATURE_NEON)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 49, "arm-neon.xml", 0); + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 33, "arm-vfp3.xml", 0); + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, + 17, "arm-vfp.xml", 0); + } + if (!arm_feature(env, ARM_FEATURE_M)) { + /* + * A and R profile have FP sysregs FPEXC and FPSID that we + * expose to gdb. + */ + gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg, + 2, "arm-vfp-sysregs.xml", 0); + } } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml index ce3ee03ec48..9dce0a996fc 100644 --- a/gdb-xml/arm-neon.xml +++ b/gdb-xml/arm-neon.xml @@ -82,7 +82,5 @@ - - diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml new file mode 100644 index 00000000000..c4aa2721c8d --- /dev/null +++ b/gdb-xml/arm-vfp-sysregs.xml @@ -0,0 +1,17 @@ + + + + + + + diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml index b20881e9a99..ebed5b3d573 100644 --- a/gdb-xml/arm-vfp.xml +++ b/gdb-xml/arm-vfp.xml @@ -23,7 +23,5 @@ - - diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml index 227afd8017f..ef391c7144d 100644 --- a/gdb-xml/arm-vfp3.xml +++ b/gdb-xml/arm-vfp3.xml @@ -39,7 +39,5 @@ - - From patchwork Thu Sep 30 15:11:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514917 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp285898jam; Thu, 30 Sep 2021 08:36:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzWRTtg2hZKSEHs5l3EVFSqKuQSuX8tcDXL5bj7nJkeejA2u4Ag2vzqLcvUTWBu0aj5UJJK X-Received: by 2002:a17:906:1f81:: with SMTP id t1mr7367544ejr.510.1633016209149; Thu, 30 Sep 2021 08:36:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016209; cv=none; d=google.com; s=arc-20160816; b=r7DyGxw0D4f2423XD2ECa3y9In2/SdFKZL5YSxwCKWGyqxLQTxdnOwDKugFzbid+m8 bHIHkjdhWGKAM6C6dA3F++Z1hRGRnUBUc361QONNjU06wtn6q4X6oWoNFjN+ile3WdfQ yNGIaLKhy6Uz6hNOHg8Q3YUaf++wBf5hHKDURzxoml6g7ycxN0gQ7m+y5WxH4ncewoNf 555O5xvo6O8u1SStl5rpaTbcFgufAHN1NY4M+DFwIBPGf9Mh8B4NyWz/lDCfalLkFCVv E8YDC6r0Y8h19dh86GUKzQHc0eZFkZ2eLFhxPEwD7dQcTa7SyxRKVbdk7rbJMIa7c3rZ d71A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ltrwZB9sEHVMQxcU5PD2L5k5iwXwH2nTHJ4GVcoHnr0=; b=mOfUS5mtjjmDiUIbTHKdfdYcRVnoRk71GzsNvmRHHEwwNg+z8Td6wrAOIgGld5M3P8 UXe2RPetZ2j2g0TAfwdLFQ6kVdLa4R3df1njbBz/wnFifHgeGjAjHzaZZTvJd4ZuA0xL 1J3Fht7OMLf6jgWZqRbfEgqRSSrewKQehoUkqbiV3i4IiggZPpMv8HTiTBB7QhWtwpe8 cBEVFk2y1GQi2yboHpW+J0DvuOQnxE9HPrdK+1UEM4A6ps/Rij3/okPJ00tAy8Tjnwmp cYCO1c2bSqYNJ2TdNj1tJ+nabguB1D3fAZNJ11LNnuI1O6iKzAW/fNYTKNRhzfbC9XZr BIaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zZYrLbl+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y13si4499047edm.398.2021.09.30.08.36.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:36:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zZYrLbl+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVy75-0001PE-VN for patch@linaro.org; Thu, 30 Sep 2021 11:36:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjV-0000N9-Al for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:26 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46011) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjP-00043x-1C for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:23 -0400 Received: by mail-wr1-x42a.google.com with SMTP id d21so10619719wra.12 for ; Thu, 30 Sep 2021 08:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ltrwZB9sEHVMQxcU5PD2L5k5iwXwH2nTHJ4GVcoHnr0=; b=zZYrLbl+MGVSkw08Ahtc3uRNU3xm0CVbhtAzFpz6oho8KyKoB3cKlUdV3jbnukFQlo 17AHN+r4q12iBSgBX8WE5cCQkZ5GfMjv5MjVFfpxO/AZ0CW/ylVZ5ZMDtA5ie1wiGjeW gbyiXHmWJiH43wiCocvCLEThabe6CAoRVntdueBLbXub5t/tKSczAXdq0F9bTD6w3iTx trYTKo2NlCTOOQUJE7HlJty6vAgQzfx8YOuec32PuOYCuc5FOrx/N5uhE9CAGKOnAc3j f6FcCNcKO+0JHIBTEMk28H4ZNuQyu6b5YfSUtWtzlW1SbM9IfTBP0hRtBIb0nVNbIjST pQUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ltrwZB9sEHVMQxcU5PD2L5k5iwXwH2nTHJ4GVcoHnr0=; b=dYOSniO09WNhqA/b3rcEbKoDtAAy7E+sQ9nGlBoVHLgFpYR4O07DP+uJWcdsdmFEZz 55iJ79iIBoXSMDSAk4RvE7oQ1PuRVZ+m3teXzV1fjwg4R0+StDXFBvcLlJtUqY8Fg7MP qfDfQoCbBPfOJKH5lfo85ccfIhQN0HF1AM0wIIAudXYgTdaxsTKurcKQeadray64U5oQ iHw2KQ6RSwq4hP7cB8y8M9HwXLbKSLb4IRsedIzVYarcegE0cTJ5H2ir6bSJp8QRbHdb kYqitF9B/m/tW9tHJ3GtQUDM0g4bLVssVESfg9pJGZ7Ceg2TdnpwmEB63qzmRjzP061L rwVA== X-Gm-Message-State: AOAM530Iw3RjzLPhCLg/1HqrIa9NWPkvo4AnJQIj562e02xCGxKDpQOy HpV4QhqXnlB+yPwLjmo1cCPfSoVt3E4vfQ== X-Received: by 2002:a5d:4526:: with SMTP id j6mr6689986wra.224.1633014736849; Thu, 30 Sep 2021 08:12:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/22] scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() Date: Thu, 30 Sep 2021 16:11:55 +0100 Message-Id: <20210930151201.9407-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function scsi_bus_new() creates a new SCSI bus; callers can either pass in a name argument to specify the name of the new bus, or they can pass in NULL to allow the bus to be given an automatically generated unique name. Almost all callers want to use the autogenerated name; the only exception is the virtio-scsi device. Taking a name argument that should almost always be NULL is an easy-to-misuse API design -- it encourages callers to think perhaps they should pass in some standard name like "scsi" or "scsi-bus". We don't do this anywhere for SCSI, but we do (incorrectly) do it for other bus types such as i2c. The function name also implies that it will return a newly allocated object, when it in fact does in-place allocation. We more commonly name such functions foo_init(), with foo_new() being the allocate-and-return variant. Replace all the scsi_bus_new() callsites with either: * scsi_bus_init() for the usual case where the caller wants an autogenerated bus name * scsi_bus_init_named() for the rare case where the caller needs to specify the bus name and document that for the _named() version it's then the caller's responsibility to think about uniqueness of bus names. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Message-id: 20210923121153.23754-2-peter.maydell@linaro.org --- include/hw/scsi/scsi.h | 30 ++++++++++++++++++++++++++++-- hw/scsi/esp-pci.c | 2 +- hw/scsi/esp.c | 2 +- hw/scsi/lsi53c895a.c | 2 +- hw/scsi/megasas.c | 3 +-- hw/scsi/mptsas.c | 2 +- hw/scsi/scsi-bus.c | 4 ++-- hw/scsi/spapr_vscsi.c | 3 +-- hw/scsi/virtio-scsi.c | 4 ++-- hw/scsi/vmw_pvscsi.c | 3 +-- hw/usb/dev-storage-bot.c | 3 +-- hw/usb/dev-storage-classic.c | 4 ++-- hw/usb/dev-uas.c | 3 +-- 13 files changed, 43 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h index 0b726bc78c6..a567a5ed86b 100644 --- a/include/hw/scsi/scsi.h +++ b/include/hw/scsi/scsi.h @@ -146,8 +146,34 @@ struct SCSIBus { const SCSIBusInfo *info; }; -void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host, - const SCSIBusInfo *info, const char *bus_name); +/** + * scsi_bus_init_named: Initialize a SCSI bus with the specified name + * @bus: SCSIBus object to initialize + * @bus_size: size of @bus object + * @host: Device which owns the bus (generally the SCSI controller) + * @info: structure defining callbacks etc for the controller + * @bus_name: Name to use for this bus + * + * This in-place initializes @bus as a new SCSI bus with a name + * provided by the caller. It is the caller's responsibility to make + * sure that name does not clash with the name of any other bus in the + * system. Unless you need the new bus to have a specific name, you + * should use scsi_bus_new() instead. + */ +void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, + const SCSIBusInfo *info, const char *bus_name); + +/** + * scsi_bus_init: Initialize a SCSI bus + * + * This in-place-initializes @bus as a new SCSI bus and gives it + * an automatically generated unique name. + */ +static inline void scsi_bus_init(SCSIBus *bus, size_t bus_size, + DeviceState *host, const SCSIBusInfo *info) +{ + scsi_bus_init_named(bus, bus_size, host, info, NULL); +} static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d) { diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 9db10b1a487..dac054aeed4 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -388,7 +388,7 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); s->irq = pci_allocate_irq(dev); - scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info); } static void esp_pci_scsi_exit(PCIDevice *d) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 4ac21147888..8454ed17735 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -1348,7 +1348,7 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); - scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); } static void sysbus_esp_hard_reset(DeviceState *dev) diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index e2c19180a0d..85e907a7854 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -2309,7 +2309,7 @@ static void lsi_scsi_realize(PCIDevice *dev, Error **errp) pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io); QTAILQ_INIT(&s->queue); - scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info); } static void lsi_scsi_exit(PCIDevice *dev) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 8f2389d2c6a..4ff51221d4c 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -2416,8 +2416,7 @@ static void megasas_scsi_realize(PCIDevice *dev, Error **errp) s->frames[i].state = s; } - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), - &megasas_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info); } static Property megasas_properties_gen1[] = { diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c index db3219e7d20..f6c77655443 100644 --- a/hw/scsi/mptsas.c +++ b/hw/scsi/mptsas.c @@ -1315,7 +1315,7 @@ static void mptsas_scsi_realize(PCIDevice *dev, Error **errp) s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); - scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info); } static void mptsas_scsi_uninit(PCIDevice *dev) diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index 2a0a98cac91..e28a6ea053a 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -134,8 +134,8 @@ void scsi_device_unit_attention_reported(SCSIDevice *s) } /* Create a scsi bus, and attach devices to it. */ -void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host, - const SCSIBusInfo *info, const char *bus_name) +void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, + const SCSIBusInfo *info, const char *bus_name) { qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name); bus->busnr = next_scsi_bus++; diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index c210262484a..a07a8e1523f 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -1216,8 +1216,7 @@ static void spapr_vscsi_realize(SpaprVioDevice *dev, Error **errp) dev->crq.SendFunc = vscsi_do_crq; - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), - &vscsi_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &vscsi_scsi_info); /* ibmvscsi SCSI bus does not allow hotplug. */ qbus_set_hotplug_handler(BUS(&s->bus), NULL); diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c index 6d807302870..51fd09522ac 100644 --- a/hw/scsi/virtio-scsi.c +++ b/hw/scsi/virtio-scsi.c @@ -1019,8 +1019,8 @@ static void virtio_scsi_device_realize(DeviceState *dev, Error **errp) return; } - scsi_bus_new(&s->bus, sizeof(s->bus), dev, - &virtio_scsi_scsi_info, vdev->bus_name); + scsi_bus_init_named(&s->bus, sizeof(s->bus), dev, + &virtio_scsi_scsi_info, vdev->bus_name); /* override default SCSI bus hotplug-handler, with virtio-scsi's one */ qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev)); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 1f30cb020a1..cd76bd67ab7 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -1180,8 +1180,7 @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp) s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), - &pvscsi_scsi_info, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info); /* override default SCSI bus hotplug-handler, with pvscsi's one */ qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s)); pvscsi_reset_state(s); diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c index 68ebaca10c6..b24b3148c28 100644 --- a/hw/usb/dev-storage-bot.c +++ b/hw/usb/dev-storage-bot.c @@ -37,8 +37,7 @@ static void usb_msd_bot_realize(USBDevice *dev, Error **errp) s->dev.auto_attach = 0; } - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), - &usb_msd_scsi_info_bot, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &usb_msd_scsi_info_bot); usb_msd_handle_reset(dev); } diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c index 3d017a4e679..00f25bade28 100644 --- a/hw/usb/dev-storage-classic.c +++ b/hw/usb/dev-storage-classic.c @@ -65,8 +65,8 @@ static void usb_msd_storage_realize(USBDevice *dev, Error **errp) usb_desc_create_serial(dev); usb_desc_init(dev); dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE); - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), - &usb_msd_scsi_info_storage, NULL); + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), + &usb_msd_scsi_info_storage); scsi_dev = scsi_bus_legacy_add_drive(&s->bus, blk, 0, !!s->removable, s->conf.bootindex, s->conf.share_rw, s->conf.rerror, s->conf.werror, diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c index f6309a5ebfd..599d6b52a01 100644 --- a/hw/usb/dev-uas.c +++ b/hw/usb/dev-uas.c @@ -938,8 +938,7 @@ static void usb_uas_realize(USBDevice *dev, Error **errp) uas->status_bh = qemu_bh_new(usb_uas_send_status_bh, uas); dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE); - scsi_bus_new(&uas->bus, sizeof(uas->bus), DEVICE(dev), - &usb_uas_scsi_info, NULL); + scsi_bus_init(&uas->bus, sizeof(uas->bus), DEVICE(dev), &usb_uas_scsi_info); } static const VMStateDescription vmstate_usb_uas = { From patchwork Thu Sep 30 15:11:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514916 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp283436jam; Thu, 30 Sep 2021 08:34:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxVvSPdFPT4vCzoodUrnz/7mHhKCXWRefY4ZVN1/pRGqgKYA5elsr0T1GyWj/1VwD8o8Q/z X-Received: by 2002:a5d:4a0a:: with SMTP id m10mr7091033wrq.330.1633016050629; Thu, 30 Sep 2021 08:34:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016050; cv=none; d=google.com; s=arc-20160816; b=fZpgXWCpXS8ZjVIsNbhor6bHuaNZE2Ce+vmR7Ix9KSiEoWGJX2913S06UBhoVpoGaK XKrw8eKbqANDySHQWo5f7ypYwKmzfRjCJUHOo37ZOSCchv10B4Y0cUYvZwNHOXuMBwbw EJwL+05fUo6RIjTfwdeF9GvmeXoNOaOLTLATNYZcTCxMn5hyfSeufnV5WpwYuD8I6ocI rHM4G3jz1daneJJIt3UHE76LWT9ytyQ0SycHbc0ukSjfG79KLHZKtaTH1MJXLLjDlY+i odZKUcgCukeBIcj9UkkpMqFvcwEoy6GAJE38zLNgULqDetnsS8KCZZSX1WgkvqaL1WVB EWkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zPpRQrWSyjrRJfT0bIIpJXg1qS4RrwpRld2bjFRckaw=; b=XEJrC2dn/8rEf57vIk8Q/ZWXlfvbaQX5nA/4lYO1LSSep42nDzgKNf69o0nWNigU1u Mlv5aCCM7Kc7Ge/brfgZpLZfe9I6B7mEbR3L3+r6auitjinUJHv+hpvR4cd0S+iuSJsn 2jFzMdhFktR7VPvwFY4xXNxPFJhGW6l4/rFEZsHzQGK6uQLym8QGOSjaDWf7bFi0eyY7 g3mtj3KbuwqIHJuHc+NlP2bQqTMXT0iDLEH81U0hKiJN8gv1Wq84ETyPxbcHWWT97wtt FwxATXAqAVP66SpEXH9ByC7pj5WPXts/sn75S5KvnXrpbxTgcx4BQIvVqSdh5a1D79av fzJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bRs+islm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i6si4354396wry.578.2021.09.30.08.34.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:34:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bRs+islm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVy4X-0006LH-IJ for patch@linaro.org; Thu, 30 Sep 2021 11:34:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjR-0000J2-KP for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:43930) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjP-00044X-Ai for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:21 -0400 Received: by mail-wr1-x432.google.com with SMTP id x20so10642236wrg.10 for ; Thu, 30 Sep 2021 08:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zPpRQrWSyjrRJfT0bIIpJXg1qS4RrwpRld2bjFRckaw=; b=bRs+islmHLkB3MMy7DkBIu15VNGnQJ08mxpv4Z8jjk1jkgnqZNvLCp6+kqZYM/4/Lj iOpxfAkm/lG0i0AijrVMTvXsqgXBc86uAMyp+2Yko+PEze2MTrozGGnSTHOoAqOypAxP 7KmoEoBnjcM86MJgw3d2u58xHUFCEzbbQyiaYu/rWarV4EySefOcGv6xz5/Fwc3JhTac 7XeIBsy1JCPmMQnq53Mr3ZPr8u3v2u2+DeiEXN2DiWUvOVEKX0MYtvZrAX8BHikxdbNp UWI+OI6bGh/7miv5SLn8zZ6LvbV5uJpCQBHUdLUOyAh4fRdFnKSn1iY6Ao6ZotidPJd6 tr8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zPpRQrWSyjrRJfT0bIIpJXg1qS4RrwpRld2bjFRckaw=; b=qzEOOg8YiOxJZb7prtCcyOiZ9Eme1cGD6zqjfHscvVEZ9EShbHVvNWp63wXgC2cPBd vtGiONrcx5J0NN0MCSh98rM7mHJViN9e7xlIKUl/7X/fffh8COzuJ4w3fPEGPbAjXRAR 2rkqfMnEF3k3OHiMQmrSpYWqRhjBpNMEIeOD0A63HY8eHcsCdTN8PNssu6WjmjssuWZz d7H2oLo2/3JngozrdYVwXzmDryabgpo5asdHyUtFZ80m46l6y+JuSjrBVieq9XgoXYrz RXs6pOPS/LRc32GoZcqE+xDMSXFcgSZLNjXDT7Udr58H5N5QY/YSVhnkXHHlCcq2HmQ2 1gCw== X-Gm-Message-State: AOAM532gijxRjZCV/9Iyub2nufb4WMwerVlNwcap1fuHADMtxkFQahT4 4fIPLLFUGuIE1QZAxRkWlMYCKt+WFou0Jw== X-Received: by 2002:a05:6000:188d:: with SMTP id a13mr6926982wri.103.1633014737391; Thu, 30 Sep 2021 08:12:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/22] ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() Date: Thu, 30 Sep 2021 16:11:56 +0100 Message-Id: <20210930151201.9407-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to line with a "_init for in-place init, _new for allocate-and-return" convention. Drop the 'name' argument, because the only caller does not pass in a name. If a future caller does need to specify the bus name, we should create an ipack_bus_init_named() function at that point. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Message-id: 20210923121153.23754-3-peter.maydell@linaro.org --- include/hw/ipack/ipack.h | 8 ++++---- hw/ipack/ipack.c | 10 +++++----- hw/ipack/tpci200.c | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/include/hw/ipack/ipack.h b/include/hw/ipack/ipack.h index 75014e74ae1..cbcdda509d3 100644 --- a/include/hw/ipack/ipack.h +++ b/include/hw/ipack/ipack.h @@ -73,9 +73,9 @@ extern const VMStateDescription vmstate_ipack_device; VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice) IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot); -void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size, - DeviceState *parent, - const char *name, uint8_t n_slots, - qemu_irq_handler handler); +void ipack_bus_init(IPackBus *bus, size_t bus_size, + DeviceState *parent, + uint8_t n_slots, + qemu_irq_handler handler); #endif diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c index f19ecaeb1cf..d28e7f6449e 100644 --- a/hw/ipack/ipack.c +++ b/hw/ipack/ipack.c @@ -30,12 +30,12 @@ IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot) return NULL; } -void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size, - DeviceState *parent, - const char *name, uint8_t n_slots, - qemu_irq_handler handler) +void ipack_bus_init(IPackBus *bus, size_t bus_size, + DeviceState *parent, + uint8_t n_slots, + qemu_irq_handler handler) { - qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, name); + qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL); bus->n_slots = n_slots; bus->set_irq = handler; } diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c index d107e134c4e..1f764fc85ba 100644 --- a/hw/ipack/tpci200.c +++ b/hw/ipack/tpci200.c @@ -611,8 +611,8 @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp) pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2); pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3); - ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL, - N_MODULES, tpci200_set_irq); + ipack_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), + N_MODULES, tpci200_set_irq); } static const VMStateDescription vmstate_tpci200 = { From patchwork Thu Sep 30 15:11:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514918 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp286539jam; Thu, 30 Sep 2021 08:37:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyUCEwVrF3jXOmaVbUoFCSwCPOIrLVb5k/2VidNVecuAWmiz8YKwynlALP8a+EQnn/gECbC X-Received: by 2002:a17:906:8281:: with SMTP id h1mr7191058ejx.352.1633016257690; Thu, 30 Sep 2021 08:37:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016257; cv=none; d=google.com; s=arc-20160816; b=EpKgd6mo5VP9f8kbcq43v/EQ8ff9nL0npFrEvPVnTXeJTpN04H5pRPouiD8893HIzg dVKmBTM7CFmA/7kHY8PdcIEadwKSxf1eSeUNPiZyNJLuWXH0d2aKT1BZWCr3uXcA/G4X ufaPG8GFZxaIIBY0eCqbFjNTlAcsCEKpiDyN2YNRHJIkIT+lKn7WLEDM0ZNvUMFoAKTk VaeA3Em8Zy3wSBZ6Zl1/rVRubZqgAU2hfyks5vnATgs8gPWLuBW7dYTy4KjR+ajo2J6V hqClCfF7Pm4s710yxvzxhtB6saoqhFGTUnebYKqFrOZu4cKXQ91TaqC1JiavA06MIDS0 u+Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zBrqIS4U/yt/jAHt0whMwGGRWmZzZZu7ttseo1tsd6I=; b=p1ZFrPAK9E+0GUfmLVHhCQGvIG9ldKiL0Ndej6n6atJdz01GImxn2E3TA9BQivVtfV 9P9ZAMCOKynsaAE/Nq7/6qUZ7AYE16u2/Yapptx+ymb1blfAhMGIipJ2owBcyuqA2f7i P0Crc3VgrIxXcM07GrXCUpQJkAyTWaXissccrnw3CPsMkPw1DlcJ5C+fYz7C07HFNAI/ /xpvwy7meE8Bwiqk8MMPd9qK5WeIt8q5qsjL5O3ZFcFNSQLPTWWhH9LRx3C9a4uaxJS5 +DoVIevSmEwQ8Wq3k6fP+BbHSAExiJNaV1UriIZZ+u0VF74n0R8+kKRcrkPecAeXtu5o WZow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xw3Awss3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 5si3595519ejm.381.2021.09.30.08.37.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:37:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xw3Awss3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVy7s-0004CF-Hz for patch@linaro.org; Thu, 30 Sep 2021 11:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjV-0000NA-Cj for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:26 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:56039) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjP-00044f-Ca for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:24 -0400 Received: by mail-wm1-x330.google.com with SMTP id v127so4936824wme.5 for ; Thu, 30 Sep 2021 08:12:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zBrqIS4U/yt/jAHt0whMwGGRWmZzZZu7ttseo1tsd6I=; b=xw3Awss35kvHr64MrazMEI7Hnh2dlBPiRQ1NE5uO1nLCTyyqWEGQE7zPulZe8pq9Nf Ibj1JMVDojVp+McXlxt4ecMcePt/jAMwJj2T8ZkUxVTHXe2qlU++a5DDaS5R5JpCCs2A ZH1TCXQJOy8I1TeJ+k76S+P411Rl+dgorzS3BnLZyak/ZzyfC3kATBqiCC56fyRV47IR Osb7ro+9Klu+cjZy7QB38mPHcXzmeEbHvHOBFevaBGyQJP+fSvLyjE+k+CW0V3oNnxGL L475UJSs8oGN5HRFzz1od7sx1ZB7vG0+Lh5VqADk3xlQp05L/Sxa6V+FUQbwVLOofFjb Es6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zBrqIS4U/yt/jAHt0whMwGGRWmZzZZu7ttseo1tsd6I=; b=TEkFY9GKrYAOEL+ALD0KdsDbJmcn4uvBJKmv0cYQGL0We845h+r8UgbGVflafc0TlM sIgzBGtcmM3n7Z3gIwcktV5j8siss6vwZ/NnCg8MAtX1izpXqRQLhseiZgwe8R+tYhoa SALo0wQlgVslrJ6sPTxlKz9kZd3MI2NWJthgLTzBHA3l6OR94hb0uQy/kNwpOQ2H4Zmz EX2+uY8n4Nzd5J0dtEYcWfrngp3xgOfVF8WJ6xdRqEGveLUecB/QXJOIa/vj3nNNEP+X MimnsHBP+FYEK97uHk9a84Us6Pc/iF5j/3ak2EfoKPblULsPxC0Njph/t8mJGryU/tMa +xFw== X-Gm-Message-State: AOAM53110Xg+quJ7s35UfOHaw8XslFEbByG88aMfHOiiSjY+Q1gdl1mg w4Bm+TFifyKjJNlA7c+hob0abYyPouaAkQ== X-Received: by 2002:a1c:e90a:: with SMTP id q10mr6078059wmc.108.1633014737974; Thu, 30 Sep 2021 08:12:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/22] pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() Date: Thu, 30 Sep 2021 16:11:57 +0100 Message-Id: <20210930151201.9407-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename the pci_root_bus_new_inplace() function to pci_root_bus_init(); this brings the bus type in to line with a "_init for in-place init, _new for allocate-and-return" convention. To do this we need to rename the implementation-internal function that was using the pci_root_bus_init() name to pci_root_bus_internal_init(). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Message-id: 20210923121153.23754-4-peter.maydell@linaro.org --- include/hw/pci/pci.h | 10 +++++----- hw/pci-host/raven.c | 4 ++-- hw/pci-host/versatile.c | 6 +++--- hw/pci/pci.c | 26 +++++++++++++------------- 4 files changed, 23 insertions(+), 23 deletions(-) -- 2.20.1 diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index d0f4266e372..7fc90132cf1 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -403,11 +403,11 @@ OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) bool pci_bus_is_express(PCIBus *bus); -void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, - const char *name, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - uint8_t devfn_min, const char *typename); +void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, + const char *name, + MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + uint8_t devfn_min, const char *typename); PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 3be27f0a14d..6e514f75eb8 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -300,8 +300,8 @@ static void raven_pcihost_initfn(Object *obj) memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR, &s->pci_io_non_contiguous, 1); memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); - pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, - &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); + pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, + &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); /* Bus master address space */ memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB); diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 3553277f941..f66384fa02d 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -405,9 +405,9 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp) memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB); memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB); - pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci", - &s->pci_mem_space, &s->pci_io_space, - PCI_DEVFN(11, 0), TYPE_PCI_BUS); + pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), dev, "pci", + &s->pci_mem_space, &s->pci_io_space, + PCI_DEVFN(11, 0), TYPE_PCI_BUS); h->bus = &s->pci_bus; object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 23d2ae2ab23..19881c84f23 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -432,10 +432,10 @@ bool pci_bus_bypass_iommu(PCIBus *bus) return host_bridge->bypass_iommu; } -static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - uint8_t devfn_min) +static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, + MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + uint8_t devfn_min) { assert(PCI_FUNC(devfn_min) == 0); bus->devfn_min = devfn_min; @@ -460,15 +460,15 @@ bool pci_bus_is_express(PCIBus *bus) return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); } -void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, - const char *name, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - uint8_t devfn_min, const char *typename) +void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, + const char *name, + MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + uint8_t devfn_min, const char *typename) { qbus_create_inplace(bus, bus_size, typename, parent, name); - pci_root_bus_init(bus, parent, address_space_mem, address_space_io, - devfn_min); + pci_root_bus_internal_init(bus, parent, address_space_mem, + address_space_io, devfn_min); } PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, @@ -479,8 +479,8 @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, PCIBus *bus; bus = PCI_BUS(qbus_create(typename, parent, name)); - pci_root_bus_init(bus, parent, address_space_mem, address_space_io, - devfn_min); + pci_root_bus_internal_init(bus, parent, address_space_mem, + address_space_io, devfn_min); return bus; } From patchwork Thu Sep 30 15:11:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514919 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp288044jam; Thu, 30 Sep 2021 08:39:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwuspontJr0q5sSJzT7V2iSK6VK9b9L1kAeWeC2AMFSZluQDrdg29tTrQgk99K5fUAaDot/ X-Received: by 2002:a1c:1b07:: with SMTP id b7mr6095169wmb.42.1633016359574; Thu, 30 Sep 2021 08:39:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016359; cv=none; d=google.com; s=arc-20160816; b=Q8lNps6yi7kza99B9KIAlLsmSE0mEnJ/ROJ1C37pgm3NhXdCRfLz0BN1EuwhR5GgqJ 3rN/CV+eo/jVLFjRZxqQmT0SdhSLV8UYeGY9BYBCzvmQwvG28lQzsXu0/cRMOaeFNvxX 8MusWrK3en442YIK05XrT9BZhAwg03TVyhi9MvZXPECE64UYLMNQF2GFyKLhbTlprirW jxG1gmzpXugkiaPNwoK2K2m4VrDkxWgC2FhLPSlJmJMiCvrqSfX6ZRzvli8PnHrll+kv bb7Aa4sWJLz8ZKHKWy2qCzFr8dC1L01uKeTFyK+sJxzfjGQAiu3FWAbJwC8rNKikamUT CY2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=prEV87x91iZDmCND6IZHC08ppGLS8d5D7g1utOkuyiQ=; b=zxLUYXZtHqc2CNmY/+GgSM1UTpuE7rVZ60Lhow8DKIsQ2Lun5SuirQ6RZnR8y0K0as XyaAqQ/joTtkAh8c1Mk5q6OBHCRJ6tDPZAEGqgV0xII9VYspDaTfnvGLYECRVxjrB4xj 0hUq81ItKkZPxacMVvpMDQYpw5XkXO4Yyk892hzeh7BU+KdLjhg7fod26npdQn2E4H70 TnirPgJXEl/lYPmXSIn/sD379YEA6cmcV3VIJ8kjt2pRZiTRl0SJw5lW8RRqQHthbFNS NvM00JCn/A5LeEamoxAG1AzSbmG0g7ejg0xT2uUOQ0wZKGXd48ss61IvK32GQQNlebgu BfVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMWY70aN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r2si3338197wro.557.2021.09.30.08.39.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:39:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMWY70aN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVy9W-0007lH-GB for patch@linaro.org; Thu, 30 Sep 2021 11:39:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjV-0000NB-BG for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:26 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:45662) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjQ-00045t-IB for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:23 -0400 Received: by mail-wm1-x329.google.com with SMTP id b192-20020a1c1bc9000000b0030cfaf18864so4601222wmb.4 for ; Thu, 30 Sep 2021 08:12:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=prEV87x91iZDmCND6IZHC08ppGLS8d5D7g1utOkuyiQ=; b=EMWY70aNkal4Y2LqYw2RDQcrHqfSHXB9icWcIx2QMseJmwUfIdvEpwY2G8mbqxiozh IEcViRZjbDImdrdC5pKDwU+6kQNqTv0vzBEUvtcRDOnWF3omKN1Fbr+FOKAWMyy0UYFk haO/z1b3UPZVTyJQS73wVr96wXszPO2LuQk5Ff5xCdXuVNukDMdD3FgGhfn4VmbP5cJy JAVO+bIqP7tCw3f+FmTvIX/KOaerXV3Cz1Cjc8NqTvqoBPpvd7zL7gzvgZuXP7aNLBA5 ViqcdbGXmpzQAduml0zQSsiyXzwAhUdrcEhoOYKO9Zhazru2IVh4FlvEf27HEBQaERXr GgJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=prEV87x91iZDmCND6IZHC08ppGLS8d5D7g1utOkuyiQ=; b=bQkYhKDI7MGHUeMNsnwr+r1pubzla2BSlQBK/Pmyezbaz/9YcNwTT77qCYvGsMTVls LEdLhJx29z1q0uN4hXWSUBgXA62YjRKPjLqzI8oGovEYcTM42We5RMVvSUzfcSMTRG9U 2hvep3Zz6sCJZX1sqRoj/KBAaouDUdJAwdf1UbAAaZzzFOUV8H40CrJvfRM2NvKCpVg6 QAsl4Yb5RwbJR1scVMRBxM3HbRk4/a8nj8vABUuBoknehuPkcBaWmki1i+WejPh+t1u/ 8AQTIz0d/tuBKTovYcp7qntr71bMpWESG0O9blvIuxTxKC2zr9NlIifco7ncj4CfFzqI BkRQ== X-Gm-Message-State: AOAM531xe1smmUQpyUxuJJgz7CECiZM2D+lgDoDHNizehE3EY9Y7dZQZ o9vcQceUK2i9jFVMpwH2FnrbL+O5Zo1Y4A== X-Received: by 2002:a1c:7c0e:: with SMTP id x14mr5806398wmc.6.1633014738828; Thu, 30 Sep 2021 08:12:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/22] qbus: Rename qbus_create_inplace() to qbus_init() Date: Thu, 30 Sep 2021 16:11:58 +0100 Message-Id: <20210930151201.9407-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename qbus_create_inplace() to qbus_init(); this is more in line with our usual naming convention for functions that in-place initialize objects. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Message-id: 20210923121153.23754-5-peter.maydell@linaro.org --- include/hw/qdev-core.h | 4 ++-- hw/audio/intel-hda.c | 2 +- hw/block/fdc.c | 2 +- hw/block/swim.c | 3 +-- hw/char/virtio-serial-bus.c | 4 ++-- hw/core/bus.c | 11 ++++++----- hw/core/sysbus.c | 10 ++++++---- hw/gpio/bcm2835_gpio.c | 3 +-- hw/ide/qdev.c | 2 +- hw/ipack/ipack.c | 2 +- hw/misc/mac_via.c | 4 ++-- hw/misc/macio/cuda.c | 4 ++-- hw/misc/macio/macio.c | 4 ++-- hw/misc/macio/pmu.c | 4 ++-- hw/nubus/nubus-bridge.c | 2 +- hw/nvme/ctrl.c | 4 ++-- hw/nvme/subsys.c | 3 +-- hw/pci/pci.c | 2 +- hw/pci/pci_bridge.c | 4 ++-- hw/s390x/event-facility.c | 4 ++-- hw/s390x/virtio-ccw.c | 3 +-- hw/scsi/scsi-bus.c | 2 +- hw/sd/allwinner-sdhost.c | 4 ++-- hw/sd/bcm2835_sdhost.c | 4 ++-- hw/sd/pl181.c | 3 +-- hw/sd/pxa2xx_mmci.c | 4 ++-- hw/sd/sdhci.c | 3 +-- hw/sd/ssi-sd.c | 3 +-- hw/usb/bus.c | 2 +- hw/usb/dev-smartcard-reader.c | 3 +-- hw/virtio/virtio-mmio.c | 3 +-- hw/virtio/virtio-pci.c | 3 +-- 32 files changed, 54 insertions(+), 61 deletions(-) -- 2.20.1 diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 34c8a7506a1..ebca8cf9fca 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -678,8 +678,8 @@ DeviceState *qdev_find_recursive(BusState *bus, const char *id); typedef int (qbus_walkerfn)(BusState *bus, void *opaque); typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque); -void qbus_create_inplace(void *bus, size_t size, const char *typename, - DeviceState *parent, const char *name); +void qbus_init(void *bus, size_t size, const char *typename, + DeviceState *parent, const char *name); BusState *qbus_create(const char *typename, DeviceState *parent, const char *name); bool qbus_realize(BusState *bus, Error **errp); void qbus_unrealize(BusState *bus); diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index 4330213fff1..8ce9df64e3e 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -52,7 +52,7 @@ void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, hda_codec_response_func response, hda_codec_xfer_func xfer) { - qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); + qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL); bus->response = response; bus->xfer = xfer; } diff --git a/hw/block/fdc.c b/hw/block/fdc.c index 9014cd30b3a..fa933cd3263 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -77,7 +77,7 @@ static const TypeInfo floppy_bus_info = { static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev) { - qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); + qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); bus->fdc = fdc; } diff --git a/hw/block/swim.c b/hw/block/swim.c index 509c2f49003..333da08ce09 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -421,8 +421,7 @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp) Swim *sys = SWIM(dev); SWIMCtrl *swimctrl = &sys->ctrl; - qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, - NULL); + qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL); swimctrl->bus.ctrl = swimctrl; } diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index dd6bc27b3b5..f01ec2137c9 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -1048,8 +1048,8 @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp) config_size); /* Spawn a new virtio-serial bus on which the ports will ride as devices */ - qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS, - dev, vdev->bus_name); + qbus_init(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS, + dev, vdev->bus_name); qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser)); vser->bus.vser = vser; QTAILQ_INIT(&vser->ports); diff --git a/hw/core/bus.c b/hw/core/bus.c index 9cfbc3a6877..cec49985024 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -99,7 +99,8 @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb, } } -static void qbus_init(BusState *bus, DeviceState *parent, const char *name) +static void qbus_init_internal(BusState *bus, DeviceState *parent, + const char *name) { const char *typename = object_get_typename(OBJECT(bus)); BusClass *bc; @@ -151,11 +152,11 @@ static void bus_unparent(Object *obj) bus->parent = NULL; } -void qbus_create_inplace(void *bus, size_t size, const char *typename, - DeviceState *parent, const char *name) +void qbus_init(void *bus, size_t size, const char *typename, + DeviceState *parent, const char *name) { object_initialize(bus, size, typename); - qbus_init(bus, parent, name); + qbus_init_internal(bus, parent, name); } BusState *qbus_create(const char *typename, DeviceState *parent, const char *name) @@ -163,7 +164,7 @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam BusState *bus; bus = BUS(object_new(typename)); - qbus_init(bus, parent, name); + qbus_init_internal(bus, parent, name); return bus; } diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index aaae8e23cc4..05c1da3d311 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -340,11 +340,13 @@ static BusState *main_system_bus; static void main_system_bus_create(void) { - /* assign main_system_bus before qbus_create_inplace() - * in order to make "if (bus != sysbus_get_default())" work */ + /* + * assign main_system_bus before qbus_init() + * in order to make "if (bus != sysbus_get_default())" work + */ main_system_bus = g_malloc0(system_bus_info.instance_size); - qbus_create_inplace(main_system_bus, system_bus_info.instance_size, - TYPE_SYSTEM_BUS, NULL, "main-system-bus"); + qbus_init(main_system_bus, system_bus_info.instance_size, + TYPE_SYSTEM_BUS, NULL, "main-system-bus"); OBJECT(main_system_bus)->free = g_free; } diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c index abdddbc67c2..c995bba1d9f 100644 --- a/hw/gpio/bcm2835_gpio.c +++ b/hw/gpio/bcm2835_gpio.c @@ -299,8 +299,7 @@ static void bcm2835_gpio_init(Object *obj) DeviceState *dev = DEVICE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_SD_BUS, DEVICE(s), "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(s), "sd-bus"); memory_region_init_io(&s->iomem, obj, &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000); diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c index e70ebc83a07..ca844419106 100644 --- a/hw/ide/qdev.c +++ b/hw/ide/qdev.c @@ -71,7 +71,7 @@ static const TypeInfo ide_bus_info = { void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev, int bus_id, int max_units) { - qbus_create_inplace(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL); + qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL); idebus->bus_id = bus_id; idebus->max_units = max_units; } diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c index d28e7f6449e..ae20f36da68 100644 --- a/hw/ipack/ipack.c +++ b/hw/ipack/ipack.c @@ -35,7 +35,7 @@ void ipack_bus_init(IPackBus *bus, size_t bus_size, uint8_t n_slots, qemu_irq_handler handler) { - qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL); + qbus_init(bus, bus_size, TYPE_IPACK_BUS, parent, NULL); bus->n_slots = n_slots; bus->set_irq = handler; } diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index d1abcd97b51..993bac017db 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -1038,8 +1038,8 @@ static void mos6522_q800_via1_init(Object *obj) sysbus_init_mmio(sbd, &v1s->via_mem); /* ADB */ - qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), - TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); + qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), + TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB); } diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index edbd4186b2a..e917a6a095b 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -553,8 +553,8 @@ static void cuda_init(Object *obj) memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000); sysbus_init_mmio(sbd, &s->mem); - qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, - DEVICE(obj), "adb.0"); + qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, + DEVICE(obj), "adb.0"); } static Property cuda_properties[] = { diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 4515296e66a..c1fad43f6c6 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -387,8 +387,8 @@ static void macio_instance_init(Object *obj) memory_region_init(&s->bar, obj, "macio", 0x80000); - qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS, - DEVICE(obj), "macio.0"); + qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS, + DEVICE(obj), "macio.0"); object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA); diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 71924d4768c..4ad4f50e08c 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -754,8 +754,8 @@ static void pmu_realize(DeviceState *dev, Error **errp) timer_mod(s->one_sec_timer, s->one_sec_target); if (s->has_adb) { - qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, - dev, "adb.0"); + qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, + dev, "adb.0"); adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s); } } diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c index c517a8a7047..a42c86080f2 100644 --- a/hw/nubus/nubus-bridge.c +++ b/hw/nubus/nubus-bridge.c @@ -18,7 +18,7 @@ static void nubus_bridge_init(Object *obj) NubusBridge *s = NUBUS_BRIDGE(obj); NubusBus *bus = &s->bus; - qbus_create_inplace(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL); + qbus_init(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL); qdev_init_gpio_out(DEVICE(s), bus->irqs, NUBUS_IRQS); } diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 2f247a9275c..6a571d18cfa 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -6539,8 +6539,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) return; } - qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, - &pci_dev->qdev, n->parent_obj.qdev.id); + qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, + &pci_dev->qdev, n->parent_obj.qdev.id); nvme_init_state(n); if (nvme_init_pci(n, pci_dev, errp)) { diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c index 93c35950d69..495dcff5ebb 100644 --- a/hw/nvme/subsys.c +++ b/hw/nvme/subsys.c @@ -50,8 +50,7 @@ static void nvme_subsys_realize(DeviceState *dev, Error **errp) { NvmeSubsystem *subsys = NVME_SUBSYS(dev); - qbus_create_inplace(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, - dev->id); + qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id); nvme_subsys_setup(subsys); } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 19881c84f23..14cb15a0aa1 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -466,7 +466,7 @@ void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, MemoryRegion *address_space_io, uint8_t devfn_min, const char *typename) { - qbus_create_inplace(bus, bus_size, typename, parent, name); + qbus_init(bus, bus_size, typename, parent, name); pci_root_bus_internal_init(bus, parent, address_space_mem, address_space_io, devfn_min); } diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 3789c17edc2..d1f902ee862 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -374,8 +374,8 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename) br->bus_name = dev->qdev.id; } - qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), - br->bus_name); + qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), + br->bus_name); sec_bus->parent_dev = dev; sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn; sec_bus->address_space_mem = &br->address_space_mem; diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c index ed92ce510d9..6fa47b889ca 100644 --- a/hw/s390x/event-facility.c +++ b/hw/s390x/event-facility.c @@ -427,8 +427,8 @@ static void init_event_facility(Object *obj) sclp_event_set_allow_all_mask_sizes); /* Spawn a new bus for SCLP events */ - qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus), - TYPE_SCLP_EVENTS_BUS, sdev, NULL); + qbus_init(&event_facility->sbus, sizeof(event_facility->sbus), + TYPE_SCLP_EVENTS_BUS, sdev, NULL); object_initialize_child(obj, TYPE_SCLP_QUIESCE, &event_facility->quiesce, diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 6a2df1c1e9a..c845a92c3a8 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -1261,8 +1261,7 @@ static void virtio_ccw_bus_new(VirtioBusState *bus, size_t bus_size, DeviceState *qdev = DEVICE(dev); char virtio_bus_name[] = "virtio-bus"; - qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_CCW_BUS, - qdev, virtio_bus_name); + qbus_init(bus, bus_size, TYPE_VIRTIO_CCW_BUS, qdev, virtio_bus_name); } static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data) diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index e28a6ea053a..77325d8cc7a 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -137,7 +137,7 @@ void scsi_device_unit_attention_reported(SCSIDevice *s) void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, const SCSIBusInfo *info, const char *bus_name) { - qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name); + qbus_init(bus, bus_size, TYPE_SCSI_BUS, host, bus_name); bus->busnr = next_scsi_bus++; bus->info = info; qbus_set_bus_hotplug_handler(BUS(bus)); diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index bea6d97ef87..9166d6638de 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -738,8 +738,8 @@ static void allwinner_sdhost_init(Object *obj) { AwSdHostState *s = AW_SDHOST(obj); - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), + TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s, TYPE_AW_SDHOST, 4 * KiB); diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c index 50f5fdb88bc..088a7ac6ed4 100644 --- a/hw/sd/bcm2835_sdhost.c +++ b/hw/sd/bcm2835_sdhost.c @@ -403,8 +403,8 @@ static void bcm2835_sdhost_init(Object *obj) { BCM2835SDHostState *s = BCM2835_SDHOST(obj); - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), + TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus"); memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s, TYPE_BCM2835_SDHOST, 0x1000); diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c index 960f1550981..5e554bd4676 100644 --- a/hw/sd/pl181.c +++ b/hw/sd/pl181.c @@ -506,8 +506,7 @@ static void pl181_init(Object *obj) qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1); qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1); - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_PL181_BUS, dev, "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_PL181_BUS, dev, "sd-bus"); } static void pl181_class_init(ObjectClass *klass, void *data) diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index 3dd2fc7a83f..124fbf8bbd4 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -560,8 +560,8 @@ static void pxa2xx_mmci_instance_init(Object *obj) qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1); qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1); - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), + TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus"); } static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 5b8678110b0..c9dc065cc52 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1337,8 +1337,7 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) void sdhci_initfn(SDHCIState *s) { - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), - TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 97ee58e20cf..e60854eeefc 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -373,8 +373,7 @@ static void ssi_sd_realize(SSIPeripheral *d, Error **errp) DeviceState *carddev; DriveInfo *dinfo; - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, - DEVICE(d), "sd-bus"); + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus"); /* Create and plug in the sd card */ /* FIXME use a qdev drive property instead of drive_get_next() */ diff --git a/hw/usb/bus.c b/hw/usb/bus.c index 07083349f51..5d441a70650 100644 --- a/hw/usb/bus.c +++ b/hw/usb/bus.c @@ -82,7 +82,7 @@ const VMStateDescription vmstate_usb_device = { void usb_bus_new(USBBus *bus, size_t bus_size, USBBusOps *ops, DeviceState *host) { - qbus_create_inplace(bus, bus_size, TYPE_USB_BUS, host, NULL); + qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL); qbus_set_bus_hotplug_handler(BUS(bus)); bus->ops = ops; bus->busnr = next_usb_bus++; diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c index f7043075be5..91ffd9f8ae8 100644 --- a/hw/usb/dev-smartcard-reader.c +++ b/hw/usb/dev-smartcard-reader.c @@ -1320,8 +1320,7 @@ static void ccid_realize(USBDevice *dev, Error **errp) usb_desc_create_serial(dev); usb_desc_init(dev); - qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), - NULL); + qbus_init(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), NULL); qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev)); s->intr = usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP); s->bulk = usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP); diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 1af48a1b044..7b3ebca1781 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -733,8 +733,7 @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp) VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d); SysBusDevice *sbd = SYS_BUS_DEVICE(d); - qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, - d, NULL); + qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL); sysbus_init_irq(sbd, &proxy->irq); if (!kvm_eventfds_enabled()) { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 6e16e2705ce..750aa47ec14 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2187,8 +2187,7 @@ static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size, DeviceState *qdev = DEVICE(dev); char virtio_bus_name[] = "virtio-bus"; - qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, - virtio_bus_name); + qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name); } static void virtio_pci_bus_class_init(ObjectClass *klass, void *data) From patchwork Thu Sep 30 15:11:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514921 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp291071jam; Thu, 30 Sep 2021 08:42:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXy4tUQ9OnsPshhZjwIzvIFRmalUKwXawLxctVQaWfvPfmwPQL7+7bZUUvXRDlYVSdbGZU X-Received: by 2002:a05:6102:2db:: with SMTP id h27mr4569860vsh.60.1633016579658; Thu, 30 Sep 2021 08:42:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016579; cv=none; d=google.com; s=arc-20160816; b=p0WGgOSvjKOQ3Yzs/bn6mN8eBcSN9yJtkcoO0yl+9b5s+6e0XpkC1omSC+s3XJfkUj +2bx5gK1997ucKZEgHCnl5oqW0GTNF6jp/PHzG4ttBqOE0TYBle/qpVuGC68Vyl9Xi0V 3KuNkrcZ9oTrZDRQ+XOOJUUVxV1nVwEa6493WO9Yqb+3EoKMcq4QRvbxK84KflpUDFu2 5JNCTqN6YOLOEDPEu6c4ogFivU8Vy6UoOJWk1HlrM30lVtEBe3CDbgd2TqjMsbH8aq6v oJ5vnpQGAzDZ/RggEuiH3KL8AnQ5mZKNFa6UswP9ZELhJXgEHzyPgxwJUP9aXWKczjhP E68A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=55hOMrop2FTkEEIXtaj0g/HwY66d/fQrrEiGqMXLaFA=; b=OzHO32cQVbliF/lULWGtj7MftE3yKCfb4Y2nGYzOyuRRPF9MH/UiDC+HNmgaPpXSfK VJj67jjPQICErcsE2kGUZn7DG6XzdaK7VzeFMVMZdtP9szily6UNouE7lQRz9IhH1aQ0 f5E4uFMgJnq9f3uq2f7BVc5fX2Ev3EQ8cOUq+ryIQzoBgJGTour1Tv/23aVJXJJF9sMK LWZsn8SmgGXLFKnnjGGVF+JH/iPqHbUNo982389Dg0q2OSFzaQDwJbRgUJCZSJ34Buxn xNkh3vGOR81kEHWqw/oGONgPEolX4XMtlrXWvGCMLybvaVhA8EjoNO5JruSwi3P6Mw4R UlfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F/DN9r1t"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h15si2954976vkn.3.2021.09.30.08.42.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:42:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F/DN9r1t"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVyD4-0005Qz-UU for patch@linaro.org; Thu, 30 Sep 2021 11:42:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjV-0000N8-Ax for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:26 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46012) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjR-00046c-8m for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:23 -0400 Received: by mail-wr1-x42a.google.com with SMTP id d21so10620065wra.12 for ; Thu, 30 Sep 2021 08:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=55hOMrop2FTkEEIXtaj0g/HwY66d/fQrrEiGqMXLaFA=; b=F/DN9r1trB2AFmBjTpgeTjhauyULh+TpypaF5dPPDzY+hOg5m6HrKfr2sK3lWT2Smz qw1NNpJGkqCWMzbuTR66woEumSZ1cAeFvHJDnogmFE7I7a5mOKVTmVvzz7Ca8CMEEsnB 7YZedc9Pe97U4SgWM6hEV+4zzg+wcgp2Xj6kN/ujsNXajwjZaBoywQ9KL7BFnH6NBCeI S4K7qeU7Vj1focC5eEg9v5o2XNCBdWfnLmaKx02LlCLXIaUX0MrnWRgenTGTJw4QGKDv 6JEmm+ADi4irssdMdA0Tt3jimqi9T6/gNG2kzMK/BtnwF8BTYtkwLk11MUlghhyG9/Uv /5Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=55hOMrop2FTkEEIXtaj0g/HwY66d/fQrrEiGqMXLaFA=; b=jqlzObL6f62dM+8ki5swg33OYPrFZJ8BbLgacF7m4i9/6V7qZdWopQUCo/luuEqs6Y 5EDCwX4xAlghMhfcv9u4uGIl9vm6BchH9/PC8LPNPNxuZj6qV+SRwP1CjvJ9lzVR6DeM +9Iyl33us3+xnP1RYMjVox/XLaL2/UQ5hXwYpmhIldoN4HodoC0kK1B7SVbvDhKfNQRn XVZ/F2PGZuKa9fPrDAzt3scO0NmgJcbupEDlYl1xebjoZKNNt4Ar+C+VlbwA2tAbL8cp pxk4qvlB1BcAX7OFKDor+q1h4RGvGPipqDBWVMgcDc3woMUsCxdSq2jgqeE4j7hOoJ25 PNZg== X-Gm-Message-State: AOAM531BZlrSCNymXIFEbqPwfc5ySR1i3vsx3zjVlkHQdmhWmZvQ1nDX QIZ21JnidJ57eVSqgrxA/wFERGXtMb06Mw== X-Received: by 2002:adf:fe89:: with SMTP id l9mr6869581wrr.0.1633014739473; Thu, 30 Sep 2021 08:12:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/22] qbus: Rename qbus_create() to qbus_new() Date: Thu, 30 Sep 2021 16:11:59 +0100 Message-Id: <20210930151201.9407-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename the "allocate and return" qbus creation function to qbus_new(), to bring it into line with our _init vs _new convention. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Corey Minyard Message-id: 20210923121153.23754-6-peter.maydell@linaro.org --- include/hw/qdev-core.h | 2 +- hw/core/bus.c | 2 +- hw/hyperv/vmbus.c | 2 +- hw/i2c/core.c | 2 +- hw/isa/isa-bus.c | 2 +- hw/misc/auxbus.c | 2 +- hw/pci/pci.c | 2 +- hw/ppc/spapr_vio.c | 2 +- hw/s390x/ap-bridge.c | 2 +- hw/s390x/css-bridge.c | 2 +- hw/s390x/s390-pci-bus.c | 2 +- hw/ssi/ssi.c | 2 +- hw/xen/xen-bus.c | 2 +- hw/xen/xen-legacy-backend.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index ebca8cf9fca..4ff19c714bd 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -680,7 +680,7 @@ typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque); void qbus_init(void *bus, size_t size, const char *typename, DeviceState *parent, const char *name); -BusState *qbus_create(const char *typename, DeviceState *parent, const char *name); +BusState *qbus_new(const char *typename, DeviceState *parent, const char *name); bool qbus_realize(BusState *bus, Error **errp); void qbus_unrealize(BusState *bus); diff --git a/hw/core/bus.c b/hw/core/bus.c index cec49985024..c7831b5293b 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -159,7 +159,7 @@ void qbus_init(void *bus, size_t size, const char *typename, qbus_init_internal(bus, parent, name); } -BusState *qbus_create(const char *typename, DeviceState *parent, const char *name) +BusState *qbus_new(const char *typename, DeviceState *parent, const char *name) { BusState *bus; diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c index c9887d5a7bc..dbce3b35fba 100644 --- a/hw/hyperv/vmbus.c +++ b/hw/hyperv/vmbus.c @@ -2729,7 +2729,7 @@ static void vmbus_bridge_realize(DeviceState *dev, Error **errp) return; } - bridge->bus = VMBUS(qbus_create(TYPE_VMBUS, dev, "vmbus")); + bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus")); } static char *vmbus_bridge_ofw_unit_address(const SysBusDevice *dev) diff --git a/hw/i2c/core.c b/hw/i2c/core.c index 416372ad00c..0e7d2763b9e 100644 --- a/hw/i2c/core.c +++ b/hw/i2c/core.c @@ -60,7 +60,7 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name) { I2CBus *bus; - bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name)); + bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name)); QLIST_INIT(&bus->current_devs); vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus); return bus; diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c index cffaa35e9cf..6c31398dda6 100644 --- a/hw/isa/isa-bus.c +++ b/hw/isa/isa-bus.c @@ -64,7 +64,7 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); } - isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL)); + isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL)); isabus->address_space = address_space; isabus->address_space_io = address_space_io; return isabus; diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c index 434ff8d910d..8a8012f5f08 100644 --- a/hw/misc/auxbus.c +++ b/hw/misc/auxbus.c @@ -65,7 +65,7 @@ AUXBus *aux_bus_init(DeviceState *parent, const char *name) AUXBus *bus; Object *auxtoi2c; - bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name)); + bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name)); auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c", &error_abort, NULL); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 14cb15a0aa1..186758ee11f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -478,7 +478,7 @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, { PCIBus *bus; - bus = PCI_BUS(qbus_create(typename, parent, name)); + bus = PCI_BUS(qbus_new(typename, parent, name)); pci_root_bus_internal_init(bus, parent, address_space_mem, address_space_io, devfn_min); return bus; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index b59452bcd62..b975ed29cad 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -577,7 +577,7 @@ SpaprVioBus *spapr_vio_bus_init(void) sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* Create bus on bridge device */ - qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); + qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); bus = SPAPR_VIO_BUS(qbus); bus->next_reg = SPAPR_VIO_REG_BASE; diff --git a/hw/s390x/ap-bridge.c b/hw/s390x/ap-bridge.c index 8bcf8ece9dd..ef8fa2b15be 100644 --- a/hw/s390x/ap-bridge.c +++ b/hw/s390x/ap-bridge.c @@ -55,7 +55,7 @@ void s390_init_ap(void) sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* Create bus on bridge device */ - bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS); + bus = qbus_new(TYPE_AP_BUS, dev, TYPE_AP_BUS); /* Enable hotplugging */ qbus_set_hotplug_handler(bus, OBJECT(dev)); diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index 191b29f0771..4017081d49c 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -106,7 +106,7 @@ VirtualCssBus *virtual_css_bus_init(void) sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* Create bus on bridge device */ - bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css"); + bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css"); cbus = VIRTUAL_CSS_BUS(bus); /* Enable hotplugging */ diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 6c0225c3a01..6fafffb029a 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -813,7 +813,7 @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp) qbus_set_hotplug_handler(bus, OBJECT(dev)); phb->bus = b; - s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL)); + s->bus = S390_PCI_BUS(qbus_new(TYPE_S390_PCI_BUS, dev, NULL)); qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev)); s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal, diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index e5d7ce95237..003931fb509 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -107,7 +107,7 @@ DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name) SSIBus *ssi_create_bus(DeviceState *parent, const char *name) { BusState *bus; - bus = qbus_create(TYPE_SSI_BUS, parent, name); + bus = qbus_new(TYPE_SSI_BUS, parent, name); return SSI_BUS(bus); } diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c index 8c588920d9f..416583f130b 100644 --- a/hw/xen/xen-bus.c +++ b/hw/xen/xen-bus.c @@ -1398,7 +1398,7 @@ type_init(xen_register_types) void xen_bus_init(void) { DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE); - BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL); + BusState *bus = qbus_new(TYPE_XEN_BUS, dev, NULL); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); qbus_set_bus_hotplug_handler(bus); diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c index dd8ae1452d1..be3cf4a195e 100644 --- a/hw/xen/xen-legacy-backend.c +++ b/hw/xen/xen-legacy-backend.c @@ -702,7 +702,7 @@ int xen_be_init(void) xen_sysdev = qdev_new(TYPE_XENSYSDEV); sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal); - xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus"); + xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus"); qbus_set_bus_hotplug_handler(xen_sysbus); return 0; From patchwork Thu Sep 30 15:12:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514905 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp269259jam; Thu, 30 Sep 2021 08:19:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPIxkP0iSL0KFhr0SaLBCsQLjhKWMsyb6u2Ry4rjRrmuIS0Lya/tpo8iLef26EK12V7Pup X-Received: by 2002:a50:e1cd:: with SMTP id m13mr7770830edl.93.1633015174588; Thu, 30 Sep 2021 08:19:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633015174; cv=none; d=google.com; s=arc-20160816; b=gA46XqBF1QawVeFovvYvoTYJl+VqL75In9YM7NrfMu4ri1LpHx5zMMdIS0o2Rq8EKz JHAQBgOypzeH/IELOQdnZ9MfYY4xN+QVQlu5LhFbb85G567KDl3nk2wcK8cJvJ9W9E/p vorqaD6fZ21gszr6Ofcyn6b9qQciMe0l/wPthjiLiiZu/BVrPbcWW+hvNcwpMm9vlgtn sdFiKM/hEUoWsac0ixLg4XdVG3dO8KiArUfAOMUjsHoRW8atsTgf0L6wGWflYIFd8VxR L2K71h6V0c+ROARdlJ4D1Fjs7uYP9cfUK+P0o3Q5/gxuly9ckz6mnJR6Qqk9U6Y7kgSV pW1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hUV8cdtZODcPaV6FC7zTXHhba91EQCF96FYNJ54a0C8=; b=gq4DpQqNYpuSahdAaTunRfLe7YKXRM5TzbeWK3VTnnwgLOLMBXba9U6LZg1bE1Z/AQ IV1tLNR5Hjyey1hidycbSPz+/N6rSYAECVpr/lA4GeCXCMLL0l2AmalbySMES4F5XOHE 0lZQ3Ax5ckN/SrNsgjXznmiKjCGhSpfNEG7xOzdMstLazW9Pzj8s+TbMwQ5ju6A41w73 +97pj2L0T9Cya1xQW0TmrpLthngNRoqRaKLwR1H78kMNk3gmCkusw8/Oi8gmlgMmF5eD nL9ztgQnmJRtnyFRkAf4CA4Hzt9fw1ucDZJshR7JlR3gHFio2hFuw2+iOUcU7WjSMhZL CEEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vo2n6LgP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d4si4746600edm.247.2021.09.30.08.19.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:19:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vo2n6LgP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVxqO-0001KS-Ep for patch@linaro.org; Thu, 30 Sep 2021 11:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjX-0000Oy-CC for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:29 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:34660) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjT-00046z-76 for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:26 -0400 Received: by mail-wr1-x42b.google.com with SMTP id t8so10713325wri.1 for ; Thu, 30 Sep 2021 08:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hUV8cdtZODcPaV6FC7zTXHhba91EQCF96FYNJ54a0C8=; b=vo2n6LgPy5gfdYM5oZDTBB1f4Bsir4idyO2oLImuBVNlc25QtKQUfwwwK0OuOFQk8m ylMC/D+hHMnBMQ+XFN2iUCW/4l8Pj35PNYEy5tpYgZ/rI9fwj8asyOwEGZWtlDEI7nuU 4R+gyjPhaEy8ySWgWLRnLoBXgMRGeGb/Gh262nDNcSwPAxRPr0qDhIVZrGMWA77Dtvm+ 9ojgYtSzVD863kV/ug5k1BZWmoJ296KLGMBSwwwSGz+wsQ0/MmHkQVJYreS3nN3oUn2J aLSevC7IRGV+4lFZMiA/5T5OXYG6C59b9cKnY0wPO7ldGq/BJMTKvhU5oyPive9V5sOH x5Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hUV8cdtZODcPaV6FC7zTXHhba91EQCF96FYNJ54a0C8=; b=O/ggP1w7OVfzC8bm2kNkP8XmDAdwAXWdkajvLOXUKFOuD9voe3uxaxNfpMrxilR/41 BinnNBXOo//OtmUipbjqcop/yGWEyG1EbH/4plTcPEeHgsycjfkc8DQagl8K3UUSgyb4 Zj3k7Li9+mc5EF6r8A7fLIYjIlpIlFVD+zOyHoFwDJUnLoBqJlaIXjgxn8c1i4V2GqkY xzbkoTfZM6hdMhLNPF/rVLJK4R49UYAB1NNVZPGToSNMH7Qen8F1wZqq4N8vrBT7eEQ0 vHINygQWAvNv3NQbC7g4PD7esxMgaPzxbn2XbBWqkKEeLWdG/EZp/EzOmJEOVBtBqvLz /1nQ== X-Gm-Message-State: AOAM532jI7uj69EeDsMwykyBKSjVPQVJi9q58W1F9NsWWtmnpQz6PrNM ikuUc6Wzr0hZzO6akaWhiYhDW6FuVJVFag== X-Received: by 2002:a5d:47a4:: with SMTP id 4mr6997613wrb.374.1633014740407; Thu, 30 Sep 2021 08:12:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/22] ide: Rename ide_bus_new() to ide_bus_init() Date: Thu, 30 Sep 2021 16:12:00 +0100 Message-Id: <20210930151201.9407-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function ide_bus_new() does an in-place initialization. Rename it to ide_bus_init() to follow our _init vs _new convention. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Corey Minyard Reviewed-by: John Snow Acked-by: John Snow (Feel free to merge.) Message-id: 20210923121153.23754-7-peter.maydell@linaro.org --- include/hw/ide/internal.h | 4 ++-- hw/ide/ahci.c | 2 +- hw/ide/cmd646.c | 2 +- hw/ide/isa.c | 2 +- hw/ide/macio.c | 2 +- hw/ide/microdrive.c | 2 +- hw/ide/mmio.c | 2 +- hw/ide/piix.c | 2 +- hw/ide/qdev.c | 2 +- hw/ide/sii3112.c | 2 +- hw/ide/via.c | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 79172217ccb..97e7e59dc58 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -648,8 +648,8 @@ void ide_atapi_cmd(IDEState *s); void ide_atapi_cmd_reply_end(IDEState *s); /* hw/ide/qdev.c */ -void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev, - int bus_id, int max_units); +void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev, + int bus_id, int max_units); IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive); int ide_handle_rw_error(IDEState *s, int error, int op); diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index f2c51574839..a94c6e26fb0 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1548,7 +1548,7 @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) for (i = 0; i < s->ports; i++) { AHCIDevice *ad = &s->dev[i]; - ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); + ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); ide_init2(&ad->port, irqs[i]); ad->hba = s; diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index c2546314855..94c576262c1 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -293,7 +293,7 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) qdev_init_gpio_in(ds, cmd646_set_irq, 2); for (i = 0; i < 2; i++) { - ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i)); bmdma_init(&d->bus[i], &d->bmdma[i], d); diff --git a/hw/ide/isa.c b/hw/ide/isa.c index 6bc19de2265..24bbde24c2b 100644 --- a/hw/ide/isa.c +++ b/hw/ide/isa.c @@ -73,7 +73,7 @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp) ISADevice *isadev = ISA_DEVICE(dev); ISAIDEState *s = ISA_IDE(dev); - ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2); + ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2); ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2); isa_init_irq(isadev, &s->irq, s->isairq); ide_init2(&s->bus, s->irq); diff --git a/hw/ide/macio.c b/hw/ide/macio.c index b270a101632..b03d401ceb5 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -449,7 +449,7 @@ static void macio_ide_initfn(Object *obj) SysBusDevice *d = SYS_BUS_DEVICE(obj); MACIOIDEState *s = MACIO_IDE(obj); - ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); + ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000); sysbus_init_mmio(d, &s->mem); sysbus_init_irq(d, &s->real_ide_irq); diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c index 58a14fea363..6df9b4cbbe1 100644 --- a/hw/ide/microdrive.c +++ b/hw/ide/microdrive.c @@ -605,7 +605,7 @@ static void microdrive_init(Object *obj) { MicroDriveState *md = MICRODRIVE(obj); - ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1); + ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1); } static void microdrive_class_init(ObjectClass *oc, void *data) diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index 36e2f4790ab..fb2ebd4847f 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -142,7 +142,7 @@ static void mmio_ide_initfn(Object *obj) SysBusDevice *d = SYS_BUS_DEVICE(obj); MMIOState *s = MMIO_IDE(obj); - ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); + ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); sysbus_init_irq(d, &s->irq); } diff --git a/hw/ide/piix.c b/hw/ide/piix.c index d3e738320be..ce89fd0aa36 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -137,7 +137,7 @@ static int pci_piix_init_ports(PCIIDEState *d) int i, ret; for (i = 0; i < 2; i++) { - ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, port_info[i].iobase2); if (ret) { diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c index ca844419106..618045b85ac 100644 --- a/hw/ide/qdev.c +++ b/hw/ide/qdev.c @@ -68,7 +68,7 @@ static const TypeInfo ide_bus_info = { .class_init = ide_bus_class_init, }; -void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev, +void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev, int bus_id, int max_units) { qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL); diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 34c347b9c20..46204f10d75 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -283,7 +283,7 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) qdev_init_gpio_in(ds, sii3112_set_irq, 2); for (i = 0; i < 2; i++) { - ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); + ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i)); bmdma_init(&s->bus[i], &s->bmdma[i], s); diff --git a/hw/ide/via.c b/hw/ide/via.c index be09912b334..94cc2142c70 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -190,7 +190,7 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) qdev_init_gpio_in(ds, via_ide_set_irq, 2); for (i = 0; i < 2; i++) { - ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i)); bmdma_init(&d->bus[i], &d->bmdma[i], d); From patchwork Thu Sep 30 15:12:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 514920 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:4087:0:0:0:0 with SMTP id m7csp288602jam; Thu, 30 Sep 2021 08:40:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycz1V/S0i2YQo5cFHJplP+JvV9PYoI4MPDqIq+/UZlP/TmGW95DHPMMaDGyx/7odSa+n7I X-Received: by 2002:a05:6102:222f:: with SMTP id d15mr5950682vsb.16.1633016400940; Thu, 30 Sep 2021 08:40:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633016400; cv=none; d=google.com; s=arc-20160816; b=kwWhaseVNkd1VTOYigGByxzj1p0H0uyjkC8foPgLdoJL6CUjdpNsx7goV7nAVN8V3o oAYXpvkdb+Kqt61X8oBkDzOkiVF+cVkFkkOeaiWbzvC++fzAb6dMXGDDxtYWRYuTybkM +0CG7wqosL/9QP6M3vhkMxvx1Sak/ZKYoThqgGDf/uOSBxOZdRBbV2bRgC+1V46PpQDL xEkjBnV7J6jJiXQB2ggdEEu60e6o2QIq9YUQzyNNMdoWySyti94yvApX3BWZD0/QJNzM VetYCOobS8ITZvD+WhNm1MwyEl853ku8+/0LlFhHOq7AzEuwzT4tjPiKa7hUqREap2jC VpVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eE5hlGewDD9+3dCoxNYhNH6vg+idFDYR6hzN8PkHQWs=; b=G5UwenBepdlL0rzPO/SG6OtlRRYIkpXz5Fs18ourH6RYH9Rrii3sUNx/PjRsIXdVUi iYZpOwmGS1XEJL+KpQFtCWkQX0O2LaVRAjaIt0OsiPr/cECYysjQ+Y54IDwEop98XlAU mYNY5/ptZfWO2WjwGmgiEBXyiq7/672y9V08xxNmhtL0qHpGNL18ZJNRAL/41jyJpva0 GC3oTPlJcnux8apeAhc1WDNR8OHm9vftsyo2NPWj41i6zPQamaHb8MZnox31ulPtXDAX mhRyl2o9jkep6vQjJVmdKUJqHrFJ44VNlJr8MKgOzCBBIln3uUDK7vq1DfaEfZZRhQmi uCPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ec8cx/xW"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y1si2946007vsl.209.2021.09.30.08.40.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 30 Sep 2021 08:40:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ec8cx/xW"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mVyAC-0001XJ-6d for patch@linaro.org; Thu, 30 Sep 2021 11:40:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mVxjZ-0000Pv-8I for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:29 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:37377) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mVxjU-000479-7k for qemu-devel@nongnu.org; Thu, 30 Sep 2021 11:12:27 -0400 Received: by mail-wm1-x333.google.com with SMTP id r83-20020a1c4456000000b0030cfc00ca5fso8752293wma.2 for ; Thu, 30 Sep 2021 08:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eE5hlGewDD9+3dCoxNYhNH6vg+idFDYR6hzN8PkHQWs=; b=ec8cx/xWhQrIanR/T3xUeMxZtjOb7CY6RJDNOzoYhJ52L1T/ZYPeHEm3ghPSqHDCKu 5qHLiXEf7vN3/qKFlCimn2KhEZFlRbBIISjMP6pgn74tQEl5n7TQfphboIpHFUhaWJao MJqn0i1B7mwdrjeLnw/SlQp9oLUUinr0EtkVUe7r8hQem+nMLc5MKPuQlfAfF3gqLE74 d8jHaQNFl2KtulpdE/G4KyOahxxCrTtU44V20eSXZyO3vRM+HzvGp/WSpwPzh5c8ATVV 0ACRkJXsXZvjoWSLSCQmQLBjT6MByx+OPtJ4/oWxp6YgRn6MCQTpzWZtzJaEegjahqx2 372A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eE5hlGewDD9+3dCoxNYhNH6vg+idFDYR6hzN8PkHQWs=; b=jipRtexkMx4kJw8mrC9ZVPx029Oed6n9ABu4QtU6qP038Hjo/zSCrzCGtyNXg8rQwt LGF2bRMeXg0gKmjbESqm6aktBvqdBJYq08OunXXamPhCZ+qEg4sSr8uLhvCsf2SThpFI /eG3zlxbRtMnh2kkWn0a20V6oQy8Dzv3K7n7L8m6fTdqwpMTeZKdtcexbXuBWmoFt6zp WtNIIfcaBsneuQVpr6VsL3hzDmcLaW2h4wUiB9KG8lnJ2kEvtzC4jFYAnaoSgx9NguKE nw2vZ4V3H64M8E3SbfnI+e22Q3jFTAIDAVy7fALF/2R7e6Kfye39VshTKMDYpfgso/ea bofQ== X-Gm-Message-State: AOAM533cCT0lBZ0BW5vrFPIFkz6wZqhCe4ezcHi4pXi7aCAvElQu3rbn yY8A3unX5x31h3B2OnF1N/IOfqPlRyJ24A== X-Received: by 2002:a1c:9a4f:: with SMTP id c76mr4037963wme.22.1633014740899; Thu, 30 Sep 2021 08:12:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g8sm1952098wrm.46.2021.09.30.08.12.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Sep 2021 08:12:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/22] hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 Date: Thu, 30 Sep 2021 16:12:01 +0100 Message-Id: <20210930151201.9407-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org> References: <20210930151201.9407-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Xuzhou Cheng The Linux spi-imx driver does not work on QEMU. The reason is that the state of m25p80 loops in STATE_READING_DATA state after receiving RDSR command, the new command is ignored. Before sending a new command, CS line should be pulled high to make the state of m25p80 back to IDLE. Currently the SPI flash CS line is connected to the SPI controller, but on the real board, it's connected to GPIO3_19. This matches the ecspi1 device node in the board dts. ecspi1 node in imx6qdl-sabrelite.dtsi: &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; flash: m25p80@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; }; }; Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to spi1 on sabrelite machine. Verified this patch on Linux v5.14. Logs: # echo "01234567899876543210" > test # mtd_debug erase /dev/mtd0 0x0 0x1000 Erased 4096 bytes from address 0x00000000 in flash # mtd_debug write /dev/mtdblock0 0x0 20 test Copied 20 bytes from test to address 0x00000000 in flash # mtd_debug read /dev/mtdblock0 0x0 20 test_out Copied 20 bytes from address 0x00000000 in flash to test_out # cat test_out 01234567899876543210# Signed-off-by: Xuzhou Cheng Reported-by: Guenter Roeck Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210927142825.491-1-xchengl.cn@gmail.com Signed-off-by: Peter Maydell --- hw/arm/sabrelite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 29fc777b613..553608e5835 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -87,7 +87,7 @@ static void sabrelite_init(MachineState *machine) qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal); cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); - sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line); + qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line); } } }