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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id k28sm2083577ljn.57.2021.10.05.12.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 12:49:13 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Mauri Sandberg , DENG Qingfang Subject: [PATCH net-next 1/3 v5] net: dsa: rtl8366rb: Support disabling learning Date: Tue, 5 Oct 2021 21:47:02 +0200 Message-Id: <20211005194704.342329-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211005194704.342329-1-linus.walleij@linaro.org> References: <20211005194704.342329-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The RTL8366RB hardware supports disabling learning per-port so let's make use of this feature. Rename some unfortunately named registers in the process. Suggested-by: Vladimir Oltean Cc: Alvin Šipraga Cc: Mauri Sandberg Cc: Florian Fainelli Cc: DENG Qingfang Reviewed-by: Vladimir Oltean Signed-off-by: Linus Walleij --- ChangeLog v4->v5: - Collect Vladimir's review tag. ChangeLog v3->v4: - No changes, rebased on other patches. ChangeLog v2->v3: - Disable learning by default, learning will be turned on selectively using the callback. ChangeLog v1->v2: - New patch suggested by Vladimir. --- drivers/net/dsa/rtl8366rb.c | 50 ++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 6 deletions(-) -- 2.31.1 diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index bb9d017c2f9f..b3056064b937 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -42,9 +43,12 @@ /* Port Enable Control register */ #define RTL8366RB_PECR 0x0001 -/* Switch Security Control registers */ -#define RTL8366RB_SSCR0 0x0002 -#define RTL8366RB_SSCR1 0x0003 +/* Switch per-port learning disablement register */ +#define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002 + +/* Security control, actually aging register */ +#define RTL8366RB_SECURITY_CTRL 0x0003 + #define RTL8366RB_SSCR2 0x0004 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) @@ -927,13 +931,14 @@ static int rtl8366rb_setup(struct dsa_switch *ds) /* layer 2 size, see rtl8366rb_change_mtu() */ rb->max_mtu[i] = 1532; - /* Enable learning for all ports */ - ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0); + /* Disable learning for all ports */ + ret = regmap_write(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL, + RTL8366RB_PORT_ALL); if (ret) return ret; /* Enable auto ageing for all ports */ - ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0); + ret = regmap_write(smi->map, RTL8366RB_SECURITY_CTRL, 0); if (ret) return ret; @@ -1272,6 +1277,37 @@ static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port, return ret; } +static int +rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + /* We support enabling/disabling learning */ + if (flags.mask & ~(BR_LEARNING)) + return -EINVAL; + + return 0; +} + +static int +rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct realtek_smi *smi = ds->priv; + int ret; + + if (flags.mask & BR_LEARNING) { + ret = regmap_update_bits(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL, + BIT(port), + (flags.val & BR_LEARNING) ? 0 : BIT(port)); + if (ret) + return ret; + } + + return 0; +} + static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct realtek_smi *smi = ds->priv; @@ -1682,6 +1718,8 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_vlan_del = rtl8366_vlan_del, .port_enable = rtl8366rb_port_enable, .port_disable = rtl8366rb_port_disable, + .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, + .port_bridge_flags = rtl8366rb_port_bridge_flags, .port_change_mtu = rtl8366rb_change_mtu, .port_max_mtu = rtl8366rb_max_mtu, }; From patchwork Tue Oct 5 19:47:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 515259 Delivered-To: patch@linaro.org Received: by 2002:ac0:890a:0:0:0:0:0 with SMTP id 10csp2143587imy; Tue, 5 Oct 2021 12:49:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYmYROPWufSYHbqtlsausolCzucsUpFMcueg5jPeIEfy+R+7rOdWotfcr97Kvifzn38VId X-Received: by 2002:a17:906:d541:: with SMTP id cr1mr28393818ejc.81.1633463361049; Tue, 05 Oct 2021 12:49:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633463361; cv=none; d=google.com; s=arc-20160816; b=io2AXt1l0sir5f+up+fZpjvtYEHBycZdheyDx2EfGC+DeCqoHGGawiGBfdEkg0PTml Jq8cpFQoR3gntaif57ZmBjP0EoX50h7cUZ68EKqq9CTi4NQNBupWnk1H4U63chmKggVq oV2v4ffF6U3eLEkbJA10zkWkFuUzNCv3uvoTT+eDmcHZhVPyrDUNkChDJwpC2HRkF0CK IuIGIrg7w/kYneMtZXIG/YUV3Ju8ufTpoTpGu4otiKgq8JSRX8cgxQzwUDAsbNqQW7Ju 1jWqLp/HpeEbUjB0fAMTIPEwernBTatMshkCELazfLKXbuk8v1IX2IUQbVgZ+Ptod/Uj cixA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DpxUMZjEmbxwlgRUpAcp+St9BsqthlNtt9JsygSxW+o=; b=BureycwN08A5aSJmuburosLQP6mapn523PwG3md5/xkdcLYVhgIziDUysXIH9wCpLm bEr1IhYa3EYLsriq8GnepW7JBvq4gLYq+YxChoFkS/o47XTOgS6T0PYKqvloAgIotLoH n/Tukn4uyhXoViNRmG1TGQ2lTj9ugpVfYrUQlVll2jDdxvrLp1XWo0OhLgTlpyFGLKUY DVbmZyCMoWrsf2hOkVh8C0aE4Isaji7kpJirPez56ZFVU2YqmHERbysr1udggl74UEjf h2Q+pbLHuZmnQlutbAmV0IiH6/PY0i3bo2l+gQegabCCKioQ2kWqPVdUxm6Hcwk7ASGX TihA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NItpHXRH; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id k28sm2083577ljn.57.2021.10.05.12.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 12:49:14 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , Mauri Sandberg , DENG Qingfang , =?utf-8?q?Alvin_=C5=A0ipraga?= Subject: [PATCH net-next 2/3 v5] net: dsa: rtl8366rb: Support fast aging Date: Tue, 5 Oct 2021 21:47:03 +0200 Message-Id: <20211005194704.342329-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211005194704.342329-1-linus.walleij@linaro.org> References: <20211005194704.342329-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This implements fast aging per-port using the special "security" register, which will flush any learned L2 LUT entries on a port. The vendor API just enabled setting and clearing this bit, so we set it to age out any entries on the port and then we clear it again. Suggested-by: Vladimir Oltean Cc: Mauri Sandberg Cc: DENG Qingfang Cc: Florian Fainelli Reviewed-by: Alvin Šipraga Signed-off-by: Linus Walleij --- ChangeLog v4->v5: - Update changelog a bit what else can we do. ChangeLog v3->v4: - No changes, rebased on the other patches. ChangeLog v2->v3: - Underscore that this only affects learned L2 entries, not static ones. ChangeLog v1->v2: - New patch suggested by Vladimir. --- drivers/net/dsa/rtl8366rb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.31.1 Reviewed-by: Vladimir Oltean diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index b3056064b937..c78e4220ddd1 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -1308,6 +1308,19 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, return 0; } +static void +rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) +{ + struct realtek_smi *smi = ds->priv; + + /* This will age out any learned L2 entries */ + regmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL, + BIT(port), BIT(port)); + /* Restore the normal state of things */ + regmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL, + BIT(port), 0); +} + static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct realtek_smi *smi = ds->priv; @@ -1720,6 +1733,7 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_disable = rtl8366rb_port_disable, .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, .port_bridge_flags = rtl8366rb_port_bridge_flags, + .port_fast_age = rtl8366rb_port_fast_age, .port_change_mtu = rtl8366rb_change_mtu, .port_max_mtu = rtl8366rb_max_mtu, }; From patchwork Tue Oct 5 19:47:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 515260 Delivered-To: patch@linaro.org Received: by 2002:ac0:890a:0:0:0:0:0 with SMTP id 10csp2143609imy; Tue, 5 Oct 2021 12:49:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYys3J5YmqF4K2KoAdajUbs80ZbayGjXgXz9L9tpvOVK9kj0Lyy1DxbV9mP7ubjPQAMWJX X-Received: by 2002:a17:906:2a44:: with SMTP id k4mr27256533eje.328.1633463363911; Tue, 05 Oct 2021 12:49:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633463363; cv=none; d=google.com; s=arc-20160816; b=ubN5c6oQ3r5nQknwgBS0tO0UbprKvSlbISb13duyz+LtUCRgHAJSehDKs4VBOYAAVo eouWyhuH5WAIkOF3PBe9NxurMUqSLoiAk/PDcbRRRgZO5KVluPhFjTouxuH7GnNyTILn DdoW9Nyi50ngu6wuvm4P/950mBe726GV1iwnzfKd4dj6rN70YkwlUgi0jyU4IlKAyAYd wqsIcar/JemLe1D0aAl/NFZ6D+wlgy1uJLej3hnbC8i79DX7a9ntqSKxRzuDYE1GNCiA H3Pf3K+k4h+zQWOgrQYDIEaeybj35QLhJid6xdsS44Em9ve0Laz/pPESJrm86KldHXZ6 tfEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pku09rj7/VU7FTxKbOt83SUvrPCcVT0ttGrANV0CkWQ=; b=TS7XbTy4O/Zw0LInP3jq6ofcRLyJkO8Jk7++l5ry1iFsib1tCsTBVYRiEk3vn4n1x9 rkYVdnFXiRYsuLwg81qZa86F11MnQ9l2+sfZGOCG+lPL+6+k7hjtlC4rEdheN0BBzJ0t bzSTXC/Yjrv0j58DICR1PckQFtTmYijlYYUI8cbYH/OqkBn+9WlWJg+TAagnNGfP42s3 bJqZMomn2n3GlZZ0LV3xEiAi5nl0vL54vmQXmRUPKO1t86uBP2082OyaJafU//nSYqnL 5I2kxbfHkE4YLVq9rXfKUZohSqRkCItrmESK+Li7pxOnsTQeQ9ViNsunZvajezowzKmQ vYzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dBimG1es; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id k28sm2083577ljn.57.2021.10.05.12.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 12:49:16 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski Cc: netdev@vger.kernel.org, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Mauri Sandberg , DENG Qingfang Subject: [PATCH net-next 3/3 v5] net: dsa: rtl8366rb: Support setting STP state Date: Tue, 5 Oct 2021 21:47:04 +0200 Message-Id: <20211005194704.342329-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211005194704.342329-1-linus.walleij@linaro.org> References: <20211005194704.342329-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This adds support for setting the STP state to the RTL8366RB DSA switch. This rids the following message from the kernel on e.g. OpenWrt: DSA: failed to set STP state 3 (-95) Since the RTL8366RB has one STP state register per FID with two bit per port in each, we simply loop over all the FIDs and set the state on all of them. Cc: Vladimir Oltean Cc: Alvin Šipraga Cc: Mauri Sandberg Cc: DENG Qingfang Signed-off-by: Linus Walleij --- ChangeLog v4->v5: - Rename register from RTL8368S* to RTL8366RB as all other registers. (RTL8368S is some similar ASIC maybe the same.) - Rename registers from "SPT" to "STP", we assume this is just a typo in the vendor tree. - Create RTL8366RB_STP_STATE_MASK() and RTL8366RB_STP_STATE() macros and use these. ChangeLog v1->v4: - New patch after discovering that we can do really nice bridge offloading with these bits. --- drivers/net/dsa/rtl8366rb.c | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.31.1 Reviewed-by: Vladimir Oltean diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index c78e4220ddd1..d2370cda4be0 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -110,6 +110,18 @@ #define RTL8366RB_POWER_SAVING_REG 0x0021 +/* Spanning tree status (STP) control, two bits per port per FID */ +#define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */ +#define RTL8366RB_STP_STATE_DISABLED 0x0 +#define RTL8366RB_STP_STATE_BLOCKING 0x1 +#define RTL8366RB_STP_STATE_LEARNING 0x2 +#define RTL8366RB_STP_STATE_FORWARDING 0x3 +#define RTL8366RB_STP_MASK GENMASK(1, 0) +#define RTL8366RB_STP_STATE(port, state) \ + ((state) << ((port) * 2)) +#define RTL8366RB_STP_STATE_MASK(port) \ + RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK) + /* CPU port control reg */ #define RTL8368RB_CPU_CTRL_REG 0x0061 #define RTL8368RB_CPU_PORTS_MSK 0x00FF @@ -234,6 +246,7 @@ #define RTL8366RB_NUM_LEDGROUPS 4 #define RTL8366RB_NUM_VIDS 4096 #define RTL8366RB_PRIORITYMAX 7 +#define RTL8366RB_NUM_FIDS 8 #define RTL8366RB_FIDMAX 7 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */ @@ -1308,6 +1321,40 @@ rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, return 0; } +static void +rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) +{ + struct realtek_smi *smi = ds->priv; + u32 val; + int i; + + switch (state) { + case BR_STATE_DISABLED: + val = RTL8366RB_STP_STATE_DISABLED; + break; + case BR_STATE_BLOCKING: + case BR_STATE_LISTENING: + val = RTL8366RB_STP_STATE_BLOCKING; + break; + case BR_STATE_LEARNING: + val = RTL8366RB_STP_STATE_LEARNING; + break; + case BR_STATE_FORWARDING: + val = RTL8366RB_STP_STATE_FORWARDING; + break; + default: + dev_err(smi->dev, "unknown bridge state requested\n"); + return; + }; + + /* Set the same status for the port on all the FIDs */ + for (i = 0; i < RTL8366RB_NUM_FIDS; i++) { + regmap_update_bits(smi->map, RTL8366RB_STP_STATE_BASE + i, + RTL8366RB_STP_STATE_MASK(port), + RTL8366RB_STP_STATE(port, val)); + } +} + static void rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) { @@ -1733,6 +1780,7 @@ static const struct dsa_switch_ops rtl8366rb_switch_ops = { .port_disable = rtl8366rb_port_disable, .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, .port_bridge_flags = rtl8366rb_port_bridge_flags, + .port_stp_state_set = rtl8366rb_port_stp_state_set, .port_fast_age = rtl8366rb_port_fast_age, .port_change_mtu = rtl8366rb_change_mtu, .port_max_mtu = rtl8366rb_max_mtu,