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[23.128.96.18]) by mx.google.com with ESMTP id h7si1158223pgq.411.2021.10.07.18.25.32; Thu, 07 Oct 2021 18:25:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JpdfMMMW; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235563AbhJHB1Z (ORCPT + 17 others); Thu, 7 Oct 2021 21:27:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbhJHB1Z (ORCPT ); Thu, 7 Oct 2021 21:27:25 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D423C061570 for ; Thu, 7 Oct 2021 18:25:30 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id y15so32488739lfk.7 for ; Thu, 07 Oct 2021 18:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D/FnULHtOSn2r5lygapPAHJMuBEtxiZqi9m5HusuZIQ=; b=JpdfMMMWW2nPaI/K2OrZTUJ1ABBi7mYPTEPpP/qdP2k69L9XHKfRXN9EScbtOXHIIk 07oX9fTBSctsN0nS+r9pG3J+QQjq9ZGN2jdR5Js0CgYP75VYCrYTFtd3UAwZxIRQnXrm 5uXbKlOcWcs2fhesulYbaZV+AQOV/fcFCh5LQ1qAyc1b/vTozLhkkx3RuBCeWKhj/ani 3xpPK0QunT7ZB8abxJ4q2DGd567nZNUVTPLIcT4EHcUk/BniG8vMgWd6c31oetZhYZrZ Cc6e4gwqIF3hOwqvuK/Qf6amcnn/xSOtuO3tQ7WiBldAFqPb5wX50d6nARxveyVfQnSM 9iRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D/FnULHtOSn2r5lygapPAHJMuBEtxiZqi9m5HusuZIQ=; b=vDl5/8X9IWfrMmQTyVjjSxbiEUJBEqO30++XH8ILzBuPWXh9uNjRdhZqOut4VVgpO0 558KLP/HIAk2yfa+r5KUxBSAiwnjaOvway7XuJIwoKcga0TyoHzc8x/5SWYEm4QrMd0H 44YXiIt7l2v/jSGvRXTbwQjle3RRjYK/sfjC54JBdp46Na/3LEUly67/oVjXUztXvwNz ZlUNNqu7Dtj4CmaGw2UM7fmZZPMdqxAmT/K024ci2A5RdN1QPAVELeyQuT5O8vECFqjl Cf4nLPBkBuV+sOxZOffEUZCOt6/g5t1ZMxYIuw/c9+qDuUztJtoFVi8SBRZrknhXdZs9 O9lQ== X-Gm-Message-State: AOAM530bG4hB7rlCz9xT4bHjg9tH+z1GabCj0vNF7Q0NS+iSXOxezX56 mZeVpM1a2cYsBv/sTwIbisvxyrAzOcPvAg== X-Received: by 2002:a05:651c:d0:: with SMTP id 16mr374187ljr.428.1633656328842; Thu, 07 Oct 2021 18:25:28 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 01/25] dt-bindings: pinctrl: qcom, pmic-mpp: Convert qcom pmic mpp bindings to YAML Date: Fri, 8 Oct 2021 04:25:00 +0300 Message-Id: <20211008012524.481877-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert Qualcomm PMIC MPP bindings from .txt to .yaml format. Signed-off-by: Dmitry Baryshkov --- .../bindings/pinctrl/qcom,pmic-mpp.txt | 187 ----------------- .../bindings/pinctrl/qcom,pmic-mpp.yaml | 188 ++++++++++++++++++ 2 files changed, 188 insertions(+), 187 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt deleted file mode 100644 index 5363d44cbb74..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ /dev/null @@ -1,187 +0,0 @@ -Qualcomm PMIC Multi-Purpose Pin (MPP) block - -This binding describes the MPP block(s) found in the 8xxx series -of PMIC's from Qualcomm. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,pm8018-mpp", - "qcom,pm8019-mpp", - "qcom,pm8038-mpp", - "qcom,pm8058-mpp", - "qcom,pm8821-mpp", - "qcom,pm8841-mpp", - "qcom,pm8916-mpp", - "qcom,pm8917-mpp", - "qcom,pm8921-mpp", - "qcom,pm8941-mpp", - "qcom,pm8950-mpp", - "qcom,pmi8950-mpp", - "qcom,pm8994-mpp", - "qcom,pma8084-mpp", - "qcom,pmi8994-mpp", - - And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" - if the device is on an spmi bus or an ssbi bus respectively. - -- reg: - Usage: required - Value type: - Definition: Register base of the MPP block and length. - -- interrupts: - Usage: required - Value type: - Definition: Must contain an array of encoded interrupt specifiers for - each available MPP - -- gpio-controller: - Usage: required - Value type: - Definition: Mark the device node as a GPIO controller - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - the first cell will be used to define MPP number and the - second denotes the flags for this MPP - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of MPP pins affected by the properties specified in - this subnode. Valid pins are: - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 - mpp1-mpp4 for pma8084 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "digital", - "analog", - "sink" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - Valid values are 600, 10000 and 30000 in bidirectional mode - only, i.e. when operating in qcom,analog-mode and input and - outputs are enabled. The hardware ignores the configuration - when operating in other modes. - -- bias-high-impedance: - Usage: optional - Value type: - Definition: The specified pins will put in high-Z mode and disabled. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode, i.e. their input - buffer is enabled - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- power-source: - Usage: optional - Value type: - Definition: Selects the power source for the specified pins. Valid power - sources are defined in - -- qcom,analog-level: - Usage: optional - Value type: - Definition: Selects the source for analog output. Valued values are - defined in - PMIC_MPP_AOUT_LVL_* - -- qcom,dtest: - Usage: optional - Value type: - Definition: Selects which dtest rail to be routed in the various functions. - Valid values are 1-4 - -- qcom,amux-route: - Usage: optional - Value type: - Definition: Selects the source for analog input. Valid values are - defined in - PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... -- qcom,paired: - Usage: optional - Value type: - Definition: Indicates that the pin should be operating in paired mode. - -Example: - - mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pm8841_default>; - - pm8841_default: default { - gpio { - pins = "mpp1", "mpp2", "mpp3", "mpp4"; - function = "digital"; - input-enable; - power-source = ; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml new file mode 100644 index 000000000000..475733cabb02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC Multi-Purpose Pin (MPP) block + +maintainers: + - Bjorn Andersson + +description: + This binding describes the MPP block(s) found in the 8xxx series of + PMIC's from Qualcomm. + +properties: + compatible: + items: + - enum: + - qcom,pm8018-mpp + - qcom,pm8019-mpp + - qcom,pm8038-mpp + - qcom,pm8058-mpp + - qcom,pm8821-mpp + - qcom,pm8841-mpp + - qcom,pm8916-mpp + - qcom,pm8917-mpp + - qcom,pm8921-mpp + - qcom,pm8941-mpp + - qcom,pm8950-mpp + - qcom,pmi8950-mpp + - qcom,pm8994-mpp + - qcom,pma8084-mpp + - qcom,pmi8994-mpp + + - enum: + - qcom,spmi-mpp + - qcom,ssbi-mpp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 12 + description: + Must contain an array of encoded interrupt specifiers for + each available MPP + + gpio-controller: true + gpio-line-names: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + const: 2 + description: + The first cell will be used to define gpio number and the + second denotes the flags for this gpio + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-pmic-mpp-state" + - patternProperties: + "mpp": + $ref: "#/$defs/qcom-pmic-mpp-state" + additionalProperties: false + +$defs: + qcom-pmic-mpp-state: + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. Valid pins are + - mpp1-mpp4 for pm8841 + - mpp1-mpp4 for pm8916 + - mpp1-mpp8 for pm8941 + - mpp1-mpp4 for pm8950 + - mpp1-mpp4 for pmi8950 + - mpp1-mpp4 for pma8084 + + items: + pattern: "^mpp([0-9]+)$" + + function: + items: + - enum: + - digital + - analog + - sink + + bias-disable: true + bias-pull-up: true + bias-high-impedance: true + input-enable: true + output-high: true + output-low: true + power-source: true + + qcom,analog-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog output. Valued values are defined in + PMIC_MPP_AOUT_LVL_* + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,atest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects ATEST rail to route to GPIO when it's + configured in analog-pass-through mode. + enum: [1, 2, 3, 4] + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects DTEST rail to route to GPIO when it's + configured as digital input. + enum: [1, 2, 3, 4] + + qcom,amux-route: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog input. Valid values are defined in + PMIC_MPP_AMUX_ROUTE_CH5, + PMIC_MPP_AMUX_ROUTE_CH6... + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,paired: + - description: + Indicates that the pin should be operating in paired mode. + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + + pm8841_mpp: mpps@a000 { + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; + reg = <0xa000 0>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpp 0 0 4>; + gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL", + "BT_LED_CTRL", "GPIO-F"; + interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8841_default>; + + mpp1-state { + pins = "mpp1"; + function = "digital"; + input-enable; + power-source = ; + }; + + default-state { + gpio-mpp { + pins = "mpp1", "mpp2", "mpp3", "mpp4"; + function = "digital"; + input-enable; + power-source = ; + }; + }; + }; +... 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Schema for other possible nodes does not exist yet. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/mfd/qcom-pm8xxx.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml index 9065ec53e643..10021eb7103e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml @@ -38,10 +38,22 @@ properties: interrupt-controller: true patternProperties: + "gpio@[0-9a-f]+$": + type: object + $ref: "../pinctrl/qcom,pmic-gpio.yaml" + + "mpps@[0-9a-f]+$": + type: object + $ref: "../pinctrl/qcom,pmic-mpp.yaml" + "rtc@[0-9a-f]+$": type: object $ref: "../rtc/qcom-pm8xxx-rtc.yaml" + "xoadc@[0-9a-f]+$": + type: object + $ref: "../iio/adc/qcom,pm8018-adc.yaml" + required: - compatible - '#address-cells' From patchwork Fri Oct 8 01:25:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515531 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675162ime; Thu, 7 Oct 2021 18:25:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpfMzOOFycxLY+8dmLn41p+QLnecIAwBTMKa3WkjinvI/S+0lm7c1RC1Ki+LI9QuSTrHUv X-Received: by 2002:a62:1553:0:b0:44c:67cf:e669 with SMTP id 80-20020a621553000000b0044c67cfe669mr7505938pfv.55.1633656339523; Thu, 07 Oct 2021 18:25:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656339; cv=none; d=google.com; s=arc-20160816; b=eGtS8RF02VIOwRFGgw+6ypTMKX4a4f7mQ2u0vWSRTGDRAWDxpjkV1MIWFp7p6jObPc moIkZKTT6v9S6besKgUFYn8yiTud+Jb+gLw6qa+TeJ0RdkC/W8f3mcCPBEWlEZi2/kL0 Z1Iw3Pp9O/367N7NUBBQPAVdxdBO4f52iAQI1Nyp9IE8WhQ3XE3xrNBkh5LQ9J4UdONb QXHOHaW+YRYiMQ8uwCbIFZv2DsLC2Ck2YB9dCwyrSchpN9ztOKm9Lq6VL2mZOTkOTQDV NbBRggNDqoMew8AxRqvahDdPs91SgJmaGknnBkJq7IdmKWWccAudmMMyKoUuB5kkbrGl xRfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sE/GeDbmDq0h+hKpjaIbLxWeY1CrCvRz2kO4vU6ead4=; b=fNDqG7bznS4Ji+8oF7rbrIFH0rDErftMvpYhWqqvHmc6YuauxSYW9AD+2E4ZaWlMHm eqk7iPAHzNOgVnJn+wBDBhPzEYk3ZpGnPoDFHKV1n0BUxml456eMUVFqtjewitc/30bv OVBhKRAv63qeLZJxtrUwdUDOBJ0hJNzDeyN0zuQANtFxcoyGOj4OUmp/UnDKqGjxgXu3 wium9ISTUjLom9RAFkBKnxM2hOd/bl4KL9lqQM2pkEUDqD4SURECihKS91L8Wd7j9TUi J8wWOC2MbPysbXvK6YHG3HzjIC4omnWQ/itbB66YSRp5phI9f5616181cUadHvG6xx26 /Ezw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mO2BfTUS; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8941.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index c1f2012d1c8b..cf8daa2fe144 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -79,6 +79,7 @@ pm8941_mpps: mpps@a000 { reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8941_mpps 0 0 8>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515532 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675183ime; Thu, 7 Oct 2021 18:25:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJya2ZzIJonj76/uXWK2IDih95wPBdHAU7VNeVIlKDfi9w8oZ6C/u4lrXTIHTjpa6aniyA/a X-Received: by 2002:a17:90a:4306:: with SMTP id q6mr9108166pjg.202.1633656341055; Thu, 07 Oct 2021 18:25:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656341; cv=none; d=google.com; s=arc-20160816; b=mJptG488hrUJBtyhItrz4lOHjI0TsCIMqqxm8KwQUw7aNl/hNnhQseDv3wum+t1k8/ bhO8duDfwtkBfzQmG4QtsJfhE2b4cn7LmYMbTnL0mPdltJNf8XXhCShgRWQFCRHDl7u3 M5vzu2iDiNRTWgm8+5lQbUCEGItuz8hohD1U6L8E6DBeGdg3HOVMlQlCaiFaExXiq++Y +1WqnQ7R0P7h0Jj5k2ue302pBoOXFrW1ZCffv69Gz0n+eQqNNJDW3oyhTb57AXQbNoav SWGPzYXutD7xDOzwzwyG5KrWcKpcsR1WH5nFHZLlS86363gPDJzytXSPwuQN9dg+KGCt 34tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=l105OhexlN6YNfKbmvTA4DJELYmmbABapWIiAJPQyxM=; b=w/oLaGcb8OV23QzpJJEQw4o2EbH6tgXg7POaOo8Op3n5RQccs8QXRO6xudOyNhSXSR +lnyOFgeVCTjK6ZDjbyRN+6UsEjcpm3OtfsQkzYyFr0oBZlFBzqaiw6IcFTn2ShIyEej hvMaJFAuqS2HGuMUGPjFjbay3nYaGocfrf/XrbiBr4kc6NLMQXjR/DsguknWJww9cAFz DhQjMv4HblDywbue8eNKqXCbwYKYrITRPb2Mb7UhLTBvmeZ+67VyNnkWVGuHk6EI6yYq n5nOxkR3rhee3ZlP//9390r7YrWD+wb6FIV9L2roG03RwVZCe8MpX1CWttgWF9kWV31D 6H8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y/co2dD2"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pma8084.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index e921c5e93a5d..fcee2afe6740 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -42,6 +42,7 @@ pma8084_mpps: mpps@a000 { reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pma8084_mpps 0 0 8>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515535 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675223ime; Thu, 7 Oct 2021 18:25:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxWrG02R3QcvzZkXV2NCdvcBzcehiNfyT5vpTk/JXkz56rM0sJpDE91ODUqrWKT6vOwcPul X-Received: by 2002:a17:90a:e453:: with SMTP id jp19mr9091253pjb.11.1633656344802; Thu, 07 Oct 2021 18:25:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656344; cv=none; d=google.com; s=arc-20160816; b=H6Y4IoS/LNSDLcvGMq18Nt8brjgRBJ54o7kZNyKmrNYhxL+AM7y0m7h/GxuLlY1CXv z7G/HrKgFv49ZfF+D6h0JnBFCL1RzqhY6Anv2UNJmnPMKcjlghlBLp3+h+9/K60GfITb ZFxMdF29+91GWLiVYGoNq6BkCTs42amUojxHNMH4mn4Op/12kHGGXO9UBHaSTQy29GVV 6iGKizdvQtR51jDiJ4IRvr054SUfHrZS7Zo9rc5bo1KGafcJPlzBzh0BTiGPux+6Zqkq wDhzZChO5JyRt5Gug+wmUzC6HBGqCQRsC7AsiEEis1EZ73rF17rD65/c5HYhjQj4zOaL wLMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N1fDvr411Sym7LpWWuQWuBZ0aeO9/HmmaZ6tC+1sj4g=; b=GI370CNOiOwgCWJD1zcduMy8U5BKjGyrSoTvjUaPlDnNHkWoFmaD7R1gmlD/pucKQ+ ejgco0hciZJ/2L9gQRLoCjEUP3Hp2JjPn3v3uSuJO8nT/mUxF5LUbbCYoRYYnwHGz1DR T3kOUSHQa5+yCDhxmg8pV1065WuZ/n9WdxnAsvyg63C/N+wlpi3kuw1p6DGFwTHGyUm7 aMZzaPZ/Kx9v8d9Oej8hCRSOCuhKC3IYasJL0THStTZ8M8aIaQi2Et40XO8ecRrNRwGH KXzvDJTErNgXTDnVRBbfsAHsYV/sOP1IqNv2rVR6sioMWy8jsPhGC5PqNplHdrKEJYOz WqUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZCazwiO1; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Also add gpio-ranges property to mpps device tree node, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index f931cb0de231..7d9e25dd9e3a 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -91,10 +91,11 @@ rtc@6000 { }; pm8916_mpps: mpps@a000 { - compatible = "qcom,pm8916-mpp"; + compatible = "qcom,pm8916-mpp", "qcom,spmi-mpp"; reg = <0xa000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pm8916_mpps 0 0 4>; interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, <0 0xa1 0 IRQ_TYPE_NONE>, <0 0xa2 0 IRQ_TYPE_NONE>, From patchwork Fri Oct 8 01:25:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515537 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675251ime; Thu, 7 Oct 2021 18:25:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyeQyT635tQrO/B2B0LftmyKIRcNAQZngxkSfup00NJ+/TRFaSoa8VUHL0IsbnPxBv4Q2Li X-Received: by 2002:a63:ed4a:: with SMTP id m10mr2376262pgk.448.1633656348246; Thu, 07 Oct 2021 18:25:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656348; cv=none; d=google.com; s=arc-20160816; b=cODXGcLEoLGOpZ6k33aTjxaya1ufvNtq5SKVhYKgBUwFdv67j6GvNNKDyz060aqebU r0BsHscvBDpYpRwKKSkBTrHBTBbHiZbp572dKmDbjxEENHurV0N1fxowwC/f5ayVVlFr bMrGBmgCa65oIASR//R7NHLSFQNnwBqV9vC2OvqUEoiqHnd0klOiV11/8YFrdMLXVuY4 Ox73Rp27+vfVyYvBuakIZ/6CI3P8DDN8R4yPZfm5q44RvSBgjvWIINM0NJjbEvflHoGj +sqZaRo57hSty/7pYJ683GyIO3UCJQ6CvbQ/C+JahDiUJHyl+AXVXcLzH9aNzo8OOEN6 Edbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+kHxD4AyFKHTUkzUIxG/0HGOEUmjqFeIEbITSocdKfU=; b=0j/6hx1vgOAKW3/4EyQHDF6tw/0z5dP78h6rCtUwLO+y2+gAnefVtLynvT4XVAsNFA FP3Vn+jaK5U5GEXctSoTk6JyUcEPBvWnzDFC5WT0PbvK9w05i4QwhGwAiXQ57f26ps7F Nuvq1qD4MW7jHqJk8fZWu8DKAK7FQKDV2PVIENd0MELhMeOCSfqvzrF5P7lYSjVQnEjr v3vA4/5nWJQTBPU5yaqC/fY0zoby6lK/lWilVOxt1Ugq3OK8Ajue+1hXgRV6vndF5zFu ew1Bsyc1KtdcrgYaLp3wKqlwJazw1s8pm7lgfBu7GbcIo08R2VOqyj3VKKduTugfvyOv KvBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FnMeBDx4; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h7si1158223pgq.411.2021.10.07.18.25.48; Thu, 07 Oct 2021 18:25:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FnMeBDx4; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239061AbhJHB1l (ORCPT + 17 others); Thu, 7 Oct 2021 21:27:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236805AbhJHB1c (ORCPT ); Thu, 7 Oct 2021 21:27:32 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F99CC061772 for ; Thu, 7 Oct 2021 18:25:37 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id b20so32911285lfv.3 for ; Thu, 07 Oct 2021 18:25:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kHxD4AyFKHTUkzUIxG/0HGOEUmjqFeIEbITSocdKfU=; b=FnMeBDx4co3rsikNmA1+yvAsBmxVSkiWs5uWbbwykTb4OfQVbqqzyofcLbaA/OeBbU 5lFh3JQm9/xHlSNWM+xdsRNLzzGpKY3s6B0sSE9eU2GB9wZUmHhUTEJEYX1kOya4MV6q L6DpFPTtXVpbVwnhr3bryYfzAUjfRnoUAtw6ofnOu/+RhslY7TUA54T0xBekKxQYKGRK prTgFfgfgau71HWn0+4NAjzNk3yfvqx5JV4yY77kXNJ/ArBufx0hc7zKJ2E9YdsiYJzg VCbEwswd+sq9yDKO2D5o88li6S7B9gJu1lHpH29lOiff0ULC1S2dpxlwCZqnI0U21OqY 4mqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kHxD4AyFKHTUkzUIxG/0HGOEUmjqFeIEbITSocdKfU=; b=o89GZAKW8PU1NcLyz5dFETxXfxT7s3wqX4uO09rgiFD0t8iQarGfPrsvpwTeynuog4 picJqpCTudD/XI330Y9kvBBbVwCMsrL49kS2PQN3uuQ4W29zbl5XiJ6Nyle2RmyDDOBP 2R4+lI4vcl8TTWbbcNK7jsXAttcmChaBp+zhkFQQS1ZWZ059ccNBrcRXZPqOXBzZQj8T X/Gvcj+XJ7nZ4n881bT55YPoSxcb0kEJKqnXGLX8ymIJ7pt7Wwys8l23SfHqLhVRRt19 xEO4ISMHFrg2BEObQD8beS4Lq4De637KLD7jXulkUtSh2zKHz/vvLANOQ8JkOKucy8eD e5Ww== X-Gm-Message-State: AOAM533tusRA0h4fpfX7K7A1aMJ4MqSZIXDGIbSPyBqhJFHEoD2OAcwz icJTYzL3n7PZbWaQbm9YwQf15Q== X-Received: by 2002:a05:6512:3d13:: with SMTP id d19mr7190869lfv.607.1633656336004; Thu, 07 Oct 2021 18:25:36 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 12/25] arm64: dts: qcom: apq8016-sbc: fix mpps state names Date: Fri, 8 Oct 2021 04:25:11 +0300 Message-Id: <20211008012524.481877-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The majority of device tree nodes for mpps use xxxx-state as pinctrl nodes. Change names of mpps pinctrl nodes for the apq8016-sbc board to follow that pattern. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index f8d8f3e3664e..a250145849cd 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -809,7 +809,7 @@ &pm8916_mpps { pinctrl-names = "default"; pinctrl-0 = <&ls_exp_gpio_f>; - ls_exp_gpio_f: pm8916-mpp4 { + ls_exp_gpio_f: pm8916-mpp4-state { pins = "mpp4"; function = "digital"; @@ -817,7 +817,7 @@ ls_exp_gpio_f: pm8916-mpp4 { power-source = ; // 1.8V }; - pm8916_mpps_leds: pm8916-mpps-leds { + pm8916_mpps_leds: pm8916-mpps-state { pins = "mpp2", "mpp3"; function = "digital"; From patchwork Fri Oct 8 01:25:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515540 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675308ime; Thu, 7 Oct 2021 18:25:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxyI+NOn1YGDq3knct8vdejT7Htsw6Hx3ketxSou09f4Ew30BNJejx6My+AWA2B70zBF216 X-Received: by 2002:a17:902:7e84:b0:13e:d793:20d8 with SMTP id z4-20020a1709027e8400b0013ed79320d8mr6767647pla.67.1633656353450; Thu, 07 Oct 2021 18:25:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656353; cv=none; d=google.com; s=arc-20160816; b=mi2W5U5MuVtjkASWZFdKOhHyDCUcCO2987wehaOnjfz6YNBp2UOCl9wAGC313iTW5x qYoxU+qqRk073l0BCzCOYFlVvZWx8Etq6+Qcs/lwJ1yHIyhE+PxFyWkL2JlmzZ8s/pRw xWjU2jG9LOAKbIeslGgj0qnD90iJgTEpcLxdyiHfbHPRDsAiHTpXDOYEJW/ERfPgQC0R M8PSU0EZkpfeBZEgYkVSLhSh7890jNAwKNoFKTq3P/IJgyfOckZKfX9uwt5gNXtBH03J R2nbi15f6j+qKRQN/r3RZ8FY4IFlfHAr+Uvwv3kg85jPxSn3h1zW4P3ebHSMTsoanOz7 pJ9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E2YJV+cRv0tFDhiSivfR6SvH37WdzUlDmvLwCor6dDY=; b=hWfbiKvo6EGTg3mS+xeDKCHLDVCS3A3wampQlefTwEm5wbdRQ9L/Vu7LW9FLsMGfWf PnMir2cPCE6aeYqhprV13SihBwoVIh187Gi9J6oWhgV/oCPv/qerwPywLshtM49yOftU hukfo76VQQM51k1qKz8z501E1cLM8SO6VptGHVMD5IEYkOYySYGufEGaDYVR2usS22G2 CdMlyxyv03F422i0imqGxE41p9p3c0RxBYgNuL4P6ilPibqMe9iTf+MLkqiJcqW3SrS1 ndyWHyNkoPYOwTbwhOrhlMbUomYu1BrlfxlqZF+te5fin7wS3Ktt8T5bshwefKAhkVGX WtzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L0KijY6p; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h7si1158223pgq.411.2021.10.07.18.25.53; Thu, 07 Oct 2021 18:25:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L0KijY6p; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238708AbhJHB1o (ORCPT + 17 others); Thu, 7 Oct 2021 21:27:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229529AbhJHB1i (ORCPT ); Thu, 7 Oct 2021 21:27:38 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 381DDC061775 for ; Thu, 7 Oct 2021 18:25:40 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id i24so30955889lfj.13 for ; Thu, 07 Oct 2021 18:25:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E2YJV+cRv0tFDhiSivfR6SvH37WdzUlDmvLwCor6dDY=; b=L0KijY6p8P4ir96ydYttFpDY6QH7wz+RURuOgIU/aV3EWWykzGCdoVOkpmyqYnWJCU f/uf8ZfYuItGUqG2gOYku+cVct63S3Ox/oYW7iWw9tkZFDTaFXmgNlmTCAlcmQJnFuYh NJ9YmcW+Ruh9GVh8CmEWV5ci7N536jf8ZQH1h55ZS8xtubS4+Kl7cCabNakQ9b/RzTFc 30FEZFZojfOcK4/XAFxqk3OU/n0UHEuaaCEHL5/MqqW9VdActROsO2bRnb74c1B7QrWq EQVQ1+vhgA03SY9HBbOuHb7tTXqvVd6HztM9Lh4QtQpVHTYse6HGhRJPwTUDwWBug6AZ 7vRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E2YJV+cRv0tFDhiSivfR6SvH37WdzUlDmvLwCor6dDY=; b=NwVKLuVagW++gpyKQSkgZMnT5qbyj5ls5bGVnEE7YZmy0d6bFUMTh5sj6lohBrHTio pKJwqlT1Aa6M1sO91R9yX1KPCPX8msJ+tpYFXR8HWWvkquYCfNCwa5+avOioWg4VssGD YHwqZ1mAp51EJLHV9PGKE1OsquoxZPINzXNlUpdMjTfqMApLw7BcnudwTdwm4u4Fu4Xv pLdpAQsjIpcr+Oc+nUwVfCYMDgPXLQDwyfeOB/7kyxvuTbDfaGZtXb6pmzsn5e4z99br /68Z/vkA8PYSNSeZ7XqQzN5uotxuVy16LMvpRSJAHjk/tmVS1771ajlYx4wQ/heXtWPU v5Jg== X-Gm-Message-State: AOAM533Lz9+4Gh7qBf+9ZAo8QQzBeK259Ryh96T7OChvryMQ4B/hYBC0 gffI4zhjZZn9hs+9zBD5bXX75Q== X-Received: by 2002:a05:6512:260f:: with SMTP id bt15mr7472700lfb.134.1633656338589; Thu, 07 Oct 2021 18:25:38 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id s4sm112875ljp.115.2021.10.07.18.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 18:25:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 16/25] pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip Date: Fri, 8 Oct 2021 04:25:15 +0300 Message-Id: <20211008012524.481877-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> References: <20211008012524.481877-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org spmi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the spmi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 86 ++++++++++++++++++++----- 1 file changed, 69 insertions(+), 17 deletions(-) -- 2.30.2 diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index a9f994863126..b80723928b7e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -103,7 +103,6 @@ /** * struct pmic_mpp_pad - keep current MPP settings * @base: Address base in SPMI device. - * @irq: IRQ number which this MPP generate. * @is_enabled: Set to false when MPP should be put in high Z state. * @out_value: Cached pin output value. * @output_enabled: Set to true if MPP output logic is enabled. @@ -121,7 +120,6 @@ */ struct pmic_mpp_pad { u16 base; - int irq; bool is_enabled; bool out_value; bool output_enabled; @@ -143,6 +141,7 @@ struct pmic_mpp_state { struct regmap *map; struct pinctrl_dev *ctrl; struct gpio_chip chip; + struct irq_chip irq; }; static const struct pinconf_generic_params pmic_mpp_bindings[] = { @@ -622,16 +621,6 @@ static int pmic_mpp_of_xlate(struct gpio_chip *chip, return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; } -static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) -{ - struct pmic_mpp_state *state = gpiochip_get_data(chip); - struct pmic_mpp_pad *pad; - - pad = state->ctrl->desc->pins[pin].drv_data; - - return pad->irq; -} - static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct pmic_mpp_state *state = gpiochip_get_data(chip); @@ -651,7 +640,6 @@ static const struct gpio_chip pmic_mpp_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_mpp_of_xlate, - .to_irq = pmic_mpp_to_irq, .dbg_show = pmic_mpp_dbg_show, }; @@ -796,13 +784,53 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, return 0; } +static int pmic_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pmic_mpp_state *state = container_of(domain->host_data, + struct pmic_mpp_state, + chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PMIC_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pmic_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PMIC_MPP_PHYSICAL_OFFSET; +} + +static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; + + return 0; +} + static int pmic_mpp_probe(struct platform_device *pdev) { + struct irq_domain *parent_domain; + struct device_node *parent_node; struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pindesc; struct pinctrl_desc *pctrldesc; struct pmic_mpp_pad *pad, *pads; struct pmic_mpp_state *state; + struct gpio_irq_chip *girq; int ret, npins, i; u32 reg; @@ -857,10 +885,6 @@ static int pmic_mpp_probe(struct platform_device *pdev) pindesc->number = i; pindesc->name = pmic_mpp_groups[i]; - pad->irq = platform_get_irq(pdev, i); - if (pad->irq < 0) - return pad->irq; - pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; ret = pmic_mpp_populate(state, pad); @@ -880,6 +904,34 @@ static int pmic_mpp_probe(struct platform_device *pdev) if (IS_ERR(state->ctrl)) return PTR_ERR(state->ctrl); + parent_node = of_irq_find_parent(state->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + state->irq.name = "spmi-mpp", + state->irq.irq_ack = irq_chip_ack_parent, + state->irq.irq_mask = irq_chip_mask_parent, + state->irq.irq_unmask = irq_chip_unmask_parent, + state->irq.irq_set_type = irq_chip_set_type_parent, + state->irq.irq_set_wake = irq_chip_set_wake_parent, + state->irq.flags = IRQCHIP_MASK_ON_SUSPEND, + + girq = &state->chip.irq; + girq->chip = &state->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pmic_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_mpp_domain_translate; + ret = gpiochip_add_data(&state->chip, state); if (ret) { dev_err(state->dev, "can't add gpio chip\n"); From patchwork Fri Oct 8 01:25:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515544 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675396ime; Thu, 7 Oct 2021 18:26:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwrRibz+eZ92rPQqGeflDGm5xrW6pb+t3kOzn7oBCrhx14sDvzF6vQi/NrQ2YRmf+Kaz89T X-Received: by 2002:a17:90a:de16:: with SMTP id m22mr8589436pjv.54.1633656360851; Thu, 07 Oct 2021 18:26:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656360; 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The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8841.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.30.2 diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index b6066c27732c..2caf71eacb52 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -16,10 +16,8 @@ pm8841_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8841_mpps 0 0 4>; - interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, - <4 0xa1 0 IRQ_TYPE_NONE>, - <4 0xa2 0 IRQ_TYPE_NONE>, - <4 0xa3 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; temp-alarm@2400 { From patchwork Fri Oct 8 01:25:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515546 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1675433ime; Thu, 7 Oct 2021 18:26:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxx+RlHyqv2lD5DeC2gA9CCtpdkr+af0erQNb9QQIJeEffO7RqGQSqXIx4KqiZj9hIYEAIH X-Received: by 2002:aa7:83d1:0:b0:44c:654a:be1d with SMTP id j17-20020aa783d1000000b0044c654abe1dmr7222847pfn.68.1633656363961; Thu, 07 Oct 2021 18:26:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633656363; cv=none; d=google.com; s=arc-20160816; b=Dsg4jxcCn83h9j2sZ1Z6zozj/asqTX8PYxr+hXF8e1dybWUIg5k5qfz1LxReV4FG3h CPVOIwlTEIoZSdp2SgpzNuIoJtbEV0c51juyy/mt/N96j245UrSvzYSxfMEFgG10hLMG eV3fHAsAFGxSIbeEC9vE2teS8rd6gaJSLChgqKANpfTtWFlDHy3Hpm+Aluk2IOSq16Nm E/onVt/WM/rnLvMkwlmSbv5iMnovgpvklo9Jc08XDgm0iBjuqGyrTkUxQyATpgmFGYLC qJvj0o+CGTv+2V6J5OxvSFC0JY1rIe8dKLu0+rlRntHeTqSL1Jyh5RZmCpOemdECSxDp VcPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=b0AQXKDQSfjbcdAy/YvhgqCZpI+nhwsFNhGswrbVvuY=; b=yjwVHLLgiDTTAoVtQvi7lEphZdWGO90mYXc82/6qmkmiNtLstIuJGkomMDLaEs/CjW ZrMx7PDOBcJa1boUQlexFcgBVxiMjYXQSQtRnvj9djI46hsU6z4FiomhcK4yzTabnczq FmdIDLK+qWp4o2lxAJ0s8t7i6owTYhAN65lSwKGSu/j3qX6j5F6fjxnGJvTj6tMJXfcJ vlK414bjKK7VXicCRweHBqRhrET9axHWLHQq6v1nbosrN954tQ8vXcilqs9C0Qf0RCse 1VH4AF5T8CjUugB0CEHjG+Selq8GNjOjTMan9bM0Of9YbiNjqn1CqnYk/4vaCn6m6s+Z UNmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IqLbkhJJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-pm8941.dtsi | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) -- 2.30.2 diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index cf8daa2fe144..da00b8f5eecd 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -80,14 +80,8 @@ pm8941_mpps: mpps@a000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pm8941_mpps 0 0 8>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pm8941_temp: temp-alarm@2400 {