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[62.248.207.242]) by smtp.gmail.com with ESMTPSA id p9sm687138lfe.3.2021.10.11.02.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Oct 2021 02:48:26 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Andy Gross Cc: Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Thara Gopinath Subject: [PATCH] dts: qcom: msm8996: Add device tree entries to support crypto engine Date: Mon, 11 Oct 2021 12:48:22 +0300 Message-Id: <20211011094822.1580122-1-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The change adds description of Qualcomm crypto engine controller and BAM associated with it. The change is inspired by commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine.") While performance of cryptographic algorithms executed on QCE is lower than e.g. ones tinkered for ARM NEON, the offloaded execution would make sense: # cryptsetup benchmark | grep aes aes-cbc 128b 71.0 MiB/s 71.9 MiB/s aes-cbc 256b 62.4 MiB/s 62.4 MiB/s aes-xts 256b 70.7 MiB/s 70.8 MiB/s aes-xts 512b 62.0 MiB/s 63.3 MiB/s Signed-off-by: Vladimir Zapolskiy Cc: Thara Gopinath --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.33.0 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 52df22ab3f6a..a03cbeb58246 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -705,6 +705,28 @@ tsens1: thermal-sensor@4ad000 { #thermal-sensor-cells = <1>; }; + cryptobam: dma@644000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00644000 0x24000>; + interrupts = ; + clocks = <&gcc GCC_CE1_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely = <1>; + }; + + crypto: crypto@67a000 { + compatible = "qcom,crypto-v5.4"; + reg = <0x0067a000 0x6000>; + clocks = <&gcc GCC_CE1_AHB_CLK>, + <&gcc GCC_CE1_AXI_CLK>, + <&gcc GCC_CE1_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + }; + tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; reg = <0x00740000 0x40000>;