From patchwork Tue Oct 19 00:00:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515937 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp70586imp; Mon, 18 Oct 2021 17:06:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwisTiKFim8dyZRnIRCEBulSMpLbFjbRBx2q8hV9dhFmo1eWoY7BeteA6/RD74qhywYxhRv X-Received: by 2002:a05:6102:c0d:: with SMTP id x13mr9896473vss.54.1634602009655; Mon, 18 Oct 2021 17:06:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602009; cv=none; d=google.com; s=arc-20160816; b=jENZS3NaU2bHKvcsdWr5ZSnhOCqCxRP6p97WX4twY8B3ExSjohW14XKTH3gwdqvnxs jQKlGrDxrcpwc80TfnhlnsyVtHVFoOm5MDLFyrKglyXDMb86vAaM5fB14ePClr4huShQ eONxV1BKDwiwvu+5Vdaxbsq/FszbuoBQW5kxdWSE1wCpEyfgvRX+hfH60VdGUJgAnywh rOceGGOgwCXf4wODpyIxZfYl2peCYL64VXoV8QuU1Zv0MKct8zI8L/mRT50wwcC+Orol f9+jJOLCdeDXd+xl6eUio4NY6vJYqQeImVIyyYz/xN8qJRnPrjSiJZzafUSwRCxkpmDt v7eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=Bipwhp9Krm16LjUeGkPwJ8Um9jNSSpBwGWGDLBu3HIhBo7nspBi1aYdHH51HDYrd71 0AsmlGf992YoXl6oR4k9gUQ7xiWuV+vLbizl3v6ZFy3W1UvoXCp4/nvMkVawQx/1u4Ks 2z1w1HX5KGpPk/uGX2iGDfHtsiV4zLNpZ5M2o8DrL9UNO6Q9ynd2IWegnHQK06GnB4an +XcTqMutMi6XjS0ib7fNWYIVC1uLYXUg8DLQ4gfUpjuE5JAxC3y8WJ4sLsPsvMNzAO7o LYDkr3ewp26lIsrc79bkSSQDIH4gpVRRhG877eOiGpvkXsyOlS+2G/GFMXtNHAidKJbz gckQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lw+0xg2B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j13si4600339vkd.65.2021.10.18.17.06.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:06:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lw+0xg2B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcceX-0002cp-02 for patch@linaro.org; Mon, 18 Oct 2021 20:06:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZB-0004cq-FD for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:17 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:44974) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZ5-0001c1-Ld for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:16 -0400 Received: by mail-pj1-x1036.google.com with SMTP id oa12-20020a17090b1bcc00b0019f715462a8so1248284pjb.3 for ; Mon, 18 Oct 2021 17:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=Lw+0xg2BsoNfCVm3hNJS+cG2SBZjjs3TAxsdAXW1unLolldclQTMvVzXB7lhO+x587 zN4iCH1Xu1Cd+mnY86hukVpNLYwQKXZDy879SQdZVA/kq33U9X4H4H7xkxBlUeHLMMF5 BMioFc8dHY/DS8OrPd14jm/w6ubKHi6658p7rRLXkXXFa/BLo7Vf1nXZumAwIghiSyJI +YW2ldDOEJZFv/tVphPsIrKAdSGUWhAS+XlULINftazRmoKyoPb78AXxyOC3WgxlxRrH 2LjayybZwtiJ1Ug/5MDUYCQ8Vi/rAU90ztSE/PLDY+8FF+uDYajmG+iKC4WYpIoYveuN fCMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ur4NYkKvb4IwfCVRQ66xGSUcq2q0ktl5nOkYZP/fju8=; b=miKLNP6ws8+oDR/KjB6B+5NU/vXf/9MnC7iAElEPbkqDEAe7nqeSHmMXFTH/6cjZDt VCHk+2+Q/xMBKEPy+0+WnqE8xci4ayuoHrBZxlJ47mIX/fOiz4+amgur9sMEpbiAI5ei 9wKFvdK7VS/fZa1aXblHGQJLYmMRNm+AgSIfoIVj1m0sl1Pjiw2NYdlHEpcPaDbT9r02 DKu1PeeDRK1a99zHQZObd129Fhd+XCzmzn3BxqmjetOHe1Y9ba5fjWi/6Wt62EYtvglT NuLKFW/sQ2QOQ/nuMrjR8sGhC7FJ0rMpg0+o9B+DWw5lI4bclXopCMdLGnJmEALAEDe9 fexw== X-Gm-Message-State: AOAM533N99TuEo6XONqkE76OcPWndXuRBMmZd7nyZc9u5mQPwN+Gw+8i ymXjPcNtYir9rr2g1+8ATj2X0U1pKW0= X-Received: by 2002:a17:902:7616:b0:13f:354a:114f with SMTP id k22-20020a170902761600b0013f354a114fmr31104803pll.8.1634601670165; Mon, 18 Oct 2021 17:01:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Date: Mon, 18 Oct 2021 17:00:53 -0700 Message-Id: <20211019000108.3678724-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to cpu_helper.c, as it is large and growing. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 47 ++------------------------------------- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e55b2f5b1..7084efc452 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc; - *cs_base = 0; - - if (riscv_has_ext(env, RVV)) { - uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); - flags = FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); - flags = FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - } else { - flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; -#else - flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; - } - - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d41d5cd27c..14d1d3cb72 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc; + *cs_base = 0; + + if (riscv_has_ext(env, RVV)) { + uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + flags = FIELD_DP32(flags, TB_FLAGS, VILL, + FIELD_EX64(env->vtype, VTYPE, VILL)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, + FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + } else { + flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + flags |= TB_FLAGS_MSTATUS_FS; +#else + flags |= cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + flags |= env->mstatus & MSTATUS_FS; + } + + if (riscv_has_ext(env, RVH)) { + if (env->priv == PRV_M || + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, + get_field(env->mstatus_hs, MSTATUS_FS)); + } +#endif + + *pflags = flags; +} + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { From patchwork Tue Oct 19 00:00:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515933 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp67448imp; Mon, 18 Oct 2021 17:03:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyUHZv4amyoAs63nQt8DaaakwFLKmhSyP5ssfLLgjGgN13RWCIYLg8BDGKgUfVsGFWAc67T X-Received: by 2002:a05:6102:a35:: with SMTP id 21mr31210325vsb.32.1634601784669; Mon, 18 Oct 2021 17:03:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634601784; cv=none; d=google.com; s=arc-20160816; b=GAn27shxtE/AFRod/VuB5TuEEd/tW7TONdgvWV3bRRoaA52a0SRATjtUaFT5grmZHV 6EAnROHsh+MomNkSoN/1bJf+FjXCyvnvTCTLYIaUHoQV2t0CluU4hDxJqFDBDeXxFZmx /ZF5c7WTuRRlVo2G3+Iao9AwL2lt47HBTqtyiaxEHcEqzHKpLgAGVPgBcT2hXOBC6yE9 HmGv82QIFfI5BKHo4Y4LJHuySUy/jvlRS31J4JDh34jPh1JClQjWySUmYeOi4yd4GSwT 0aVmsZmC/NcYBSZjTLpLpfSKnZ9Zd9QfCDzOR05k7INcMs8HPGS8t/YoSfbnQ8wK0EUv XzOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JW/tzOqQKK5hRD4CRoj0kca6rOybKGXTUDDhLFOWwb8=; b=N48OxRYsRsxjyD9f3NI3cCaoSZaHhh5qKCwnTTLa9lQ/CjnlpLIXyZroLGuLk8BSZQ VFqqa8RsIbpMzdxqddaSwToWwbgEHsQnvnaqZQJou1vi46D6XekqNWM0PgGoenXFcWa7 gXkxx0Q/LyCRXUaVS1JqqsX87e0L4R+Q9qUkIxE4/Ta8zmaKDJAvk8Rf7mfy0WEjFlYs 1yn2LLGGWv8bybokqv8otbLHOiKsx9/ZTfqXYeO7X+H+65QaB1MVakEUVsoPww1Ojf+u x/JakhWqROPUQfeI+JsM3w6mx//phBP41MLbChMmQNzGiU42GattSmt2+b13ed1pdU/3 Psvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="rwAI9/EI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m25si11296462ual.102.2021.10.18.17.03.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:03:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="rwAI9/EI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccau-0004f2-1r for patch@linaro.org; Mon, 18 Oct 2021 20:03:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZB-0004ct-J5 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:17 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:38830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZ6-0001d3-FG for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:16 -0400 Received: by mail-pl1-x632.google.com with SMTP id i5so6175565pla.5 for ; Mon, 18 Oct 2021 17:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JW/tzOqQKK5hRD4CRoj0kca6rOybKGXTUDDhLFOWwb8=; b=rwAI9/EIpVqwgULEbFSMPpiM1lrpuntD/n+xTqIW6499dGzikZ2uzEdWrwbtdSk/uR NQW6psEvyT46J/G0pHyxxNf9lomJqZpwh/xlemFC7awfWV9WI9w+/BTgCedWVkB+tmY/ uRmhRIdAHEdSenzCqi2LJ/9ZyGHtcBIUsOzQgTJpIfR7taKBsUydzIqa6K0sao1uLkVb JIEYePKgxmz5BuQ0O72pC5UOnEHI7Jgg1Vd9FV6YcYRzzAjgdxs7fQeaKLdrpzIfaahF 2NMbS5UR8KkxKyXSPoZYhc28sY9f+q907JiZF+mXnRJBWCN5q5HSx69RgstOaiKmwbfJ x4nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JW/tzOqQKK5hRD4CRoj0kca6rOybKGXTUDDhLFOWwb8=; b=6vMdpJQ/LXBEPQAQWedbSdP6e+abb5iZEP/OY+/hwTsGOnkE2rZykRS0POZMcNQEKI l/hNhR9qhe8YxsDTf+qvTXukU/uiO+Bzt23OE0DqpKHXzdJfSlQps3F43wEC+rIXLsPN gD+dcjlca+A2st4DJDH62lfnixWF2n1glwvWqQPnXVz+WuTOsH73H1Pshrr9Iitoxt8q TBsRPXcqh2fkQNkNoreGKfyIyWAATE6yw2d1b/qRhquE0XwXtHb42q6IrG4TwtkueKPe OvlrYAZn8PMaRuDd3rRX96DC057LKCvIXZiZWoIXvpagOhgu0LGeOGPf0rwTJo3ocgh6 XKAg== X-Gm-Message-State: AOAM531HD61NqbozwnNn6fBWgiYq5EFphHFxmf34EghlX2z5Y8RUHEvP dvmDgUL5IB2FZ6yfCnlXzwOnWbLRV/Vq0Q== X-Received: by 2002:a17:90b:1e01:: with SMTP id pg1mr2363214pjb.81.1634601670806; Mon, 18 Oct 2021 17:01:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration Date: Mon, 18 Oct 2021 17:00:54 -0700 Message-Id: <20211019000108.3678724-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the MXL_RV* defines to enumerators. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu_bits.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a9ee..e248c6bf6d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -364,9 +364,11 @@ #define MISA32_MXL 0xC0000000 #define MISA64_MXL 0xC000000000000000ULL -#define MXL_RV32 1 -#define MXL_RV64 2 -#define MXL_RV128 3 +typedef enum { + MXL_RV32 = 1, + MXL_RV64 = 2, + MXL_RV128 = 3, +} RISCVMXL; /* sstatus CSR bits */ #define SSTATUS_UIE 0x00000001 From patchwork Tue Oct 19 00:00:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515935 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp67614imp; Mon, 18 Oct 2021 17:03:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhJY30jOkgipOLQx57/h9dFPs1BMGmgun0imc6a2F8gq9v6JzfOIGObU0vfZwVxX8RB0sq X-Received: by 2002:ab0:6c4b:: with SMTP id q11mr31850708uas.128.1634601795282; Mon, 18 Oct 2021 17:03:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634601795; cv=none; d=google.com; s=arc-20160816; b=BlP+wCItWvrkdIlYeD4bkHiQpoTh5QpWuW7V9R6AcfjjpsReoIHhk/alLYFIkCxcU0 nC5DvmJl9yC7kFXfh+v52wqZCAYpurq8deZhGHjZul7KwIgLs7XUyI3PGeZqUKXS2RdP i6ExJzbuCOdg8ltYNjnJ3ni5h4aUZDb95qPC+qWGnSv+MMJY3ct7Tgeif+8//j3RNJre reUA7aDt2BlwkS5xGks+wn9kJLlOXkxOgk6DThbgOa/Qr56a62jOmdt89JZ+BUnJYXUc fJFnvkF7uCM6iumoVzRO5Lod0BIMT7cL7/givIDl2UFbWU2UEJ07jn0UbhueB3NOJ78v bxUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=axUeM4wR3ZbiQZ9gN07cf/OmbYseQ9DiBDAnxCabNms=; b=HDVpX+KRzYXr3vs8kVi8A0fXcPK547S5yPDVI0Zm5j2SqWeb5LdkLEBZRzCbK/BX2E cp37JAIUEXgbpdxk9xPFQGgIjuBKpkBXkTyHWe+E+/PQdPkf6P7OPkhgWCwo03378qpG VBKwrgeiPqjiGgTz+Bc8ZvH0BZoed5VxZxlbY6vuWPkl6v9fuy4RRedeiIMJpTRx7bI/ JgrnLlCGIrMZv2VhERD3zepYy2ohWIRgjzNl/GTCzsPpwKIV+oBvWsBGm6BbUvXGWUZu nq9EP7TiOmilKIxgxI4CGgRbxEGiEcGt0IVMzmaktr2/AxHXCiuhS1JRY6KjIEoOOw4J o2tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aFzEHouC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f9si18469987uax.99.2021.10.18.17.03.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:03:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aFzEHouC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccb4-0005AD-J9 for patch@linaro.org; Mon, 18 Oct 2021 20:03:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43080) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZB-0004cs-J2 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:17 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:35411) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZ7-0001e7-8Z for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:17 -0400 Received: by mail-pl1-x633.google.com with SMTP id b14so2634299plg.2 for ; Mon, 18 Oct 2021 17:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=axUeM4wR3ZbiQZ9gN07cf/OmbYseQ9DiBDAnxCabNms=; b=aFzEHouCxEj85T69ULvc0piF0i29mwJqs2wx8yhzUXYfP3cbst9K+ykL2rhwfQ1DdU K0Rv/UJbItT5h9W+bVMLlI2EuT3mJsN1Q81H4ou1IrxxpWh6TntP4BOfaqls18Ur1L8j vEHn3j+PGEc7DhuYNWmYxP4HgjPfxPzM0Mjxct2ReJKImPYgHmUcU8stPlKwRCZtYEre F5uFB5TH79PA/cYXCGmeLxypUcsu953j2JQvaYUfp6CqdLL/GYeeHG1OWCw+MBVG2RjE 98xNSZxD3HXiscCxvXt610W9j/1vOqiLFCy/tr7LNBY/GAeSisuMwgoGLKZr+LHjZjHk ujPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=axUeM4wR3ZbiQZ9gN07cf/OmbYseQ9DiBDAnxCabNms=; b=hs1CCrvYnHyUwrukIrYT7eJNpu0+FvIusgtC01E46P5SIkBo8Ri+RXirXlWTgXJvzF IT3SzAGyY1wmq2wVXelrnNdhTHkwuOMCS2/ncJuxGQvwY0+4JhmW3tpTuMCev7LO4+u/ zI0TrPTRF8+jbQQxZh21B9kQNNO1VTMNt2snLhyCif+DZOC+q5+eBUPld0FRnJOdbYcg SKY0fIQ8j6WwmTNSMkUTyuPBVq1TElHOiMwyXqB3tQ4C8VGL6enRNX2vptGPFGnbMW1P fOvYbrDXwgHO4MiYm4X83kVb6N7o7Rqg4ugrDRMegbrJKBYvD//zc+HM8DQpQBZwnreF iZPg== X-Gm-Message-State: AOAM532dldqx8Bd3AzPaq9qlrEHXFQQNpy/u6tZHue1BNgOKyN5ffv4q N2/5P7js+Ype6x4Uo29CiFxzLIG1qMWuIw== X-Received: by 2002:a17:902:8504:b0:13f:7f2f:502 with SMTP id bj4-20020a170902850400b0013f7f2f0502mr28192765plb.65.1634601671450; Mon, 18 Oct 2021 17:01:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext Date: Mon, 18 Oct 2021 17:00:55 -0700 Message-Id: <20211019000108.3678724-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 15 +++---- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu.c | 78 +++++++++++++++++++++---------------- target/riscv/csr.c | 44 ++++++++++++++------- target/riscv/gdbstub.c | 8 ++-- target/riscv/machine.c | 10 +++-- target/riscv/translate.c | 10 +++-- 8 files changed, 100 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7084efc452..e708fcc168 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#include "cpu_bits.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -51,9 +52,6 @@ # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') @@ -133,8 +131,12 @@ struct CPURISCVState { target_ulong priv_ver; target_ulong bext_ver; target_ulong vext_ver; - target_ulong misa; - target_ulong misa_mask; + + /* RISCVMXL, but uint32_t for vmstate migration */ + uint32_t misa_mxl; /* current mxl */ + uint32_t misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; /* current extensions */ + uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t features; @@ -313,7 +315,7 @@ struct RISCVCPU { static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { - return (env->misa & ext) != 0; + return (env->misa_ext & ext) != 0; } static inline bool riscv_feature(CPURISCVState *env, int feature) @@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) } #include "cpu_user.h" -#include "cpu_bits.h" extern const char * const riscv_int_regnames[]; extern const char * const riscv_fpr_regnames[]; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2404d482ba..214c1aa40d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void) uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); - return cpu->env.misa & mask; + return cpu->env.misa_ext & mask; #undef MISA_BIT } diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9859a366e4..e5bb6d908a 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->gpr[xSP] = regs->sp; env->elf_flags = info->elf_flags; - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); exit(EXIT_FAILURE); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..fdf031a394 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) bool riscv_cpu_is_32bit(CPURISCVState *env) { - if (env->misa & RV64) { - return false; - } - - return true; + return env->misa_mxl == MXL_RV32; } -static void set_misa(CPURISCVState *env, target_ulong misa) +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { - env->misa_mask = env->misa = misa; + env->misa_mxl_max = env->misa_mxl = mxl; + env->misa_ext_mask = env->misa_ext = ext; } static void set_priv_version(CPURISCVState *env, int priv_ver) @@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; #if defined(TARGET_RISCV32) - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_11_0); } @@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV64); + set_misa(env, MXL_RV64, 0); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv64_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, RV32); + set_misa(env, MXL_RV32, 0); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } static void rv32_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); @@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj) static void rv32_imafcu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); @@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev) mcc->parent_reset(dev); #ifndef CONFIG_USER_ONLY + env->misa_mxl = env->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause = 0; @@ -388,7 +386,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = 0; - target_ulong target_misa = env->misa; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -434,8 +431,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_resetvec(env, cpu->cfg.resetvec); - /* If only XLEN is set for misa, then set misa from properties */ - if (env->misa == RV32 || env->misa == RV64) { + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + break; +#endif + case MXL_RV32: + break; + default: + g_assert_not_reached(); + } + assert(env->misa_mxl_max == env->misa_mxl); + + /* If only MISA_EXT is unset for misa, then set it from properties */ + if (env->misa_ext == 0) { + uint32_t ext = 0; + /* Do some ISA extension error checking */ if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, @@ -462,38 +474,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { - target_misa |= RVI; + ext |= RVI; } if (cpu->cfg.ext_e) { - target_misa |= RVE; + ext |= RVE; } if (cpu->cfg.ext_m) { - target_misa |= RVM; + ext |= RVM; } if (cpu->cfg.ext_a) { - target_misa |= RVA; + ext |= RVA; } if (cpu->cfg.ext_f) { - target_misa |= RVF; + ext |= RVF; } if (cpu->cfg.ext_d) { - target_misa |= RVD; + ext |= RVD; } if (cpu->cfg.ext_c) { - target_misa |= RVC; + ext |= RVC; } if (cpu->cfg.ext_s) { - target_misa |= RVS; + ext |= RVS; } if (cpu->cfg.ext_u) { - target_misa |= RVU; + ext |= RVU; } if (cpu->cfg.ext_h) { - target_misa |= RVH; + ext |= RVH; } if (cpu->cfg.ext_v) { int vext_version = VEXT_VERSION_0_07_1; - target_misa |= RVV; + ext |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -532,7 +544,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_vext_version(env, vext_version); } - set_misa(env, target_misa); + set_misa(env, env->misa_mxl, ext); } riscv_cpu_register_gdb_regs_for_features(cs); @@ -705,7 +717,7 @@ char *riscv_isa_string(RISCVCPU *cpu) char *isa_str = g_new(char, maxlen); char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa & RV(riscv_exts[i])) { + if (cpu->env.misa_ext & RV(riscv_exts[i])) { *p++ = qemu_tolower(riscv_exts[i]); } } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 23fbbd3216..d0c86a300d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) /* loose check condition for fcsr in vector extension */ - if ((csrno == CSR_FCSR) && (env->misa & RVV)) { + if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { return RISCV_EXCP_NONE; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { @@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { - if (env->misa & RVV) { + if (env->misa_ext & RVV) { return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; @@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, static RISCVException read_misa(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->misa; + target_ulong misa; + + switch (env->misa_mxl) { + case MXL_RV32: + misa = (target_ulong)MXL_RV32 << 30; + break; +#ifdef TARGET_RISCV64 + case MXL_RV64: + misa = (target_ulong)MXL_RV64 << 62; + break; +#endif + default: + g_assert_not_reached(); + } + + *val = misa | env->misa_ext; return RISCV_EXCP_NONE; } @@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + /* + * misa.MXL writes are not supported by QEMU. + * Drop writes to those bits. + */ + /* Mask extensions that are not supported by this hart */ - val &= env->misa_mask; + val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); @@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= ~RVC; } - /* misa.MXL writes are not supported by QEMU */ - if (riscv_cpu_is_32bit(env)) { - val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); - } else { - val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + /* If nothing changed, do nothing. */ + if (val == env->misa_ext) { + return RISCV_EXCP_NONE; } /* flush translation cache */ - if (val != env->misa) { - tb_flush(env_cpu(env)); - } - - env->misa = val; - + tb_flush(env_cpu(env)); + env->misa_ext = val; return RISCV_EXCP_NONE; } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a7a9c0b1fe..5257df0217 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) { if (n < 32) { - if (env->misa & RVD) { + if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); } - if (env->misa & RVF) { + if (env->misa_ext & RVF) { return gdb_get_reg32(buf, env->fpr[n]); } /* there is hole between ft11 and fflags in fpu.xml */ @@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (env->misa & RVD) { + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-64bit-fpu.xml", 0); - } else if (env->misa & RVF) { + } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 16a08302da..f64b2a96c1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), - VMSTATE_UINTTL(env.misa, RISCVCPU), - VMSTATE_UINTTL(env.misa_mask, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl, RISCVCPU), + VMSTATE_UINT32(env.misa_ext, RISCVCPU), + VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6d7fbca1fa..66857732e8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,7 +55,8 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - target_ulong misa; + RISCVMXL xl; + uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; uint32_t mstatus_hs_fs; @@ -86,7 +87,7 @@ typedef struct DisasContext { static inline bool has_ext(DisasContext *ctx, uint32_t ext) { - return ctx->misa & ext; + return ctx->misa_ext & ext; } #ifdef TARGET_RISCV32 @@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) #else static inline bool is_32bit(DisasContext *ctx) { - return (ctx->misa & RV32) == RV32; + return ctx->xl == MXL_RV32; } #endif @@ -513,7 +514,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->misa = env->misa; + ctx->xl = env->misa_mxl; + ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->vlen = cpu->cfg.vlen; From patchwork Tue Oct 19 00:00:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515938 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp70661imp; Mon, 18 Oct 2021 17:06:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyKROjABIQ7Z/3R+cWuxhY3uX9tusNfqjn0WFOpyqvz9HU73Y1JLNYFTh3DeiNvCQXnrAF1 X-Received: by 2002:a05:6102:6d1:: with SMTP id m17mr13891055vsg.48.1634602015589; Mon, 18 Oct 2021 17:06:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602015; cv=none; d=google.com; s=arc-20160816; b=xLCEAMXhSYRx2OJt7rf0LC6Td8W41jrQVPDh/Q0ZrzLf+0iZ1s8sLvDakSGPLCpFNc LxS+56Y6qZGBbmuEHSP/eT42Cvz6tFN5liXJiZCsH82uK6W3D4Ll3c82jWy6Sx1d5nv5 2IRLOcQ8Lc7KSBcTL1SgjFCQba+B8nEbeyByg9NWEhRQotZmJysvwOJCY2XZOes75U3+ Fg/iZ1ChczYXxRnspch7fq9ktRVyJh1iO2hwbzX2w1ibKDvZrFCYqRSnJIpO/1RYrIwo OQ2ugSC4ZCaCGpYKAO0e66Ex0RbrTbXIwD+Y7wR/h52KlYgsY8CYtDaEtGPMYM0M/kAI ZTbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X6q/MRbAFAFtB483mpgrCV5jJyP32WJZt950gYxzILo=; b=MX3VHsWdRpNNCXCddggAy7STavT0BDVXo/t/KUm9wpkR1A7YoeIvvAmLdVM89I04zI X2TXVZZbCICO8ehKhqoFDCHXcJA1UJ1YxbRMZO/VnTvx6grzQOFWOXuuZhfsltWp+6TK D0w1zWntwyrJp+hV43sfemGh1Ai12SiMd8a0DOerXsBi/EBsGdayYU4FRAFh/bgbU7A7 hLEBCp6qv79eiP1KBvHTlYiH5+W+Hc8e49fHQf0TbzaPLGDn8HRvBd19wZMIdNMfdIZE +lIXyDNq1Hf2jzz40WTTmVcJ1MTLW2A4RIUgji1qyBRZJfJ7byUa8ffz8TSec0WrjeSY OxAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D9SMLCQk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n19si6570034vsp.32.2021.10.18.17.06.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:06:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D9SMLCQk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccec-0002os-RY for patch@linaro.org; Mon, 18 Oct 2021 20:06:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZI-0004r1-EJ for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:29 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:44027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZA-0001eq-W7 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:23 -0400 Received: by mail-pl1-x62e.google.com with SMTP id y1so12402463plk.10 for ; Mon, 18 Oct 2021 17:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X6q/MRbAFAFtB483mpgrCV5jJyP32WJZt950gYxzILo=; b=D9SMLCQk4xys5O2tx8HEYrtQcmzmLTgdrni+qaPj5G9W9zsIn6aWC5hsqpMWryHAAd rwszmVwzaa+t6ruxxOVZWe2Gyz7sBJrix0itmMKNEhyDAnrpC8nSMmDK0+o8jsYG0Itq 0gCLvnHtPqnHXtXdXllv2ykX5t11Os1HPISaerfaGvvs5H5lqAMofrx7cYq+X8FkOuV4 X/JVRK7+solem5rXdFLcwOzAlxZP/IJPbVxqio8lVgpWRnbtJBB+BFO/xGP0sgviM+eE HAQ87iGpkVN5e55Thv1+luGMldQ3xZqrVZihNOFx4j08A3t7Z32HRsiK7W7soDbkUZp3 +Nug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X6q/MRbAFAFtB483mpgrCV5jJyP32WJZt950gYxzILo=; b=MLRgryIQRSyIrLRUey5D1dwjI9c61APA2sZCYBxPYu/2ym8jgMzb8NSg8LuT9JhXhO dK8OB0/h0ltHfjFPK3mkZU8yyBWYA5AzpxkBwb+PxyafspcdZOqCkhVz+62LyiJJGjtW cXD/QOfa4mvMaEQnuQVqdAcQ4r9my1NiaT0RJoeiG2u+i2NkJrKJ6MV61+HhKIeDunIK RkkhfBOD7iuV6+3XUPTxK9cVDeV1FmLkYMzy+uThbPoQI1us/ocb0CT8fPUNCQks20n1 vGhcshhkbeJ1q7thyQSLYQznHVK8f8jbJ5+8jXzryfzJ5L6BoLw2fQfi6zzwzTX3lSzq bGBg== X-Gm-Message-State: AOAM532c3Cqf0w2bhT0GQMc3vXmYLFTYz6NrQW6C8PEQdLdxK2/bfaFQ Ri0rtNo3EiJaOPN73+rdB8qt1yimxFqQEQ== X-Received: by 2002:a17:90a:384a:: with SMTP id l10mr2362607pjf.168.1634601672258; Mon, 18 Oct 2021 17:01:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Date: Mon, 18 Oct 2021 17:00:56 -0700 Message-Id: <20211019000108.3678724-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 9 ++++++++- hw/riscv/boot.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 24 ++++++++++++++---------- target/riscv/cpu_helper.c | 12 ++++++------ target/riscv/csr.c | 24 ++++++++++++------------ target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 4 ++-- 8 files changed, 45 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e708fcc168..d0e82135a9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1) FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) -bool riscv_cpu_is_32bit(CPURISCVState *env); +#ifdef TARGET_RISCV32 +#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +{ + return env->misa_mxl; +} +#endif /* * A simplification for VLMAX diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 993bf89064..d1ffc7b56c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -35,7 +35,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { - return riscv_cpu_is_32bit(&harts->harts[0].env); + return harts->harts[0].env.misa_mxl_max == MXL_RV32; } target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 01badea99c..37963becae 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) #if defined(TARGET_ARM) return is_a64(env); #elif defined(TARGET_RISCV) - return !riscv_cpu_is_32bit(env); + return riscv_cpu_mxl(env) != MXL_RV32; #else #error un-handled architecture #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fdf031a394..1857670a69 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - return env->misa_mxl == MXL_RV32; -} - static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max = env->misa_mxl = mxl; @@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", (target_ulong)(env->mstatus >> 32)); } @@ -372,10 +367,16 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: info->print_insn = print_insn_riscv32; - } else { + break; + case MXL_RV64: info->print_insn = print_insn_riscv64; + break; + default: + g_assert_not_reached(); } } @@ -631,10 +632,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (riscv_cpu_is_32bit(env)) { + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: return g_strdup("riscv:rv32"); - } else { + case MXL_RV64: return g_strdup("riscv:rv64"); + default: + g_assert_not_reached(); } } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 14d1d3cb72..403f54171d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; + uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | MSTATUS64_UXL | sd; @@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, if (first_stage == true) { if (use_background) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->vsatp, SATP32_MODE); } else { @@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, vm = get_field(env->vsatp, SATP64_MODE); } } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 0; } else { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; vm = get_field(env->hgatp, SATP32_MODE); } else { @@ -558,7 +558,7 @@ restart: } target_ulong pte; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { pte = address_space_ldl(cs->as, pte_addr, attrs, &res); } else { pte = address_space_ldq(cs->as, pte_addr, attrs, &res); @@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, int page_fault_exceptions, vm; uint64_t stap_mode; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { stap_mode = SATP32_MODE; } else { stap_mode = SATP64_MODE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d0c86a300d..9c0753bc8b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) static RISCVException ctr32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno) static RISCVException any32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; } @@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { if (riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { @@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static int validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; } else { return valid_vm_1_10_64[vm & 0xf]; @@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); @@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { mask |= SSTATUS32_SD; } else { mask |= SSTATUS64_SD; @@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { vm = validate_vm(env, get_field(val, SATP32_MODE)); mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); asid = (val ^ env->satp) & SATP32_ASID; @@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->hstatus; - if (!riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) != MXL_RV32) { /* We only support 64-bit VSXL */ *val = set_field(*val, HSTATUS_VSXL, 2); } @@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus = val; - if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); } if (get_field(val, HSTATUS_VSBE) != 0) { @@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, return RISCV_EXCP_ILLEGAL_INST; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); } else { env->htimedelta = val; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5257df0217..23429179e2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64; + int bitsize = 16 << env->misa_mxl_max; int i; g_string_printf(s, ""); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index f7e6ea72b3..7efb4b62c1 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env) target_ulong last_size; int last_attr; - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; vm = get_field(env->satp, SATP32_MODE); } else { @@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (riscv_cpu_is_32bit(env)) { + if (riscv_cpu_mxl(env) == MXL_RV32) { if (!(env->satp & SATP32_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; From patchwork Tue Oct 19 00:00:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515939 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp70712imp; Mon, 18 Oct 2021 17:07:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZaHyOQiqjH6bUAyvg79aO1wBFaMlt3po55qbY8e43PvDM9GbStgOaa9so0vvg1DRFmm8w X-Received: by 2002:ab0:72d5:: with SMTP id g21mr29244637uap.102.1634602020367; Mon, 18 Oct 2021 17:07:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602020; cv=none; d=google.com; s=arc-20160816; b=Ux7yMDijf+4KnMl7TBqLUZLumVoWivgr1YzZTcTN7RsWj69ANaMdAOtenVcwzVj+N5 P2L4xI/UG1I+S6KvxQ1F7MwQD85ADyrpdowQUBjHZ+iYncAfmrWi5yJe3lhBuZNPi9G5 7C2nmKqyb4cDlyDnxoJ3/s4K8/EnEB/9Aoz6Debmtl3DBhGr2nrEfugG6D5iUXpPaHd7 nuZsBso2bXRX2gVsXNEPN1BbaMlRfOh17A6jym+VY1dU1gis+O7ntM5ccLLpnUzNONTs UbUCL5TQ0F4X49JDhTzJ9sfuEaZgtuH3AIF9lvBy+ZltdfjyYFYKjQimRlT0Umt5ArRu 7j2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JntjpE4dbZf2jEil4I0MzTIE4C49WVyfW1GrdUDx7w8=; b=pn4MIKyV3ol62D+3NSFcA91RNPiKx6NKTxRiwZhCtpdKkyC55ThyvCPusRtJpzusCK GT24nA5pjuUGO+1IAfqOopa7YaeA2DZFIBatiSLn325R3QPRndF6LAGcQDUEjC/2rJEG xh9mGWecEZnoJQ9erWEuJusM0QZe9hd9+TWDcNQ1QWyS8aE+Gys+Gnb0+KJv6Nzr0KPY Eef78tV9jRsutZH2liHOmFhHe1QPe08aVmjZKZNMzK49PswOnhoSVe/WYIz2t01EE0gt STgvueGuYvjNtTygNVhvfPOJr1ilfuEvKBi7UE32ijHr6VeWP4p27IhhhbNy4bFaUPQ/ 5QXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EpEJvLj0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h22si9432110vsl.360.2021.10.18.17.07.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:07:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EpEJvLj0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcceh-00039i-Ol for patch@linaro.org; Mon, 18 Oct 2021 20:06:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZF-0004ju-6I for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:21 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:33513) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZA-0001ez-VD for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:20 -0400 Received: by mail-pj1-x1032.google.com with SMTP id q10-20020a17090a1b0a00b001a076a59640so882617pjq.0 for ; Mon, 18 Oct 2021 17:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JntjpE4dbZf2jEil4I0MzTIE4C49WVyfW1GrdUDx7w8=; b=EpEJvLj0PD95egCk2WB4x+DM4vQTtGq5QrMQmZ6G8gXWA7PcosXEFHw/exDVEJhkJ+ HLgwgoJ8RSeAU+wrg16xhBLLLg6k0b6xP6YpKKAJVWuigND2ROGOmLfgOrSaJnW1ojNo Mj2zCQbHTDPMwOUln1ecCLo29g0kc3aaQjlURdbdwZh7p4hD6GwsdRvv+dHKCP/uVLXo w2A082Wq0eREGtevdTkap34cYsMyRdzxSYDpvJHNZclPLe5aBTldfua2dvu+J9e5jphk N7jTYQNxrdOZ+ZrWfUdivst3b4nnkg/7pNr9bWCqlYS1EzrH6FzhbPQuP5na1HGdXZ3G jaEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JntjpE4dbZf2jEil4I0MzTIE4C49WVyfW1GrdUDx7w8=; b=1YygYfEq4iuWR2ZFbsDFFEPvXFHKMryKR4G5lD0e3N6mV26cqsaJOY0wTTAXYkxVwD KzyIusDzqB7L/dbtm2zN44sjMXmHCSTwdWRmVlWd0EVR6TRPfvsuS8L/uqp043Mm/qsZ z/fSDm8MOk4kjWBKOu/tlGkeft1qCHk80c5QkkA/w/vLfyvD786r4LmWz8pqKZ7tZ/lx VJYmVYQfAWmWAzb86HgTlZvrR1SXM57M3p5dW2ipwWtiQRh8j4WMR8NwDncDWT4LJjqQ 8lkPH/pDyulDTZ8ntrb1KeX9xSJtoNb5MoKrUG5gvp40x9E0FY4X9tHhvy8itQqSdxoP 8tTQ== X-Gm-Message-State: AOAM532Y+ELWktpRu8EFHXLAYsTEiE/xflbqjvjMcexVXIoVRv8kIuPS +G/0TlZXq5OYQec2JS7ETwqZR7Qze/vvPw== X-Received: by 2002:a17:90b:120c:: with SMTP id gl12mr2443975pjb.50.1634601672944; Mon, 18 Oct 2021 17:01:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Date: Mon, 18 Oct 2021 17:00:57 -0700 Message-Id: <20211019000108.3678724-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++ target/riscv/csr.c | 3 +++ target/riscv/translate.c | 2 +- 5 files changed, 47 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e82135a9..c24bc9a039 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ +FIELD(TB_FLAGS, XL, 12, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1857670a69..4e1920d5f0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev) env->misa_mxl = env->misa_mxl_max; env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); + if (env->misa_mxl > MXL_RV32) { + /* + * The reset status of SXL/UXL is undefined, but mstatus is WARL + * and we must ensure that the value after init is valid for read. + */ + env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); + env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); + } env->mcause = 0; env->pc = env->resetvec; env->two_stage_lookup = false; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 403f54171d..429afd1f48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +static RISCVMXL cpu_get_xl(CPURISCVState *env) +{ +#if defined(TARGET_RISCV32) + return MXL_RV32; +#elif defined(CONFIG_USER_ONLY) + return MXL_RV64; +#else + RISCVMXL xl = riscv_cpu_mxl(env); + + /* + * When emulating a 32-bit-only cpu, use RV32. + * When emulating a 64-bit cpu, and MXL has been reduced to RV32, + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened + * back to RV64 for lower privs. + */ + if (xl != MXL_RV32) { + switch (env->priv) { + case PRV_M: + break; + case PRV_U: + xl = get_field(env->mstatus, MSTATUS64_UXL); + break; + default: /* PRV_S | PRV_H */ + xl = get_field(env->mstatus, MSTATUS64_SXL); + break; + } + } + return xl; +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #endif + flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + *pflags = flags; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9c0753bc8b..c4a479ddd2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = set_field(mstatus, MSTATUS32_SD, dirty); } else { mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + /* SXL and UXL fields are for now read only */ + mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); + mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus = mstatus; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 66857732e8..f7634c175a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -514,7 +514,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->virt_enabled = false; #endif - ctx->xl = env->misa_mxl; ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; @@ -526,6 +525,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; ctx->w = false; ctx->ntemp = 0; From patchwork Tue Oct 19 00:00:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515943 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp72215imp; Mon, 18 Oct 2021 17:09:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyaSVCcf9w/DlCqcwFHl0YJG4e5x85ltaafmsse3tWi5rliiBfuHzpS+TWXjCuXiOgJpzw X-Received: by 2002:ab0:812:: with SMTP id a18mr28934020uaf.33.1634602148552; Mon, 18 Oct 2021 17:09:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602148; cv=none; d=google.com; s=arc-20160816; b=XSw+xcUW1cYEgqzDKCOazHExjGfzHmifp/gg7PFI04SdI/wZxHe8jaNjhOcjSxfDo3 ZndDGy4upaVlDadS1l1xp3AYYuYMFJcw0FV3cKI26K4z767ua4w9kB0alumSZEkDv/Cl g/s8qi4VADu+bzmYBOd5mhE/pw1dvP4YX003w91LEG6c/hz6NOovjAQxBNgHEAlmNJVU i7Wzl/Ljg7YB8KZNa0R6OqePnje/X/VTttQIxM3eOvqRUZ3hbENFiD+YvqeQft6tPe9g wrg2okbx43GnwtOzJ4KBip3pa0IUkoFECshV8Vgm/OVSrI8QNBtKwRE2nDJzFVEiSAWC otog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bokkmTqu3PPB9lUNeGMuiR/uQoelWheprwGuLtvEEIw=; b=RanevYpVgaa78bqNH2D8d+QTK3UhVBGUqZQ/OIgLziZrunlvj4rv33yhqsS8Y/v2RG 3kg+koN1rHkzjEbgJVpJ0cWrjeyXOjhe8noVti14YBDggTdHZvTC4NgvWwNy2w9+Y/sd Ij2ZZK+wpMMyCKr3a8m0IFYTnEYBzbMd/C7grVdL+EF359Wi6ZqjAy1yQZlv0auEOyj8 STmjB7rCZOzhqHDo48oMHqCAgOCvBpRlu/fiAPt+LcTPEsH46g+IVqNBiZXO02xKN8r8 147tckog4aqBGfa2CN+9GQnH7x3RzUTdDk3xXMNH+dpr+R57nGp7Ue0UAwCQ8AbFU3xk +yug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OUiOPg4+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o13si5422525uar.208.2021.10.18.17.09.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:09:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OUiOPg4+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccgl-0000js-Vq for patch@linaro.org; Mon, 18 Oct 2021 20:09:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZF-0004k0-7p for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:21 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:53198) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZA-0001fg-V8 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:20 -0400 Received: by mail-pj1-x1035.google.com with SMTP id oa4so13360944pjb.2 for ; Mon, 18 Oct 2021 17:01:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bokkmTqu3PPB9lUNeGMuiR/uQoelWheprwGuLtvEEIw=; b=OUiOPg4+zVJ2nH/6xLZiBrwgcE/K7PCJ037FJdmrKuEU4EkRqlM+FQprzhR5xZ3QpL uiGAH29PTfcLMkMtLVTZBBdF08i242pRM+eE7hIel4fX7rjBFoJXuZOtvPsQBT7z/eVr 1QgjDRfDWMNolkd3HEtlrfnSw1XyCZMocyW9hF0iptDu1K9L+bdiiE+3r10RvH+Q0qzA XIeKvsbnHIlYHUW48JtRGoJqeq8Gei6vz/rGAMDccQvaDtNNs29wIkmbAUxKUmjAT7dC OAwLBKukrF1lHzvFa4vqzqijqoTTd6DyiEavQ2xoU4l5wDP1YEoN3tmcZKOwCjMpJLuN pL/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bokkmTqu3PPB9lUNeGMuiR/uQoelWheprwGuLtvEEIw=; b=oKHiGj/fZjFgmuQKYq8isPxFUW4UtnCw/6/+GFADAzEN3n1nBsW222OFMQmeefpdv0 RoH0xvL4lLTHhlmcLkso8l0Ugwx54ih+/6IP/NXs/N7DNcyDwMxKrRMYYCBHfZvSAITn 3CbDbw3llg4pZEqYbCCnV3Ekw1q2+7OHL39Wb2bOOW/2WaA4dXTkS00ZCn9KMp71KzPj ykQ+85norVz+s0LXyWTG1LAy+PN30Hyg77i7h8OFVRvo3X1hCPCftoTcCLwvvg7tMozP lqLjQWAAIiMMdzA5oFp8TqFginV4TWdzxAweUuGoeGLo0t3qlEqzRL4Q56SwHTmW9iPK 3P1A== X-Gm-Message-State: AOAM533v2Ti8ar1AiREfkAxYKbrUdp5RhsrxO1C732IAjgFVs+LV6xbU 5AvI/mOA36VheNsMb6BFHE8l6iiDTu40+g== X-Received: by 2002:a17:90b:1b42:: with SMTP id nv2mr2370959pjb.91.1634601673688; Mon, 18 Oct 2021 17:01:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 Date: Mon, 18 Oct 2021 17:00:58 -0700 Message-Id: <20211019000108.3678724-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the same REQUIRE_64BIT check that we use elsewhere, rather than open-coding the use of is_32bit. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 081a5ca34d..d60279b295 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) static bool amo_check64(DisasContext *s, arg_rwdvm* a) { - return !is_32bit(s) && amo_check(s, a); + REQUIRE_64BIT(s); + return amo_check(s, a); } GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) From patchwork Tue Oct 19 00:00:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515934 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp67593imp; Mon, 18 Oct 2021 17:03:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytfY6p+8iohORLImtY0FjBj79Fl7xFU9XiWURPaAKC5Ch4Gd85b4kGgkdYUHnbb3Her5gp X-Received: by 2002:a67:c30b:: with SMTP id r11mr32204240vsj.20.1634601794331; Mon, 18 Oct 2021 17:03:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634601794; cv=none; d=google.com; s=arc-20160816; b=0yiXVVKS2CthwoezqsJdXhHITXb8no5eIbce1bfDMWjVWF2IEGbJqUEub07kL6sXwc kmz4hX9FSIo1HWQvhcReCSq4i9OsFN14nGHfoDY9iCnQOgl1U1Yl7sH4F7DQOtYDPnWK R8OgNQVrMFBONUwW/QB+2pGCYfrkyBek9W+TmZy+b3Bu8bcvQEZGD+fTc2TuCKYGyFbm 9rqhHIKrHOa53LlkdcYh0GZA+JPWU2aux/MFECQ/VOXnC4djwoRCGTNEaLJEyPdqvfhh TPPj4dQQOcRfId0iGiPFnVL9POBNaWvozCG/awrz6hoqke1SVWyJDMI0fa+eFMX6dpVO MCYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mfu2QZ3gpRQ8C8fsN7554x8wxijvHESDqJdXEHq27p8=; b=FI60QNbst0aIGArC5oEgSQRo5CRH4sPUUEBhsnSlXKTSqvuCC1fK/PoPKcpGXrjh+A azFIfqm5OWIL9VNJhNyZaEW17JX98GaK+3r0msOO+BGc/hMxZAPYRrzsudc7IKpDtrkO 01XCYUnQmT7FSoI/pTK/VbsFJVSVVsdi7miqWQq29Dsl7SfMmUwD4/+5mkyPTFk8UKZF 8gJ9QKw9bbseGSVj1A++7URpEefTbX4bTcCcSCjyU/W/Vw5eWvOgPIQpPFT4LTUZO432 UGV0udv1NPdPW8Rmg8DmWBu2Z2nqWto0RY0DZp/SlETTFZK3gYU3+3FBbbkZ7NAuacoi VfVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pF9qsYkm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w5si3130561uaq.76.2021.10.18.17.03.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:03:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pF9qsYkm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccb3-0005D4-NR for patch@linaro.org; Mon, 18 Oct 2021 20:03:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZG-0004oT-Hb for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:22 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:38881) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZB-0001hf-06 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:22 -0400 Received: by mail-pj1-x102a.google.com with SMTP id g13-20020a17090a3c8d00b00196286963b9so638245pjc.3 for ; Mon, 18 Oct 2021 17:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mfu2QZ3gpRQ8C8fsN7554x8wxijvHESDqJdXEHq27p8=; b=pF9qsYkm+jAYNkcC5qyBCtWEvJLsIEptPifDCNVETkymDhzKKQu3ai6+bw1vQ8IyDx ytwwP9/oNEC5pWbhUBSDYH8b3/+yNQ6MLcnBeCoku6iZO2xWO8jDIoFYY6fVMhViGlTH D4UhqsTfV+u1hf6v3IUQe6vHCXPZ9F1USYnN3Pv9xp3PJ4q+gvps4eIQK0i16HD2WG3J GwW14jPeoqA/a9XtigxZs+wnu6xW56F1o+OPsGtjN6uUHkwqcuoo5bf4/0gFdPfiiq+i +PleDMH23DYYo6OcvL2Vo1RE34tmVOVShg+pcz1wSeKm0yXZHhdTCw7wif1PiZw48hBH OUwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mfu2QZ3gpRQ8C8fsN7554x8wxijvHESDqJdXEHq27p8=; b=JV8MzDEfxuJQ0/foU7TP1cclvE5N+aI/D3F9kEmmg4Sek+Prlui/SZMTQdzZ+1MCTn yNp98zU7QX35cySoRcS+kPwobfRZuS6tkV43j3anMLRVOUAffQuRjF8Ej4v6RKgATT3s BffyDNNzq1Jg1J46l1eoKpLW0itHlLrjYP+qTgdcziMl+tJizpL3LWyawKLCA7/yY4Pp KvOHDt32iy8K2/ocRalgWpMzmKVMDdRRZPIPuVer5eHjOX5h4ad+cEe2yZ8v6T/xwfFo YO2p4e+Qifdv1INEfYfgG4UkquoyarQdqlaY0P5GnxzioVcQEwiHDIK0AIMQGEgBj5lx xDuQ== X-Gm-Message-State: AOAM53178FpKggrj99QsuVdoWaJ7Bhx1Bqy2pDi+MKLKFq23ARYP+XFK Dlg3V/xuus0pIDtd/HvvKXZpg3avKYAUXg== X-Received: by 2002:a17:90a:c795:: with SMTP id gn21mr2402194pjb.112.1634601674755; Mon, 18 Oct 2021 17:01:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op Date: Mon, 18 Oct 2021 17:00:59 -0700 Message-Id: <20211019000108.3678724-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index d60279b295..d16446d3bb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) gen_helper_exit_atomic(cpu_env); s->base.is_jmp = DISAS_NORETURN; return true; - } else { - if (s->sew == 3) { - if (!is_32bit(s)) { - fn = fnsd[seq]; - } else { - /* Check done in amo_check(). */ - g_assert_not_reached(); - } - } else { - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - } + } + + switch (s->sew) { + case 0 ... 2: + assert(seq < ARRAY_SIZE(fnsw)); + fn = fnsw[seq]; + break; + case 3: + /* XLEN check done in amo_check(). */ + assert(seq < ARRAY_SIZE(fnsd)); + fn = fnsd[seq]; + break; + default: + g_assert_not_reached(); } data = FIELD_DP32(data, VDATA, MLEN, s->mlen); From patchwork Tue Oct 19 00:01:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515941 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp72145imp; Mon, 18 Oct 2021 17:09:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzAXzXTGml0OP4MsVC9EbhuORSE7cv5sTQn4yj2sgl5y/rUQZKbEvBAjfpShPlWpzL+zDvt X-Received: by 2002:a67:ab48:: with SMTP id k8mr32270513vsh.30.1634602143713; Mon, 18 Oct 2021 17:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602143; cv=none; d=google.com; s=arc-20160816; b=dnyzW+NYbPV3cMkgcuMLBO8UPFXNPlfCeAZnXE3txktJzFQw89CumeNjpYcjIdVMug FVHzGmz4Yv2JDOuz1ygbbSjVV30WQsyM/5g/bb5KgAn5uEg2dPe9KDLwX7HiFL5CsxDZ EPFDHevJ0MlaeAh4M14ojLQ2a0L7TDhMscPriVVSgc94fjQDHc8S5lSq+HwrRoSfhB2J jZBd93wsu4QZB7ruCFiDLc//ZoKbn3aWT6Ly6OUTowzo7Kv5UJaMnk60Fb8NuciNLA6a ytGmgL3qIs9a5W76vHT7iL/1ItvbA3Dfk76+4gzm7rQJw8auNRWEjSIMJHaMC/j6OY9b HFbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=edH/POVbw08zofw7DVs7aX5K2Qy9VoOU3+jO1Dt/KD8=; b=AbABRbFGMw9PbKkOJg7MZJExCgQ2+JE6Ytex1pA1rR24cV84PAeCdrtgTJDIpiFcOr mSU11dYne59fijDzc9+prRJDbpb0LbBEwrC0bDwM33RFfrh8cIlEBv++n3lYlwnO/oz7 j8asrrqaLegzbBeHb2ZlGwpQSkP3PNPU0rCoaiBOYkMOTi85RFSWm6pU/Ybg6ryz1CyI B0IkxGhk8oNDuVgUGH4uolbpI4KMc56v7BtClMZHlyGBpXWZOgx0ThrKDZMV1/a7Un51 c8h1MzGefLsck6129kwvoLUl75v22gyGHoiCDxV5EcUlz5HPLMlRBwrv2wV5nQlecN4H JfcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hIrPs1TD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r5si1053585uah.138.2021.10.18.17.09.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hIrPs1TD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36546 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccgh-0000QC-47 for patch@linaro.org; Mon, 18 Oct 2021 20:09:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZG-0004om-KB for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:22 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:44031) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZB-0001hr-22 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:22 -0400 Received: by mail-pl1-x632.google.com with SMTP id y1so12402547plk.10 for ; Mon, 18 Oct 2021 17:01:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=edH/POVbw08zofw7DVs7aX5K2Qy9VoOU3+jO1Dt/KD8=; b=hIrPs1TDpOsgg1x1CJH8gJOIwQo+N/4Bn9Lm2oxdtvDghlaLGnmG0jiSTOBa3UM9u7 idiEWUgl4bWpAqdnAINX841WZOpXJWpepK21EoS6YToV7UlYkBudKNtBiZ0W15NNgar7 fFbzxwysWPLasm1cunHch+zYw/Nks4orrhh54AISHBDgiylSsUTOxj1EIN1TcGzwabH9 JxJXAq29aXcscFwBImqrU2T094nZI2gYFepjL+FVDXIExQcnaoKYynoesmReaFrl0QaU /KlrgWfJqp33IKTma6KsADpo/EZYMH1Unb21ZlcbtSHJKXwiDjMAQz82lSQqEZXrcGB5 06sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=edH/POVbw08zofw7DVs7aX5K2Qy9VoOU3+jO1Dt/KD8=; b=x6AlAYxTpj+2vul139BlNOn8np4I27qx/90FaakY2/HbVnfgbCRUK1kRHd0DmF2EbR ROuz69L07k2ghbE5+zAGfyt9FqfuO2ZN2LIrT9q57p5IKGfvHOoW/a0jK5tCJQAcCVJg U+355gatUhncEqozwOiSkKFOKOhTbavrCfls/lktElZlARtTXyWKY+IhgFl1qKAlNtWZ uXyoiFz1itPvXWhfFL4pkebaJmZCPetHewGBC++nodopy4bX48GRyfX5SGM0l7Dh9TG/ D7/rmJohhQ/u/lLrsy4IdGWHcYyfEW8TEjYaoFw+dvoB0/Qg+MPdDVFimsGzhIEWbVql 4llw== X-Gm-Message-State: AOAM531vzVtpaNcjxeT37cnZaUSnfCDrF+UhWg1VJpbKwbm4DJROMK/J FjAX1DbF5fB6lq0Uh4vgVpOKIi8C3cB8QA== X-Received: by 2002:a17:90b:390d:: with SMTP id ob13mr2366528pjb.49.1634601675516; Mon, 18 Oct 2021 17:01:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen Date: Mon, 18 Oct 2021 17:01:00 -0700 Message-Id: <20211019000108.3678724-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f7634c175a..3f1abbac5c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -91,16 +91,19 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) } #ifdef TARGET_RISCV32 -# define is_32bit(ctx) true +#define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) -# define is_32bit(ctx) false +#define get_xl(ctx) MXL_RV64 #else -static inline bool is_32bit(DisasContext *ctx) -{ - return ctx->xl == MXL_RV32; -} +#define get_xl(ctx) ((ctx)->xl) #endif +/* The word size for this machine mode. */ +static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) +{ + return 16 << get_xl(ctx); +} + /* The word size for this operation. */ static inline int oper_len(DisasContext *ctx) { @@ -257,7 +260,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; + target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -316,16 +319,16 @@ EX_SH(12) } \ } while (0) -#define REQUIRE_32BIT(ctx) do { \ - if (!is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_32BIT(ctx) do { \ + if (get_xl(ctx) != MXL_RV32) { \ + return false; \ + } \ } while (0) -#define REQUIRE_64BIT(ctx) do { \ - if (is_32bit(ctx)) { \ - return false; \ - } \ +#define REQUIRE_64BIT(ctx) do { \ + if (get_xl(ctx) < MXL_RV64) { \ + return false; \ + } \ } while (0) static int ex_rvc_register(DisasContext *ctx, int reg) From patchwork Tue Oct 19 00:01:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515946 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp74796imp; Mon, 18 Oct 2021 17:12:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyuSRrZv0jqLTZ9UMzsZhaUmL8uB4c2Na/J5BxyXu0R+snefutcpTOsiwONPuSHMfRCqERD X-Received: by 2002:a67:f6d7:: with SMTP id v23mr31675637vso.22.1634602341045; Mon, 18 Oct 2021 17:12:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602341; cv=none; d=google.com; s=arc-20160816; b=tfDW1NxwNjsXXjPEQfJo/B5vo9Whdxmj9J+g1xJhoJo6yoVu+VTEieh3Ss8NRAC3zG s8wfBNfmHK+w45O4eYC40YKGXRPG0HFWcws53IrTphRoZdMliX/ezREe+OEpDbTbEKGP 62h3pPkFAuAWY1KrzjIAMqqZ5XXUBlNMe5vY+qSK05PsyCIICnf6XLHQHt2t7QTlUXlm qXZnIAeiop0x2nJSGmxhxqZNACOBRsKTt5WEfpVIUUKm8hzMRXkNQ6zkAMsBMvf//+Q4 E0rkpnO+QL/AXA+5dqU1CFrNX3XMuirUdQgZcrmghbpIoRab4bEB+yCtA3zVMW1xgIbD vcaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RhOWPOoSXwweVtycAdzhpA4lVh0XeqXeQd1YcMV7tQk=; b=dBU7+GC7PxeGrKVVNlkIianhOVr8W4QLGxLiGjU7PcEPYdlAWDLl5chn6DAvBmYWTL F6WzESv4hVUouBQ8xIMD1x+sZmP2OT7Nwiu1mFU6+mBRfrI9xplBjfegAP6MO9qETA81 QvYwgSBLM+S+83VplsEvnLt+76lA4XxquqCCR9bHUe70mJ8KGdH1h+mzAO6M/ohoAhNR 1N9ocXtyWjgz/pZn7k2WJiC05rardUDFNib1SBhPnLgT4vMTK8YDHgvei7W/2UQE53Ee CO8B/UPUt8KOT2ROMuKSxcXshd3NU8FDBduy+TkYK9FpoK+0yMxtSjK6J1jwEvRfgo9Q 8xdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yLFtwFqI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u15si510044vsk.289.2021.10.18.17.12.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:12:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yLFtwFqI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccjs-0006OW-Ad for patch@linaro.org; Mon, 18 Oct 2021 20:12:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZN-0004sF-S3 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:31 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:37521) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZB-0001i3-Vm for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:24 -0400 Received: by mail-pj1-x102c.google.com with SMTP id lk8-20020a17090b33c800b001a0a284fcc2so650498pjb.2 for ; Mon, 18 Oct 2021 17:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RhOWPOoSXwweVtycAdzhpA4lVh0XeqXeQd1YcMV7tQk=; b=yLFtwFqIrmGB9eLNzusTK/EamWOjXkqrmwpmdMGfZdu5gyCysiSmCnIGucoL5Wmv+4 0DEXCU26Dhqs6SfcvN/is1SDZEFwcHsOsxXCGOn6826rZEzUz+B2G/CCJTffAhnlTSh7 R+gIXGIMRWyyuMudpJn2KyMQrpmuZ4z9wagoF3k7ZOQZkFnvp5dv8Znu5a3Xcs4ylny6 qctrGKOR1B56yPIJFvHb6rdFC3YUHC2hEiB7jrYQh/88OhCKpe4BjXMZTQpg0Pjp2nau XdLR9TqghDb47j6k1WpJW5ujnVIY2X71b/+R5PUmr4Ata5/i+u53veZRIKc9UohZN0WP EwXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RhOWPOoSXwweVtycAdzhpA4lVh0XeqXeQd1YcMV7tQk=; b=vCjafB48w0MEQxdkVtGgSDkEKsh6kMOm4HpnNY9iFAQBqxAJytLIWM282Tnzjt3KO8 QpcncjYm/1GWfoPio7AhUMUj4YPc/VqZ5ayy4aQE/I7mxNfMz0D8IhlKseBev5W7lLxT ud+SX9+uzwUnSc+Q3EUtzEhNXw6MHmvhKYGlL/r0YztKcZ90TOSYgN33MqU20OZ9g2AW WlLKjm/lAgIVzhV7QOYa1gM9GaPX6AIzXYefRJ0j78yjZNuIlJ0LBlAEFFUdHptANFF7 iiYZIk9zB6cmz1VgRmVc5pqsq3htXp2mxkcd6G83qnc9gqR3E2wVBDhYUgnkP9IbxP6u +o5g== X-Gm-Message-State: AOAM530YGrk4z1/qnFxDX510nHsYADpSN1/mg1J6KBZZlppGRpb1jbm1 l9Zjts9geXy9Yj4qPQ3hNaalNOyv06Qrnw== X-Received: by 2002:a17:90b:1112:: with SMTP id gi18mr2406418pjb.136.1634601676345; Mon, 18 Oct 2021 17:01:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol Date: Mon, 18 Oct 2021 17:01:01 -0700 Message-Id: <20211019000108.3678724-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 71 ++++++++++++++++--------- target/riscv/insn_trans/trans_rvb.c.inc | 8 +-- target/riscv/insn_trans/trans_rvi.c.inc | 18 +++---- target/riscv/insn_trans/trans_rvm.c.inc | 10 ++-- 4 files changed, 63 insertions(+), 44 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3f1abbac5c..6ed925c003 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,7 +67,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; - bool w; + RISCVMXL ol; bool virt_enabled; bool ext_ifencei; bool hlsx; @@ -104,12 +104,17 @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) return 16 << get_xl(ctx); } -/* The word size for this operation. */ -static inline int oper_len(DisasContext *ctx) -{ - return ctx->w ? 32 : TARGET_LONG_BITS; -} +/* The operation length, as opposed to the xlen. */ +#ifdef TARGET_RISCV32 +#define get_ol(ctx) MXL_RV32 +#else +#define get_ol(ctx) ((ctx)->ol) +#endif +static inline int get_olen(DisasContext *ctx) +{ + return 16 << get_ol(ctx); +} /* * RISC-V requires NaN-boxing of narrower width floating point values. @@ -197,24 +202,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) return ctx->zero; } - switch (ctx->w ? ext : EXT_NONE) { - case EXT_NONE: - return cpu_gpr[reg_num]; - case EXT_SIGN: - t = temp_new(ctx); - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); - return t; - case EXT_ZERO: - t = temp_new(ctx); - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); - return t; + switch (get_ol(ctx)) { + case MXL_RV32: + switch (ext) { + case EXT_NONE: + break; + case EXT_SIGN: + t = temp_new(ctx); + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); + return t; + case EXT_ZERO: + t = temp_new(ctx); + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); + return t; + default: + g_assert_not_reached(); + } + break; + case MXL_RV64: + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + return cpu_gpr[reg_num]; } static TCGv dest_gpr(DisasContext *ctx, int reg_num) { - if (reg_num == 0 || ctx->w) { + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { return temp_new(ctx); } return cpu_gpr[reg_num]; @@ -223,10 +238,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) { if (reg_num != 0) { - if (ctx->w) { + switch (get_ol(ctx)) { + case MXL_RV32: tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); - } else { + break; + case MXL_RV64: tcg_gen_mov_tl(cpu_gpr[reg_num], t); + break; + default: + g_assert_not_reached(); } } } @@ -387,7 +407,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { TCGv dest, src1; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -406,7 +426,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { TCGv dest, src1, src2; - int max_len = oper_len(ctx); + int max_len = get_olen(ctx); if (a->shamt >= max_len) { return false; @@ -430,7 +450,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); TCGv ext2 = tcg_temp_new(); - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1); + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); func(dest, src1, ext2); gen_set_gpr(ctx, a->rd, dest); @@ -530,7 +550,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; - ctx->w = false; ctx->ntemp = 0; memset(ctx->temp, 0, sizeof(ctx->temp)); @@ -554,9 +573,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) CPURISCVState *env = cpu->env_ptr; uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); + ctx->ol = ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; - ctx->w = false; for (int i = ctx->ntemp - 1; i >= 0; --i) { tcg_temp_free(ctx->temp[i]); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 185c3e9a60..66dd51de49 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rorw); } @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); } @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, gen_rolw); } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index a6a57c94bb..9cf0383cfb 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -331,14 +331,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a) static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl); } static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } @@ -350,7 +350,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt) static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } @@ -362,42 +362,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } static bool trans_addw(DisasContext *ctx, arg_addw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl); } static bool trans_subw(DisasContext *ctx, arg_subw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl); } static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl); } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl); } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { REQUIRE_64BIT(ctx); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl); } diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index b89a85ad3a..9a1fe3c799 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl); } @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_div); } @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_divu); } @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_SIGN, gen_rem); } @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVM); - ctx->w = true; + ctx->ol = MXL_RV32; return gen_arith(ctx, a, EXT_ZERO, gen_remu); } From patchwork Tue Oct 19 00:01:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515936 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp70542imp; Mon, 18 Oct 2021 17:06:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEqLQd/gcuDnjg9aW5tQnTaOhJLLVmc18QT5mYdoERHdQe5GQCBTTfm/WaO5lsOKgFeQ25 X-Received: by 2002:ab0:56ca:: with SMTP id c10mr30073974uab.7.1634602005956; Mon, 18 Oct 2021 17:06:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602005; cv=none; d=google.com; s=arc-20160816; b=ypzFe+DFMmIKqjtgKFS13bceffJX+tr2yPA/R1aFlMcg9fkkuqnGfieGmGiMrG9XEW 43wnO5eJHeGweLh7xmLSeAByGeFlhisgdBuzvAACZ7eLxzUecqiRONd6dssff83iCVJ/ UXpb9RQDWnhUhm+Kw2WhjNPjJTytzpxywUWJsgOEVFqrnp1LtrI4EcEoozzUSbklPWSN 7sw2+cNrZ9vRkqYPlyB8+pAJ+Bs3knGG926vXxsQto1UAUUjmU9BmPMLdU8OBT56pbFv nR65lvNM5HQMfKE9eYHTfj1XTh20nGYf9Bfj2D++J5TnSvJxpT6SZG0bKUzRn/Wt18iC +COw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=70ix3AhGljp8w7VYIEJb5B8tKM59m/WakgkEPwbsgro=; b=XRzPQJ1UfVK1Accw9FWqHqNxzvsBrWFQauTXQ18oU3HXBWOIr98GfpEInWm9CjsbEA PVpsWiTKwPRXhpIXarD3uVc5Iw/DSc/zuJ9vFykGC3WO49jqWcJxB36u/RDL3ZHQN/s8 K64EFGsjFkQH2CFyyie07X3jOaCAhpNC/I/UnOhb1JFtehvhsoXSZ+lMLpPD2scFkdkF fCf8tncMHIloQkFVrc4A8XUMrdns8UnwUoYE2ip5p3aF0l3A/elXF4R8g8CRMBN1REhS v3fLbVE/0IqYZKfrUPbVnNSQXinyqfsvAEH20UWKWHxRqyp1lylazaVe0Y9rVQHu6asF ztXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ajMxC7w9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e8si31395vsj.39.2021.10.18.17.06.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:06:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ajMxC7w9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mcceT-0002Lc-AX for patch@linaro.org; Mon, 18 Oct 2021 20:06:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZN-0004sT-UD for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:31 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:44971) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZC-0001in-J3 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:29 -0400 Received: by mail-pj1-x1032.google.com with SMTP id oa12-20020a17090b1bcc00b0019f715462a8so1248490pjb.3 for ; Mon, 18 Oct 2021 17:01:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=70ix3AhGljp8w7VYIEJb5B8tKM59m/WakgkEPwbsgro=; b=ajMxC7w9tYWnmaPRpjSiKkmExW80tFn5lLQw4d/Y8jLUCe1twJ0h6bdMpw7VTkYlQ1 BRJqrgLr7sSg1/SER5x9fcshTxUa/UIFWv+NKxoXtKH/EqXlIDUM+6TEJDgFi2/MkeZ2 NiO95U6dKwtu9xS1Yh74nVoqpMllbMZE1C8r5z9sXFAJumxXq/PUhQXLgugs3gTjAZc2 FnOB7e/nfN/hWQrc8rsKPPMki9sbid+TZCdxbpoKS1k0yei1NGGpQnPl+BxZvHVVzkR+ I8hR0yHyOFH6WVPm98LrB6BnUuAzJYY0NYli3A7pf/qW592B1C1cYCq/zSOr1XP5Jp+h 2+Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70ix3AhGljp8w7VYIEJb5B8tKM59m/WakgkEPwbsgro=; b=BfiCRL8JQPxqssJS2mfBaNMERZYKyq7yC2h/tVSpaP3yr8FiXL1xVzxhIjFD9jcLTt jlv6yFY5x+R+4HaDuHH4RAJQifh58FG1YzQSYv3uzbQTdf6lE2zf6O/RwPVkjvDzaaMs o7gBBH917Cb1dAc6Y3Pu6jwMGvb/17bS37vdZCriZYw1Fc4qMPdQfoG82cVBAJCCWY40 XAf58fE1qg0IR1eNsViWgCuaecc4bBAptmBI4veVbDu9Q5JFQdVqWSeYQPeeek39cB87 UZDUuP8wcvi2ZU8j8SHlYGj+1EHvbDeZJUtvgoiAs4GEqdjuNcexKbaA3kzbq5YRxP26 vsug== X-Gm-Message-State: AOAM530GjyT+j6b72m7cLQuLRNsIwOxkpbcH3nH3+m/Ks+9rBoJcLuTq Ixame9uXfG6IqDQXCRFprxrpjjvr17OIWw== X-Received: by 2002:a17:90b:23d1:: with SMTP id md17mr2392777pjb.215.1634601677159; Mon, 18 Oct 2021 17:01:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM Date: Mon, 18 Oct 2021 17:01:02 -0700 Message-Id: <20211019000108.3678724-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 +++++++++++++++ target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++--- 2 files changed, 39 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6ed925c003..5d54570cc9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -403,6 +403,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_arith(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc index 9a1fe3c799..2af0e5c139 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -33,10 +33,16 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) tcg_temp_free(discard); } +static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_mul_tl(ret, s1, s2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulh); + return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w); } static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -54,10 +60,23 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(rh); } +static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + tcg_gen_ext32s_tl(t1, arg1); + tcg_gen_ext32u_tl(t2, arg2); + tcg_gen_mul_tl(ret, t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_gen_sari_tl(ret, ret, 32); +} + static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhsu); + return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w); } static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) @@ -71,7 +90,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, EXT_NONE, gen_mulhu); + /* gen_mulh_w works for either sign as input. */ + return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w); } static void gen_div(TCGv ret, TCGv source1, TCGv source2) From patchwork Tue Oct 19 00:01:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515940 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp71845imp; Mon, 18 Oct 2021 17:08:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMJIIX9lSZw+vsXmhXThYU9dE4akMkn9I3X6o1vFjgXk41RcyJV+s0pqPYMMT4ieuo5Ucz X-Received: by 2002:a67:d28f:: with SMTP id z15mr31270586vsi.44.1634602119841; Mon, 18 Oct 2021 17:08:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602119; cv=none; d=google.com; s=arc-20160816; b=x72EA8ZHVWrOehTIgb2QBoFyb6cOZCeJwzBYLOXRHBHysPr9CV19RtYhj9kdRi/AY1 pOIOt7Ur0or8kfnGISYvp5EwLTc24mdc3cG2m0hUzjZZqP+aTH/KJXaRZ73TptyHY0ce L13EdGKnGZORfDpGjBi8SeJ5m/vx6rgnO1ilV+/RmRStCja05otSVJqQpgNDOqnk5+1Q GedYM1pUEjxzjRQ/IueeeDMknrYNOZEt1UbhVQuXjy+Q7p2vxXAZrF8/kURVwxbC0ard IE3yA5T64yTv9fhTKdyzQrrut25DlNCL7BgjtteQ9E/6EhOEThBUALSmZAi8hlPp0x7U pIWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VHU6Zq495CGWvucF4SFdns/LDCGAVtayMjBnfRKFC6c=; b=WvlI/nbGXlyCNQnH8GiOvbN7K5Xqni37CCtccMkkbwFA9r/MVbgxHnECqaTutB/KDi zR06w0fflagr5s5ApD+7nRnaG/we5lv4S8gJT0tWTyO5UcSm9PiBdU2JzrzpyjgCAOIe IV7KXIlHuuHg7P7Ig+wNuWyNdcfFVRA1V8FRE4Keml1mnwFbdNOpaRnhXYh9f+9PUacq g9zX79nyXxZIKcqvfvkxEGzbk3bPAvzL5nQfSo0zjprj+NzP4JGxfB+fL+Fyq5AfILGo jz2dCh0Yh4CHQbKVGijKXueYcPD/2JKjw3oAHbcCxm73Tj7lGUmKXVDrL9P3twKQnBhV ixOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R7qxaeBs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x21si6581412vsi.377.2021.10.18.17.08.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:08:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R7qxaeBs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccgJ-0008PC-5k for patch@linaro.org; Mon, 18 Oct 2021 20:08:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZO-0004su-8t for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:31 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:40844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZD-0001kL-GY for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:29 -0400 Received: by mail-pf1-x432.google.com with SMTP id o133so16038325pfg.7 for ; Mon, 18 Oct 2021 17:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VHU6Zq495CGWvucF4SFdns/LDCGAVtayMjBnfRKFC6c=; b=R7qxaeBsIX1on9YaubihiUsdFKU5s4m5VHATXWnawa6mtoHiWPjo1PZWHhdUkTdk2M 4n4JA4K723xeMyrw8Ih2uwPfwqzkKuTxKJIMUdOPy3lSbNugJAbQA7qgiH3upGV5Kl3g fMXnT+LuTxjfc8MW3NR1ggx1hSPW1QuMSPTLpPo+rZXxg8ud2plBgmY7/uO398lRbeQr VapxWghOPZ8sBNq4CkdRQBiIYArno46Mpbyu+7jKHYiqYdKmZYwaD9HgOlIq6LT8wWxJ Xob0wQSRHMdJLXWar3KY39pEzHYgVOqr3NozxKkj8DJ/pjDsGQXaKlRGOEnRss6r01tb EaGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VHU6Zq495CGWvucF4SFdns/LDCGAVtayMjBnfRKFC6c=; b=IHFxwlsP2HIVl7ZTpxREbpVOC8Iz4LqsIXcxJdpCnRxg3kTjs+VK75jt90H+b4ZA75 pwWNDNpOBQVhWrpPNJtxicw44KeP30rXyMQF/6uSnD1eovLukxcDWWvff8i8YG6SuDOL xzT+XWw/I7N+C7e1QR7+7q9Dqt8Nbgl2LQkZIPkDuJ9s8q06YQtFkY7HqBLI08tNcqKY nKkprQ5zGTM5l9GhfHhtRzQU9NzXJWQc3/RKVvLcsENJ1JTohgTBWavJtAOHh2CDNx4l sauxjAvYv1QG8HY4CgnM+rFP0/uZ27ry0jfbThd3tRQq1xTa7TPjh7XMbr60A5VGDe7r +S1Q== X-Gm-Message-State: AOAM531NjcP3m0miQYoLP2+oZeXPujI2buZQvQRLGO6A643VEi8lSstW 0e2p6K58fkVuwXF7AAgB1tK6TKnClVR3Tg== X-Received: by 2002:a63:5453:: with SMTP id e19mr25953496pgm.178.1634601678001; Mon, 18 Oct 2021 17:01:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 Date: Mon, 18 Oct 2021 17:01:03 -0700 Message-Id: <20211019000108.3678724-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Acked-by: Alistair Francis Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 66dd51de49..c62eea433a 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } +static void gen_rev8_32(TCGv ret, TCGv src1) +{ + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS); +} + static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a) { REQUIRE_32BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32); } static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a) From patchwork Tue Oct 19 00:01:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515944 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp74727imp; Mon, 18 Oct 2021 17:12:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyG3MvbHCCwEt5FTUGICHZrMQF4MGmzMHS0ZQ4J8RTEgicIUmZgJmfzUzI87ILMUGK/F5EH X-Received: by 2002:ab0:6154:: with SMTP id w20mr6321525uan.25.1634602336001; Mon, 18 Oct 2021 17:12:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602335; cv=none; d=google.com; s=arc-20160816; b=oVzEBmAd90Vfu+CqyR1PTKMdlLxnIQQx3hJqEuGVYkaG7A/39v37sEQH1HRFV7Ce6a qa16ebwJBRwrkjO6uSCOMyB0o6oa70ZvjHxketYM4UM8wraJLTCEwtFIyp513NyUsvZT v14dGiR7FPXQ1rjF4afy8oYMHbSAXEWIb2KJcNqPTZuhIKiV9IkwpVdcgfZFOBLw8ZOC nPkSQjTg++I/NbMoHOPfKgCED07E2ibuEj7prx6zT0A25o35vomK8zPL5QxGFNgLiAD9 vpxml3WbpndnIJznEdVuGIi9a2baR6/KiwZRcEu2+eePVGnLz9EuJvx8mXJR8NvtR6vL bb5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c7yPgPOtdXc8cLGoEleP9T3gCAQ/J91zHEOZFu0LBcU=; b=Wuyj1SUUETzrHj17ojkzSspNPocFdsLta4PT0MXiY83SjH1qoTIFRTAcb2p1JsSwVC IYqY+zY6cWIWCrvVVyqkV0BV8nKhVrR9VcJLixr71+Q5+EAl+Qam5jq8rhBlgCsQrDbX EjMBEz5jUKD13ljCCQfH6ACRM0e2+1CQoffO28lQdba7olPwKIRUvExGeeY66vCA4R0j WJtldbVlcKjWG3crASQggJSJKkXQ3QTonEejfaJIDFiso3snT2tvYXOD/FN3i2+qI4Xd NIvmW7pr8G/RsBLuWG1A99QlK1DRHvJDk+f0vLp0cM5Kg5dTSWeAcTfp/rw8LVqB0VeJ RgpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=woBCMuca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g4si6450271uap.165.2021.10.18.17.12.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:12:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=woBCMuca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccjn-0006Ch-CO for patch@linaro.org; Mon, 18 Oct 2021 20:12:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZS-00050B-31 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:34 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:43844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZE-0001lF-5F for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:33 -0400 Received: by mail-pg1-x52b.google.com with SMTP id r2so17691085pgl.10 for ; Mon, 18 Oct 2021 17:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c7yPgPOtdXc8cLGoEleP9T3gCAQ/J91zHEOZFu0LBcU=; b=woBCMucaWtY+UI1ywYdNCmU3tGp0PtxvIiIqce98ZwdAoldf3Yy6dIwdP0mL1M1ZL6 UTNKR+z9O73aoZCC1E8xzRMPNU3P4A/PPS/SGsskx5znhtXHXhmP+jJUvLlfMod1pUYv 5U4ir1o3cTFlgsa65c9+qLtos0L5OhjTX8bdw0k9P8yLKcYf7Revkvy+/muYSVZw5ZDU SGlYXeQg2OWj6DuWMQMtExrGTq4LCwZi2Ffhd5dEQZRvQBlS2ye7lIri5ot6wk/hkSx0 OVszfbPa05WNsjKe+lGM8PvlWyZxLGPyvFJUEYvQAWWsYErBqoRYASxuc+SytaZ+hhZL OopQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c7yPgPOtdXc8cLGoEleP9T3gCAQ/J91zHEOZFu0LBcU=; b=zz/h2IoSbo3ULyy6/QFxdrW8BBB4xyUFMZOd1pI23w5T7CGqsFDZjHdU+h+aX47jQY NBc2JRXPT/pprFPDfjuLJCcr2ALwxFIFJWV6d+3rqgmtADHMBqfcabyUwfWGfol2w4R0 A5nME9KMIxCYm1+ZKx4ZOD/r8iplQ/1qRQLuUK+wxq/njYDtzllmY78s4YhJUm9Mx5eg vl7EDrbGNMZ12ujvWJuae4Nu/2hl54pP3iwU21JIC5z47pTKSsN5EARSB/eBTeUytWYC 4FB7Jbun2hhhsaVgClisL4NThDdA3LV7zNFuJyexVFmZyTwtnIo/7yL5DLA1UXWO3Gsa 3ZEA== X-Gm-Message-State: AOAM5311A1YwvA7Q0C53g/Y/I1iqs8VmvwJOJ8D9HQbmpU0v2pZ8GEYv MHnVijjDPrKWnIqw9kMUKByUJxem6J7gnA== X-Received: by 2002:a63:2484:: with SMTP id k126mr26091938pgk.297.1634601678794; Mon, 18 Oct 2021 17:01:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB Date: Mon, 18 Oct 2021 17:01:04 -0700 Message-Id: <20211019000108.3678724-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The count zeros instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 16 ++++++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++------------- 2 files changed, 32 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5d54570cc9..ebcd1c8431 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -486,6 +486,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, return true; } +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv), + void (*f_32)(TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_unary(ctx, a, ext, f_tl); +} + static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) { DisasContext *ctx = container_of(dcbase, DisasContext, base); diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index c62eea433a..0c2120428d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1) tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_clzw(TCGv ret, TCGv arg1) +{ + TCGv t = tcg_temp_new(); + tcg_gen_shli_tl(t, arg1, 32); + tcg_gen_clzi_tl(ret, t, 32); + tcg_temp_free(t); +} + static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_clz); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); } static void gen_ctz(TCGv ret, TCGv arg1) @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1) tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); } +static void gen_ctzw(TCGv ret, TCGv arg1) +{ + tcg_gen_ctzi_tl(ret, arg1, 32); +} + static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_ZERO, gen_ctz); + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) @@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); } -static void gen_clzw(TCGv ret, TCGv arg1) -{ - TCGv t = tcg_temp_new(); - tcg_gen_shli_tl(t, arg1, 32); - tcg_gen_clzi_tl(ret, t, 32); - tcg_temp_free(t); -} - static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) return gen_unary(ctx, a, EXT_NONE, gen_clzw); } -static void gen_ctzw(TCGv ret, TCGv arg1) -{ - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); - tcg_gen_ctzi_tl(ret, ret, 64); -} - static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, gen_ctzw); + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); } static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) From patchwork Tue Oct 19 00:01:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515942 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp72165imp; Mon, 18 Oct 2021 17:09:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwquATZFCbru2SVS9W7yn9Pnm6dNnWkMsSCY6DppEhpedyMd8d66sGRf6lOwv5UWnvLjUg1 X-Received: by 2002:a67:c908:: with SMTP id w8mr32237172vsk.2.1634602145760; Mon, 18 Oct 2021 17:09:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602145; cv=none; d=google.com; s=arc-20160816; b=JhPU64C7kNcyiVtnndSuFSMHpftSCvRJhBZtTDhe2dYlVxr+WRdipwuaHJhwQGYiZ3 VnM+sIOJ/6J5PzxKU0a1QfSplBDRlqMoLL2y77kgl93tG7tlnlcmyeYHJ39AzhScS1k/ ij5l9BF562qz/69SIX8nZTAgh7PK/aUJj+s9yx9o9O070NX0DwF8MXxUcpL+tLBykex0 9HHZRBmcEEUkoTJuu2qv3l2sbdnkgoVvRcBt2K7R6kS+ZObSkdQurenzQXK/3fvqOrUc dNOc36eXjutWOnhv2P3c3fib42fCVupxFwBGtvbbQ22iRVDSU79rEqtIbjChG2KK+2SU Vhyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v38EgObVIQZxnJyRBCc7mAXK+cvyWQc+ZvLKbhcUEpc=; b=eMp/narNy983cqv1RmijswMJpUwhBbnR9TxFVjm5yTmQ2xPTaRmySlyDB4xOEUrti3 7D9pqJIC8QWffA9cRkEkQJvxZo9GU5Q4nYyH7w28kVzPZDnTOx9y1vu1J1A94BYauPtQ xUv3239b+6PY7fioxk4+WsXmRMDd1jOFTx1tDqIF0QAVOl+5YL9ItFBZ6nqyLK0pjn2C VOsMV1UYqDT66YTHEtzO2X1hK00p6o3lnZcXp+kkw2WBnFMdLsBqNt4JZPlVJSKLvgzL NkFQ6l9+Kk2irxfe6hf4awV+L8XLgRzsbcfA9V0+JjX+CNSxH8GmBCM3/V1JXWRcaKjA kKbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=l+IKxgPe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p6si1292768vse.95.2021.10.18.17.09.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:09:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=l+IKxgPe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccgj-0000UO-3J for patch@linaro.org; Mon, 18 Oct 2021 20:09:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZS-00050F-3Q for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:34 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:35463) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZE-0001lX-Uo for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:32 -0400 Received: by mail-pg1-x52d.google.com with SMTP id e7so17736224pgk.2 for ; Mon, 18 Oct 2021 17:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v38EgObVIQZxnJyRBCc7mAXK+cvyWQc+ZvLKbhcUEpc=; b=l+IKxgPe6q3NntPeN7/pgNueU3oalEnsj71rx1BMQFY88ZEwkFl6BiHcHRYw22rhQR gRWvb27pl6RaUu/mgW8cIJkj93Ie+AJ5ZlmubQuQZ+QWdvPzaoTxtpKj98GXENAXdfir Q9YZVOKxjgasLqGSI8voT38djA5bcqvx6hNubASgmrpnR37zwDMMt8KdWlBwYcDTIdQG URS586XRC8aLJU8/cWqL9wiHUBclAXUDS3EMQOC9PDjvhEcpQeEDZh1Zzb/jOT+3Cz38 gY6TndAqGZGfrQMS7nku+WEZnC/+X3/ey9rX7sLch5xRwdILuP3NGn7+Wssje8j1+/hw r7Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v38EgObVIQZxnJyRBCc7mAXK+cvyWQc+ZvLKbhcUEpc=; b=thDAY40qcROcopF+5ZLSSg1GDOdaqDUGAVjMV67IGCQNEIn9weYaTn80agLOJjp/vq dvHfAIb50/G7Bo2/wlW5f8VIt7FJUSIV962niunbaTK97rZfq1NY4qjRuHiWBTR2D98J Ksa8J0N7rExeWitKoATY9LIsdPWyAkPokw4hpfGV0KaUGirwbNkY8em9Xu/ezlwH7xXk 4UuGaSUbdRj7zUKuC8sXp33SJw4M8+aCnP8OLx68Mpd9MQtT5FHmiQxDUQodjHhuCagF dC63FhqXnnc6JkRx+Cekp5V676krMAVtZDXWzvmkkgU8KbleGWjAvCo5FrZzBAtXsI/X RqCQ== X-Gm-Message-State: AOAM530SgwO9ApzD9yzMfqW39AUbJsny3yulVdZpc50WAs9jkzJxetft T+AVKIcrRykaGXYr8DnoJd++vPqKilGSXQ== X-Received: by 2002:a63:7d01:: with SMTP id y1mr26415290pgc.343.1634601679405; Mon, 18 Oct 2021 17:01:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI Date: Mon, 18 Oct 2021 17:01:05 -0700 Message-Id: <20211019000108.3678724-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/translate.c | 31 +++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++----------- target/riscv/insn_trans/trans_rvi.c.inc | 26 +++---- 3 files changed, 97 insertions(+), 52 deletions(-) -- 2.25.1 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ebcd1c8431..de013fbf9b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -438,6 +438,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, return true; } +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, + DisasExtend ext, + void (*f_tl)(TCGv, TCGv, target_long), + void (*f_32)(TCGv, TCGv, target_long)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift_imm_fn(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { @@ -474,6 +490,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift(ctx, a, ext, f_tl); +} + static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, void (*func)(TCGv, TCGv)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0c2120428d..cc39e6033b 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -227,22 +227,70 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw); +} + +static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_rotri_i32(t1, t1, shamt); + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_ZBB(ctx); - return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw); +} + +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, arg2); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_ZBB(ctx); - return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); + return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw); } static void gen_rev8_32(TCGv ret, TCGv src1) @@ -349,24 +397,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl); } -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotr_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); @@ -380,25 +410,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a) REQUIRE_64BIT(ctx); REQUIRE_ZBB(ctx); ctx->ol = MXL_RV32; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw); -} - -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - /* truncate to 32-bits */ - tcg_gen_trunc_tl_i32(t1, arg1); - tcg_gen_trunc_tl_i32(t2, arg2); - - tcg_gen_rotl_i32(t1, t1, t2); - - /* sign-extend 64-bits */ - tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw); } static bool trans_rolw(DisasContext *ctx, arg_rolw *a) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 9cf0383cfb..91dc438a3a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -268,14 +268,26 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); +} + static bool trans_srli(DisasContext *ctx, arg_srli *a) { - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_shri_tl, gen_srliw); +} + +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } static bool trans_srai(DisasContext *ctx, arg_srai *a) { - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_sari_tl, gen_sraiw); } static bool trans_add(DisasContext *ctx, arg_add *a) @@ -342,11 +354,6 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } -static void gen_srliw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); @@ -354,11 +361,6 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); } -static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) -{ - tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); -} - static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); From patchwork Tue Oct 19 00:01:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515945 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp74785imp; Mon, 18 Oct 2021 17:12:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwy/l9SR056m/UziRmy0RbvYayr9pqOXpsKcpvOBHzfTFWOoqIBMBA0ode13SxUhh9Zql/K X-Received: by 2002:a1f:608a:: with SMTP id u132mr29065782vkb.19.1634602340612; Mon, 18 Oct 2021 17:12:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602340; cv=none; d=google.com; s=arc-20160816; b=XnJ0vUXrC+LO7lDpYfng+BntdEd57HPCTc4mKc2ayKVDq+xA4IqjstsZIRyx3eqGor i5XJhEek7+jKILyRyqqA8IOvxKoqxCB1axp0J7mJklPnkQlzQG8oLbhEhLXXYvXJoGky TdvheBr3Ku5/VFSgPQW6OyniE0FgCDywEozcpVO0CFBTkw6r/+dxMClyArECe2zXVh8Y Q0bE+XvutpswO3tV/FOwvucpv8DII4FCNppRXUZPws1J/VIsAoaoS+jALoKopMruDCKB CQRxrRiy1XDLOEnqp9+nbqcoQVdqU89B1/OnSNFHO8Dx+viYt8CRBL6C+3Or9QBMdjoc YFjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E6ifnB9fQVtM5sdP3JDCZC+MLNkcLrpq6cl5OiAtX44=; b=QnJxXoDqBx4Lhz3lSZSOaus/s8jlhEgiAza8VEFjR4d0tyyG1rABA93PSfSKAa3fvv o/yBX784Eh9ObTXkCjUERthZ0PNsxWiLu9pw4+4JcSe4qLVtSXTZbEz7gV+LejZsP4i/ n5FAQoRQeL6WEaAIZe2+Q3EbP4q41m5Q09nvv+jHWK4kEeWTxWltzxsdHsnsBF6i5f55 LRsENrufCBqD8wVdxHN/tQ+xNl4EO45zmrSd2GoIrJnoJnaXVBOzFAXW+XX92SRCYHdX 3GxHBW4DUByxjOrO1TgOJoBkkjgLyyqYbwgVZIR5sMqHS+32UPbwPnZC4Alsbpdaq427 xeCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="R/RMLEBf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t14si236224uar.240.2021.10.18.17.12.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:12:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="R/RMLEBf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccjs-0006VL-1m for patch@linaro.org; Mon, 18 Oct 2021 20:12:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZT-000523-1C for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:35 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:37809) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZF-0001lk-Ki for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:34 -0400 Received: by mail-pg1-x533.google.com with SMTP id s136so14478072pgs.4 for ; Mon, 18 Oct 2021 17:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E6ifnB9fQVtM5sdP3JDCZC+MLNkcLrpq6cl5OiAtX44=; b=R/RMLEBfZY7ivGnrhUt5U55HvG/Zvrqwz0Qr/B9wTuKeWczvvllYcSdOhBg6qd06KE Qkg1kuECc0MH3lAvpFYhVAu2tYRIa+NrZTj+KslKqmwwQrrXrnihqMib3ADFqKJm1Vnu 0nK2dq70TkwObe8jnSYd8rV/2zF6i5CnqS8Vev4gbzeDkjBaUgsaeQ9l+1Avxs6yf4qL yc8Cg95t438ylIBLRoPPr/bN+aoVw5icWqkuLTO3h9YAVGbbOtbySz7tYN3idasrsGjk fVS7Q73eW2KkCIbN7AAwoBAheecp0Wd8xTHQ7UzMlblvqpwk2eGd+jEODpxDYCnKetTy lLTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E6ifnB9fQVtM5sdP3JDCZC+MLNkcLrpq6cl5OiAtX44=; b=gK5fFpLHZu+Bx5md7K+2aY7Bh+vnAyaxBhs1d4VmHIjESiddDTWWHIISI3aMMvSv4D Q+KhRlDrVOpkWYCfntlhEz5RqyBg2bMU6gXX4fBf4PfrVoqKyMwAEmL1si0O2hFIiNwr vZDmjTA3C3S3jVLDBVGmE0S+9E+qvwvav2oWT4mAwpIiIGp9tv6KlTIjyDGx25N1Sun/ TsGcwnA6ntBTfm5cfbtOqU9nTGTGxKgHkI96mV8MYN+TsI7dxPubBCBK76iGQnwk2Znh QBjxey8mTEwh1c0l34wgfFZ9RM55Fk3VS3/yszEVG9GWxqH/oegOJ/oJqatfDph2GQYr Kk6g== X-Gm-Message-State: AOAM531m3wIyqZeAqHHVs4lCcbFKVeYKR9+QLOwiEJXGBhU079GLjR66 h/ikrkwxS2MwTfEZfhlwA+L3PQ1hAr4/ww== X-Received: by 2002:a63:e115:: with SMTP id z21mr26245263pgh.306.1634601680030; Mon, 18 Oct 2021 17:01:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump Date: Mon, 18 Oct 2021 17:01:06 -0700 Message-Id: <20211019000108.3678724-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allocate 8 columns per register name. Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e1920d5f0..f352c2b74c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); } #endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #endif for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s " TARGET_FMT_lx, + qemu_fprintf(f, " %-8s " TARGET_FMT_lx, riscv_int_regnames[i], env->gpr[i]); if ((i & 3) == 3) { qemu_fprintf(f, "\n"); } } + if (flags & CPU_DUMP_FPU) { for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s %016" PRIx64, + qemu_fprintf(f, " %-8s %016" PRIx64, riscv_fpr_regnames[i], env->fpr[i]); if ((i & 3) == 3) { qemu_fprintf(f, "\n"); From patchwork Tue Oct 19 00:01:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515947 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp76188imp; Mon, 18 Oct 2021 17:14:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsvgnR+vPV8dRg7lkGYu8YJfsKd6GcexqjC55Kf8KvZCqCaV/+/Xujfu9k6K3jBDQ3iaX+ X-Received: by 2002:ab0:6d8d:: with SMTP id m13mr29188913uah.113.1634602450831; Mon, 18 Oct 2021 17:14:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602450; cv=none; d=google.com; s=arc-20160816; b=gaVVE08IUIg23JmZ+95PWOTyPlcKyuCkH9/zeIyKHtdEZwr04VJlz1mHcOUlrFtGrI lBFtONuYPI9sukA5dQ+iSP4FmwjDaWe3GNbWBbYiKOjGEHkvxjvTEGGUE2HgRtUE6hyc OfrVtVC6nSBM9vsvCx+p3Ph7kBk+tsl/eWNmghZn2ALBfvn1bBUM4IRlZeps9315ryxk 5Ob6sNaexUWrFcJC1q8PTNp3MKvLeQClkcQpggkXHaMZ5EPTOXfs/UCf19fZKluMuQTP zX/aHW+A9vEUDx7llJU9A2nnLfoFwQijqPTGpS8UFt9LcC9OCS0TbaGCzMZFLVKNR/j4 /rOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0Uy+EMg3VuLMVRYQKBMZoT0zq//rHXap3pUqZ5CBHGc=; b=QG5NdrIZnGTbDp5apsjL0TONcp/h0WKxoJNCKVJJTd9EpDWlFZiaXj8kbSS71cqTrV AV4etUzsZQrnScmm6ea0H2H2dLiDFfQqGIQkrDnZsl71CwqflFvfZvTJkGcPppMtU+7O 9byHLbRl1j/RuYU3ZXpauWovCISHC3Wbqq/PPTab6dCQ/+mAV/rhUe5cnxF1oNAU1AZR C1Vk8BOlvyk613Z0OB/dCxGi2SkAkLPmXns2zN7IovU3Bap4184ZqrRpqr+rt3XICVxv VnUB4M5Pd+9lusQ3tiwEEm5rPxFVsJL+rODNPD5fJznR+CWui1OFSGA/TDtZxNz6jl/T cxxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=T9mvGZ1H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z14si13978491vse.110.2021.10.18.17.14.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:14:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=T9mvGZ1H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccle-0002ZI-60 for patch@linaro.org; Mon, 18 Oct 2021 20:14:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZT-000525-FV for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:35 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:36421) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZG-0001mi-92 for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:35 -0400 Received: by mail-pf1-x42c.google.com with SMTP id m26so16059401pff.3 for ; Mon, 18 Oct 2021 17:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Uy+EMg3VuLMVRYQKBMZoT0zq//rHXap3pUqZ5CBHGc=; b=T9mvGZ1HotAqhPr7Qz4XIks4xqUpqgDzXrLpEZOEPa23ccHbxvTxSl4izWudwdx8OW fO8B668eULvZGL50+uQVwP3Ess4u76l9OlN83bqqYDE+vY6aDg8UFp/Av5+cATSDxhqx osU0bYTbJY8dcMrvOny+Vlz6HaPxRfULk4RJ3zAmDLbu8PMHRilUzYPA8OaUQeML/TN3 YCxlslP4cbfyDcb/lYwGXk+53YC6nbkz/srUottFmm/8b2b4zfDvkZk1nfglCNrdFmyT UHHseDToPgwPkIOGlHyRmr/Rr/6fDkxtQHmC+YPxVO8Drspa2DfOyLVeUeDefHpIaFOY GrRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Uy+EMg3VuLMVRYQKBMZoT0zq//rHXap3pUqZ5CBHGc=; b=VM3seK4Fv5x2cheusqxl5Nlm+8sT1hiwlbjtoX+FgighbOUKhlUoaBgqZqrtz2G/Fj EAx331oaM/it0i5GI1kYPjmmYnMWxl5s7/3BfPqdDJtVXvayyiA9GPR/F4TA1hdRhuQx 6pt4zi11PjAR9HsZktW6nL/2sAb/d6dQa9ufpTj7he8b6dyA60FKdOGD2rPYfbyb2Clf /XSkAmS1NUlkEOz1qhyARZeAE3K+qQfXNgvtvIPJ3sIOFE36w6PjaVErwQjN4ZsPbFH/ zVqJCDJK7qQN56WSmL2a+aTXzJlE/XyxVN0ayP2OyZZ6EZxTCOQ7H4P6mjbdaJCPzuFf eodQ== X-Gm-Message-State: AOAM533u9C8El92lXYDuS4WTRRHNWbNIoJFQws3runLuuvAVUElCpCAQ h/NaOrpUXLTcxWKNEvpYnZQP4/VXgN0rIg== X-Received: by 2002:a65:6a0f:: with SMTP id m15mr26313241pgu.298.1634601680630; Mon, 18 Oct 2021 17:01:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump Date: Mon, 18 Oct 2021 17:01:07 -0700 Message-Id: <20211019000108.3678724-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the official debug read interface to the csrs, rather than referencing the env slots directly. Put the list of csrs to dump into a table. Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 99 +++++++++++++++++++++++++--------------------- 1 file changed, 55 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f352c2b74c..b81b880900 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -241,52 +241,63 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #endif qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); + #ifndef CONFIG_USER_ONLY - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_mxl(env) == MXL_RV32) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); + { + static const struct { + const char *name; + int csrno; + int misa; + bool rv32; + } dump_csrs[] = { + { "mhartid", CSR_MHARTID }, + { "mstatus", CSR_MSTATUS }, + { "mstatush", CSR_MSTATUSH, 0, true }, + { "hstatus", CSR_HSTATUS, RVH }, + { "vsstatus", CSR_VSSTATUS, RVH }, + { "mip", CSR_MIP }, + { "mie", CSR_MIE }, + { "mideleg", CSR_MIDELEG }, + { "hideleg", CSR_HIDELEG, RVH }, + { "medeleg", CSR_MEDELEG }, + { "hedeleg", CSR_HEDELEG, RVH }, + { "mtvec", CSR_MTVEC }, + { "stvec", CSR_STVEC }, + { "vstvec", CSR_VSTVEC, RVH }, + { "mepc", CSR_MEPC }, + { "sepc", CSR_SEPC }, + { "vsepc", CSR_VSEPC, RVH }, + { "mcause", CSR_MCAUSE }, + { "scause", CSR_SCAUSE }, + { "vscause", CSR_VSCAUSE, RVH }, + { "mtval", CSR_MTVAL }, + { "stval", CSR_STVAL }, + { "htval", CSR_HTVAL, RVH }, + { "mtval2", CSR_MTVAL2, RVH }, + { "mscratch", CSR_MSCRATCH }, + { "sscratch", CSR_SSCRATCH }, + { "satp", CSR_SATP}, + }; + + bool rv32 = riscv_cpu_mxl(env) == MXL_RV32; + + for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { + target_ulong val = 0; + RISCVException result; + + if (dump_csrs[i].misa && !riscv_has_ext(env, dump_csrs[i].misa)) { + continue; + } + if (dump_csrs[i].rv32 && !rv32) { + continue; + } + + result = riscv_csrrw_debug(env, dump_csrs[i].csrno, &val, 0, 0); + assert(result == RISCV_EXCP_NONE); + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + dump_csrs[i].name, val); + } } - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", - (target_ulong)env->vsstatus); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); #endif for (i = 0; i < 32; i++) { From patchwork Tue Oct 19 00:01:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515948 Delivered-To: patch@linaro.org Received: by 2002:ac0:cd8c:0:0:0:0:0 with SMTP id d12csp77637imp; Mon, 18 Oct 2021 17:16:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwEVBL+Hw2wsJiT7cMtp+kzHF9xuJJ9k4gCP2MKS4MOVZm9FcI3quecQfbwhP06ijuR9b7 X-Received: by 2002:a05:6102:1609:: with SMTP id cu9mr27950465vsb.55.1634602567351; Mon, 18 Oct 2021 17:16:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634602567; cv=none; d=google.com; s=arc-20160816; b=FCKFys8sZYjqA/MBq4pFMj2lGcQEPCeAmu8WpuhWB/18YVPq86VSLqSDHM2gAeOXAw kLnV3cjQ6PBuPktDTDliB5Yj0pEPnEGLSzZ40+yqINVY9VH2qd6Uhu1q+S9O4erph4Ze oVoHV2ilu/1H1dsMGNEqtK/MjtBrGat55nBNJh8QY7cgAZod0uYu3EBJPGCeJGPNYIMd 81ZplIRvnEJbbx/Jl9wWOYqoqTiOZPPHAMrhfYt0yxBiO0b4KAI+GKPqXHlzZtlsIyNv 2DiBn6kHPS8ITKP5NhQeJyglapDdN6qccEcTh6CxBOmO15MWuIO1G22cK4/4xVAu4GK+ A/qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=XGRntGz593OLzsAlQ4peZOHZeqbLYQi+6QYHLP1rd+LBsXLd1loMsGQA3OJaCTdavC PH+Vv7BUnit3KbwHUf33G9L1iYHJHxOfVj7l1ks5QPtMmSJtDC3oWERw7T+/eDwUOwQg PuUsdpm0myn/IlUHz5dQFg8RCmpwagk+cPa5pLot6GNV05WwCd2mrobrbnLcFUxs9BZi PN+EApGl/foTSrARMJDZFhxLQLcT38Ac2jCjeylEdDSPwEs/vdW8idHXVvQg5u6YoUvs TOvnc+RfrahGoP7+4tu5HiLqna+A3VG/kf6DjymENyYjyRIwM4D1y+DQ6kaHXcH+vzvg DfVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mOa5XS+C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b23si11906300uam.33.2021.10.18.17.16.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Oct 2021 17:16:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mOa5XS+C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mccnW-000500-OS for patch@linaro.org; Mon, 18 Oct 2021 20:16:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mccZU-00053E-Vz for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:41 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:38622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mccZI-0001nj-4O for qemu-devel@nongnu.org; Mon, 18 Oct 2021 20:01:36 -0400 Received: by mail-pf1-x431.google.com with SMTP id k26so16054030pfi.5 for ; Mon, 18 Oct 2021 17:01:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=mOa5XS+CnoMwE7kXn80tS1WwIXH2ThuYKDDNaWe/fjMKBUJ1MeeURqmvqUNSCrAVEB xSkp9wf6mXBJNhuaa4TOPC1H6MmMKJbBNSkWd7mnIL3Irx8PmaBjjaigvHE9BRTTH2z+ ajajCCOJq8EM53r6SnSGiQz2AauSZWeNTqZVmLen4CYMdk+X//UrPR5f1ddSdqLAbcbd M7SMcC0+IQ5Wqg/a6IudtHov/WhL9IrBcQ02Y1PHWZe/BAdTlJ66rlw0MFUHvjaOu3lK 2lLMJnRTJCYmmkBsa/nDDdm8rGOEC5R2MNLs314NJc5uLmmqqcK3vW6QHWMf6Xuec95u nFVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RT2VpKAEfApm7ELgrgjYw2HluCj4mChRvtgjB+9QAL8=; b=gCa0+0JBAGjEi5R9KirnoEZlSjbfT0KYNWgZXevtzCPpFGDSTCu/Gw+x+M1zTWFNNN 40MysqUSmWLwaKK7ohwvJBow3SQqUpSqAHhVItnLnXH/YjVYTZfOSq5tcQHegKwhpioF chOyKf3+sqLGiLw1AqQE3aXx/NZhX3VsNO6k7VZIQA9RiLb1Z8ifjxc8DwXFkO3NPRLA ms2/5d40I+gJAiBqD0fqYBffw73x50ep0v9/qvpQmS9IOqzOQN0dRB6LbVYxka+QOSay Oizkc+3EWN9OK9gO4p1j60gCO8923MtM3GBylMTECMUAAcz2hPuBPG2zgIB0fKxh/6bB +5qQ== X-Gm-Message-State: AOAM532vwDrmXiVWYEpSse3f/OXxRoTNQcUYShD3rxZsoq5zvEAFL3Qe afG3oovPFE2EXOqNatBHpHjHPmv+yE+eDg== X-Received: by 2002:a63:f62:: with SMTP id 34mr25909411pgp.159.1634601681515; Mon, 18 Oct 2021 17:01:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q14sm3068220pfk.3.2021.10.18.17.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 17:01:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand Date: Mon, 18 Oct 2021 17:01:08 -0700 Message-Id: <20211019000108.3678724-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org> References: <20211019000108.3678724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The position of this read-only field is dependent on the current cpu width. Rather than having to compute that difference in many places, compute it only on read. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 37 ++++++++++++++++++++++--------------- target/riscv/translate.c | 5 ++--- 3 files changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 429afd1f48..0d1132f39d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -185,10 +185,9 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL | sd; + MSTATUS64_UXL; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c4a479ddd2..69e4d65fcd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -477,10 +477,28 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno, } /* Machine Trap Setup */ + +/* We do not store SD explicitly, only compute it on demand. */ +static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) +{ + if ((status & MSTATUS_FS) == MSTATUS_FS || + (status & MSTATUS_XS) == MSTATUS_XS) { + switch (xl) { + case MXL_RV32: + return status | MSTATUS32_SD; + case MXL_RV64: + return status | MSTATUS64_SD; + default: + g_assert_not_reached(); + } + } + return status; +} + static RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mstatus; + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); return RISCV_EXCP_NONE; } @@ -498,7 +516,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, { uint64_t mstatus = env->mstatus; uint64_t mask = 0; - int dirty; /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -520,12 +537,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mstatus = (mstatus & ~mask) | (val & mask); - dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | - ((mstatus & MSTATUS_XS) == MSTATUS_XS); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mstatus = set_field(mstatus, MSTATUS32_SD, dirty); - } else { - mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + if (riscv_cpu_mxl(env) == MXL_RV64) { /* SXL and UXL fields are for now read only */ mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); @@ -798,13 +810,8 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, { target_ulong mask = (sstatus_v1_10_mask); - if (riscv_cpu_mxl(env) == MXL_RV32) { - mask |= SSTATUS32_SD; - } else { - mask |= SSTATUS64_SD; - } - - *val = env->mstatus & mask; + /* TODO: Use SXL not MXL. */ + *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index de013fbf9b..35245aafa7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; - target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; if (ctx->mstatus_fs != MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ @@ -288,7 +287,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_temp_free(tmp); } @@ -299,7 +298,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_temp_free(tmp); }