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Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 142 +++++++++++++++++++++++++------------------------ 1 file changed, 72 insertions(+), 70 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index c239c3bd07..148e360fc6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -41,7 +41,7 @@ typedef struct TempOptInfo { TCGTemp *prev_copy; TCGTemp *next_copy; uint64_t val; - uint64_t mask; + uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */ } TempOptInfo; static inline TempOptInfo *ts_info(TCGTemp *ts) @@ -81,7 +81,7 @@ static void reset_ts(TCGTemp *ts) ti->next_copy = ts; ti->prev_copy = ts; ti->is_const = false; - ti->mask = -1; + ti->z_mask = -1; } static void reset_temp(TCGArg arg) @@ -111,14 +111,14 @@ static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts) if (ts->kind == TEMP_CONST) { ti->is_const = true; ti->val = ts->val; - ti->mask = ts->val; + ti->z_mask = ts->val; if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { /* High bits of a 32-bit quantity are garbage. */ - ti->mask |= ~0xffffffffull; + ti->z_mask |= ~0xffffffffull; } } else { ti->is_const = false; - ti->mask = -1; + ti->z_mask = -1; } } @@ -186,7 +186,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) const TCGOpDef *def; TempOptInfo *di; TempOptInfo *si; - uint64_t mask; + uint64_t z_mask; TCGOpcode new_op; if (ts_are_copies(dst_ts, src_ts)) { @@ -210,12 +210,12 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) op->args[0] = dst; op->args[1] = src; - mask = si->mask; + z_mask = si->z_mask; if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { /* High bits of the destination are now garbage. */ - mask |= ~0xffffffffull; + z_mask |= ~0xffffffffull; } - di->mask = mask; + di->z_mask = z_mask; if (src_ts->type == dst_ts->type) { TempOptInfo *ni = ts_info(si->next_copy); @@ -621,7 +621,7 @@ void tcg_optimize(TCGContext *s) } QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { - uint64_t mask, partmask, affected, tmp; + uint64_t z_mask, partmask, affected, tmp; int nb_oargs, nb_iargs; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; @@ -855,170 +855,172 @@ void tcg_optimize(TCGContext *s) /* Simplify using known-zero bits. Currently only ops with a single output argument is supported. */ - mask = -1; + z_mask = -1; affected = -1; switch (opc) { CASE_OP_32_64(ext8s): - if ((arg_info(op->args[1])->mask & 0x80) != 0) { + if ((arg_info(op->args[1])->z_mask & 0x80) != 0) { break; } QEMU_FALLTHROUGH; CASE_OP_32_64(ext8u): - mask = 0xff; + z_mask = 0xff; goto and_const; CASE_OP_32_64(ext16s): - if ((arg_info(op->args[1])->mask & 0x8000) != 0) { + if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) { break; } QEMU_FALLTHROUGH; CASE_OP_32_64(ext16u): - mask = 0xffff; + z_mask = 0xffff; goto and_const; case INDEX_op_ext32s_i64: - if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { + if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { break; } QEMU_FALLTHROUGH; case INDEX_op_ext32u_i64: - mask = 0xffffffffU; + z_mask = 0xffffffffU; goto and_const; CASE_OP_32_64(and): - mask = arg_info(op->args[2])->mask; + z_mask = arg_info(op->args[2])->z_mask; if (arg_is_const(op->args[2])) { and_const: - affected = arg_info(op->args[1])->mask & ~mask; + affected = arg_info(op->args[1])->z_mask & ~z_mask; } - mask = arg_info(op->args[1])->mask & mask; + z_mask = arg_info(op->args[1])->z_mask & z_mask; break; case INDEX_op_ext_i32_i64: - if ((arg_info(op->args[1])->mask & 0x80000000) != 0) { + if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { break; } QEMU_FALLTHROUGH; case INDEX_op_extu_i32_i64: /* We do not compute affected as it is a size changing op. */ - mask = (uint32_t)arg_info(op->args[1])->mask; + z_mask = (uint32_t)arg_info(op->args[1])->z_mask; break; CASE_OP_32_64(andc): /* Known-zeros does not imply known-ones. Therefore unless op->args[2] is constant, we can't infer anything from it. */ if (arg_is_const(op->args[2])) { - mask = ~arg_info(op->args[2])->mask; + z_mask = ~arg_info(op->args[2])->z_mask; goto and_const; } /* But we certainly know nothing outside args[1] may be set. */ - mask = arg_info(op->args[1])->mask; + z_mask = arg_info(op->args[1])->z_mask; break; case INDEX_op_sar_i32: if (arg_is_const(op->args[2])) { tmp = arg_info(op->args[2])->val & 31; - mask = (int32_t)arg_info(op->args[1])->mask >> tmp; + z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp; } break; case INDEX_op_sar_i64: if (arg_is_const(op->args[2])) { tmp = arg_info(op->args[2])->val & 63; - mask = (int64_t)arg_info(op->args[1])->mask >> tmp; + z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp; } break; case INDEX_op_shr_i32: if (arg_is_const(op->args[2])) { tmp = arg_info(op->args[2])->val & 31; - mask = (uint32_t)arg_info(op->args[1])->mask >> tmp; + z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp; } break; case INDEX_op_shr_i64: if (arg_is_const(op->args[2])) { tmp = arg_info(op->args[2])->val & 63; - mask = (uint64_t)arg_info(op->args[1])->mask >> tmp; + z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp; } break; case INDEX_op_extrl_i64_i32: - mask = (uint32_t)arg_info(op->args[1])->mask; + z_mask = (uint32_t)arg_info(op->args[1])->z_mask; break; case INDEX_op_extrh_i64_i32: - mask = (uint64_t)arg_info(op->args[1])->mask >> 32; + z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32; break; CASE_OP_32_64(shl): if (arg_is_const(op->args[2])) { tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); - mask = arg_info(op->args[1])->mask << tmp; + z_mask = arg_info(op->args[1])->z_mask << tmp; } break; CASE_OP_32_64(neg): /* Set to 1 all bits to the left of the rightmost. */ - mask = -(arg_info(op->args[1])->mask - & -arg_info(op->args[1])->mask); + z_mask = -(arg_info(op->args[1])->z_mask + & -arg_info(op->args[1])->z_mask); break; CASE_OP_32_64(deposit): - mask = deposit64(arg_info(op->args[1])->mask, - op->args[3], op->args[4], - arg_info(op->args[2])->mask); + z_mask = deposit64(arg_info(op->args[1])->z_mask, + op->args[3], op->args[4], + arg_info(op->args[2])->z_mask); break; CASE_OP_32_64(extract): - mask = extract64(arg_info(op->args[1])->mask, - op->args[2], op->args[3]); + z_mask = extract64(arg_info(op->args[1])->z_mask, + op->args[2], op->args[3]); if (op->args[2] == 0) { - affected = arg_info(op->args[1])->mask & ~mask; + affected = arg_info(op->args[1])->z_mask & ~z_mask; } break; CASE_OP_32_64(sextract): - mask = sextract64(arg_info(op->args[1])->mask, - op->args[2], op->args[3]); - if (op->args[2] == 0 && (tcg_target_long)mask >= 0) { - affected = arg_info(op->args[1])->mask & ~mask; + z_mask = sextract64(arg_info(op->args[1])->z_mask, + op->args[2], op->args[3]); + if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) { + affected = arg_info(op->args[1])->z_mask & ~z_mask; } break; CASE_OP_32_64(or): CASE_OP_32_64(xor): - mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask; + z_mask = arg_info(op->args[1])->z_mask + | arg_info(op->args[2])->z_mask; break; case INDEX_op_clz_i32: case INDEX_op_ctz_i32: - mask = arg_info(op->args[2])->mask | 31; + z_mask = arg_info(op->args[2])->z_mask | 31; break; case INDEX_op_clz_i64: case INDEX_op_ctz_i64: - mask = arg_info(op->args[2])->mask | 63; + z_mask = arg_info(op->args[2])->z_mask | 63; break; case INDEX_op_ctpop_i32: - mask = 32 | 31; + z_mask = 32 | 31; break; case INDEX_op_ctpop_i64: - mask = 64 | 63; + z_mask = 64 | 63; break; CASE_OP_32_64(setcond): case INDEX_op_setcond2_i32: - mask = 1; + z_mask = 1; break; CASE_OP_32_64(movcond): - mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask; + z_mask = arg_info(op->args[3])->z_mask + | arg_info(op->args[4])->z_mask; break; CASE_OP_32_64(ld8u): - mask = 0xff; + z_mask = 0xff; break; CASE_OP_32_64(ld16u): - mask = 0xffff; + z_mask = 0xffff; break; case INDEX_op_ld32u_i64: - mask = 0xffffffffu; + z_mask = 0xffffffffu; break; CASE_OP_32_64(qemu_ld): @@ -1026,43 +1028,43 @@ void tcg_optimize(TCGContext *s) MemOpIdx oi = op->args[nb_oargs + nb_iargs]; MemOp mop = get_memop(oi); if (!(mop & MO_SIGN)) { - mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; + z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; } } break; CASE_OP_32_64(bswap16): - mask = arg_info(op->args[1])->mask; - if (mask <= 0xffff) { + z_mask = arg_info(op->args[1])->z_mask; + if (z_mask <= 0xffff) { op->args[2] |= TCG_BSWAP_IZ; } - mask = bswap16(mask); + z_mask = bswap16(z_mask); switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { case TCG_BSWAP_OZ: break; case TCG_BSWAP_OS: - mask = (int16_t)mask; + z_mask = (int16_t)z_mask; break; default: /* undefined high bits */ - mask |= MAKE_64BIT_MASK(16, 48); + z_mask |= MAKE_64BIT_MASK(16, 48); break; } break; case INDEX_op_bswap32_i64: - mask = arg_info(op->args[1])->mask; - if (mask <= 0xffffffffu) { + z_mask = arg_info(op->args[1])->z_mask; + if (z_mask <= 0xffffffffu) { op->args[2] |= TCG_BSWAP_IZ; } - mask = bswap32(mask); + z_mask = bswap32(z_mask); switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { case TCG_BSWAP_OZ: break; case TCG_BSWAP_OS: - mask = (int32_t)mask; + z_mask = (int32_t)z_mask; break; default: /* undefined high bits */ - mask |= MAKE_64BIT_MASK(32, 32); + z_mask |= MAKE_64BIT_MASK(32, 32); break; } break; @@ -1074,9 +1076,9 @@ void tcg_optimize(TCGContext *s) /* 32-bit ops generate 32-bit results. For the result is zero test below, we can ignore high bits, but for further optimizations we need to record that the high bits contain garbage. */ - partmask = mask; + partmask = z_mask; if (!(def->flags & TCG_OPF_64BIT)) { - mask |= ~(tcg_target_ulong)0xffffffffu; + z_mask |= ~(tcg_target_ulong)0xffffffffu; partmask &= 0xffffffffu; affected &= 0xffffffffu; } @@ -1472,7 +1474,7 @@ void tcg_optimize(TCGContext *s) vs the high word of the input. */ do_setcond_high: reset_temp(op->args[0]); - arg_info(op->args[0])->mask = 1; + arg_info(op->args[0])->z_mask = 1; op->opc = INDEX_op_setcond_i32; op->args[1] = op->args[2]; op->args[2] = op->args[4]; @@ -1498,7 +1500,7 @@ void tcg_optimize(TCGContext *s) } do_setcond_low: reset_temp(op->args[0]); - arg_info(op->args[0])->mask = 1; + arg_info(op->args[0])->z_mask = 1; op->opc = INDEX_op_setcond_i32; op->args[2] = op->args[3]; op->args[3] = op->args[5]; @@ -1543,7 +1545,7 @@ void tcg_optimize(TCGContext *s) /* Default case: we know nothing about operation (or were unable to compute the operation result) so no propagation is done. We trash everything if the operation is the end of a basic - block, otherwise we only trash the output args. "mask" is + block, otherwise we only trash the output args. "z_mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { memset(&temps_used, 0, sizeof(temps_used)); @@ -1554,7 +1556,7 @@ void tcg_optimize(TCGContext *s) /* Save the corresponding known-zero bits mask for the first output argument (only one supported so far). */ if (i == 0) { - arg_info(op->args[i])->mask = mask; + arg_info(op->args[i])->z_mask = z_mask; } } } From patchwork Thu Oct 21 21:04:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516070 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp325067imj; Thu, 21 Oct 2021 14:07:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzElxY91IJgRtYKcjWX7EkyQVasgr/pn0fA1XVh3IgFuW+r3TgXr3X55V0c1h6bonciZuzq X-Received: by 2002:a9d:5f85:: with SMTP id g5mr6664293oti.139.1634850464362; Thu, 21 Oct 2021 14:07:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850464; cv=none; d=google.com; s=arc-20160816; b=QtnsbJE1i4VL/sbrKMb0m7sm4/ReiNcHwH51vTXA8qr4eqvDIDMVnkhNStreA7qzuo Et1uuSbgQpV7iR9e/TuqR6+TdlQ41rhYVKXUPBg1u6wC0tK5p+aVvssmg6BhPQJrrUVe /DcTOS3D/lSbtnZ3sB0aorTFrq2Tz0Wjgy9aWJ6WEeRQIx5UnWgin3q5LSjt5EqU3Co8 utbvOH583GwmLMfCIQzX1m/zVSmexa/78k4gZBARw9XTUa6GF3wvMU6fHd3BxZ/oCzkD mEy+/72vQ4iGD4ptXLV/FReE8IRvhk+baK1wKdz4q3RW5cOTQ8Yf6OczANFo8tHajg39 yjXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3tm/mv7jQgw3lkRY+9RCN5oOaA0owVdGo1tTQjUcFmI=; b=j2TDeUldAlgGbAHd2tDy0Lw8wF5tBhQx/NAVC7zwRewF4ZcriX00YPUozhgrWuflAK HTbPK3G14wjMuy6JbWLLA3uRkcw9B521uIdJRcIGYpZqg7roQxoHXOdeVZOawlH0UCKd Eb3Vm1fnaitdKKnJ7H3dT2UHXzH/LykiLwSL7cpaMhSDrBFf1eHyEz0hJK7Hk0MKkFEz gUldrazqbs+EENZLOGlLtI7iTiT0TFHlC7H5G/VraXDbXJGrbv96WhRBR1GVz88h7s1w GH0DeGrokYFMszEXL+xB+qtw8LbT7L8ssm/VycMamCVda3G7XmvTwXJdvdFgg8ZUhUa4 2PoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=r6afmPtC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 77 ++++++++++++++++++++++++++------------------------ 1 file changed, 40 insertions(+), 37 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index 148e360fc6..b76991215e 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -44,6 +44,10 @@ typedef struct TempOptInfo { uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */ } TempOptInfo; +typedef struct OptContext { + TCGTempSet temps_used; +} OptContext; + static inline TempOptInfo *ts_info(TCGTemp *ts) { return ts->state_ptr; @@ -90,15 +94,15 @@ static void reset_temp(TCGArg arg) } /* Initialize and activate a temporary. */ -static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts) +static void init_ts_info(OptContext *ctx, TCGTemp *ts) { size_t idx = temp_idx(ts); TempOptInfo *ti; - if (test_bit(idx, temps_used->l)) { + if (test_bit(idx, ctx->temps_used.l)) { return; } - set_bit(idx, temps_used->l); + set_bit(idx, ctx->temps_used.l); ti = ts->state_ptr; if (ti == NULL) { @@ -122,9 +126,9 @@ static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts) } } -static void init_arg_info(TCGTempSet *temps_used, TCGArg arg) +static void init_arg_info(OptContext *ctx, TCGArg arg) { - init_ts_info(temps_used, arg_temp(arg)); + init_ts_info(ctx, arg_temp(arg)); } static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) @@ -229,7 +233,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } -static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used, +static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx, TCGOp *op, TCGArg dst, uint64_t val) { const TCGOpDef *def = &tcg_op_defs[op->opc]; @@ -246,7 +250,7 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used, /* Convert movi to mov with constant temp. */ tv = tcg_constant_internal(type, val); - init_ts_info(temps_used, tv); + init_ts_info(ctx, tv); tcg_opt_gen_mov(s, op, dst, temp_arg(tv)); } @@ -605,7 +609,7 @@ void tcg_optimize(TCGContext *s) { int nb_temps, nb_globals, i; TCGOp *op, *op_next, *prev_mb = NULL; - TCGTempSet temps_used; + OptContext ctx = {}; /* Array VALS has an element for each temp. If this temp holds a constant then its value is kept in VALS' element. @@ -615,7 +619,6 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; - memset(&temps_used, 0, sizeof(temps_used)); for (i = 0; i < nb_temps; ++i) { s->temps[i].state_ptr = NULL; } @@ -634,14 +637,14 @@ void tcg_optimize(TCGContext *s) for (i = 0; i < nb_oargs + nb_iargs; i++) { TCGTemp *ts = arg_temp(op->args[i]); if (ts) { - init_ts_info(&temps_used, ts); + init_ts_info(&ctx, ts); } } } else { nb_oargs = def->nb_oargs; nb_iargs = def->nb_iargs; for (i = 0; i < nb_oargs + nb_iargs; i++) { - init_arg_info(&temps_used, op->args[i]); + init_arg_info(&ctx, op->args[i]); } } @@ -720,7 +723,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(rotr): if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); continue; } break; @@ -1085,7 +1088,7 @@ void tcg_optimize(TCGContext *s) if (partmask == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); continue; } if (affected == 0) { @@ -1102,7 +1105,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mulsh): if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); continue; } break; @@ -1129,7 +1132,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(sub): CASE_OP_32_64_VEC(xor): if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); continue; } break; @@ -1149,7 +1152,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = arg_info(op->args[1])->val; tmp = dup_const(TCGOP_VECE(op), tmp); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1157,7 +1160,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_dup2_vec: assert(TCG_TARGET_REG_BITS == 32); if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], + tcg_opt_gen_movi(s, &ctx, op, op->args[0], deposit64(arg_info(op->args[1])->val, 32, 32, arg_info(op->args[2])->val)); break; @@ -1183,7 +1186,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extrh_i64_i32: if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1194,7 +1197,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, op->args[2]); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1224,7 +1227,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1235,7 +1238,7 @@ void tcg_optimize(TCGContext *s) TCGArg v = arg_info(op->args[1])->val; if (v != 0) { tmp = do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); } else { tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); } @@ -1248,7 +1251,7 @@ void tcg_optimize(TCGContext *s) tmp = deposit64(arg_info(op->args[1])->val, op->args[3], op->args[4], arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1257,7 +1260,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1266,7 +1269,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1283,7 +1286,7 @@ void tcg_optimize(TCGContext *s) tmp = (int32_t)(((uint32_t)v1 >> shr) | ((uint32_t)v2 << (32 - shr))); } - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1292,7 +1295,7 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); if (tmp != 2) { - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); break; } goto do_default; @@ -1302,7 +1305,7 @@ void tcg_optimize(TCGContext *s) op->args[1], op->args[2]); if (tmp != 2) { if (tmp) { - memset(&temps_used, 0, sizeof(temps_used)); + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); op->opc = INDEX_op_br; op->args[0] = op->args[3]; } else { @@ -1358,8 +1361,8 @@ void tcg_optimize(TCGContext *s) rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a); - tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a); + tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32)); break; } goto do_default; @@ -1374,8 +1377,8 @@ void tcg_optimize(TCGContext *s) rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r); - tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r); + tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32)); break; } goto do_default; @@ -1386,7 +1389,7 @@ void tcg_optimize(TCGContext *s) if (tmp != 2) { if (tmp) { do_brcond_true: - memset(&temps_used, 0, sizeof(temps_used)); + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); op->opc = INDEX_op_br; op->args[0] = op->args[5]; } else { @@ -1402,7 +1405,7 @@ void tcg_optimize(TCGContext *s) /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - memset(&temps_used, 0, sizeof(temps_used)); + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); op->opc = INDEX_op_brcond_i32; op->args[0] = op->args[1]; op->args[1] = op->args[3]; @@ -1428,7 +1431,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - memset(&temps_used, 0, sizeof(temps_used)); + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); op->opc = INDEX_op_brcond_i32; op->args[1] = op->args[2]; op->args[2] = op->args[4]; @@ -1463,7 +1466,7 @@ void tcg_optimize(TCGContext *s) op->args[5]); if (tmp != 2) { do_setcond_const: - tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp); + tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); } else if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) && arg_is_const(op->args[3]) @@ -1533,7 +1536,7 @@ void tcg_optimize(TCGContext *s) if (!(tcg_call_flags(op) & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { for (i = 0; i < nb_globals; i++) { - if (test_bit(i, temps_used.l)) { + if (test_bit(i, ctx.temps_used.l)) { reset_ts(&s->temps[i]); } } @@ -1548,7 +1551,7 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "z_mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - memset(&temps_used, 0, sizeof(temps_used)); + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); } else { do_reset_output: for (i = 0; i < nb_oargs; i++) { From patchwork Thu Oct 21 21:04:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516074 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp329338imj; Thu, 21 Oct 2021 14:12:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy/gnh7Nt+Kq5XYHtuqg8eSSq2V/vpwrg6ofwdonRGSpRgQIS1cEo8kqN5Me8fz3juJZAPQ X-Received: by 2002:a9d:7985:: with SMTP id h5mr4331120otm.146.1634850745575; Thu, 21 Oct 2021 14:12:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850745; cv=none; d=google.com; s=arc-20160816; b=0FzGCy9aKMkS0MeWewh08pMjum6B8G6BtHs7ous5R/V69Q5q3hEniSNEsoxTZR7C1v QebiGtIlYsSonGxS/7RoR8ebT4mfy3mL/EIdpEcr7x9TTxmHhkdpExSKdHL+li2tnz4O ipUkTvCCbYJfvk32tb4QAMKzcJ2skUMtDe5BTTRz9Cckips2BPHAys+iS+QsWbu7NuAZ xjkvtPICi1En7dWZVbPRIUjMFzysXX1R+x7iU83iZAj2hkQS9Zr1OTnG1EqWzN+TjNgX Edqf1Ke2xHUGy7J6XCXSuHD58dD+mHgk5g9i1et4k07Gey1GfKslJX5+kIhkYWB/Lb4N a4jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HTEAzVkcMCO7a4k6lv4UnDVLadp4ueNJigeT/4NE84k=; b=iv/bbVtx9JO62XPWGgsuYxYMScmoXsHeFbJkdO0mDtOvySE097nXK8NsjWlAkUMwuI G0BFz6S6Qi0ZnuOKOohUDDLTm0W2Br1+ITTRfvZ9xDBq/8QPnwj4ySYINlcsDaNhPQ9U WeCY4y4eQ9nCKyQbzTUBuvX2a90DS9zI10lwVGYSGwno4N3a1MX5raxRcLLeuk8ayDdK rBptIOB3hJVWCW6P/huNYZ0+q3YZe389neNJTrgP1rC/XN47rFmqV1WPJKUphNPXSXcm SCikQkdCc5Yaniqa5Co2ni2rByndkBgum2SCzBlt8nViUnO2XqjF6lGIUPluaTSBc4IK 5lQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=idRccxEw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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When fully folding an opcode to mov/movi, use "continue" to process the next opcode, else break to fall into the final cleanup. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 190 ++++++++++++++++++++++++------------------------- 1 file changed, 94 insertions(+), 96 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index b76991215e..a37efff4d0 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1146,16 +1146,16 @@ void tcg_optimize(TCGContext *s) switch (opc) { CASE_OP_32_64_VEC(mov): tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); - break; + continue; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { tmp = arg_info(op->args[1])->val; tmp = dup_const(TCGOP_VECE(op), tmp); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; case INDEX_op_dup2_vec: assert(TCG_TARGET_REG_BITS == 32); @@ -1163,13 +1163,13 @@ void tcg_optimize(TCGContext *s) tcg_opt_gen_movi(s, &ctx, op, op->args[0], deposit64(arg_info(op->args[1])->val, 32, 32, arg_info(op->args[2])->val)); - break; + continue; } else if (args_are_copies(op->args[1], op->args[2])) { op->opc = INDEX_op_dup_vec; TCGOP_VECE(op) = MO_32; nb_iargs = 1; } - goto do_default; + break; CASE_OP_32_64(not): CASE_OP_32_64(neg): @@ -1187,9 +1187,9 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(bswap16): CASE_OP_32_64(bswap32): @@ -1198,9 +1198,9 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding(opc, arg_info(op->args[1])->val, op->args[2]); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(add): CASE_OP_32_64(sub): @@ -1228,9 +1228,9 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding(opc, arg_info(op->args[1])->val, arg_info(op->args[2])->val); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(clz): CASE_OP_32_64(ctz): @@ -1242,9 +1242,9 @@ void tcg_optimize(TCGContext *s) } else { tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); } - break; + continue; } - goto do_default; + break; CASE_OP_32_64(deposit): if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { @@ -1252,27 +1252,27 @@ void tcg_optimize(TCGContext *s) op->args[3], op->args[4], arg_info(op->args[2])->val); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(extract): if (arg_is_const(op->args[1])) { tmp = extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(sextract): if (arg_is_const(op->args[1])) { tmp = sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(extract2): if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { @@ -1287,40 +1287,40 @@ void tcg_optimize(TCGContext *s) ((uint32_t)v2 << (32 - shr))); } tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(setcond): tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); if (tmp != 2) { tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - break; + continue; } - goto do_default; + break; CASE_OP_32_64(brcond): tmp = do_constant_folding_cond(opc, op->args[0], op->args[1], op->args[2]); - if (tmp != 2) { - if (tmp) { - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - op->opc = INDEX_op_br; - op->args[0] = op->args[3]; - } else { - tcg_op_remove(s, op); - } + switch (tmp) { + case 0: + tcg_op_remove(s, op); + continue; + case 1: + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); + op->opc = opc = INDEX_op_br; + op->args[0] = op->args[3]; break; } - goto do_default; + break; CASE_OP_32_64(movcond): tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[5]); if (tmp != 2) { tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]); - break; + continue; } if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { uint64_t tv = arg_info(op->args[3])->val; @@ -1330,7 +1330,7 @@ void tcg_optimize(TCGContext *s) if (fv == 1 && tv == 0) { cond = tcg_invert_cond(cond); } else if (!(tv == 1 && fv == 0)) { - goto do_default; + break; } op->args[3] = cond; op->opc = opc = (opc == INDEX_op_movcond_i32 @@ -1338,7 +1338,7 @@ void tcg_optimize(TCGContext *s) : INDEX_op_setcond_i64); nb_iargs = 2; } - goto do_default; + break; case INDEX_op_add2_i32: case INDEX_op_sub2_i32: @@ -1363,9 +1363,9 @@ void tcg_optimize(TCGContext *s) rh = op->args[1]; tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a); tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32)); - break; + continue; } - goto do_default; + break; case INDEX_op_mulu2_i32: if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { @@ -1379,39 +1379,40 @@ void tcg_optimize(TCGContext *s) rh = op->args[1]; tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r); tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32)); - break; + continue; } - goto do_default; + break; case INDEX_op_brcond2_i32: tmp = do_constant_folding_cond2(&op->args[0], &op->args[2], op->args[4]); - if (tmp != 2) { - if (tmp) { - do_brcond_true: - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - op->opc = INDEX_op_br; - op->args[0] = op->args[5]; - } else { + if (tmp == 0) { do_brcond_false: - tcg_op_remove(s, op); - } - } else if ((op->args[4] == TCG_COND_LT - || op->args[4] == TCG_COND_GE) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0 - && arg_is_const(op->args[3]) - && arg_info(op->args[3])->val == 0) { + tcg_op_remove(s, op); + continue; + } + if (tmp == 1) { + do_brcond_true: + op->opc = opc = INDEX_op_br; + op->args[0] = op->args[5]; + break; + } + if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE) + && arg_is_const(op->args[2]) + && arg_info(op->args[2])->val == 0 + && arg_is_const(op->args[3]) + && arg_info(op->args[3])->val == 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - op->opc = INDEX_op_brcond_i32; + op->opc = opc = INDEX_op_brcond_i32; op->args[0] = op->args[1]; op->args[1] = op->args[3]; op->args[2] = op->args[4]; op->args[3] = op->args[5]; - } else if (op->args[4] == TCG_COND_EQ) { + break; + } + if (op->args[4] == TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ tmp = do_constant_folding_cond(INDEX_op_brcond_i32, @@ -1428,7 +1429,7 @@ void tcg_optimize(TCGContext *s) if (tmp == 0) { goto do_brcond_false; } else if (tmp != 1) { - goto do_default; + break; } do_brcond_low: memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); @@ -1436,7 +1437,9 @@ void tcg_optimize(TCGContext *s) op->args[1] = op->args[2]; op->args[2] = op->args[4]; op->args[3] = op->args[5]; - } else if (op->args[4] == TCG_COND_NE) { + break; + } + if (op->args[4] == TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ tmp = do_constant_folding_cond(INDEX_op_brcond_i32, @@ -1455,9 +1458,6 @@ void tcg_optimize(TCGContext *s) } else if (tmp == 1) { goto do_brcond_true; } - goto do_default; - } else { - goto do_default; } break; @@ -1467,12 +1467,13 @@ void tcg_optimize(TCGContext *s) if (tmp != 2) { do_setcond_const: tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); - } else if ((op->args[5] == TCG_COND_LT - || op->args[5] == TCG_COND_GE) - && arg_is_const(op->args[3]) - && arg_info(op->args[3])->val == 0 - && arg_is_const(op->args[4]) - && arg_info(op->args[4])->val == 0) { + continue; + } + if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) + && arg_is_const(op->args[3]) + && arg_info(op->args[3])->val == 0 + && arg_is_const(op->args[4]) + && arg_info(op->args[4])->val == 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_setcond_high: @@ -1482,7 +1483,9 @@ void tcg_optimize(TCGContext *s) op->args[1] = op->args[2]; op->args[2] = op->args[4]; op->args[3] = op->args[5]; - } else if (op->args[5] == TCG_COND_EQ) { + break; + } + if (op->args[5] == TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ tmp = do_constant_folding_cond(INDEX_op_setcond_i32, @@ -1499,7 +1502,7 @@ void tcg_optimize(TCGContext *s) if (tmp == 0) { goto do_setcond_high; } else if (tmp != 1) { - goto do_default; + break; } do_setcond_low: reset_temp(op->args[0]); @@ -1507,7 +1510,9 @@ void tcg_optimize(TCGContext *s) op->opc = INDEX_op_setcond_i32; op->args[2] = op->args[3]; op->args[3] = op->args[5]; - } else if (op->args[5] == TCG_COND_NE) { + break; + } + if (op->args[5] == TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ tmp = do_constant_folding_cond(INDEX_op_setcond_i32, @@ -1526,14 +1531,21 @@ void tcg_optimize(TCGContext *s) } else if (tmp == 1) { goto do_setcond_const; } - goto do_default; - } else { - goto do_default; } break; - case INDEX_op_call: - if (!(tcg_call_flags(op) + default: + break; + } + + /* Some of the folding above can change opc. */ + opc = op->opc; + def = &tcg_op_defs[opc]; + if (def->flags & TCG_OPF_BB_END) { + memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); + } else { + if (opc == INDEX_op_call && + !(tcg_call_flags(op) & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { for (i = 0; i < nb_globals; i++) { if (test_bit(i, ctx.temps_used.l)) { @@ -1541,29 +1553,15 @@ void tcg_optimize(TCGContext *s) } } } - goto do_reset_output; - default: - do_default: - /* Default case: we know nothing about operation (or were unable - to compute the operation result) so no propagation is done. - We trash everything if the operation is the end of a basic - block, otherwise we only trash the output args. "z_mask" is - the non-zero bits mask for the first output arg. */ - if (def->flags & TCG_OPF_BB_END) { - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - } else { - do_reset_output: - for (i = 0; i < nb_oargs; i++) { - reset_temp(op->args[i]); - /* Save the corresponding known-zero bits mask for the - first output argument (only one supported so far). */ - if (i == 0) { - arg_info(op->args[i])->z_mask = z_mask; - } + for (i = 0; i < nb_oargs; i++) { + reset_temp(op->args[i]); + /* Save the corresponding known-zero bits mask for the + first output argument (only one supported so far). */ + if (i == 0) { + arg_info(op->args[i])->z_mask = z_mask; } } - break; } /* Eliminate duplicate and redundant fence instructions. */ From patchwork Thu Oct 21 21:04:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516081 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp335681imj; Thu, 21 Oct 2021 14:19:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyrw6dUqpMn4ocuILfMsB1RGh0w5mMVAGjm596bOgjL2rw3HjxYrBm7I6nu8sBSq8GS+Kc2 X-Received: by 2002:a05:6830:134a:: with SMTP id r10mr6876735otq.141.1634851147613; Thu, 21 Oct 2021 14:19:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851147; cv=none; d=google.com; s=arc-20160816; b=vGUdpOkEmD4WMWPC2SzpX+HtwrOaMDZ3Oq5tFdHAn1vJLrMrbl5n0NtutetPjmBNWU uGQ9qimfFBVTEjokwUcJkvGxs8QI2H1yLNC6Vq40huGV9BqAAp3J3JGGZY4Wq3KinIf7 0sfprdR8FpOqOz3E8DaRbDXCAtbrdppdQ6RbVLROvTBgoG+tska9w7WhUw/pTR/7JEfB tkUTwfI9GpHBhKH9ALD5DllUwP3R6MsAnPl75V9WDbGpZSrGkWmSbvC488ccQdmmYx/5 3k+MAKJ5VbVSs90cVo17Z7qpBg1B5lvQdQ54E2dTYJ4hZ+xdDixIyWh7Y2AKnAKpS68i ce1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5/xA01W4KeTA9PL1ecjuRsphIv0Hw/RH1bb0Ef8kKFU=; b=03ovHqFneCbjrJwJLE3Q8bXgpBqubJ1EDWgjAA4RS3hysKxY2ZW//7s2hYqb5RO8CN QYJMlGB+aCWKHY0iHLf/CLaYcgucp6DUQbzwZAu2qnwY/bBlKWxGofCF1YabVM4AJwve r4yqnqLJxWdMNJj/2dEHPt3d6Rsqf/CDX/P4WIl9umiGppfgOw5vVM2aIuRoE9v+SHW0 TT92MARbWxy6oNj/yhMMUO18nNyEPRlA+GBNHGdftE3wv56LGam9CZROK75Tyj1s7BLE E0f4se/b82Jgxzy5mtwWBW+vLyjanTtRjoSbYGWFeV2pGJWmRkqm6lqDQp9MHv/BpH9m L3LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wjxfVPmP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 67 +++++++++++++++++++++++++------------------------- 1 file changed, 34 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index a37efff4d0..627a5b39f6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -45,6 +45,7 @@ typedef struct TempOptInfo { } TempOptInfo; typedef struct OptContext { + TCGContext *tcg; TCGTempSet temps_used; } OptContext; @@ -183,7 +184,7 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) +static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) { TCGTemp *dst_ts = arg_temp(dst); TCGTemp *src_ts = arg_temp(src); @@ -194,7 +195,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) TCGOpcode new_op; if (ts_are_copies(dst_ts, src_ts)) { - tcg_op_remove(s, op); + tcg_op_remove(ctx->tcg, op); return; } @@ -233,8 +234,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src) } } -static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx, - TCGOp *op, TCGArg dst, uint64_t val) +static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, + TCGArg dst, uint64_t val) { const TCGOpDef *def = &tcg_op_defs[op->opc]; TCGType type; @@ -251,7 +252,7 @@ static void tcg_opt_gen_movi(TCGContext *s, OptContext *ctx, /* Convert movi to mov with constant temp. */ tv = tcg_constant_internal(type, val); init_ts_info(ctx, tv); - tcg_opt_gen_mov(s, op, dst, temp_arg(tv)); + tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); } static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) @@ -609,7 +610,7 @@ void tcg_optimize(TCGContext *s) { int nb_temps, nb_globals, i; TCGOp *op, *op_next, *prev_mb = NULL; - OptContext ctx = {}; + OptContext ctx = { .tcg = s }; /* Array VALS has an element for each temp. If this temp holds a constant then its value is kept in VALS' element. @@ -723,7 +724,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(rotr): if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == 0) { - tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); + tcg_opt_gen_movi(&ctx, op, op->args[0], 0); continue; } break; @@ -838,7 +839,7 @@ void tcg_optimize(TCGContext *s) if (!arg_is_const(op->args[1]) && arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); continue; } break; @@ -848,7 +849,7 @@ void tcg_optimize(TCGContext *s) if (!arg_is_const(op->args[1]) && arg_is_const(op->args[2]) && arg_info(op->args[2])->val == -1) { - tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); continue; } break; @@ -1088,12 +1089,12 @@ void tcg_optimize(TCGContext *s) if (partmask == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); + tcg_opt_gen_movi(&ctx, op, op->args[0], 0); continue; } if (affected == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); continue; } @@ -1105,7 +1106,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mulsh): if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); + tcg_opt_gen_movi(&ctx, op, op->args[0], 0); continue; } break; @@ -1118,7 +1119,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(or): CASE_OP_32_64_VEC(and): if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); continue; } break; @@ -1132,7 +1133,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(sub): CASE_OP_32_64_VEC(xor): if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_movi(s, &ctx, op, op->args[0], 0); + tcg_opt_gen_movi(&ctx, op, op->args[0], 0); continue; } break; @@ -1145,14 +1146,14 @@ void tcg_optimize(TCGContext *s) allocator where needed and possible. Also detect copies. */ switch (opc) { CASE_OP_32_64_VEC(mov): - tcg_opt_gen_mov(s, op, op->args[0], op->args[1]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); continue; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { tmp = arg_info(op->args[1])->val; tmp = dup_const(TCGOP_VECE(op), tmp); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1160,7 +1161,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_dup2_vec: assert(TCG_TARGET_REG_BITS == 32); if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tcg_opt_gen_movi(s, &ctx, op, op->args[0], + tcg_opt_gen_movi(&ctx, op, op->args[0], deposit64(arg_info(op->args[1])->val, 32, 32, arg_info(op->args[2])->val)); continue; @@ -1186,7 +1187,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extrh_i64_i32: if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1197,7 +1198,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, op->args[2]); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1227,7 +1228,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { tmp = do_constant_folding(opc, arg_info(op->args[1])->val, arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1238,9 +1239,9 @@ void tcg_optimize(TCGContext *s) TCGArg v = arg_info(op->args[1])->val; if (v != 0) { tmp = do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); } else { - tcg_opt_gen_mov(s, op, op->args[0], op->args[2]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]); } continue; } @@ -1251,7 +1252,7 @@ void tcg_optimize(TCGContext *s) tmp = deposit64(arg_info(op->args[1])->val, op->args[3], op->args[4], arg_info(op->args[2])->val); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1260,7 +1261,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = extract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1269,7 +1270,7 @@ void tcg_optimize(TCGContext *s) if (arg_is_const(op->args[1])) { tmp = sextract64(arg_info(op->args[1])->val, op->args[2], op->args[3]); - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1286,7 +1287,7 @@ void tcg_optimize(TCGContext *s) tmp = (int32_t)(((uint32_t)v1 >> shr) | ((uint32_t)v2 << (32 - shr))); } - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1295,7 +1296,7 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); if (tmp != 2) { - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } break; @@ -1319,7 +1320,7 @@ void tcg_optimize(TCGContext *s) tmp = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[5]); if (tmp != 2) { - tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]); + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]); continue; } if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { @@ -1361,8 +1362,8 @@ void tcg_optimize(TCGContext *s) rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)a); - tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a); + tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32)); continue; } break; @@ -1377,8 +1378,8 @@ void tcg_optimize(TCGContext *s) rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(s, &ctx, op, rl, (int32_t)r); - tcg_opt_gen_movi(s, &ctx, op2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r); + tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32)); continue; } break; @@ -1466,7 +1467,7 @@ void tcg_optimize(TCGContext *s) op->args[5]); if (tmp != 2) { do_setcond_const: - tcg_opt_gen_movi(s, &ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); continue; } if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) From patchwork Thu Oct 21 21:04:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516069 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp325016imj; Thu, 21 Oct 2021 14:07:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytSZ4ZOvZ1CyOS/u0aIETWCZkmhh0SQ3nsqLuGHOBixIjOBOUemDdxLSlXI32qkNodKsbK X-Received: by 2002:a9d:3e4a:: with SMTP id h10mr6628261otg.147.1634850460399; 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Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index 627a5b39f6..b875d76354 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -46,6 +46,7 @@ typedef struct TempOptInfo { typedef struct OptContext { TCGContext *tcg; + TCGOp *prev_mb; TCGTempSet temps_used; } OptContext; @@ -609,7 +610,7 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) void tcg_optimize(TCGContext *s) { int nb_temps, nb_globals, i; - TCGOp *op, *op_next, *prev_mb = NULL; + TCGOp *op, *op_next; OptContext ctx = { .tcg = s }; /* Array VALS has an element for each temp. @@ -1566,7 +1567,7 @@ void tcg_optimize(TCGContext *s) } /* Eliminate duplicate and redundant fence instructions. */ - if (prev_mb) { + if (ctx.prev_mb) { switch (opc) { case INDEX_op_mb: /* Merge two barriers of the same type into one, @@ -1580,7 +1581,7 @@ void tcg_optimize(TCGContext *s) * barrier. This is stricter than specified but for * the purposes of TCG is better than not optimizing. */ - prev_mb->args[0] |= op->args[0]; + ctx.prev_mb->args[0] |= op->args[0]; tcg_op_remove(s, op); break; @@ -1597,11 +1598,11 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_st_i64: case INDEX_op_call: /* Opcodes that touch guest memory stop the optimization. */ - prev_mb = NULL; + ctx.prev_mb = NULL; break; } } else if (opc == INDEX_op_mb) { - prev_mb = op; + ctx.prev_mb = op; } } } From patchwork Thu Oct 21 21:04:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516077 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp332624imj; Thu, 21 Oct 2021 14:16:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGJagWVO7vliyWPEaV/YYULwk0SyakkSvEczcoAuW0YuIjgoSS++d1wDuDOqw0xzcfQIKB X-Received: by 2002:aca:5bd6:: with SMTP id p205mr6060257oib.35.1634850965854; Thu, 21 Oct 2021 14:16:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850965; cv=none; d=google.com; s=arc-20160816; b=pAzbOB+0UBRBk76Fe315YQIaz1NlGqLEv5zd8ctFElscbflIa7DKXjcTU6ZnMICyNm MdGScH/v2B+Hqr86ejoQtemSjdRHAtJRHt+CnUwmcUBRNH0kdHIYz83OzTLyI10TJ9Na tuN8i2MizyObq53C3jPP0kUA5zTgkaY12hWOIq5QlTWFnwO43A7cQEabUyklhOoJ2DEZ a7LyqV/mIldtaeDjqobn98nJiCWs8Kaj/Obo3uKJinBUYl8nULO/BXn/y3xhlZBjJIyP QpcHxE2gASu4mkrJ5kRyUb4kRbamLlgrk2wLDrJwqOGjyigHF9EYgz94uiLSZpZFdVVb yRCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WL784dDelb2n11jVqBh0M/kFnuIJJZnBgr5d6GB5NwI=; b=HC/aBilK1IjrilUJldx8R+CHd/OCU0bXo/j7JuzxT0btmWDJskRHg2RKWzyaeeSHk3 40FYttGDxCcYtFxbUPo/YTdyCF4AAu71wgY0KB/DfPLDuTGeTOxh5zVBDT4g2RIO3N45 FPUUo6+kM3208o6Ej43LsUDsxXNOqBYYWrDvQEtFnwNKpmGfLL+W1UumdnUvw3bsl0YC u7rlC3EGYQ5DHH05zM//F8YLHjuOqcsXqbqaQRz2/jWZJXX/Yf0epoKTyWzU10hRkBHq QSeNVzevu6SCmlvI4KHG5W7M0B71jHDR2qr1PnQrDa1vORJZigUlgIwzO+kdyGdowFvG ztCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o+4VwUGN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f22si8914599oti.113.2021.10.21.14.16.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:16:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o+4VwUGN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfPw-0002uC-4o for patch@linaro.org; Thu, 21 Oct 2021 17:16:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfG0-0007Lr-V4 for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:50 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:43683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfFz-0004Ai-CJ for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:48 -0400 Received: by mail-pf1-x430.google.com with SMTP id 187so1740137pfc.10 for ; Thu, 21 Oct 2021 14:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WL784dDelb2n11jVqBh0M/kFnuIJJZnBgr5d6GB5NwI=; b=o+4VwUGNeGhwSx8oa9IEgXhF+l2DIrUA0F3msQm23RheJUISRjECD0DIiqppMSItvX d431NUEvyGitkCifYXBdbofLv7SVAbmi9h7Cb+cvZrzJmkQXoZIhYSn7e6FdLoOYa6PK 4Vvx+pP3wMGJU+D6NI2I3oMGRvg/ba0JbZfgKQ2IPorFm8LKpcZ7OIc/6fDaEYgVW3MR 1pvKqmD7EiZb14a/AU1m3QVheUP8PdjWYk+vqdNg5wCrhIEHwp19NcOoYHWijbnzJQ9B NMCEVbDnfKv5+XFPzCqJgC9OHFgF99m2k0ddyaUo0GeChi2eMFO1pYjDAeuub1vI8ypm 4R0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WL784dDelb2n11jVqBh0M/kFnuIJJZnBgr5d6GB5NwI=; b=QOVgM4GaFnv9DVB/TDlAaCFRdlNSBQXWKBBYJUzPt29Ik0ODPCtyCVv/pRwrAFiHFw VIyFwFPrC45cjtR/tFr7hrJj9k8vQc6Im2Or65in+yaXQyJuERgQiH/eXC8HBF7J/mBb oNaCPTlAWzUtNFz5parmxyp6eaxZO+AjrHdQAroezoS3BF07SPW6+sguqeC3kP6iB54W fEvsRh5EE8KdRq189bLHiX/ymSwjHA7b9k2m+UGHtNVDQHLIL7G1q/IOBBITRpa2JUoE fLft4Hrw5tDhiIFbDmZ7WL58njt3CSvnDdesww1UvGHIT0bcxfABC+n6qjlDBMLZbjQ2 5+Qg== X-Gm-Message-State: AOAM531d/OoJIaMHFBnDBvN62l6ff7ILWb1ClyVIKIMjaVc/8VHIPxEZ HbNGT1GflXZlxMRLfeA6EoPHopeDJqi19Q== X-Received: by 2002:aa7:9ec6:0:b0:44d:6650:c1ff with SMTP id r6-20020aa79ec6000000b0044d6650c1ffmr8165414pfq.15.1634850345046; Thu, 21 Oct 2021 14:05:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:05:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/48] tcg/optimize: Split out init_arguments Date: Thu, 21 Oct 2021 14:04:57 -0700 Message-Id: <20211021210539.825582-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org, =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There was no real reason for calls to have separate code here. Unify init for calls vs non-calls using the call path, which handles TCG_CALL_DUMMY_ARG. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index b875d76354..019c5aaf81 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -128,11 +128,6 @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts) } } -static void init_arg_info(OptContext *ctx, TCGArg arg) -{ - init_ts_info(ctx, arg_temp(arg)); -} - static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts) { TCGTemp *i, *g, *l; @@ -606,6 +601,16 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) return false; } +static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args) +{ + for (int i = 0; i < nb_args; i++) { + TCGTemp *ts = arg_temp(op->args[i]); + if (ts) { + init_ts_info(ctx, ts); + } + } +} + /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { @@ -636,19 +641,11 @@ void tcg_optimize(TCGContext *s) if (opc == INDEX_op_call) { nb_oargs = TCGOP_CALLO(op); nb_iargs = TCGOP_CALLI(op); - for (i = 0; i < nb_oargs + nb_iargs; i++) { - TCGTemp *ts = arg_temp(op->args[i]); - if (ts) { - init_ts_info(&ctx, ts); - } - } } else { nb_oargs = def->nb_oargs; nb_iargs = def->nb_iargs; - for (i = 0; i < nb_oargs + nb_iargs; i++) { - init_arg_info(&ctx, op->args[i]); - } } + init_arguments(&ctx, op, nb_oargs + nb_iargs); /* Do copy propagation */ for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { From patchwork Thu Oct 21 21:04:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516071 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp328859imj; Thu, 21 Oct 2021 14:11:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2tjkrmLvlCpLjkVgG/iTXBbpYEO4v33ho+4MIWaNYs59PKTP68hh8mUcuvm7AONaO0q0R X-Received: by 2002:aca:e141:: with SMTP id y62mr6672416oig.124.1634850716838; Thu, 21 Oct 2021 14:11:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850716; cv=none; d=google.com; s=arc-20160816; b=ErIgiCV/gLXImAy8QPH4/rUA6puvsfraIt+L1zJKNCP/vvp48joQF0Fcv2CniL5QsD 9GldZgN77alyyhJJJCyrUHhOWlfZXvliBksU5dkLvQeJb/2/YtYxGFlG+ZMYOnFuERjJ 3/o8jGhWxqMCPRrVZ2C0jqHcKNxyqX0NU0umifyZqkB1RKkJ/LxKtXY9FeMFokQ8cu19 TclHY+KK+zlKsp5O+Zvnnzho5Ap+EbybQlxY5JatQEh48m0AcSjKskzuB/z4TSZIV8jf MqtGlg0eSBdaDb+GFuXYc2OJYVt0SNuJyBe8REigWuzemXAz5aHdARmpJ1jOzFiajZ6F sHXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=apxi4gdi/2+dlekZiDFnJhG83/VEpB6pYIdUYdxg0AQ=; b=TWFZfWFEwKVTIoBf3tkIE/PWT5vLnnq8+4wjiL9Uins94V6dXpWA/qFP9sByIt4LS5 PZQjJ/OYophD2JsbKFT8Ou/yxP5kxTsbmgOeOVEGQaZ5aoMAnWVvq+6X32F3w17nVNk6 qYPXk9b4oQYV2ZO2wNVVO3P/qfYo2CMy5lhFAfn8L0QKVskCJXj4mV2ATVxOpgPk2iZ4 Ke972qKNIWUO3BhKkuyYTqJYI8/kYJaTtXmXnqYosOArAL4V4TD1HR9OHDQeRLIykfef wqdGwH6APtcZR906Y7+2NLeS9LMFPsLNW13JWVsbGOPSpFMaOC0JOUXqxcoCv29HyK+D vjbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vgFIiUdt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x24si7220952ood.10.2021.10.21.14.11.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:11:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vgFIiUdt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfLw-00052d-7L for patch@linaro.org; Thu, 21 Oct 2021 17:11:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfG2-0007ML-GP for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:50 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:39656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfFz-0004Ao-BI for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:50 -0400 Received: by mail-pl1-x62e.google.com with SMTP id t21so1283277plr.6 for ; Thu, 21 Oct 2021 14:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=apxi4gdi/2+dlekZiDFnJhG83/VEpB6pYIdUYdxg0AQ=; b=vgFIiUdt/DRdcilDE7sblzULs6YOVnj7H+w1K/n355ViW6VLuVD0YykLxxTjjMQeVW NZOUGR/vvIZ+o+cfjOsM4TF0a6d2IeN/jZL+tWrG3TLEnOIU5Qwoap2fScszfshUXevh lu/Hbhk0Y6zuCFAYPIAg9fjpGFzZzAX5SOidj4rLv+SktkDdl9M0bPs+fT4bgyCEbMjt libIRkIqNI3nxMgvcArYJBA/klgNuRf+9sgVUXOJOhYNtB5qYnDq+/ksHq4h6Rs/aN5f chGB1vIllzvjUvaOVVwb/bEkwhg2c0DurZXfHNa1PjD791nVbCe6/hfDPSJpY49X0oq5 WBtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=apxi4gdi/2+dlekZiDFnJhG83/VEpB6pYIdUYdxg0AQ=; b=i+jTCaXvBhhdbH2dz2rRUJdpZRCf2/pD0z9zUtOb7zGCNQUbfQ2XOIUNaWdhK6dtor A4xLP1zB9eIZ36/uw2diBe/oeknTI98SP4hvPiQXsZ+qG4V04D1usYse3hDfeIOBic9v 5+cTCndviJfEDcEQPSKtBGdY5AYWZMVoffzA4pSzJAsqSF6mYTvVSoQoIN7qya4ytzU+ gLUnEF8eTI1JW7cLU/WtCKc8Zk2O8ttWWw+J5M04av0ecE1qZfZUUluzKHrIOYhoPjhk I6iZLrA6ULQwo1dB3Y6FaZIjonbksMf7mKqrIkPvVa/u2yT9mX2HONW8a9ulHgspXjUL JC0A== X-Gm-Message-State: AOAM532w4iveUp7m1RLCeuKAZGzbQCYWrvt7ZproxBSLi3NQRkDfKsaf UVIvMHpSt/eM6JNdnIME4OgmExt8E8Bv8A== X-Received: by 2002:a17:90a:fb87:: with SMTP id cp7mr9545515pjb.114.1634850345687; Thu, 21 Oct 2021 14:05:45 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:05:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/48] tcg/optimize: Split out copy_propagate Date: Thu, 21 Oct 2021 14:04:58 -0700 Message-Id: <20211021210539.825582-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org, =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue splitting tcg_optimize. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 019c5aaf81..fad6f5de1f 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -611,6 +611,19 @@ static void init_arguments(OptContext *ctx, TCGOp *op, int nb_args) } } +static void copy_propagate(OptContext *ctx, TCGOp *op, + int nb_oargs, int nb_iargs) +{ + TCGContext *s = ctx->tcg; + + for (int i = nb_oargs; i < nb_oargs + nb_iargs; i++) { + TCGTemp *ts = arg_temp(op->args[i]); + if (ts && ts_is_copy(ts)) { + op->args[i] = temp_arg(find_better_copy(s, ts)); + } + } +} + /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { @@ -646,14 +659,7 @@ void tcg_optimize(TCGContext *s) nb_iargs = def->nb_iargs; } init_arguments(&ctx, op, nb_oargs + nb_iargs); - - /* Do copy propagation */ - for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - TCGTemp *ts = arg_temp(op->args[i]); - if (ts && ts_is_copy(ts)) { - op->args[i] = temp_arg(find_better_copy(s, ts)); - } - } + copy_propagate(&ctx, op, nb_oargs, nb_iargs); /* For commutative operations make constant second argument */ switch (opc) { From patchwork Thu Oct 21 21:04:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516075 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp331770imj; Thu, 21 Oct 2021 14:15:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxnKK9eshkAk56fxKjQjBbV9/x2RkhcJp/Gew6lImIlfaZm1zSCyryEalIY4wwTc2IDSvWP X-Received: by 2002:aca:310e:: with SMTP id x14mr6113650oix.2.1634850912279; Thu, 21 Oct 2021 14:15:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850912; cv=none; d=google.com; s=arc-20160816; b=GDM1csiO0DwV+WceS7pv0WNcPTgv8hpuZWcQJDsxVgJW61cypWdqd0C9Qx39RXC/Sz ZNCVsbqZiRS6eZkv9t34jT83I6hQsAorpxJWouNsv4ksKQic7vd1+IbiKWuNWwjjBdlS W1hSQvFqqjSSzRlrRP3su9tWr0WLK7N1QF9ZxI4gyYcymuIYaucS1SRcT71FR5Vakvs8 XGo5QgEOQf3N1vzSM8nk++gNu5mhIx1uFnOmNkeJU791Kuizq2goZu7A/xSw2m0dvr84 MYU1VVlKnCYg5l57dJ9BAoySPVKl5G4NRt0Q8AB226KsEGVEa/BmUjVJxq/TNweyt2ZS vgNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qA2L+rswn0bgEtnoIqL3DIT4FMCOfg4+ksSKsYoClOk=; b=pI81DTl3kMdKQ7kZtAdzWLy/nLyA5cKd0hDo6KdNluJ9qYqmaxCN5sSFyaBpLltblQ ZAN5UTWEMt9hz4lFUbjOFD2acbqnG1CglV6oJg6lV01EvqtzJKslhJsRlW3QkUYcMNhd j8ruZ0oPmRi0RhWzEatH2H2nWxLAHQNw29KHrsoDeNNxUqwb7v7+gOFxZI1uqL5bKIXX sDcxoRjbDXHQ+SbRJdbnu6jXtL9QTe2SlDNlwSnTv6r9RjPhTovPdqwp/YT9Jdqev72E MzuBCXiKiL/KcXUbrGiZeqrMMnumxD4enKdT/p0ePuinqn5UWDg7PHHr44bqMdEAAAOp 41vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NeP2VIx5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 63 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 41 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index fad6f5de1f..74b9aa025a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -624,10 +624,42 @@ static void copy_propagate(OptContext *ctx, TCGOp *op, } } +static bool fold_call(OptContext *ctx, TCGOp *op) +{ + TCGContext *s = ctx->tcg; + int nb_oargs = TCGOP_CALLO(op); + int nb_iargs = TCGOP_CALLI(op); + int flags, i; + + init_arguments(ctx, op, nb_oargs + nb_iargs); + copy_propagate(ctx, op, nb_oargs, nb_iargs); + + /* If the function reads or writes globals, reset temp data. */ + flags = tcg_call_flags(op); + if (!(flags & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { + int nb_globals = s->nb_globals; + + for (i = 0; i < nb_globals; i++) { + if (test_bit(i, ctx->temps_used.l)) { + reset_ts(&ctx->tcg->temps[i]); + } + } + } + + /* Reset temp data for outputs. */ + for (i = 0; i < nb_oargs; i++) { + reset_temp(op->args[i]); + } + + /* Stop optimizing MB across calls. */ + ctx->prev_mb = NULL; + return true; +} + /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { - int nb_temps, nb_globals, i; + int nb_temps, i; TCGOp *op, *op_next; OptContext ctx = { .tcg = s }; @@ -637,8 +669,6 @@ void tcg_optimize(TCGContext *s) available through the doubly linked circular list. */ nb_temps = s->nb_temps; - nb_globals = s->nb_globals; - for (i = 0; i < nb_temps; ++i) { s->temps[i].state_ptr = NULL; } @@ -647,17 +677,17 @@ void tcg_optimize(TCGContext *s) uint64_t z_mask, partmask, affected, tmp; int nb_oargs, nb_iargs; TCGOpcode opc = op->opc; - const TCGOpDef *def = &tcg_op_defs[opc]; + const TCGOpDef *def; - /* Count the arguments, and initialize the temps that are - going to be used */ + /* Calls are special. */ if (opc == INDEX_op_call) { - nb_oargs = TCGOP_CALLO(op); - nb_iargs = TCGOP_CALLI(op); - } else { - nb_oargs = def->nb_oargs; - nb_iargs = def->nb_iargs; + fold_call(&ctx, op); + continue; } + + def = &tcg_op_defs[opc]; + nb_oargs = def->nb_oargs; + nb_iargs = def->nb_iargs; init_arguments(&ctx, op, nb_oargs + nb_iargs); copy_propagate(&ctx, op, nb_oargs, nb_iargs); @@ -1549,16 +1579,6 @@ void tcg_optimize(TCGContext *s) if (def->flags & TCG_OPF_BB_END) { memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); } else { - if (opc == INDEX_op_call && - !(tcg_call_flags(op) - & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { - for (i = 0; i < nb_globals; i++) { - if (test_bit(i, ctx.temps_used.l)) { - reset_ts(&s->temps[i]); - } - } - } - for (i = 0; i < nb_oargs; i++) { reset_temp(op->args[i]); /* Save the corresponding known-zero bits mask for the @@ -1599,7 +1619,6 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st8_i32: case INDEX_op_qemu_st_i64: - case INDEX_op_call: /* Opcodes that touch guest memory stop the optimization. */ ctx.prev_mb = NULL; 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A couple of asserts need dropping, but that will take care of itself as we split the function further. Reviewed-by: Alex Bennée Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 74b9aa025a..77cdffaaef 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -675,7 +675,6 @@ void tcg_optimize(TCGContext *s) QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { uint64_t z_mask, partmask, affected, tmp; - int nb_oargs, nb_iargs; TCGOpcode opc = op->opc; const TCGOpDef *def; @@ -686,10 +685,8 @@ void tcg_optimize(TCGContext *s) } def = &tcg_op_defs[opc]; - nb_oargs = def->nb_oargs; - nb_iargs = def->nb_iargs; - init_arguments(&ctx, op, nb_oargs + nb_iargs); - copy_propagate(&ctx, op, nb_oargs, nb_iargs); + init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs); + copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs); /* For commutative operations make constant second argument */ switch (opc) { @@ -1063,7 +1060,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(qemu_ld): { - MemOpIdx oi = op->args[nb_oargs + nb_iargs]; + MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs]; MemOp mop = get_memop(oi); if (!(mop & MO_SIGN)) { z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; @@ -1122,12 +1119,10 @@ void tcg_optimize(TCGContext *s) } if (partmask == 0) { - tcg_debug_assert(nb_oargs == 1); tcg_opt_gen_movi(&ctx, op, op->args[0], 0); continue; } if (affected == 0) { - tcg_debug_assert(nb_oargs == 1); tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); continue; } @@ -1202,7 +1197,6 @@ void tcg_optimize(TCGContext *s) } else if (args_are_copies(op->args[1], op->args[2])) { op->opc = INDEX_op_dup_vec; TCGOP_VECE(op) = MO_32; - nb_iargs = 1; } break; @@ -1371,7 +1365,6 @@ void tcg_optimize(TCGContext *s) op->opc = opc = (opc == INDEX_op_movcond_i32 ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64); - nb_iargs = 2; } break; @@ -1579,6 +1572,7 @@ void tcg_optimize(TCGContext *s) if (def->flags & TCG_OPF_BB_END) { memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); } else { + int nb_oargs = def->nb_oargs; for (i = 0; i < nb_oargs; i++) { reset_temp(op->args[i]); /* Save the corresponding known-zero bits mask for the From patchwork Thu Oct 21 21:05:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516093 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp342042imj; Thu, 21 Oct 2021 14:27:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyp/KMy3SNKliwnR4dcY47dANwmeF2k20EWXuflvBu2mLucY58ZDWOFbwgexVeIUHTAEVPT X-Received: by 2002:a05:6830:1017:: with SMTP id a23mr6414698otp.381.1634851659890; Thu, 21 Oct 2021 14:27:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851659; cv=none; d=google.com; s=arc-20160816; b=MfdFkRu+Y/zAcPo8vn/2ODbZXCocrsheCNbLOnD1GhN7/rZkalcOGBQUtyUSBwo8BV BaE2ZRmKUk2Ue2Yd7oczKTFoLoZY2eBn96Z3Bca1SCafN7eX8a4OhLke2qT32vpa1nyv 7GmpA1Q+LspOycAGrpmrLV322Q4De/O367a8BW3oZhNWIjiY/vVNa/ZMj0lwWhoC/pFT K49ojsOY+gts+15vG3eu9A2oUCn37V+qdQNbNPNpjNaZY8I/JR4F6BH8HcrX10gbCzC9 YZIF9uS3jdWfT4f8d5jk+7eY9YYLX5z86bNO5+UA82XQQI2gfnt8d0bSQVydXlIVYCcR hpfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vzj+E8hckTDMXEhYEpz82x526nBjR1hng55zovif/wQ=; b=ej69LBpJuimHQ1ttzorrC3jTNrk6Xe6UoRJSh9snl6vHzijE4hayuUrOxeWag5KPEk C70gNT+a4+Nkn05a/6IkEuLgZJ9s8BUAoMaKSUJ6IY0zYR8yy8AohqXM2PmbKvDgIMyW EbZow/EsOre8IUX/ZuiGv1aIGIjmHSnmJ6n5cXK6PyrYhIm3b837/q/Pp+1Qoq+1x7Pl ikVrrkGtp+q5kQNI2+kfzpo1NsQfb/jmAWymqZGkWo+qfjsF+aFRoByGNRl4J481thL6 vcHIRBIBreI24iETj5y4rxDBFAElYuiFRTVi1JtdcO2VhgN6zTAUy4M9YLVtXdcM6J9u 3PYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ky0j1AT8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This us to use comparisons against 0 for all cases. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 +++++++++++++++++++++++++------------------------ 1 file changed, 74 insertions(+), 71 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index 77cdffaaef..19c01687b4 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -502,10 +502,12 @@ static bool do_constant_folding_cond_eq(TCGCond c) } } -/* Return 2 if the condition can't be simplified, and the result - of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, - TCGArg y, TCGCond c) +/* + * Return -1 if the condition can't be simplified, + * and the result of the condition (0 or 1) if it can. + */ +static int do_constant_folding_cond(TCGOpcode op, TCGArg x, + TCGArg y, TCGCond c) { uint64_t xv = arg_info(x)->val; uint64_t yv = arg_info(y)->val; @@ -527,15 +529,17 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, case TCG_COND_GEU: return 1; default: - return 2; + return -1; } } - return 2; + return -1; } -/* Return 2 if the condition can't be simplified, and the result - of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) +/* + * Return -1 if the condition can't be simplified, + * and the result of the condition (0 or 1) if it can. + */ +static int do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) { TCGArg al = p1[0], ah = p1[1]; TCGArg bl = p2[0], bh = p2[1]; @@ -565,7 +569,7 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) if (args_are_copies(al, bl) && args_are_copies(ah, bh)) { return do_constant_folding_cond_eq(c); } - return 2; + return -1; } static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) @@ -1321,22 +1325,21 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(setcond): - tmp = do_constant_folding_cond(opc, op->args[1], - op->args[2], op->args[3]); - if (tmp != 2) { - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); + i = do_constant_folding_cond(opc, op->args[1], + op->args[2], op->args[3]); + if (i >= 0) { + tcg_opt_gen_movi(&ctx, op, op->args[0], i); continue; } break; CASE_OP_32_64(brcond): - tmp = do_constant_folding_cond(opc, op->args[0], - op->args[1], op->args[2]); - switch (tmp) { - case 0: + i = do_constant_folding_cond(opc, op->args[0], + op->args[1], op->args[2]); + if (i == 0) { tcg_op_remove(s, op); continue; - case 1: + } else if (i > 0) { memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); op->opc = opc = INDEX_op_br; op->args[0] = op->args[3]; @@ -1345,10 +1348,10 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(movcond): - tmp = do_constant_folding_cond(opc, op->args[1], - op->args[2], op->args[5]); - if (tmp != 2) { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4-tmp]); + i = do_constant_folding_cond(opc, op->args[1], + op->args[2], op->args[5]); + if (i >= 0) { + tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]); continue; } if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { @@ -1412,14 +1415,14 @@ void tcg_optimize(TCGContext *s) break; case INDEX_op_brcond2_i32: - tmp = do_constant_folding_cond2(&op->args[0], &op->args[2], - op->args[4]); - if (tmp == 0) { + i = do_constant_folding_cond2(&op->args[0], &op->args[2], + op->args[4]); + if (i == 0) { do_brcond_false: tcg_op_remove(s, op); continue; } - if (tmp == 1) { + if (i > 0) { do_brcond_true: op->opc = opc = INDEX_op_br; op->args[0] = op->args[5]; @@ -1443,20 +1446,20 @@ void tcg_optimize(TCGContext *s) if (op->args[4] == TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[0], op->args[2], - TCG_COND_EQ); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_brcond_i32, + op->args[0], op->args[2], + TCG_COND_EQ); + if (i == 0) { goto do_brcond_false; - } else if (tmp == 1) { + } else if (i > 0) { goto do_brcond_high; } - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[1], op->args[3], - TCG_COND_EQ); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_brcond_i32, + op->args[1], op->args[3], + TCG_COND_EQ); + if (i == 0) { goto do_brcond_false; - } else if (tmp != 1) { + } else if (i < 0) { break; } do_brcond_low: @@ -1470,31 +1473,31 @@ void tcg_optimize(TCGContext *s) if (op->args[4] == TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[0], op->args[2], - TCG_COND_NE); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_brcond_i32, + op->args[0], op->args[2], + TCG_COND_NE); + if (i == 0) { goto do_brcond_high; - } else if (tmp == 1) { + } else if (i > 0) { goto do_brcond_true; } - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[1], op->args[3], - TCG_COND_NE); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_brcond_i32, + op->args[1], op->args[3], + TCG_COND_NE); + if (i == 0) { goto do_brcond_low; - } else if (tmp == 1) { + } else if (i > 0) { goto do_brcond_true; } } break; case INDEX_op_setcond2_i32: - tmp = do_constant_folding_cond2(&op->args[1], &op->args[3], - op->args[5]); - if (tmp != 2) { + i = do_constant_folding_cond2(&op->args[1], &op->args[3], + op->args[5]); + if (i >= 0) { do_setcond_const: - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); + tcg_opt_gen_movi(&ctx, op, op->args[0], i); continue; } if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) @@ -1516,20 +1519,20 @@ void tcg_optimize(TCGContext *s) if (op->args[5] == TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[1], op->args[3], - TCG_COND_EQ); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_setcond_i32, + op->args[1], op->args[3], + TCG_COND_EQ); + if (i == 0) { goto do_setcond_const; - } else if (tmp == 1) { + } else if (i > 0) { goto do_setcond_high; } - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[2], op->args[4], - TCG_COND_EQ); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_setcond_i32, + op->args[2], op->args[4], + TCG_COND_EQ); + if (i == 0) { goto do_setcond_high; - } else if (tmp != 1) { + } else if (i < 0) { break; } do_setcond_low: @@ -1543,20 +1546,20 @@ void tcg_optimize(TCGContext *s) if (op->args[5] == TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[1], op->args[3], - TCG_COND_NE); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_setcond_i32, + op->args[1], op->args[3], + TCG_COND_NE); + if (i == 0) { goto do_setcond_high; - } else if (tmp == 1) { + } else if (i > 0) { goto do_setcond_const; } - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[2], op->args[4], - TCG_COND_NE); - if (tmp == 0) { + i = do_constant_folding_cond(INDEX_op_setcond_i32, + op->args[2], op->args[4], + TCG_COND_NE); + if (i == 0) { goto do_setcond_low; - } else if (tmp == 1) { + } else if (i > 0) { goto do_setcond_const; } } From patchwork Thu Oct 21 21:05:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516089 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp340272imj; 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Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 19c01687b4..066e635f73 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -180,7 +180,7 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2) return ts_are_copies(arg_temp(arg1), arg_temp(arg2)); } -static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) +static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) { TCGTemp *dst_ts = arg_temp(dst); TCGTemp *src_ts = arg_temp(src); @@ -192,7 +192,7 @@ static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) if (ts_are_copies(dst_ts, src_ts)) { tcg_op_remove(ctx->tcg, op); - return; + return true; } reset_ts(dst_ts); @@ -228,9 +228,10 @@ static void tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) di->is_const = si->is_const; di->val = si->val; } + return true; } -static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, +static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, TCGArg dst, uint64_t val) { const TCGOpDef *def = &tcg_op_defs[op->opc]; @@ -248,7 +249,7 @@ static void tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, /* Convert movi to mov with constant temp. */ tv = tcg_constant_internal(type, val); init_ts_info(ctx, tv); - tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); + return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); } static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) From patchwork Thu Oct 21 21:05:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516078 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp332755imj; Thu, 21 Oct 2021 14:16:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzKgXh59eFq0o3c4l4CDo+JBjozbOYWq9rrjwPmpjJ4M+xzPZJiY6rFbQC7o8+qFXZzpMdJ X-Received: by 2002:a05:6830:23ac:: with SMTP id m12mr7028823ots.357.1634850972088; Thu, 21 Oct 2021 14:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850972; cv=none; d=google.com; s=arc-20160816; b=g5mbJ/5tMNrO3cZiBKwZEMwGG/r7DNPVeUIh/K/e7Bj2n7RPEsVKoosiyE1xQYQl8C z78fj7XXDPDFBmvoZLGukAjRXKVtdWOBnq1w7kck/yXin6gwJ6XwvHXkWsofWblD/pbH YfYFQXQE5fIyeNNnnbbcM8D3xLPx2YTlxJjMatFPBEUNSqPsmWm4HDv8ytGrc/tkaEcH AECCco2LFWPYOEBmJoZ9wM03r85qRVbKJPIa9n8H6vcWMveeV14QoWFOzXRA2DTqvYXg e+c2DNV4JLb9AkjzLUmEjNBV0UIwPmk3BKkYmsMr7CraShcwDMjTw6fuopBi+p9aiXa1 b/PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ek5wQYkVQoH2sT/1n0bEqo8hkSGClCj2XVIXi5hg7S8=; b=yqWC+F3HT8VEJ+wKiUr4ZZhO77CZS9EbHLMpqzHI12wrxoA7BgX00LZ02CM8r+vPtW eqQlUm6WYl7zHAtg/cjhA+GylCz/eLVBL4h4daZij0NLeJUa2SSI0PP6fwL+wxN6opyB gaAs4P0Ify2Z0pzEwPYNPE0I0HjvWMv7xhnknA6llQsU58RYSlSOV6zsANxCXXLd1aXO nXNWJXnkMOCkI2MGK+Rzs7Rzb3W49UdpnPUCYLG1nmlKkG7GAifJQyeA5/NefiAIbIpz tlkSQ7afCftRSSgFjyfus4trhI5mn596rz1tcGnrls4VuXP3p23oA4buRbbAOQHD/WfQ O7hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aVeNJzZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p24si7473253oto.133.2021.10.21.14.16.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:16:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aVeNJzZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfQ3-0003Ff-BA for patch@linaro.org; Thu, 21 Oct 2021 17:16:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfG5-0007O3-BY for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:57 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:43576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfG3-0004FU-4A for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:53 -0400 Received: by mail-pg1-x533.google.com with SMTP id r2so1386273pgl.10 for ; Thu, 21 Oct 2021 14:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ek5wQYkVQoH2sT/1n0bEqo8hkSGClCj2XVIXi5hg7S8=; b=aVeNJzZQJtwbQ3Cg8pM/oSWsNayyChEtBDLONjxPlMGH6r/JsUr3a/y+2x1thl3kL9 1sp2JOIUiLC3NBWr1G1/KStPRrqsWA8y6pfvbZd7oWD5n4Y+GewhFX9xlBu0UUac13sq Gnjb01qGkIywwczv53R1sLKS+vN69pQdVfGbp8YOQNlg/ToSLEBj/PBAClxkZg7UY7dU RdgdC+ow1OSVcsWR6J5MtcrkkIFjuWjSiLAptUl1Hr2rMoE735+GSL4CFdhbCCneBZF4 nCc3/X1V4/0n2HvNcijaEtp/7hwUeu41fiTxpu45zagM77CkuJu9HLgBr5on2Eg/goWY 1FHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ek5wQYkVQoH2sT/1n0bEqo8hkSGClCj2XVIXi5hg7S8=; b=b2Gyg00HU2F/czRVFY29Ro8Kuhwhn0ZJqGjIqlnw07dXR6croqtdeo7zLLSq2LtLuH ya+fgidMVhO3cRs4Us+k0XMiIOv8UzusEFRJWdSCwZBfelDduJq0K502tLcd68KecfVa 42sXhng0GGfzeB+qx8Dn3ZWfr5SpIxkQMH1WSQAHHPnJT58Obp/Thq7HF6X+hggm13hL 2pU/wQZ952y+m9v3AGm2QQz2S9NiywIdyKujSKSDiFoqL2yBJlCMiYgWXl2E1rHDXoCL 7Hl7EuAmbfMBRISIPsFFw10P/goGgjnoLJtPKq+q6HiYA4M/rqRYupliB216x8YTsQ4A V2IA== X-Gm-Message-State: AOAM5317uQPXSL0Z+QIxNp6adxLXvhMwy/d/H2xNSi9S22RjU5QEYBD0 PSpyzjawvRmDq/C58jbsBHtd/2+Txxg= X-Received: by 2002:a63:9dc4:: with SMTP id i187mr6319371pgd.260.1634850349588; Thu, 21 Oct 2021 14:05:49 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:05:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/48] tcg/optimize: Split out finish_folding Date: Thu, 21 Oct 2021 14:05:03 -0700 Message-Id: <20211021210539.825582-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copy z_mask into OptContext, for writeback to the first output within the new function. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 49 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 066e635f73..368457f4a2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -48,6 +48,9 @@ typedef struct OptContext { TCGContext *tcg; TCGOp *prev_mb; TCGTempSet temps_used; + + /* In flight values from optimization. */ + uint64_t z_mask; } OptContext; static inline TempOptInfo *ts_info(TCGTemp *ts) @@ -629,6 +632,34 @@ static void copy_propagate(OptContext *ctx, TCGOp *op, } } +static void finish_folding(OptContext *ctx, TCGOp *op) +{ + const TCGOpDef *def = &tcg_op_defs[op->opc]; + int i, nb_oargs; + + /* + * For an opcode that ends a BB, reset all temp data. + * We do no cross-BB optimization. + */ + if (def->flags & TCG_OPF_BB_END) { + memset(&ctx->temps_used, 0, sizeof(ctx->temps_used)); + ctx->prev_mb = NULL; + return; + } + + nb_oargs = def->nb_oargs; + for (i = 0; i < nb_oargs; i++) { + reset_temp(op->args[i]); + /* + * Save the corresponding known-zero bits mask for the + * first output argument (only one supported so far). + */ + if (i == 0) { + arg_info(op->args[i])->z_mask = ctx->z_mask; + } + } +} + static bool fold_call(OptContext *ctx, TCGOp *op) { TCGContext *s = ctx->tcg; @@ -1122,6 +1153,7 @@ void tcg_optimize(TCGContext *s) partmask &= 0xffffffffu; affected &= 0xffffffffu; } + ctx.z_mask = z_mask; if (partmask == 0) { tcg_opt_gen_movi(&ctx, op, op->args[0], 0); @@ -1570,22 +1602,7 @@ void tcg_optimize(TCGContext *s) break; } - /* Some of the folding above can change opc. */ - opc = op->opc; - def = &tcg_op_defs[opc]; - if (def->flags & TCG_OPF_BB_END) { - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - } else { - int nb_oargs = def->nb_oargs; - for (i = 0; i < nb_oargs; i++) { - reset_temp(op->args[i]); - /* Save the corresponding known-zero bits mask for the - first output argument (only one supported so far). */ - if (i == 0) { - arg_info(op->args[i])->z_mask = z_mask; - } - } - } + finish_folding(&ctx, op); /* Eliminate duplicate and redundant fence instructions. */ if (ctx.prev_mb) { From patchwork Thu Oct 21 21:05:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516076 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp332392imj; Thu, 21 Oct 2021 14:15:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQhluBBaDHTXpB7UgxQKvnG2tiuJOyogmnw2O+dFsbzGsRFQB8NypBZUVOz5WUUsn3wHwv X-Received: by 2002:a05:6808:171b:: with SMTP id bc27mr6758784oib.21.1634850954338; Thu, 21 Oct 2021 14:15:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850954; cv=none; d=google.com; s=arc-20160816; b=RljTu5021PqZdK7mRf1I6sehXjtSRwDqPB69tUCO9EWlbpV1P5bmsTq0LTUxNMxKpZ QFe7fDZ820/Zsc8HNcPeAnKyNW/B1Rz/KIzetYtYNFO3VHnHB9nRRk7i0uAw2B/NcwwX C9pVNbHv5yV3bR0iIM7EcQzK4zYGL1nxgHxyv9Hds+RMbCq1kuwPki0/G/DqP+SIN3z7 oHMTFPFVVQibQULN0WzZ9r5ALWHhrtyRgoX7tKd4j8QOaP2m+fj3zsENLjE4b3+lNCc/ 8hoD4HWDiLmDN716GvYNUf12vKA1iqnCEiIonkM1kZz9j/0TmmW+8Bhat8lTO2Z1TKhP /5Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pb59zgt3BJOK/6jo6ZxRJgBUW76Zvxuzd+Eqm9jcKsI=; b=AtBtS3gRiRxv4YlXW+Go/9AWBudcQzzXWy0ruCMp3rk1TONVsHLIyS4h1tcDKHcGz8 eBw3Y9eNAtz1eKQWvH1rpzOytPNy0Px2CQdppaRmuvYkzvOJZLJUa7jhYE9Nb8qa176x bQKtkr6+yG87nGhblrlJn5gA232pJkTtsxCxxdPAwGBNeX4FncXQsd9kmt4yzuRsgb8f gRGk8b7MRGuw2sErnY19+fqTa//pcnx0M1YNErEooFtGfcrZBFPzktJueD45Lbj/hkH4 wEgDfvAsKma4IX38dUCcL7HwKPv1FQeZeCT69fyh8MOeo2veIlbZLq8EiGtIYUSNQuQ4 vPhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fm0Px4Xk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 21 Oct 2021 14:05:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/48] tcg/optimize: Use a boolean to avoid a mass of continues Date: Thu, 21 Oct 2021 14:05:04 -0700 Message-Id: <20211021210539.825582-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org, =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 368457f4a2..699476e2f1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -713,6 +713,7 @@ void tcg_optimize(TCGContext *s) uint64_t z_mask, partmask, affected, tmp; TCGOpcode opc = op->opc; const TCGOpDef *def; + bool done = false; /* Calls are special. */ if (opc == INDEX_op_call) { @@ -1212,8 +1213,8 @@ void tcg_optimize(TCGContext *s) allocator where needed and possible. Also detect copies. */ switch (opc) { CASE_OP_32_64_VEC(mov): - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); - continue; + done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); + break; case INDEX_op_dup_vec: if (arg_is_const(op->args[1])) { @@ -1602,7 +1603,9 @@ void tcg_optimize(TCGContext *s) break; } - finish_folding(&ctx, op); + if (!done) { + finish_folding(&ctx, op); + } /* Eliminate duplicate and redundant fence instructions. */ if (ctx.prev_mb) { From patchwork Thu Oct 21 21:05:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516082 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp335742imj; Thu, 21 Oct 2021 14:19:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxErQh2N5GpDZxX+bp06WUsKHj7P+hLQxZEANGhdQ2IveiOaukOxP7WsPNVnKIXftkws4yv X-Received: by 2002:a05:6830:43a5:: with SMTP id s37mr6688150otv.246.1634851153040; Thu, 21 Oct 2021 14:19:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851153; cv=none; d=google.com; s=arc-20160816; b=Ip1M2lZxF4DZSETLxt/LKJTNO74v+mPlOG0qoRd6NpEaeopr42oplXHowqO/7j5TBR CGLkB5HbVDZGrtZ/7PMS1g19xxc+V2ccbBspz0vnk/PPIvwP3EpfUfNCasKz9UmTLmaM GXmEuln4TP3rVVn0QSHnnh5Ct6HUTT28Dw4C8v6zCTjR1vjf3tKW12XkcgJF/QXRS0Ta z2YzwBP5ubQPb7bXgLovWBBJR8lPq0QxUD8cfObu9lfq//RUD8Q31i3GxZu+SVztQ36n AEpI2qwdy4i52vWQ15f2Pi39YSQ/W4tcoUNDeW1Y33ObcUm965I/uoBhSh9EXjKwv6dQ jqjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nXAcxan7S9VdDzWZ6hubQvAQCG5PQ50y7tm1Z6dakPA=; b=nGeodJg37/koKywXS0rO0aN2soxpzVmm+pjouu8zIcPnGqEeE3A78qYj8XxXN+ijEL OZ29/4FGz540Hb0PWCAQOQgyYDr3al2sWe9JL31QSECuEhMXDddbb6uaA/rNOHP6MdZl aLfoj5FuE18HZf31I4S18anh5wKojp5+CCf3WNvEMJqunTfOmn8QRB06xK4rJnPmrGuD IduGkcrGKCtNmPxdq/trvuNkxwb2Oi8IRvTqk62qgmr03ulESMihpyBTY6D5CRcLq456 NXU8CBbuiPmIoKkVUSTcKnpVI/dB0QOcGwsxdc5Mpg39ipGoDoBHHOY4kGKqdFsiqq1R mtbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JrnNYoTl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g25si8181000otn.158.2021.10.21.14.19.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:19:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JrnNYoTl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfSy-000185-Do for patch@linaro.org; Thu, 21 Oct 2021 17:19:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48368) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfGA-0007P6-C9 for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:58 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:35364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfG4-0004Gh-7B for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:05:56 -0400 Received: by mail-pl1-x632.google.com with SMTP id u6so1303309ple.2 for ; Thu, 21 Oct 2021 14:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nXAcxan7S9VdDzWZ6hubQvAQCG5PQ50y7tm1Z6dakPA=; b=JrnNYoTldP28ng84Bc9+Ixk4/ak0unO3AXg/VfqlLwFJeiIY8f2QHbKN/GF+ihbZTG qS1K+qphUsNEba3FMtnSuXotx+bjtKIWiqHBTZd9egcqOiV89uvFQkY0heIvfRgmlmy2 FEWFd/liyRxrsWZ8GGLcpuWAKh+8VuLOxK5TFTtwufj8tciHjq2Tg4hiNS6rUknfZOgy zf+BRTo4+BaMtA3RF34kFoUN+1A3Wo34r5LE1ORdW1JBKv0bdPIqymBmYzybeY/la+4W O50B6w3Yn1NURRItjzbU/XBfNqslPsJpdo0vlpMEHGvvn4zT0J/qsY87q/PKgKZmpjm9 9IrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nXAcxan7S9VdDzWZ6hubQvAQCG5PQ50y7tm1Z6dakPA=; b=53q78qI0Xme4kP4BFH8YzF9PGQj+8nPvdSCwmgXPduU2Uy5UK8tJnZnYMsnW11519c 4trYZehOReUoOFKYdCH9yXLcYST/3kBeIaRgEsgjIF9nDBU/1X0z1N1k7PA7ACC/KZ5g HfMclXOjOuxqxrF2Gm0uGtFKelPcFqNgFN76wyq1AQ6mIOrizepg+I9ShtBjGh+NKKWj 8vc0l+OnvIeKJJGRvksFJzL/JW5qa52IWf7xVNuw304vw4rHdiinWKD0xD8UyTBOh96a WlOU/rumhOozt13mU44pnJNAQG+34WwYGfR4bQ8GqtE3oZAQM8SgSN2sCoD14dweBKn+ Ip5Q== X-Gm-Message-State: AOAM530JJ5VDBpz6UNBVd96OFZBcXQs8pLK6+GkcELXyX2UjOYsXnUkc LH/Pc2zWM0FA9EYmBq0Wo5vSCNaMf1fUIQ== X-Received: by 2002:a17:90a:6942:: with SMTP id j2mr5969238pjm.113.1634850350940; Thu, 21 Oct 2021 14:05:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:05:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/48] tcg/optimize: Split out fold_mb, fold_qemu_{ld, st} Date: Thu, 21 Oct 2021 14:05:05 -0700 Message-Id: <20211021210539.825582-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This puts the separate mb optimization into the same framework as the others. While fold_qemu_{ld,st} are currently identical, that won't last as more code gets moved. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 89 +++++++++++++++++++++++++++++--------------------- 1 file changed, 51 insertions(+), 38 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index 699476e2f1..159a5a9ee5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -692,6 +692,44 @@ static bool fold_call(OptContext *ctx, TCGOp *op) return true; } +static bool fold_mb(OptContext *ctx, TCGOp *op) +{ + /* Eliminate duplicate and redundant fence instructions. */ + if (ctx->prev_mb) { + /* + * Merge two barriers of the same type into one, + * or a weaker barrier into a stronger one, + * or two weaker barriers into a stronger one. + * mb X; mb Y => mb X|Y + * mb; strl => mb; st + * ldaq; mb => ld; mb + * ldaq; strl => ld; mb; st + * Other combinations are also merged into a strong + * barrier. This is stricter than specified but for + * the purposes of TCG is better than not optimizing. + */ + ctx->prev_mb->args[0] |= op->args[0]; + tcg_op_remove(ctx->tcg, op); + } else { + ctx->prev_mb = op; + } + return true; +} + +static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) +{ + /* Opcodes that touch guest memory stop the mb optimization. */ + ctx->prev_mb = NULL; + return false; +} + +static bool fold_qemu_st(OptContext *ctx, TCGOp *op) +{ + /* Opcodes that touch guest memory stop the mb optimization. */ + ctx->prev_mb = NULL; + return false; +} + /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { @@ -1599,6 +1637,19 @@ void tcg_optimize(TCGContext *s) } break; + case INDEX_op_mb: + done = fold_mb(&ctx, op); + break; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + done = fold_qemu_ld(&ctx, op); + break; + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st8_i32: + case INDEX_op_qemu_st_i64: + done = fold_qemu_st(&ctx, op); + break; + default: break; } @@ -1606,43 +1657,5 @@ void tcg_optimize(TCGContext *s) if (!done) { finish_folding(&ctx, op); } - - /* Eliminate duplicate and redundant fence instructions. */ - if (ctx.prev_mb) { - switch (opc) { - case INDEX_op_mb: - /* Merge two barriers of the same type into one, - * or a weaker barrier into a stronger one, - * or two weaker barriers into a stronger one. - * mb X; mb Y => mb X|Y - * mb; strl => mb; st - * ldaq; mb => ld; mb - * ldaq; strl => ld; mb; st - * Other combinations are also merged into a strong - * barrier. This is stricter than specified but for - * the purposes of TCG is better than not optimizing. - */ - ctx.prev_mb->args[0] |= op->args[0]; - tcg_op_remove(s, op); - break; - - default: - /* Opcodes that end the block stop the optimization. */ - if ((def->flags & TCG_OPF_BB_END) == 0) { - break; - } - /* fallthru */ - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st8_i32: - case INDEX_op_qemu_st_i64: - /* Opcodes that touch guest memory stop the optimization. */ - ctx.prev_mb = NULL; - break; - } - } else if (opc == INDEX_op_mb) { - ctx.prev_mb = op; - } } } From patchwork Thu Oct 21 21:05:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516072 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp328968imj; Thu, 21 Oct 2021 14:12:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfNolc1BPdWxN6yzCuv7BLW1Atx4YsNukq8Koh6/CyWCtiShO/owMo9GJl/lWbM3zTxjS1 X-Received: by 2002:a4a:d6c7:: with SMTP id j7mr6290851oot.36.1634850722353; Thu, 21 Oct 2021 14:12:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634850722; cv=none; d=google.com; s=arc-20160816; b=Z6v00JO0VLPmiQSvPqPXgw7BrpxecQ46YRUa1yx1HhnT7+ZeoFzj0i/TaOwxk4xfhB pJD2W3+p7tboNma50/l61zzFwaGefeUuGmTFJBAM0lQj/22ysB1i9da2FOhDsiChMrkt vsul0bHk7rM/dhKFD0uXkZfKmwhedj8qAFdR90I8j2S6kAHJxhtIC58Ne5tjOvHdZBQ9 NWa+xpp4qsYSAIouQ/pcXVrEE5NvqkN6XgwA8rvKZ+PY2S46BOHc/Mj2ifzppZs1icsE 9BiP1B9dIx9XMChBf0uN90W7Gh6o2kvTjd+UgkSucIMNrs8CfUocTTekShALdJpLOnkk r3rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VL2DZVHiwEan+Uudq/w6Cd72DWHAAD7YXIJuDWEUvWk=; b=DTa/t5LJAsFoH7Wn65QboFuhBO34k7RtPpcm5/UnMaONOSBntxQHAQ/GMieRTusjQ4 8kAT//PdmQO0PmzMHfaTQe/ZRLgLxtYPwVElagEAjmJUfoW1lFubkMi8dXyonGWR4+gQ V+PpPs2p5c6ZYhpCAO+/AcDkAZH/33Ig95Xt4j135beP+O2s0oFw7VvrPyH5V5d6JKn3 GP5BYx0DX62L/9Xh1vXrSOdofie1Kog1nJvADof8PMZvnwYaN+rihowErB40HrIFu98m 8A2E7TOKDY5kzSrHjKCJNZfkdJIHWCc6FUc8OIzxfifZXeFFTe2P6DsMVGuHmjobLR8a 1rfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Mi7Hb9WF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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That won't last as more code gets moved. Use CASE_32_64_VEC for some logical operators that previously missed the addition of vectors. Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 254 +++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 202 insertions(+), 52 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 159a5a9ee5..e66d935808 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -660,6 +660,60 @@ static void finish_folding(OptContext *ctx, TCGOp *op) } } +/* + * The fold_* functions return true when processing is complete, + * usually by folding the operation to a constant or to a copy, + * and calling tcg_opt_gen_{mov,movi}. They may do other things, + * like collect information about the value produced, for use in + * optimizing a subsequent operation. + * + * These first fold_* functions are all helpers, used by other + * folders for more specific operations. + */ + +static bool fold_const1(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t; + + t = arg_info(op->args[1])->val; + t = do_constant_folding(op->opc, t, 0); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return false; +} + +static bool fold_const2(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + uint64_t t1 = arg_info(op->args[1])->val; + uint64_t t2 = arg_info(op->args[2])->val; + + t1 = do_constant_folding(op->opc, t1, t2); + return tcg_opt_gen_movi(ctx, op, op->args[0], t1); + } + return false; +} + +/* + * These outermost fold_ functions are sorted alphabetically. + */ + +static bool fold_add(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_and(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_andc(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + static bool fold_call(OptContext *ctx, TCGOp *op) { TCGContext *s = ctx->tcg; @@ -692,6 +746,26 @@ static bool fold_call(OptContext *ctx, TCGOp *op) return true; } +static bool fold_ctpop(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_eqv(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_exts(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_extu(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + static bool fold_mb(OptContext *ctx, TCGOp *op) { /* Eliminate duplicate and redundant fence instructions. */ @@ -716,6 +790,41 @@ static bool fold_mb(OptContext *ctx, TCGOp *op) return true; } +static bool fold_multiply(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_nand(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_neg(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_nor(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_not(OptContext *ctx, TCGOp *op) +{ + return fold_const1(ctx, op); +} + +static bool fold_or(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_orc(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) { /* Opcodes that touch guest memory stop the mb optimization. */ @@ -730,6 +839,21 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) return false; } +static bool fold_shift(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_sub(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + +static bool fold_xor(OptContext *ctx, TCGOp *op) +{ + return fold_const2(ctx, op); +} + /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { @@ -1276,26 +1400,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(not): - CASE_OP_32_64(neg): - CASE_OP_32_64(ext8s): - CASE_OP_32_64(ext8u): - CASE_OP_32_64(ext16s): - CASE_OP_32_64(ext16u): - CASE_OP_32_64(ctpop): - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - if (arg_is_const(op->args[1])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - CASE_OP_32_64(bswap16): CASE_OP_32_64(bswap32): case INDEX_op_bswap64_i64: @@ -1307,36 +1411,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(add): - CASE_OP_32_64(sub): - CASE_OP_32_64(mul): - CASE_OP_32_64(or): - CASE_OP_32_64(and): - CASE_OP_32_64(xor): - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - CASE_OP_32_64(andc): - CASE_OP_32_64(orc): - CASE_OP_32_64(eqv): - CASE_OP_32_64(nand): - CASE_OP_32_64(nor): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - CASE_OP_32_64(div): - CASE_OP_32_64(divu): - CASE_OP_32_64(rem): - CASE_OP_32_64(remu): - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, - arg_info(op->args[2])->val); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - CASE_OP_32_64(clz): CASE_OP_32_64(ctz): if (arg_is_const(op->args[1])) { @@ -1637,9 +1711,71 @@ void tcg_optimize(TCGContext *s) } break; + default: + break; + + /* ---------------------------------------------------------- */ + /* Sorted alphabetically by opcode as much as possible. */ + + CASE_OP_32_64_VEC(add): + done = fold_add(&ctx, op); + break; + CASE_OP_32_64_VEC(and): + done = fold_and(&ctx, op); + break; + CASE_OP_32_64_VEC(andc): + done = fold_andc(&ctx, op); + break; + CASE_OP_32_64(ctpop): + done = fold_ctpop(&ctx, op); + break; + CASE_OP_32_64(div): + CASE_OP_32_64(divu): + done = fold_const2(&ctx, op); + break; + CASE_OP_32_64(eqv): + done = fold_eqv(&ctx, op); + break; + CASE_OP_32_64(ext8s): + CASE_OP_32_64(ext16s): + case INDEX_op_ext32s_i64: + case INDEX_op_ext_i32_i64: + done = fold_exts(&ctx, op); + break; + CASE_OP_32_64(ext8u): + CASE_OP_32_64(ext16u): + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + done = fold_extu(&ctx, op); + break; case INDEX_op_mb: done = fold_mb(&ctx, op); break; + CASE_OP_32_64(mul): + CASE_OP_32_64(mulsh): + CASE_OP_32_64(muluh): + done = fold_multiply(&ctx, op); + break; + CASE_OP_32_64(nand): + done = fold_nand(&ctx, op); + break; + CASE_OP_32_64(neg): + done = fold_neg(&ctx, op); + break; + CASE_OP_32_64(nor): + done = fold_nor(&ctx, op); + break; + CASE_OP_32_64_VEC(not): + done = fold_not(&ctx, op); + break; + CASE_OP_32_64_VEC(or): + done = fold_or(&ctx, op); + break; + CASE_OP_32_64_VEC(orc): + done = fold_orc(&ctx, op); + break; case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: done = fold_qemu_ld(&ctx, op); @@ -1649,8 +1785,22 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_st_i64: done = fold_qemu_st(&ctx, op); break; - - default: + CASE_OP_32_64(rem): + CASE_OP_32_64(remu): + done = fold_const2(&ctx, op); + break; + CASE_OP_32_64(rotl): + CASE_OP_32_64(rotr): + CASE_OP_32_64(sar): + CASE_OP_32_64(shl): + CASE_OP_32_64(shr): + done = fold_shift(&ctx, op); + break; + CASE_OP_32_64_VEC(sub): + done = fold_sub(&ctx, op); + break; + CASE_OP_32_64_VEC(xor): + done = fold_xor(&ctx, op); break; } From patchwork Thu Oct 21 21:05:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516083 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp337778imj; Thu, 21 Oct 2021 14:21:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4kMHqTqi24i4AdgJOyDtf6CDGNPvlcLTKm1Efr3FXfsPL+hHHk0OLyxdhpVJMX7CTUlQu X-Received: by 2002:a05:6808:90e:: with SMTP id w14mr6270735oih.131.1634851311511; Thu, 21 Oct 2021 14:21:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851311; cv=none; d=google.com; s=arc-20160816; b=07faarAPCkKzzzlh6sGllwWif70IO2KMfpmUDDDzuy99fwC1VeVh25dSkX+n17/c05 U2ZdaYRIex5hGrszIc7d2BE7KRMXM7IUzy+rtWAH0CCPnXa/6i4KphKq0Eqduh5sCQdK n7wPMP+i7BNAOLW3W+oJpOnLeduCL1g+F3TZO2mYAj55qo7m1XliY+bdQyU06/CaZYku AwSa7k0LVDYm2Nb9eGGdfEs2MnKxx2kqgL7h10ghcdM9ucv7rbEo66mkx9r/vTU2gb/K wQSX5ti+C5Ms1+bCsQJTqRJtfxwLOh1vcbNpFgQmhMxM9saylFr02hsK6ixIA8wbfibb /HmA== ARC-Message-Signature: i=1; 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Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 145 ++++++++++++++++++++++++------------------------- 1 file changed, 72 insertions(+), 73 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index e66d935808..0eaa0127f3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -839,6 +839,75 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) return false; } +static bool fold_setcond2(OptContext *ctx, TCGOp *op) +{ + TCGCond cond = op->args[5]; + int i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond); + int inv = 0; + + if (i >= 0) { + goto do_setcond_const; + } + + switch (cond) { + case TCG_COND_LT: + case TCG_COND_GE: + /* + * Simplify LT/GE comparisons vs zero to a single compare + * vs the high word of the input. + */ + if (arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0 && + arg_is_const(op->args[4]) && arg_info(op->args[4])->val == 0) { + goto do_setcond_high; + } + break; + + case TCG_COND_NE: + inv = 1; + QEMU_FALLTHROUGH; + case TCG_COND_EQ: + /* + * Simplify EQ/NE comparisons where one of the pairs + * can be simplified. + */ + i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1], + op->args[3], cond); + switch (i ^ inv) { + case 0: + goto do_setcond_const; + case 1: + goto do_setcond_high; + } + + i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2], + op->args[4], cond); + switch (i ^ inv) { + case 0: + goto do_setcond_const; + case 1: + op->args[2] = op->args[3]; + op->args[3] = cond; + op->opc = INDEX_op_setcond_i32; + break; + } + break; + + default: + break; + + do_setcond_high: + op->args[1] = op->args[2]; + op->args[2] = op->args[4]; + op->args[3] = cond; + op->opc = INDEX_op_setcond_i32; + break; + } + return false; + + do_setcond_const: + return tcg_opt_gen_movi(ctx, op, op->args[0], i); +} + static bool fold_shift(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1638,79 +1707,6 @@ void tcg_optimize(TCGContext *s) } break; - case INDEX_op_setcond2_i32: - i = do_constant_folding_cond2(&op->args[1], &op->args[3], - op->args[5]); - if (i >= 0) { - do_setcond_const: - tcg_opt_gen_movi(&ctx, op, op->args[0], i); - continue; - } - if ((op->args[5] == TCG_COND_LT || op->args[5] == TCG_COND_GE) - && arg_is_const(op->args[3]) - && arg_info(op->args[3])->val == 0 - && arg_is_const(op->args[4]) - && arg_info(op->args[4])->val == 0) { - /* Simplify LT/GE comparisons vs zero to a single compare - vs the high word of the input. */ - do_setcond_high: - reset_temp(op->args[0]); - arg_info(op->args[0])->z_mask = 1; - op->opc = INDEX_op_setcond_i32; - op->args[1] = op->args[2]; - op->args[2] = op->args[4]; - op->args[3] = op->args[5]; - break; - } - if (op->args[5] == TCG_COND_EQ) { - /* Simplify EQ comparisons where one of the pairs - can be simplified. */ - i = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[1], op->args[3], - TCG_COND_EQ); - if (i == 0) { - goto do_setcond_const; - } else if (i > 0) { - goto do_setcond_high; - } - i = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[2], op->args[4], - TCG_COND_EQ); - if (i == 0) { - goto do_setcond_high; - } else if (i < 0) { - break; - } - do_setcond_low: - reset_temp(op->args[0]); - arg_info(op->args[0])->z_mask = 1; - op->opc = INDEX_op_setcond_i32; - op->args[2] = op->args[3]; - op->args[3] = op->args[5]; - break; - } - if (op->args[5] == TCG_COND_NE) { - /* Simplify NE comparisons where one of the pairs - can be simplified. */ - i = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[1], op->args[3], - TCG_COND_NE); - if (i == 0) { - goto do_setcond_high; - } else if (i > 0) { - goto do_setcond_const; - } - i = do_constant_folding_cond(INDEX_op_setcond_i32, - op->args[2], op->args[4], - TCG_COND_NE); - if (i == 0) { - goto do_setcond_low; - } else if (i > 0) { - goto do_setcond_const; - } - } - break; - default: break; @@ -1796,6 +1792,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(shr): done = fold_shift(&ctx, op); break; + case INDEX_op_setcond2_i32: + done = fold_setcond2(&ctx, op); + break; CASE_OP_32_64_VEC(sub): done = fold_sub(&ctx, op); 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[209.51.188.17]) by mx.google.com with ESMTPS id s15si11607401otu.78.2021.10.21.14.28.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:28:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bKhqNmXL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfcL-0003OZ-13 for patch@linaro.org; Thu, 21 Oct 2021 17:28:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfGG-0007dp-PQ for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:06:07 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:40707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfGA-0004IU-1H for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:06:04 -0400 Received: by mail-pf1-x42f.google.com with SMTP id o133so1754302pfg.7 for ; Thu, 21 Oct 2021 14:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=22jk084Ht2aDDriMLcF4JyJ4faz6WKunCCcyD0GHKRg=; b=bKhqNmXL60n4HFJCILoCOBbxjaK+YbtoeEI6pFTCI9l1xuBVNETaJnN/ALzNWxAByq wNmaIPSfxL+Lk1nSHWoasg/aJM6k0bEaKLzcCyec+CmsaGvhPT/xcmYrFPMyM6uIQ8rA LAoVO2OdyhJfajVpPmMM5FlJOUhiwePBD46mYo+yEfMI5heFDj2mjOhdLg5wsT8rjp/z SrrRNGaO8SiS0/gfRbxRYPAhX+tF9zUPSrR0ATMfy6zAfObumrYQ0whzX2zevVrnVHcJ VzJ9MhredxA729APannR5ln/YaUm4L5H4lPa+MPtX6ldU5pxotvpAKlo4kaXA7uSo5nH cBoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=22jk084Ht2aDDriMLcF4JyJ4faz6WKunCCcyD0GHKRg=; b=Kiikr8n5ZDGoOawkE6LBqHarodVlqFt0jw6ylXEOroQv6mVRk+sGL6pdyACU8phpxK V0Smpr5ZOU535tn30yW5TOCmklQSQxo7Os5vuAGswM0D24v2OdtOh36wkfQ7SM6duLCw WH0RLktt7EmMD0sJCAaiHvI1LFJ3PHGyxVld3EJ0xR9BMxh6iEpqAaIp2JgxxGxNIO++ W5YQPx0EBIQLMGSB4mqPss7QKxYLLymhbkFxPVwzCUyWpizvHqmv/LTOIljzCQM+qunB d3s4Q+JYJ5jZYs5o7ZbSKDZhvOkzaqiGNq7+JBVvnUdvf0sjX+B8QbSlbknDh28GyhM8 o2Sg== X-Gm-Message-State: AOAM5308HKQoussIG6f0bbsEA6fDlixJlIDGxhNsEW0O1qnsUcXqw/az 52qsGcQ3RrFp9rCrF2B92Ai3j8qcnqM1pg== X-Received: by 2002:a05:6a00:1681:b0:46f:6fc0:e515 with SMTP id k1-20020a056a00168100b0046f6fc0e515mr5557423pfc.11.1634850352969; Thu, 21 Oct 2021 14:05:52 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:05:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/48] tcg/optimize: Split out fold_brcond2 Date: Thu, 21 Oct 2021 14:05:08 -0700 Message-Id: <20211021210539.825582-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reduce some code duplication by folding the NE and EQ cases. Signed-off-by: Richard Henderson --- tcg/optimize.c | 159 +++++++++++++++++++++++++------------------------ 1 file changed, 81 insertions(+), 78 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 0eaa0127f3..61a6221ad2 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -714,6 +714,84 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_brcond2(OptContext *ctx, TCGOp *op) +{ + TCGCond cond = op->args[4]; + int i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond); + TCGArg label = op->args[5]; + int inv = 0; + + if (i >= 0) { + goto do_brcond_const; + } + + switch (cond) { + case TCG_COND_LT: + case TCG_COND_GE: + /* + * Simplify LT/GE comparisons vs zero to a single compare + * vs the high word of the input. + */ + if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == 0 && + arg_is_const(op->args[3]) && arg_info(op->args[3])->val == 0) { + goto do_brcond_high; + } + break; + + case TCG_COND_NE: + inv = 1; + QEMU_FALLTHROUGH; + case TCG_COND_EQ: + /* + * Simplify EQ/NE comparisons where one of the pairs + * can be simplified. + */ + i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0], + op->args[2], cond); + switch (i ^ inv) { + case 0: + goto do_brcond_const; + case 1: + goto do_brcond_high; + } + + i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1], + op->args[3], cond); + switch (i ^ inv) { + case 0: + goto do_brcond_const; + case 1: + op->opc = INDEX_op_brcond_i32; + op->args[1] = op->args[2]; + op->args[2] = cond; + op->args[3] = label; + break; + } + break; + + default: + break; + + do_brcond_high: + op->opc = INDEX_op_brcond_i32; + op->args[0] = op->args[1]; + op->args[1] = op->args[3]; + op->args[2] = cond; + op->args[3] = label; + break; + + do_brcond_const: + if (i == 0) { + tcg_op_remove(ctx->tcg, op); + return true; + } + op->opc = INDEX_op_br; + op->args[0] = label; + break; + } + return false; +} + static bool fold_call(OptContext *ctx, TCGOp *op) { TCGContext *s = ctx->tcg; @@ -1629,84 +1707,6 @@ void tcg_optimize(TCGContext *s) } break; - case INDEX_op_brcond2_i32: - i = do_constant_folding_cond2(&op->args[0], &op->args[2], - op->args[4]); - if (i == 0) { - do_brcond_false: - tcg_op_remove(s, op); - continue; - } - if (i > 0) { - do_brcond_true: - op->opc = opc = INDEX_op_br; - op->args[0] = op->args[5]; - break; - } - if ((op->args[4] == TCG_COND_LT || op->args[4] == TCG_COND_GE) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0 - && arg_is_const(op->args[3]) - && arg_info(op->args[3])->val == 0) { - /* Simplify LT/GE comparisons vs zero to a single compare - vs the high word of the input. */ - do_brcond_high: - op->opc = opc = INDEX_op_brcond_i32; - op->args[0] = op->args[1]; - op->args[1] = op->args[3]; - op->args[2] = op->args[4]; - op->args[3] = op->args[5]; - break; - } - if (op->args[4] == TCG_COND_EQ) { - /* Simplify EQ comparisons where one of the pairs - can be simplified. */ - i = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[0], op->args[2], - TCG_COND_EQ); - if (i == 0) { - goto do_brcond_false; - } else if (i > 0) { - goto do_brcond_high; - } - i = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[1], op->args[3], - TCG_COND_EQ); - if (i == 0) { - goto do_brcond_false; - } else if (i < 0) { - break; - } - do_brcond_low: - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - op->opc = INDEX_op_brcond_i32; - op->args[1] = op->args[2]; - op->args[2] = op->args[4]; - op->args[3] = op->args[5]; - break; - } - if (op->args[4] == TCG_COND_NE) { - /* Simplify NE comparisons where one of the pairs - can be simplified. */ - i = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[0], op->args[2], - TCG_COND_NE); - if (i == 0) { - goto do_brcond_high; - } else if (i > 0) { - goto do_brcond_true; - } - i = do_constant_folding_cond(INDEX_op_brcond_i32, - op->args[1], op->args[3], - TCG_COND_NE); - if (i == 0) { - goto do_brcond_low; - } else if (i > 0) { - goto do_brcond_true; - } - } - break; - default: break; @@ -1722,6 +1722,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(andc): done = fold_andc(&ctx, op); break; + case INDEX_op_brcond2_i32: + done = fold_brcond2(&ctx, op); + break; CASE_OP_32_64(ctpop): done = fold_ctpop(&ctx, op); break; From patchwork Thu Oct 21 21:05:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516079 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp335571imj; Thu, 21 Oct 2021 14:18:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwk9VfF4bdw23VLoVTGdQekHOcL5W3CAdZxc9LrpPuZuh6yknYXshipxB0dp2rVMQ/P7k/i X-Received: by 2002:a05:6830:1f27:: with SMTP id e7mr6845827oth.234.1634851139763; Thu, 21 Oct 2021 14:18:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851139; cv=none; d=google.com; s=arc-20160816; b=fWfMc6MjAHuld9QRzYD5VpTRTu42lDT36hX2GSoQZxS9vwpexuaLYTtmQ6cf0LrOjI RYiYUVFErj8McOFfg6KE+x5JZliEPquuBjQOJHPnhFXBK4fF9u225appLcL4AQDzGvXn bYbc35BFlgB3t6VXQqTYJBZ6/c+SfwQ8tSCBhrFGpW6VDFuz7ZaXcr23yUIvH0g/gDMc n/FYHqg/WjdZZ09+8A/2hsO1dltDWejrF8K/b+aR85CJ31X5Ws/61dzLgRlawX8ZreQ4 GsdT6/WdMOXZ0qeqoT4E16CQ2h+WGbHvzxWk6ifMHX0zlFaSKNLGQuRNG/A8ckR0Fm/I q4WQ== ARC-Message-Signature: i=1; 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Thu, 21 Oct 2021 14:05:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/48] tcg/optimize: Split out fold_brcond Date: Thu, 21 Oct 2021 14:05:09 -0700 Message-Id: <20211021210539.825582-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index 61a6221ad2..9059e917cf 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -714,6 +714,22 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_brcond(OptContext *ctx, TCGOp *op) +{ + TCGCond cond = op->args[2]; + int i = do_constant_folding_cond(op->opc, op->args[0], op->args[1], cond); + + if (i == 0) { + tcg_op_remove(ctx->tcg, op); + return true; + } + if (i > 0) { + op->opc = INDEX_op_br; + op->args[0] = op->args[3]; + } + return false; +} + static bool fold_brcond2(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[4]; @@ -1626,20 +1642,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(brcond): - i = do_constant_folding_cond(opc, op->args[0], - op->args[1], op->args[2]); - if (i == 0) { - tcg_op_remove(s, op); - continue; - } else if (i > 0) { - memset(&ctx.temps_used, 0, sizeof(ctx.temps_used)); - op->opc = opc = INDEX_op_br; - op->args[0] = op->args[3]; - break; - } - break; - CASE_OP_32_64(movcond): i = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[5]); @@ -1722,6 +1724,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(andc): done = fold_andc(&ctx, op); break; + CASE_OP_32_64(brcond): + done = fold_brcond(&ctx, op); + break; case INDEX_op_brcond2_i32: done = fold_brcond2(&ctx, op); break; From patchwork Thu Oct 21 21:05:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516080 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp335592imj; Thu, 21 Oct 2021 14:19:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzT46HAkCYOC+/e8Yep9aQN8iFKQMjHj1ECfWIn8pJgspySCv9RI/KLZZpza3KXVp+JqSzB X-Received: by 2002:a05:6820:1015:: with SMTP id v21mr6224029oor.47.1634851141091; Thu, 21 Oct 2021 14:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851141; cv=none; d=google.com; s=arc-20160816; b=rsxIczQYHLZTmIBCiIHKEr8kWg2Zb4UsspWd8eUWZ46u+tQ6trfGaUqq/J/1UDJfmM /xRd9G8xKFIC5a4JFjqA0tzLQ/AW+nxnVi+kBE1cKRz3a207KI/OMoeTzTgBHgDUgjBL Sr5uW8RwLQIJNd9xL7UO60sVj5f4rraGfL56VXOLtfrqzvUfeTnnFjT4pajKDh07v1wO Q/qPReb7yTK+w2pZWyZacs0hJ/1m1DlPav6EFP31yIeoPG9rPZRgfRyCGwsaIT/B3PgL WwDHm/6MBFmWMepvwZuVCGBq+zwKkiaJvcZCsyWHz1/7YwyFgrgnPC6DZqW4VHmuvybL 0hQA== ARC-Message-Signature: i=1; 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Thu, 21 Oct 2021 14:05:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/48] tcg/optimize: Split out fold_setcond Date: Thu, 21 Oct 2021 14:05:10 -0700 Message-Id: <20211021210539.825582-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Luis Pires Signed-off-by: Richard Henderson --- tcg/optimize.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index 9059e917cf..2086e894c6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -933,6 +933,17 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) return false; } +static bool fold_setcond(OptContext *ctx, TCGOp *op) +{ + TCGCond cond = op->args[3]; + int i = do_constant_folding_cond(op->opc, op->args[1], op->args[2], cond); + + if (i >= 0) { + return tcg_opt_gen_movi(ctx, op, op->args[0], i); + } + return false; +} + static bool fold_setcond2(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[5]; @@ -1633,15 +1644,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(setcond): - i = do_constant_folding_cond(opc, op->args[1], - op->args[2], op->args[3]); - if (i >= 0) { - tcg_opt_gen_movi(&ctx, op, op->args[0], i); - continue; - } - break; - CASE_OP_32_64(movcond): i = do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[5]); @@ -1800,6 +1802,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(shr): done = fold_shift(&ctx, op); break; + CASE_OP_32_64(setcond): + done = fold_setcond(&ctx, op); + break; case INDEX_op_setcond2_i32: done = fold_setcond2(&ctx, op); break; From patchwork Thu Oct 21 21:05:11 2021 Content-Type: text/plain; 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Thu, 21 Oct 2021 14:05:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 20/48] tcg/optimize: Split out fold_mulu2_i32 Date: Thu, 21 Oct 2021 14:05:11 -0700 Message-Id: <20211021210539.825582-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 2086e894c6..142f445cb1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -889,6 +889,24 @@ static bool fold_multiply(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { + uint32_t a = arg_info(op->args[2])->val; + uint32_t b = arg_info(op->args[3])->val; + uint64_t r = (uint64_t)a * b; + TCGArg rl, rh; + TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32); + + rl = op->args[0]; + rh = op->args[1]; + tcg_opt_gen_movi(ctx, op, rl, (int32_t)r); + tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(r >> 32)); + return true; + } + return false; +} + static bool fold_nand(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1695,22 +1713,6 @@ void tcg_optimize(TCGContext *s) } break; - case INDEX_op_mulu2_i32: - if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { - uint32_t a = arg_info(op->args[2])->val; - uint32_t b = arg_info(op->args[3])->val; - uint64_t r = (uint64_t)a * b; - TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); - - rl = op->args[0]; - rh = op->args[1]; - tcg_opt_gen_movi(&ctx, op, rl, (int32_t)r); - tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(r >> 32)); - continue; - } - break; - default: break; @@ -1764,6 +1766,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(muluh): done = fold_multiply(&ctx, op); break; + case INDEX_op_mulu2_i32: + done = fold_mulu2_i32(&ctx, op); + break; CASE_OP_32_64(nand): done = fold_nand(&ctx, op); break; From patchwork Thu Oct 21 21:05:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516091 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp341875imj; Thu, 21 Oct 2021 14:27:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgqh3xhLCE3/uvXjDn1By93o49qlZZWW0zN4sPQ78H4ytxBXAwmXKtMSp8oNgMO42MIZ5+ X-Received: by 2002:a05:6122:da7:: with SMTP id bc39mr8965236vkb.22.1634851646212; Thu, 21 Oct 2021 14:27:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851646; cv=none; d=google.com; s=arc-20160816; b=uh7UxbZqZpkW+W8m71tZPDI5yf15Nbtm6KUjZqeizfU+yHwRfIEnHQd8/M7+CRlkB6 IktydrM0cF4k+HxxaC/pLHDaqo/CIocszhWg+QGHS0k8xlLi8WFKVfKm1iusSlRXxgLT fmaBcUDsb4+DcTzldJpUj6KTCf5HnWJ/03ERg721aI2EFLKdz7xUYdCJF/k0P7uSV6z9 qx3v+W/UYok0E7/sADbkOXdH0jlDJ6gYRC5oqkc7hRiuf1UyXOJfp2NDySZaylXbFzWu S/hZEp9O5WWU8QdkkHJPX7Ch3UzuKttAdPhRIUaE0m4RhJA+4ahwOjUkB22kg2jRd5F/ F9Rw== ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson --- tcg/optimize.c | 70 +++++++++++++++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 26 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 142f445cb1..eb6f1581ac 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -704,6 +704,39 @@ static bool fold_add(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add) +{ + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) && + arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { + uint32_t al = arg_info(op->args[2])->val; + uint32_t ah = arg_info(op->args[3])->val; + uint32_t bl = arg_info(op->args[4])->val; + uint32_t bh = arg_info(op->args[5])->val; + uint64_t a = ((uint64_t)ah << 32) | al; + uint64_t b = ((uint64_t)bh << 32) | bl; + TCGArg rl, rh; + TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32); + + if (add) { + a += b; + } else { + a -= b; + } + + rl = op->args[0]; + rh = op->args[1]; + tcg_opt_gen_movi(ctx, op, rl, (int32_t)a); + tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(a >> 32)); + return true; + } + return false; +} + +static bool fold_add2_i32(OptContext *ctx, TCGOp *op) +{ + return fold_addsub2_i32(ctx, op, true); +} + static bool fold_and(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1041,6 +1074,11 @@ static bool fold_sub(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_sub2_i32(OptContext *ctx, TCGOp *op) +{ + return fold_addsub2_i32(ctx, op, false); +} + static bool fold_xor(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1686,32 +1724,6 @@ void tcg_optimize(TCGContext *s) } break; - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) - && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { - uint32_t al = arg_info(op->args[2])->val; - uint32_t ah = arg_info(op->args[3])->val; - uint32_t bl = arg_info(op->args[4])->val; - uint32_t bh = arg_info(op->args[5])->val; - uint64_t a = ((uint64_t)ah << 32) | al; - uint64_t b = ((uint64_t)bh << 32) | bl; - TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32); - - if (opc == INDEX_op_add2_i32) { - a += b; - } else { - a -= b; - } - - rl = op->args[0]; - rh = op->args[1]; - tcg_opt_gen_movi(&ctx, op, rl, (int32_t)a); - tcg_opt_gen_movi(&ctx, op2, rh, (int32_t)(a >> 32)); - continue; - } - break; default: break; @@ -1722,6 +1734,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(add): done = fold_add(&ctx, op); break; + case INDEX_op_add2_i32: + done = fold_add2_i32(&ctx, op); + break; CASE_OP_32_64_VEC(and): done = fold_and(&ctx, op); break; @@ -1816,6 +1831,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(sub): done = fold_sub(&ctx, op); break; + case INDEX_op_sub2_i32: + done = fold_sub2_i32(&ctx, op); + break; CASE_OP_32_64_VEC(xor): done = fold_xor(&ctx, op); break; From patchwork Thu Oct 21 21:05:13 2021 Content-Type: text/plain; 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Thu, 21 Oct 2021 14:05:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 22/48] tcg/optimize: Split out fold_movcond Date: Thu, 21 Oct 2021 14:05:13 -0700 Message-Id: <20211021210539.825582-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 56 ++++++++++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 25 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index eb6f1581ac..ed5a304089 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -917,6 +917,34 @@ static bool fold_mb(OptContext *ctx, TCGOp *op) return true; } +static bool fold_movcond(OptContext *ctx, TCGOp *op) +{ + TCGOpcode opc = op->opc; + TCGCond cond = op->args[5]; + int i = do_constant_folding_cond(opc, op->args[1], op->args[2], cond); + + if (i >= 0) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]); + } + + if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { + uint64_t tv = arg_info(op->args[3])->val; + uint64_t fv = arg_info(op->args[4])->val; + + opc = (opc == INDEX_op_movcond_i32 + ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64); + + if (tv == 1 && fv == 0) { + op->opc = opc; + op->args[3] = cond; + } else if (fv == 1 && tv == 0) { + op->opc = opc; + op->args[3] = tcg_invert_cond(cond); + } + } + return false; +} + static bool fold_multiply(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1700,31 +1728,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(movcond): - i = do_constant_folding_cond(opc, op->args[1], - op->args[2], op->args[5]); - if (i >= 0) { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[4 - i]); - continue; - } - if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { - uint64_t tv = arg_info(op->args[3])->val; - uint64_t fv = arg_info(op->args[4])->val; - TCGCond cond = op->args[5]; - - if (fv == 1 && tv == 0) { - cond = tcg_invert_cond(cond); - } else if (!(tv == 1 && fv == 0)) { - break; - } - op->args[3] = cond; - op->opc = opc = (opc == INDEX_op_movcond_i32 - ? INDEX_op_setcond_i32 - : INDEX_op_setcond_i64); - } - break; - - default: break; @@ -1776,6 +1779,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_mb: done = fold_mb(&ctx, op); break; + CASE_OP_32_64(movcond): + done = fold_movcond(&ctx, op); + break; CASE_OP_32_64(mul): CASE_OP_32_64(mulsh): CASE_OP_32_64(muluh): From patchwork Thu Oct 21 21:05:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516086 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp338922imj; Thu, 21 Oct 2021 14:23:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw//mePMe1A0N88hFrEKF91OCwosWVsaqVnDf7r7xyeLXBa47u94n3C4PwhVaeN2m7pj2Qi X-Received: by 2002:a67:d492:: with SMTP id g18mr9677003vsj.23.1634851401704; Thu, 21 Oct 2021 14:23:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851401; cv=none; d=google.com; s=arc-20160816; b=Yvm2AGgupv1w8WK7Q6J0alaE+6TcqRHZ704Mc1DEpNjRo/62lO1rZPYCMh9NSFVizC Kdw/SgdRhR4fYkG6ktNDVq1TEQFhnUk6rvnKsvXHmxvtBn5Jy8HDM+xLupFxoDXizyu9 lv5nN+s6zJMxhq/kstUSXE56dk394KLJouZsUxwIw4c7Kyt/buxPav9nv0zIYjwNtS3l dAleoNzRqIZ47thnxvIzMumHEz67titP7YDMTzWlEucugmkTwVLBzqYLrsr3AvnVZnrt hGIKZwdlEwP+q8cbYIPdzGfj6rHZETc+UxKU+WEa7sOArQAjKB0YUDA93FzA8i37LqMx FHCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bOobEJyobONUr+gZkyJIYSFjF1OtYpVc5oUN5hGeX/8=; b=QuKaHtQazINU/YPRCjMViqs6d+ZqiCK0KzP9m7wz38QJLO4+MRSxTivGkSCG6png9Y oDEnqm6G9ulf8kZa2xHGffW66smnmR93jcR5DxWe5meVNshPKT9L7G8X5Q2dwWHogOXt ev80YG3f3melN6ZEcz/45ENBLvzJOuvF3Zd0q1O//NGc3bKhbRXpukJeMdhaofs0L6Mi y0Q41+Hiw1iKFC8MPSQILJUQPWuP4HNrHf4kpom3P3+87BYrEsbld439FSJ8OU29dadK OWDw7BOZjX2ii/9J/lj0IjTWNuLgLTxCnRwzTZrm/lRiTOnhvC+HNtDEL/mwwheqcLj0 +e0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HExscu4f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 21 Oct 2021 14:05:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 23/48] tcg/optimize: Split out fold_extract2 Date: Thu, 21 Oct 2021 14:05:14 -0700 Message-Id: <20211021210539.825582-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index ed5a304089..885380bb22 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -883,6 +883,25 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_extract2(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + uint64_t v1 = arg_info(op->args[1])->val; + uint64_t v2 = arg_info(op->args[2])->val; + int shr = op->args[3]; + + if (op->opc == INDEX_op_extract2_i64) { + v1 >>= shr; + v2 <<= 64 - shr; + } else { + v1 = (uint32_t)v1 >> shr; + v2 = (int32_t)v2 << (32 - shr); + } + return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2); + } + return false; +} + static bool fold_exts(OptContext *ctx, TCGOp *op) { return fold_const1(ctx, op); @@ -1711,23 +1730,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(extract2): - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - uint64_t v1 = arg_info(op->args[1])->val; - uint64_t v2 = arg_info(op->args[2])->val; - int shr = op->args[3]; - - if (opc == INDEX_op_extract2_i64) { - tmp = (v1 >> shr) | (v2 << (64 - shr)); - } else { - tmp = (int32_t)(((uint32_t)v1 >> shr) | - ((uint32_t)v2 << (32 - shr))); - } - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - default: break; @@ -1762,6 +1764,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(eqv): done = fold_eqv(&ctx, op); break; + CASE_OP_32_64(extract2): + done = fold_extract2(&ctx, op); + break; CASE_OP_32_64(ext8s): CASE_OP_32_64(ext16s): case INDEX_op_ext32s_i64: From patchwork Thu Oct 21 21:05:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516098 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp345427imj; Thu, 21 Oct 2021 14:31:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxAwBzXtxPbYFe7ZsG7iJ44S/wMpGyOJzlfRYLKMt9aqPJUrRveCikWVwDedYPCJ0kubl7N X-Received: by 2002:aca:4185:: with SMTP id o127mr6706569oia.129.1634851919285; Thu, 21 Oct 2021 14:31:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851919; cv=none; d=google.com; s=arc-20160816; b=i+5v6a8VsO4RE1cqG+WKHJIal45NmmSfj5Jmp7zR9NYg8jj5tmB+SNsPN6+33PngUu K6LXhRa2oB5d5krHNnEY3lCn/H9eU8YokHILrQHiIyC424hxx6cK8J3DKzQuIzaV2TOa SSxFp9z//5v65ZsiNHjhULv9RydXdbSZ700efzi1cqfVU4DwL/Zn0JAovGZlmfMkptDT SMRBX5nESkZFXGWWYR4Sn8Xpp7OfJt9/BODuPV3GeFhx8h5uIxfqZyVvoGxHys+arIpB FG5jm5lS+6R0cJuF2npFQCWIDerAKpwkD+6g8fhq9B11ZZBB1mjyNlvEk/p5vhJDUSnr o+7w== ARC-Message-Signature: i=1; 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Thu, 21 Oct 2021 14:05:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 24/48] tcg/optimize: Split out fold_extract, fold_sextract Date: Thu, 21 Oct 2021 14:05:15 -0700 Message-Id: <20211021210539.825582-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 48 ++++++++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 885380bb22..3fffc5b200 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -883,6 +883,18 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_extract(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t; + + t = arg_info(op->args[1])->val; + t = extract64(t, op->args[2], op->args[3]); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return false; +} + static bool fold_extract2(OptContext *ctx, TCGOp *op) { if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { @@ -1111,6 +1123,18 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) return tcg_opt_gen_movi(ctx, op, op->args[0], i); } +static bool fold_sextract(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t; + + t = arg_info(op->args[1])->val; + t = sextract64(t, op->args[2], op->args[3]); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return false; +} + static bool fold_shift(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1712,24 +1736,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(extract): - if (arg_is_const(op->args[1])) { - tmp = extract64(arg_info(op->args[1])->val, - op->args[2], op->args[3]); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - - CASE_OP_32_64(sextract): - if (arg_is_const(op->args[1])) { - tmp = sextract64(arg_info(op->args[1])->val, - op->args[2], op->args[3]); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - default: break; @@ -1764,6 +1770,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(eqv): done = fold_eqv(&ctx, op); break; + CASE_OP_32_64(extract): + done = fold_extract(&ctx, op); + break; CASE_OP_32_64(extract2): done = fold_extract2(&ctx, op); break; @@ -1839,6 +1848,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_setcond2_i32: done = fold_setcond2(&ctx, op); break; + CASE_OP_32_64(sextract): + done = fold_sextract(&ctx, op); + break; CASE_OP_32_64_VEC(sub): done = fold_sub(&ctx, op); break; From patchwork Thu Oct 21 21:05:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516084 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp337812imj; 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Thu, 21 Oct 2021 14:05:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/48] tcg/optimize: Split out fold_deposit Date: Thu, 21 Oct 2021 14:05:16 -0700 Message-Id: <20211021210539.825582-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 3fffc5b200..9758d83e3e 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -878,6 +878,18 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) return fold_const1(ctx, op); } +static bool fold_deposit(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + uint64_t t1 = arg_info(op->args[1])->val; + uint64_t t2 = arg_info(op->args[2])->val; + + t1 = deposit64(t1, op->args[3], op->args[4], t2); + return tcg_opt_gen_movi(ctx, op, op->args[0], t1); + } + return false; +} + static bool fold_eqv(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1726,16 +1738,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(deposit): - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tmp = deposit64(arg_info(op->args[1])->val, - op->args[3], op->args[4], - arg_info(op->args[2])->val); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - default: break; @@ -1763,6 +1765,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(ctpop): done = fold_ctpop(&ctx, op); break; + CASE_OP_32_64(deposit): + done = fold_deposit(&ctx, op); + break; CASE_OP_32_64(div): CASE_OP_32_64(divu): done = fold_const2(&ctx, op); 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Thu, 21 Oct 2021 14:05:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 26/48] tcg/optimize: Split out fold_count_zeros Date: Thu, 21 Oct 2021 14:05:17 -0700 Message-Id: <20211021210539.825582-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 9758d83e3e..c54f839434 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -873,6 +873,20 @@ static bool fold_call(OptContext *ctx, TCGOp *op) return true; } +static bool fold_count_zeros(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t = arg_info(op->args[1])->val; + + if (t != 0) { + t = do_constant_folding(op->opc, t, 0); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); + } + return false; +} + static bool fold_ctpop(OptContext *ctx, TCGOp *op) { return fold_const1(ctx, op); @@ -1724,20 +1738,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(clz): - CASE_OP_32_64(ctz): - if (arg_is_const(op->args[1])) { - TCGArg v = arg_info(op->args[1])->val; - if (v != 0) { - tmp = do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - } else { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[2]); - } - continue; - } - break; - default: break; @@ -1762,6 +1762,10 @@ void tcg_optimize(TCGContext *s) case INDEX_op_brcond2_i32: done = fold_brcond2(&ctx, op); break; + CASE_OP_32_64(clz): + CASE_OP_32_64(ctz): + done = fold_count_zeros(&ctx, op); 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Thu, 21 Oct 2021 14:06:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/48] tcg/optimize: Split out fold_bswap Date: Thu, 21 Oct 2021 14:05:18 -0700 Message-Id: <20211021210539.825582-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org, =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index c54f839434..77b31680f1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -841,6 +841,17 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) return false; } +static bool fold_bswap(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t = arg_info(op->args[1])->val; + + t = do_constant_folding(op->opc, t, op->args[2]); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return false; +} + static bool fold_call(OptContext *ctx, TCGOp *op) { TCGContext *s = ctx->tcg; @@ -1727,17 +1738,6 @@ void tcg_optimize(TCGContext *s) } break; - CASE_OP_32_64(bswap16): - CASE_OP_32_64(bswap32): - case INDEX_op_bswap64_i64: - if (arg_is_const(op->args[1])) { - tmp = do_constant_folding(opc, arg_info(op->args[1])->val, - op->args[2]); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - default: break; @@ -1762,6 +1762,11 @@ void tcg_optimize(TCGContext *s) case INDEX_op_brcond2_i32: done = fold_brcond2(&ctx, op); break; + CASE_OP_32_64(bswap16): + CASE_OP_32_64(bswap32): + case INDEX_op_bswap64_i64: + done = fold_bswap(&ctx, op); + break; CASE_OP_32_64(clz): CASE_OP_32_64(ctz): done = fold_count_zeros(&ctx, op); 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Thu, 21 Oct 2021 14:06:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 28/48] tcg/optimize: Split out fold_dup, fold_dup2 Date: Thu, 21 Oct 2021 14:05:19 -0700 Message-Id: <20211021210539.825582-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/optimize.c | 53 +++++++++++++++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 22 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 77b31680f1..2d626c604a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -915,6 +915,31 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) return false; } +static bool fold_dup(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1])) { + uint64_t t = arg_info(op->args[1])->val; + t = dup_const(TCGOP_VECE(op), t); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + return false; +} + +static bool fold_dup2(OptContext *ctx, TCGOp *op) +{ + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + uint64_t t = deposit64(arg_info(op->args[1])->val, 32, 32, + arg_info(op->args[2])->val); + return tcg_opt_gen_movi(ctx, op, op->args[0], t); + } + + if (args_are_copies(op->args[1], op->args[2])) { + op->opc = INDEX_op_dup_vec; + TCGOP_VECE(op) = MO_32; + } + return false; +} + static bool fold_eqv(OptContext *ctx, TCGOp *op) { return fold_const2(ctx, op); @@ -1716,28 +1741,6 @@ void tcg_optimize(TCGContext *s) done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); break; - case INDEX_op_dup_vec: - if (arg_is_const(op->args[1])) { - tmp = arg_info(op->args[1])->val; - tmp = dup_const(TCGOP_VECE(op), tmp); - tcg_opt_gen_movi(&ctx, op, op->args[0], tmp); - continue; - } - break; - - case INDEX_op_dup2_vec: - assert(TCG_TARGET_REG_BITS == 32); - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - tcg_opt_gen_movi(&ctx, op, op->args[0], - deposit64(arg_info(op->args[1])->val, 32, 32, - arg_info(op->args[2])->val)); - continue; - } else if (args_are_copies(op->args[1], op->args[2])) { - op->opc = INDEX_op_dup_vec; - TCGOP_VECE(op) = MO_32; - } - break; - default: break; @@ -1781,6 +1784,12 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(divu): done = fold_const2(&ctx, op); break; + case INDEX_op_dup_vec: + done = fold_dup(&ctx, op); + break; + case INDEX_op_dup2_vec: + done = fold_dup2(&ctx, op); + break; CASE_OP_32_64(eqv): done = fold_eqv(&ctx, op); break; From patchwork Thu Oct 21 21:05:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516099 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp346569imj; 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After this, we have the option to convert the switch into a function dispatch table. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 2d626c604a..af055f05d3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1010,6 +1010,11 @@ static bool fold_mb(OptContext *ctx, TCGOp *op) return true; } +static bool fold_mov(OptContext *ctx, TCGOp *op) +{ + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); +} + static bool fold_movcond(OptContext *ctx, TCGOp *op) { TCGOpcode opc = op->opc; @@ -1733,20 +1738,11 @@ void tcg_optimize(TCGContext *s) break; } - /* Propagate constants through copy operations and do constant - folding. Constants will be substituted to arguments by register - allocator where needed and possible. Also detect copies. */ + /* + * Process each opcode. + * Sorted alphabetically by opcode as much as possible. + */ switch (opc) { - CASE_OP_32_64_VEC(mov): - done = tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); - break; - - default: - break; - - /* ---------------------------------------------------------- */ - /* Sorted alphabetically by opcode as much as possible. */ - CASE_OP_32_64_VEC(add): done = fold_add(&ctx, op); break; @@ -1816,6 +1812,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_mb: done = fold_mb(&ctx, op); break; + CASE_OP_32_64_VEC(mov): + done = fold_mov(&ctx, op); + break; CASE_OP_32_64(movcond): done = fold_movcond(&ctx, op); break; @@ -1883,6 +1882,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(xor): done = fold_xor(&ctx, op); break; + default: + break; } if (!done) { From patchwork Thu Oct 21 21:05:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516107 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp352082imj; Thu, 21 Oct 2021 14:40:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeOJouLAsZjOlsbeY9ZViBy90wFutxFDyQvkN3yIVD+FWdgdcFRQ1CuntiYZftyYxyXS85 X-Received: by 2002:a9d:6a45:: with SMTP id h5mr6762217otn.1.1634852424245; Thu, 21 Oct 2021 14:40:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852424; cv=none; d=google.com; s=arc-20160816; b=RqxYqa/NW2QN+uIDFDZVpaQqThADV+HXJCK5XPSz4Khmc7NsaUzmNlNICjMpCsjE8R u6ZjOH0BpnSywM1rw2+2JrAeEtgJ/c4aADxujdvcFlA9vce+Guk0/s1NahX6EZsPF6uO FJhmbfXERA+esIpNwRA4uIR5DNwrcaJru++DDzZWWCcHyN6MRh4FeWznVaqtioX3W9G9 qjtMopR1PNY/yfmAfMQhn5OZSBB7VQfe40sBIln8NO32daKNiW5u6lKSoskwdF/CNGEz 6vT2juhDN7M+7NKT10wxltgPIB4v1MLVAgiUrmgosNEz55DN8LNZ9vJIe6n33br+NETy sPqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2mtOn4rMVNP2RgfAFpzeI+ubeNI5mnnLuo1JiLFyiNQ=; b=SX5nhiEVVTVykga2gEBjzwwZs48Ubw9YdOpeXr4lTScVZDnA1cz6gT2frl3jhAv3C8 WtI+JXb4IA7Phf46HTNp0vc4aUxZyyrXHR2qIRxjqyGhAx1FWewfdGdCEk6lhEwr0MkS X3rPmHRr7Ct2r5tH3NnOCvWSfRoLS+OfaFWtgdQq7/jhTklkRobyHhIgLCFcvztzoGdD Ibsm5iOT0+C4ennai5uC7yaxYTv+LBqnwEJGQ+ENb52YGXr8iNq9cumFFaJ4iGgDxCd+ ulYeR7TaS4LCb6lUg/QXtsuNEG3MWedFvCE+cuJcBFhF7q/52Br4STApbf72Mhgt0TLX b7VQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JMMAYJoa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index af055f05d3..5ac7a45597 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -695,6 +695,15 @@ static bool fold_const2(OptContext *ctx, TCGOp *op) return false; } +/* If the binary operation has both arguments equal, fold to @i. */ +static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i) +{ + if (args_are_copies(op->args[1], op->args[2])) { + return tcg_opt_gen_movi(ctx, op, op->args[0], i); + } + return false; +} + /* * These outermost fold_ functions are sorted alphabetically. */ @@ -744,7 +753,11 @@ static bool fold_and(OptContext *ctx, TCGOp *op) static bool fold_andc(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xx_to_i(ctx, op, 0)) { + return true; + } + return false; } static bool fold_brcond(OptContext *ctx, TCGOp *op) @@ -1209,7 +1222,11 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) static bool fold_sub(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xx_to_i(ctx, op, 0)) { + return true; + } + return false; } static bool fold_sub2_i32(OptContext *ctx, TCGOp *op) @@ -1219,7 +1236,11 @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op) static bool fold_xor(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xx_to_i(ctx, op, 0)) { + return true; + } + return false; } /* Propagate constants and copies, fold constant expressions. */ @@ -1724,20 +1745,6 @@ void tcg_optimize(TCGContext *s) break; } - /* Simplify expression for "op r, a, a => movi r, 0" cases */ - switch (opc) { - CASE_OP_32_64_VEC(andc): - CASE_OP_32_64_VEC(sub): - CASE_OP_32_64_VEC(xor): - if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_movi(&ctx, op, op->args[0], 0); - continue; - } - break; - default: - break; - } - /* * Process each opcode. * Sorted alphabetically by opcode as much as possible. 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[209.51.188.17]) by mx.google.com with ESMTPS id 90si6303215otx.305.2021.10.21.14.30.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:30:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uoTduUiw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfdW-00066w-Il for patch@linaro.org; Thu, 21 Oct 2021 17:30:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfGL-0007fS-E4 for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:06:09 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:39654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfGH-0004bT-RL for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:06:09 -0400 Received: by mail-pl1-x62a.google.com with SMTP id t21so1283838plr.6 for ; Thu, 21 Oct 2021 14:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+uohhzNTf7E5o0HvirytHnR+Nn+FzxrY7IKuf21OlIs=; b=uoTduUiw0VNq2G20WtL0fK3YpHmLXYFNyhYdb9HjDo3WnkBPEcZcivjB8fXIKoiDNE ukBW6FSnLV1lwmpnn529Yf7h62Tig1675XOUZutQleRMOwwG3qgp024gXBHoUybO4YF2 v9yR0bnREiY0Cd9Mwwn4JFBKZZY9af0IWsfm/00cTiA1opY4loDkB5+pXdSoMn0ro8VP c0zzBKd2pHgDHZSbqE854YUEiu8NwO3FsBz8R7bASm1kdsTaR473fsaYPkb5wRPSHHdi DwC2/6oh10r2y7i9rujDuqz3S+3cqnXWtJumpK/TBnTo7vTkfP8IUJwfh4Xa3ekXrVZw 2NcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+uohhzNTf7E5o0HvirytHnR+Nn+FzxrY7IKuf21OlIs=; b=htJxo86OIwsmamcOynzbOWFhx+wImHY0x01Lny/l8CFHrco/S30NjS91+31eG7er5T lNpLOj6ATtAYcbLc258FPT15AHSQpNvcz9/j/Nofu60k0Lk5d1Tktz2S63IKmUW/6GmQ TAXOoE7ACM1coSY4Enc9PmEUCTwmOLmIvOyDuONV3e4v5bdNuRDiIKguq74B6tJw/mn5 GM+Lm/JYQaGGy1MI8xAEFaZTEOWiXVjpc/bOPVUjRnVLMZ4PDlnrr22y5PCDSJbjDSSS Mh3F+2aXRvWQkLhrOPMz4aacUp+gL+tW/bsnEmzFF07dWKP91Q1L73HsqWj9SgKGYlmG SoZA== X-Gm-Message-State: AOAM531zsvuEJoEs+h6bM1VGs4pdX9tlB65PtxsjOSgIyl7mUNQtGta4 ZrdCTuBg+c/CMw4aFHhU4eyGKqrZdKc= X-Received: by 2002:a17:90a:6b0d:: with SMTP id v13mr9331861pjj.138.1634850363487; Thu, 21 Oct 2021 14:06:03 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id g7sm5981670pgp.17.2021.10.21.14.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:06:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 31/48] tcg/optimize: Split out fold_xx_to_x Date: Thu, 21 Oct 2021 14:05:22 -0700 Message-Id: <20211021210539.825582-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org, =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pull the "op r, a, a => mov r, a" optimization into a function, and use it in the outer opcode fold functions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 5ac7a45597..8dfe8694da 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -704,8 +704,22 @@ static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i) return false; } +/* If the binary operation has both arguments equal, fold to identity. */ +static bool fold_xx_to_x(OptContext *ctx, TCGOp *op) +{ + if (args_are_copies(op->args[1], op->args[2])) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); + } + return false; +} + /* * These outermost fold_ functions are sorted alphabetically. + * + * The ordering of the transformations should be: + * 1) those that produce a constant + * 2) those that produce a copy + * 3) those that produce information about the result value. */ static bool fold_add(OptContext *ctx, TCGOp *op) @@ -748,7 +762,11 @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op) static bool fold_and(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xx_to_x(ctx, op)) { + return true; + } + return false; } static bool fold_andc(OptContext *ctx, TCGOp *op) @@ -1101,7 +1119,11 @@ static bool fold_not(OptContext *ctx, TCGOp *op) static bool fold_or(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xx_to_x(ctx, op)) { + return true; + } + return false; } static bool fold_orc(OptContext *ctx, TCGOp *op) @@ -1732,19 +1754,6 @@ void tcg_optimize(TCGContext *s) break; } - /* Simplify expression for "op r, a, a => mov r, a" cases */ - switch (opc) { - CASE_OP_32_64_VEC(or): - CASE_OP_32_64_VEC(and): - if (args_are_copies(op->args[1], op->args[2])) { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); - continue; - } - break; - default: - break; - } - /* * Process each opcode. * Sorted alphabetically by opcode as much as possible. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 8dfe8694da..78e2ff5b38 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -695,6 +695,15 @@ static bool fold_const2(OptContext *ctx, TCGOp *op) return false; } +/* If the binary operation has second argument @i, fold to @i. */ +static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i) +{ + if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) { + return tcg_opt_gen_movi(ctx, op, op->args[0], i); + } + return false; +} + /* If the binary operation has both arguments equal, fold to @i. */ static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i) { @@ -763,6 +772,7 @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op) static bool fold_and(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || + fold_xi_to_i(ctx, op, 0) || fold_xx_to_x(ctx, op)) { return true; } @@ -1076,7 +1086,11 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) static bool fold_multiply(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_i(ctx, op, 0)) { + return true; + } + return false; } static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op) @@ -1738,22 +1752,6 @@ void tcg_optimize(TCGContext *s) continue; } - /* Simplify expression for "op r, a, 0 => movi r, 0" cases */ - switch (opc) { - CASE_OP_32_64_VEC(and): - CASE_OP_32_64_VEC(mul): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - if (arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_movi(&ctx, op, op->args[0], 0); - continue; - } - break; - default: - break; - } - /* * Process each opcode. * Sorted alphabetically by opcode as much as possible. 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There are at least 4 places that used a def->flags ladder to determine the type of the operation being optimized. There were two places that assumed !TCG_OPF_64BIT means TCG_TYPE_I32, and so could potentially compute incorrect results for vector operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 130 ++++++++++++++++++++++++++++--------------------- 1 file changed, 75 insertions(+), 55 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 78e2ff5b38..c8b6afc745 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -51,6 +51,7 @@ typedef struct OptContext { /* In flight values from optimization. */ uint64_t z_mask; + TCGType type; } OptContext; static inline TempOptInfo *ts_info(TCGTemp *ts) @@ -187,7 +188,6 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) { TCGTemp *dst_ts = arg_temp(dst); TCGTemp *src_ts = arg_temp(src); - const TCGOpDef *def; TempOptInfo *di; TempOptInfo *si; uint64_t z_mask; @@ -201,16 +201,24 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) reset_ts(dst_ts); di = ts_info(dst_ts); si = ts_info(src_ts); - def = &tcg_op_defs[op->opc]; - if (def->flags & TCG_OPF_VECTOR) { - new_op = INDEX_op_mov_vec; - } else if (def->flags & TCG_OPF_64BIT) { - new_op = INDEX_op_mov_i64; - } else { + + switch (ctx->type) { + case TCG_TYPE_I32: new_op = INDEX_op_mov_i32; + break; + case TCG_TYPE_I64: + new_op = INDEX_op_mov_i64; + break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ + new_op = INDEX_op_mov_vec; + break; + default: + g_assert_not_reached(); } op->opc = new_op; - /* TCGOP_VECL and TCGOP_VECE remain unchanged. */ op->args[0] = dst; op->args[1] = src; @@ -237,20 +245,9 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, TCGArg dst, uint64_t val) { - const TCGOpDef *def = &tcg_op_defs[op->opc]; - TCGType type; - TCGTemp *tv; - - if (def->flags & TCG_OPF_VECTOR) { - type = TCGOP_VECL(op) + TCG_TYPE_V64; - } else if (def->flags & TCG_OPF_64BIT) { - type = TCG_TYPE_I64; - } else { - type = TCG_TYPE_I32; - } - /* Convert movi to mov with constant temp. */ - tv = tcg_constant_internal(type, val); + TCGTemp *tv = tcg_constant_internal(ctx->type, val); + init_ts_info(ctx, tv); return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); } @@ -420,11 +417,11 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y) } } -static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y) +static uint64_t do_constant_folding(TCGOpcode op, TCGType type, + uint64_t x, uint64_t y) { - const TCGOpDef *def = &tcg_op_defs[op]; uint64_t res = do_constant_folding_2(op, x, y); - if (!(def->flags & TCG_OPF_64BIT)) { + if (type == TCG_TYPE_I32) { res = (int32_t)res; } return res; @@ -510,19 +507,21 @@ static bool do_constant_folding_cond_eq(TCGCond c) * Return -1 if the condition can't be simplified, * and the result of the condition (0 or 1) if it can. */ -static int do_constant_folding_cond(TCGOpcode op, TCGArg x, +static int do_constant_folding_cond(TCGType type, TCGArg x, TCGArg y, TCGCond c) { uint64_t xv = arg_info(x)->val; uint64_t yv = arg_info(y)->val; if (arg_is_const(x) && arg_is_const(y)) { - const TCGOpDef *def = &tcg_op_defs[op]; - tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR)); - if (def->flags & TCG_OPF_64BIT) { - return do_constant_folding_cond_64(xv, yv, c); - } else { + switch (type) { + case TCG_TYPE_I32: return do_constant_folding_cond_32(xv, yv, c); + case TCG_TYPE_I64: + return do_constant_folding_cond_64(xv, yv, c); + default: + /* Only scalar comparisons are optimizable */ + return -1; } } else if (args_are_copies(x, y)) { return do_constant_folding_cond_eq(c); @@ -677,7 +676,7 @@ static bool fold_const1(OptContext *ctx, TCGOp *op) uint64_t t; t = arg_info(op->args[1])->val; - t = do_constant_folding(op->opc, t, 0); + t = do_constant_folding(op->opc, ctx->type, t, 0); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } return false; @@ -689,7 +688,7 @@ static bool fold_const2(OptContext *ctx, TCGOp *op) uint64_t t1 = arg_info(op->args[1])->val; uint64_t t2 = arg_info(op->args[2])->val; - t1 = do_constant_folding(op->opc, t1, t2); + t1 = do_constant_folding(op->opc, ctx->type, t1, t2); return tcg_opt_gen_movi(ctx, op, op->args[0], t1); } return false; @@ -791,7 +790,7 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) static bool fold_brcond(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[2]; - int i = do_constant_folding_cond(op->opc, op->args[0], op->args[1], cond); + int i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond); if (i == 0) { tcg_op_remove(ctx->tcg, op); @@ -836,7 +835,7 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) * Simplify EQ/NE comparisons where one of the pairs * can be simplified. */ - i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[0], + i = do_constant_folding_cond(TCG_TYPE_I32, op->args[0], op->args[2], cond); switch (i ^ inv) { case 0: @@ -845,7 +844,7 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) goto do_brcond_high; } - i = do_constant_folding_cond(INDEX_op_brcond_i32, op->args[1], + i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1], op->args[3], cond); switch (i ^ inv) { case 0: @@ -887,7 +886,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) if (arg_is_const(op->args[1])) { uint64_t t = arg_info(op->args[1])->val; - t = do_constant_folding(op->opc, t, op->args[2]); + t = do_constant_folding(op->opc, ctx->type, t, op->args[2]); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } return false; @@ -931,7 +930,7 @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op) uint64_t t = arg_info(op->args[1])->val; if (t != 0) { - t = do_constant_folding(op->opc, t, 0); + t = do_constant_folding(op->opc, ctx->type, t, 0); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); @@ -1058,9 +1057,8 @@ static bool fold_mov(OptContext *ctx, TCGOp *op) static bool fold_movcond(OptContext *ctx, TCGOp *op) { - TCGOpcode opc = op->opc; TCGCond cond = op->args[5]; - int i = do_constant_folding_cond(opc, op->args[1], op->args[2], cond); + int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); if (i >= 0) { return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]); @@ -1069,9 +1067,18 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { uint64_t tv = arg_info(op->args[3])->val; uint64_t fv = arg_info(op->args[4])->val; + TCGOpcode opc; - opc = (opc == INDEX_op_movcond_i32 - ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64); + switch (ctx->type) { + case TCG_TYPE_I32: + opc = INDEX_op_setcond_i32; + break; + case TCG_TYPE_I64: + opc = INDEX_op_setcond_i64; + break; + default: + g_assert_not_reached(); + } if (tv == 1 && fv == 0) { op->opc = opc; @@ -1162,7 +1169,7 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) static bool fold_setcond(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[3]; - int i = do_constant_folding_cond(op->opc, op->args[1], op->args[2], cond); + int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); if (i >= 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); @@ -1201,7 +1208,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) * Simplify EQ/NE comparisons where one of the pairs * can be simplified. */ - i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[1], + i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1], op->args[3], cond); switch (i ^ inv) { case 0: @@ -1210,7 +1217,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) goto do_setcond_high; } - i = do_constant_folding_cond(INDEX_op_setcond_i32, op->args[2], + i = do_constant_folding_cond(TCG_TYPE_I32, op->args[2], op->args[4], cond); switch (i ^ inv) { case 0: @@ -1312,6 +1319,15 @@ void tcg_optimize(TCGContext *s) init_arguments(&ctx, op, def->nb_oargs + def->nb_iargs); copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs); + /* Pre-compute the type of the operation. */ + if (def->flags & TCG_OPF_VECTOR) { + ctx.type = TCG_TYPE_V64 + TCGOP_VECL(op); + } else if (def->flags & TCG_OPF_64BIT) { + ctx.type = TCG_TYPE_I64; + } else { + ctx.type = TCG_TYPE_I32; + } + /* For commutative operations make constant second argument */ switch (opc) { CASE_OP_32_64_VEC(add): @@ -1392,18 +1408,18 @@ void tcg_optimize(TCGContext *s) /* Proceed with possible constant folding. */ break; } - if (opc == INDEX_op_sub_i32) { + switch (ctx.type) { + case TCG_TYPE_I32: neg_op = INDEX_op_neg_i32; have_neg = TCG_TARGET_HAS_neg_i32; - } else if (opc == INDEX_op_sub_i64) { + break; + case TCG_TYPE_I64: neg_op = INDEX_op_neg_i64; have_neg = TCG_TARGET_HAS_neg_i64; - } else if (TCG_TARGET_HAS_neg_vec) { - TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64; - unsigned vece = TCGOP_VECE(op); + break; + default: neg_op = INDEX_op_neg_vec; - have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0; - } else { + have_neg = tcg_can_emit_vec_op(neg_op, ctx.type, TCGOP_VECE(op)) > 0; break; } if (!have_neg) { @@ -1457,15 +1473,19 @@ void tcg_optimize(TCGContext *s) TCGOpcode not_op; bool have_not; - if (def->flags & TCG_OPF_VECTOR) { + switch (ctx.type) { + default: not_op = INDEX_op_not_vec; have_not = TCG_TARGET_HAS_not_vec; - } else if (def->flags & TCG_OPF_64BIT) { + break; + case TCG_TYPE_I64: not_op = INDEX_op_not_i64; have_not = TCG_TARGET_HAS_not_i64; - } else { + break; + case TCG_TYPE_I32: not_op = INDEX_op_not_i32; have_not = TCG_TARGET_HAS_not_i32; + break; } if (!have_not) { break; @@ -1736,7 +1756,7 @@ void tcg_optimize(TCGContext *s) below, we can ignore high bits, but for further optimizations we need to record that the high bits contain garbage. */ partmask = z_mask; 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Create a couple more helpers to make this easy for the outer-most logical operations. Signed-off-by: Richard Henderson --- tcg/optimize.c | 154 +++++++++++++++++++++++++++---------------------- 1 file changed, 86 insertions(+), 68 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index c8b6afc745..71b4c3edb4 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -694,6 +694,52 @@ static bool fold_const2(OptContext *ctx, TCGOp *op) return false; } +/* + * Convert @op to NOT, if NOT is supported by the host. + * Return true f the conversion is successful, which will still + * indicate that the processing is complete. + */ +static bool fold_not(OptContext *ctx, TCGOp *op); +static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx) +{ + TCGOpcode not_op; + bool have_not; + + switch (ctx->type) { + case TCG_TYPE_I32: + not_op = INDEX_op_not_i32; + have_not = TCG_TARGET_HAS_not_i32; + break; + case TCG_TYPE_I64: + not_op = INDEX_op_not_i64; + have_not = TCG_TARGET_HAS_not_i64; + break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + not_op = INDEX_op_not_vec; + have_not = TCG_TARGET_HAS_not_vec; + break; + default: + g_assert_not_reached(); + } + if (have_not) { + op->opc = not_op; + op->args[1] = op->args[idx]; + return fold_not(ctx, op); + } + return false; +} + +/* If the binary operation has first argument @i, fold to NOT. */ +static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i) +{ + if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == i) { + return fold_to_not(ctx, op, 2); + } + return false; +} + /* If the binary operation has second argument @i, fold to @i. */ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i) { @@ -703,6 +749,15 @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i) return false; } +/* If the binary operation has second argument @i, fold to NOT. */ +static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i) +{ + if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) { + return fold_to_not(ctx, op, 1); + } + return false; +} + /* If the binary operation has both arguments equal, fold to @i. */ static bool fold_xx_to_i(OptContext *ctx, TCGOp *op, uint64_t i) { @@ -781,7 +836,8 @@ static bool fold_and(OptContext *ctx, TCGOp *op) static bool fold_andc(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || - fold_xx_to_i(ctx, op, 0)) { + fold_xx_to_i(ctx, op, 0) || + fold_ix_to_not(ctx, op, -1)) { return true; } return false; @@ -982,7 +1038,11 @@ static bool fold_dup2(OptContext *ctx, TCGOp *op) static bool fold_eqv(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_not(ctx, op, 0)) { + return true; + } + return false; } static bool fold_extract(OptContext *ctx, TCGOp *op) @@ -1120,7 +1180,11 @@ static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op) static bool fold_nand(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_not(ctx, op, -1)) { + return true; + } + return false; } static bool fold_neg(OptContext *ctx, TCGOp *op) @@ -1130,12 +1194,22 @@ static bool fold_neg(OptContext *ctx, TCGOp *op) static bool fold_nor(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_not(ctx, op, 0)) { + return true; + } + return false; } static bool fold_not(OptContext *ctx, TCGOp *op) { - return fold_const1(ctx, op); + if (fold_const1(ctx, op)) { + return true; + } + + /* Because of fold_to_not, we want to always return true, via finish. */ + finish_folding(ctx, op); + return true; } static bool fold_or(OptContext *ctx, TCGOp *op) @@ -1149,7 +1223,11 @@ static bool fold_or(OptContext *ctx, TCGOp *op) static bool fold_orc(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_not(ctx, op, 0)) { + return true; + } + return false; } static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) @@ -1280,7 +1358,8 @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op) static bool fold_xor(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || - fold_xx_to_i(ctx, op, 0)) { + fold_xx_to_i(ctx, op, 0) || + fold_xi_to_not(ctx, op, -1)) { return true; } return false; @@ -1434,67 +1513,6 @@ void tcg_optimize(TCGContext *s) } } break; - CASE_OP_32_64_VEC(xor): - CASE_OP_32_64(nand): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == -1) { - i = 1; - goto try_not; - } - break; - CASE_OP_32_64(nor): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0) { - i = 1; - goto try_not; - } - break; - CASE_OP_32_64_VEC(andc): - if (!arg_is_const(op->args[2]) - && arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == -1) { - i = 2; - goto try_not; - } - break; - CASE_OP_32_64_VEC(orc): - CASE_OP_32_64(eqv): - if (!arg_is_const(op->args[2]) - && arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == 0) { - i = 2; - goto try_not; - } - break; - try_not: - { - TCGOpcode not_op; - bool have_not; - - switch (ctx.type) { - default: - not_op = INDEX_op_not_vec; - have_not = TCG_TARGET_HAS_not_vec; - break; - case TCG_TYPE_I64: - not_op = INDEX_op_not_i64; - have_not = TCG_TARGET_HAS_not_i64; - break; - case TCG_TYPE_I32: - not_op = INDEX_op_not_i32; - have_not = TCG_TARGET_HAS_not_i32; - break; - } - if (!have_not) { - break; - } - op->opc = not_op; - reset_temp(op->args[0]); - op->args[1] = op->args[i]; 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Signed-off-by: Richard Henderson --- tcg/optimize.c | 84 ++++++++++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 37 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/tcg/optimize.c b/tcg/optimize.c index 71b4c3edb4..e4cf746321 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1189,7 +1189,15 @@ static bool fold_nand(OptContext *ctx, TCGOp *op) static bool fold_neg(OptContext *ctx, TCGOp *op) { - return fold_const1(ctx, op); + if (fold_const1(ctx, op)) { + return true; + } + /* + * Because of fold_sub_to_neg, we want to always return true, + * via finish_folding. + */ + finish_folding(ctx, op); + return true; } static bool fold_nor(OptContext *ctx, TCGOp *op) @@ -1341,10 +1349,47 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) return fold_const2(ctx, op); } +static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) +{ + TCGOpcode neg_op; + bool have_neg; + + if (!arg_is_const(op->args[1]) || arg_info(op->args[1])->val != 0) { + return false; + } + + switch (ctx->type) { + case TCG_TYPE_I32: + neg_op = INDEX_op_neg_i32; + have_neg = TCG_TARGET_HAS_neg_i32; + break; + case TCG_TYPE_I64: + neg_op = INDEX_op_neg_i64; + have_neg = TCG_TARGET_HAS_neg_i64; + break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + neg_op = INDEX_op_neg_vec; + have_neg = (TCG_TARGET_HAS_neg_vec && + tcg_can_emit_vec_op(neg_op, ctx->type, TCGOP_VECE(op)) > 0); + break; + default: + g_assert_not_reached(); + } + if (have_neg) { + op->opc = neg_op; + op->args[1] = op->args[2]; + return fold_neg(ctx, op); + } + return false; +} + static bool fold_sub(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || - fold_xx_to_i(ctx, op, 0)) { + fold_xx_to_i(ctx, op, 0) || + fold_sub_to_neg(ctx, op)) { return true; } return false; @@ -1478,41 +1523,6 @@ void tcg_optimize(TCGContext *s) continue; } break; - CASE_OP_32_64_VEC(sub): - { - TCGOpcode neg_op; - bool have_neg; - - if (arg_is_const(op->args[2])) { - /* Proceed with possible constant folding. */ - break; - } - switch (ctx.type) { - case TCG_TYPE_I32: - neg_op = INDEX_op_neg_i32; - have_neg = TCG_TARGET_HAS_neg_i32; - break; - case TCG_TYPE_I64: - neg_op = INDEX_op_neg_i64; - have_neg = TCG_TARGET_HAS_neg_i64; - break; - default: - neg_op = INDEX_op_neg_vec; - have_neg = tcg_can_emit_vec_op(neg_op, ctx.type, TCGOP_VECE(op)) > 0; - break; - } - if (!have_neg) { - break; - } - if (arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == 0) { - op->opc = neg_op; - reset_temp(op->args[0]); - op->args[1] = op->args[2]; - continue; - } - } - break; default: break; } From patchwork Thu Oct 21 21:05:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516096 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp344324imj; Thu, 21 Oct 2021 14:30:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzfPLL1I1jiuB/ajx/Q0DhQWvQqyQJd7XO+1ny2tFb6hIApcskKD7Wc/S6zoC8FQC21dKWx X-Received: by 2002:a05:6808:110:: with SMTP id b16mr6284961oie.7.1634851834774; Thu, 21 Oct 2021 14:30:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634851834; cv=none; d=google.com; s=arc-20160816; b=dUxfQqe9oFjXuPA2xJob3Cq5Fa4aTsPgCrJliNQd1Q9uWP38oWbL1Mr9YInj/KNRNG qt9b+M8ifdrxNKCIwY9VoQe+H0V2k4dXIwFSnxwiy/AGZe0WNJRwZh75/WKbwQkcWPFk IGD9ODZMtgFDF9g/loLuDEYdZXCHTPS/H7U/6jimU1Xbg4t16IARC1zHswJh/tVKB94P RoOEIfsGZrIGUKkH1uTGiUUe0Gyl0e9EU17EJX000pMbsPpRANwB20zKB21bl8VzSbIV yQ9JaGAUJRi4E76123ZDO8KJlIs5gNPyC/ckAgDd0CAZpTXhsEP8UNrc46izTLqpuY0J mNJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mVQAUu9tUDiVXS3KTEo22nGHaNB56YhTgguLTU/cCL0=; b=O00RGHxGm0+ebN5f5+s0TQl61uHhaIKoDXRVEFuKylEwy6GgV0BOhO7wxYGocDdVi+ s8N9WL/n8R0SPTzB2kVqf5RRvugSZPzLYadkO3Ngu1ChCJqhet3rQO3uUZnQ7k2m00oZ Xr9TkXUs4N1AgvqG61nm8Yyg9RJcUtqRw0YV2neHLhpGrR1Kn3TCSJcYliKLyye+P1/X IdOT9rUsvCmnCQniFOnwYzaKTmkjQFj8czS9cC70Brlyn2Hz+cmN4Uca3fLPgjJpE5AR iwQCAIgQIRjn4qvEytgCztNIbhf1pZJaDql+f2qbcH291hpuVDXy2ArG92muMI+u1Bf5 xIXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="eo5tHXN/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/optimize.c | 60 +++++++++++++++++++++----------------------------- 1 file changed, 25 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index e4cf746321..af26429175 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -749,6 +749,15 @@ static bool fold_xi_to_i(OptContext *ctx, TCGOp *op, uint64_t i) return false; } +/* If the binary operation has second argument @i, fold to identity. */ +static bool fold_xi_to_x(OptContext *ctx, TCGOp *op, uint64_t i) +{ + if (arg_is_const(op->args[2]) && arg_info(op->args[2])->val == i) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); + } + return false; +} + /* If the binary operation has second argument @i, fold to NOT. */ static bool fold_xi_to_not(OptContext *ctx, TCGOp *op, uint64_t i) { @@ -787,7 +796,11 @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op) static bool fold_add(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_x(ctx, op, 0)) { + return true; + } + return false; } static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add) @@ -827,6 +840,7 @@ static bool fold_and(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || fold_xi_to_i(ctx, op, 0) || + fold_xi_to_x(ctx, op, -1) || fold_xx_to_x(ctx, op)) { return true; } @@ -837,6 +851,7 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || fold_xx_to_i(ctx, op, 0) || + fold_xi_to_x(ctx, op, 0) || fold_ix_to_not(ctx, op, -1)) { return true; } @@ -1039,6 +1054,7 @@ static bool fold_dup2(OptContext *ctx, TCGOp *op) static bool fold_eqv(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || + fold_xi_to_x(ctx, op, -1) || fold_xi_to_not(ctx, op, 0)) { return true; } @@ -1223,6 +1239,7 @@ static bool fold_not(OptContext *ctx, TCGOp *op) static bool fold_or(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || + fold_xi_to_x(ctx, op, 0) || fold_xx_to_x(ctx, op)) { return true; } @@ -1346,7 +1363,11 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) static bool fold_shift(OptContext *ctx, TCGOp *op) { - return fold_const2(ctx, op); + if (fold_const2(ctx, op) || + fold_xi_to_x(ctx, op, 0)) { + return true; + } + return false; } static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) @@ -1389,6 +1410,7 @@ static bool fold_sub(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || fold_xx_to_i(ctx, op, 0) || + fold_xi_to_x(ctx, op, 0) || fold_sub_to_neg(ctx, op)) { return true; } @@ -1404,6 +1426,7 @@ static bool fold_xor(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || fold_xx_to_i(ctx, op, 0) || + fold_xi_to_x(ctx, op, 0) || fold_xi_to_not(ctx, op, -1)) { return true; } @@ -1527,39 +1550,6 @@ void tcg_optimize(TCGContext *s) break; } - /* Simplify expression for "op r, a, const => mov r, a" cases */ - switch (opc) { - CASE_OP_32_64_VEC(add): - CASE_OP_32_64_VEC(sub): - CASE_OP_32_64_VEC(or): - CASE_OP_32_64_VEC(xor): - CASE_OP_32_64_VEC(andc): - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == 0) { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); - continue; - } - break; - CASE_OP_32_64_VEC(and): - CASE_OP_32_64_VEC(orc): - CASE_OP_32_64(eqv): - if (!arg_is_const(op->args[1]) - && arg_is_const(op->args[2]) - && arg_info(op->args[2])->val == -1) { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); - continue; - } - break; - default: - break; - } - /* Simplify using known-zero bits. Currently only ops with a single output argument is supported. */ z_mask = -1; From patchwork Thu Oct 21 21:05:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516103 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp349218imj; Thu, 21 Oct 2021 14:36:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzrRNmPz6rt81osMg4Tdj5wpG6UA+txIo41OOPH+tFPLt6eBxlba1cP5/btRWc+Ol6PXue8 X-Received: by 2002:a4a:bd12:: with SMTP id n18mr6241948oop.69.1634852198438; Thu, 21 Oct 2021 14:36:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852198; cv=none; d=google.com; s=arc-20160816; b=jEzzlBcYgo0M/RiQU6KvvINe6L5cVoiY5bJx7dV3axLoVuNv6+UIrNG0R5jIyToKN5 dvMpHrMpwZMIlKJlBHpbZyQZyxUyoOd2f76netbbO1AAnTLZBQFlJwMy+S2ZoLr0WaiZ g0yEX9wINN2ZYt+t8IjpJMmJ+J02CkEGuAb0trgwwZG3rBdGuK9sMNJ7Y7OrCFRNklXc OCGDrtyrPE29hG/lxjYDtGa2Z3Udm3BA+ocJma3NAnLtKCTuny8899vzVvIYh6bxoyLi wSoI0CFTUfQxSjVF/kA6oz8gCpXG3fEEX4x+9nlglX8Es13Cf3rBd6pBG5S76uEknVxH jcsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BUDQu/CJgwa4ODuJqZ+yd21Xfefoe1a81eW46BFAUmA=; b=XsDQJKkkILZu5PU+ttx83ve59le4SJ2WK5t26jsTyHxpVo254OUnXY9Jze1xWjY6FF w6wAwq6GaJNmkfkyV8kr8CxDTN8xXiiszwe/rahIze8QqZwWy/N+FrhNqO2X7EEzvrll EwdaEn1dfcz3aPH/14IksiKddk1Oa2r6KQ6MmczbollUNISa4qu46Vf5smw1qrj0AqZi 5JjzI9XG+NGeR86oHb+28gqBo39QAk11agY0tJvsJRkSznY4ypN1MLHC12657IaqXtHd TUB/MmABt7zLj8mmNpB1SQpydUGcs8VnYDpsmVBs+wzPmd74Qaek1j5zZIXCV+56DcLW QxAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=O1e94xnR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/optimize.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index af26429175..6c1cc3e635 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -731,6 +731,15 @@ static bool fold_to_not(OptContext *ctx, TCGOp *op, int idx) return false; } +/* If the binary operation has first argument @i, fold to @i. */ +static bool fold_ix_to_i(OptContext *ctx, TCGOp *op, uint64_t i) +{ + if (arg_is_const(op->args[1]) && arg_info(op->args[1])->val == i) { + return tcg_opt_gen_movi(ctx, op, op->args[0], i); + } + return false; +} + /* If the binary operation has first argument @i, fold to NOT. */ static bool fold_ix_to_not(OptContext *ctx, TCGOp *op, uint64_t i) { @@ -1364,6 +1373,7 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) static bool fold_shift(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || + fold_ix_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, 0)) { return true; } @@ -1532,24 +1542,6 @@ void tcg_optimize(TCGContext *s) break; } - /* Simplify expressions for "shift/rot r, 0, a => movi r, 0", - and "sub r, 0, a => neg r, a" case. */ - switch (opc) { - CASE_OP_32_64(shl): - CASE_OP_32_64(shr): - CASE_OP_32_64(sar): - CASE_OP_32_64(rotl): - CASE_OP_32_64(rotr): - if (arg_is_const(op->args[1]) - && arg_info(op->args[1])->val == 0) { - tcg_opt_gen_movi(&ctx, op, op->args[0], 0); - continue; - } - break; - default: - break; - } - /* Simplify using known-zero bits. Currently only ops with a single output argument is supported. */ z_mask = -1; From patchwork Thu Oct 21 21:05:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516101 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp346900imj; Thu, 21 Oct 2021 14:33:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyNmXmbMpeETmF648MK1Tisq9PAIjwZyS6EKiSZab9rG+cBtF7QyJoFX6LpKHDBb56Q2aaV X-Received: by 2002:a9d:490e:: with SMTP id e14mr6782708otf.194.1634852034676; Thu, 21 Oct 2021 14:33:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852034; cv=none; d=google.com; s=arc-20160816; b=u4mWm5OTuOfTmQgnpuNLIPvfrPzhtgQ28PgywqrAIg75Waea5Z2aFYIYXPLERnAmoq id1VZifUz/i1ljioZv6JmPTngmAgJNpyESRUApDDZdRRwzpLtPZ9mW6XC+7JxonSzn99 RCi43fU+YdX/+9/e81lCw2t1hNzZrQ9kPY1QrtPWFs9XMDYrGFqZCFUexLKI2ZlLHKx+ 5PWdt358FIm/uQEtZQChsHoL4sM/qE6sbB6wAZ19ROjIGnISOIfQnepa1Tcm/5dYSbaK NVNKisAjbXA8VWcydu1CUQXq813UA0gyI9M6UrBBvVD8ZP6In+IPqUzzUVL5iyxrp5tT g05A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JtUtuGyvKpjj/YC3TPlz3zim2H7HBslrDOZitZTWjgo=; b=wcQxmk5xccKUK/w4CrV5gGYpdBpy5LfHDTc7ULbAmqLqtczdLQWAny1zeMVz+py9zn e35r9nJtqokps5kEDlyb3eB72JlRAGOttfT6MLQHJAPR+4ZIJKf1EheRaCAzlhafoAS2 3zYdFz6pMwSSfDy6tP5cy7BGEBQGNj9syTI5qmw6ma6p5ZCfrRrq+wIijJzpptXgWMz7 CYlULSYAXAaVSq0jCxtR9f54jtIkuHj4DLFRB5NmvlM8FPQzHAM6QLnoZlDqXWNaJTpP gi+VbBaVTPHkBBKJs5Z0uyp/bKWnzco1bgerNDgKAtdEfiLr6TQi5z54M07Hf9eLtWE7 chnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SpLQghbp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use fold_masks when there is a possibility of the result being determined, and simply set ctx->z_mask otherwise. Signed-off-by: Richard Henderson --- tcg/optimize.c | 545 ++++++++++++++++++++++++++----------------------- 1 file changed, 294 insertions(+), 251 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 6c1cc3e635..f0086ee789 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -50,7 +50,8 @@ typedef struct OptContext { TCGTempSet temps_used; /* In flight values from optimization. */ - uint64_t z_mask; + uint64_t a_mask; /* mask bit is 0 iff value identical to first input */ + uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ TCGType type; } OptContext; @@ -694,6 +695,31 @@ static bool fold_const2(OptContext *ctx, TCGOp *op) return false; } +static bool fold_masks(OptContext *ctx, TCGOp *op) +{ + uint64_t a_mask = ctx->a_mask; + uint64_t z_mask = ctx->z_mask; + + /* + * 32-bit ops generate 32-bit results. For the result is zero test + * below, we can ignore high bits, but for further optimizations we + * need to record that the high bits contain garbage. + */ + if (ctx->type == TCG_TYPE_I32) { + ctx->z_mask |= MAKE_64BIT_MASK(32, 32); + a_mask &= MAKE_64BIT_MASK(0, 32); + z_mask &= MAKE_64BIT_MASK(0, 32); + } + + if (z_mask == 0) { + return tcg_opt_gen_movi(ctx, op, op->args[0], 0); + } + if (a_mask == 0) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); + } + return false; +} + /* * Convert @op to NOT, if NOT is supported by the host. * Return true f the conversion is successful, which will still @@ -847,24 +873,55 @@ static bool fold_add2_i32(OptContext *ctx, TCGOp *op) static bool fold_and(OptContext *ctx, TCGOp *op) { + uint64_t z1, z2; + if (fold_const2(ctx, op) || fold_xi_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, -1) || fold_xx_to_x(ctx, op)) { return true; } - return false; + + z1 = arg_info(op->args[1])->z_mask; + z2 = arg_info(op->args[2])->z_mask; + ctx->z_mask = z1 & z2; + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer affected bits from it. + */ + if (arg_is_const(op->args[2])) { + ctx->a_mask = z1 & ~z2; + } + + return fold_masks(ctx, op); } static bool fold_andc(OptContext *ctx, TCGOp *op) { + uint64_t z1; + if (fold_const2(ctx, op) || fold_xx_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, 0) || fold_ix_to_not(ctx, op, -1)) { return true; } - return false; + + z1 = arg_info(op->args[1])->z_mask; + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer anything from it. + */ + if (arg_is_const(op->args[2])) { + uint64_t z2 = ~arg_info(op->args[2])->z_mask; + ctx->a_mask = z1 & ~z2; + z1 &= z2; + } + ctx->z_mask = z1; + + return fold_masks(ctx, op); } static bool fold_brcond(OptContext *ctx, TCGOp *op) @@ -963,13 +1020,52 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) static bool fold_bswap(OptContext *ctx, TCGOp *op) { + uint64_t z_mask, sign; + if (arg_is_const(op->args[1])) { uint64_t t = arg_info(op->args[1])->val; t = do_constant_folding(op->opc, ctx->type, t, op->args[2]); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } - return false; + + z_mask = arg_info(op->args[1])->z_mask; + switch (op->opc) { + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + z_mask = bswap16(z_mask); + sign = INT16_MIN; + break; + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + z_mask = bswap32(z_mask); + sign = INT32_MIN; + break; + case INDEX_op_bswap64_i64: + z_mask = bswap64(z_mask); + sign = INT64_MIN; + break; + default: + g_assert_not_reached(); + } + + switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { + case TCG_BSWAP_OZ: + break; + case TCG_BSWAP_OS: + /* If the sign bit may be 1, force all the bits above to 1. */ + if (z_mask & sign) { + z_mask |= sign; + } + break; + default: + /* The high bits are undefined: force all bits above the sign to 1. */ + z_mask |= sign << 1; + break; + } + ctx->z_mask = z_mask; + + return fold_masks(ctx, op); } static bool fold_call(OptContext *ctx, TCGOp *op) @@ -1006,6 +1102,8 @@ static bool fold_call(OptContext *ctx, TCGOp *op) static bool fold_count_zeros(OptContext *ctx, TCGOp *op) { + uint64_t z_mask; + if (arg_is_const(op->args[1])) { uint64_t t = arg_info(op->args[1])->val; @@ -1015,12 +1113,39 @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op) } return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[2]); } + + switch (ctx->type) { + case TCG_TYPE_I32: + z_mask = 31; + break; + case TCG_TYPE_I64: + z_mask = 63; + break; + default: + g_assert_not_reached(); + } + ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask; + return false; } static bool fold_ctpop(OptContext *ctx, TCGOp *op) { - return fold_const1(ctx, op); + if (fold_const1(ctx, op)) { + return true; + } + + switch (ctx->type) { + case TCG_TYPE_I32: + ctx->z_mask = 32 | 31; + break; + case TCG_TYPE_I64: + ctx->z_mask = 64 | 63; + break; + default: + g_assert_not_reached(); + } + return false; } static bool fold_deposit(OptContext *ctx, TCGOp *op) @@ -1032,6 +1157,10 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) t1 = deposit64(t1, op->args[3], op->args[4], t2); return tcg_opt_gen_movi(ctx, op, op->args[0], t1); } + + ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask, + op->args[3], op->args[4], + arg_info(op->args[2])->z_mask); return false; } @@ -1072,6 +1201,8 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) static bool fold_extract(OptContext *ctx, TCGOp *op) { + uint64_t z_mask_old, z_mask; + if (arg_is_const(op->args[1])) { uint64_t t; @@ -1079,7 +1210,15 @@ static bool fold_extract(OptContext *ctx, TCGOp *op) t = extract64(t, op->args[2], op->args[3]); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } - return false; + + z_mask_old = arg_info(op->args[1])->z_mask; + z_mask = sextract64(z_mask_old, op->args[2], op->args[3]); + if (op->args[2] == 0) { + ctx->a_mask = z_mask_old ^ z_mask; + } + ctx->z_mask = z_mask; + + return fold_masks(ctx, op); } static bool fold_extract2(OptContext *ctx, TCGOp *op) @@ -1103,12 +1242,83 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op) static bool fold_exts(OptContext *ctx, TCGOp *op) { - return fold_const1(ctx, op); + uint64_t z_mask_old, z_mask, sign; + bool type_change = false; + + if (fold_const1(ctx, op)) { + return true; + } + + z_mask_old = z_mask = arg_info(op->args[1])->z_mask; + + switch (op->opc) { + CASE_OP_32_64(ext8s): + sign = INT8_MIN; + z_mask = (uint8_t)z_mask; + break; + CASE_OP_32_64(ext16s): + sign = INT16_MIN; + z_mask = (uint16_t)z_mask; + break; + case INDEX_op_ext_i32_i64: + type_change = true; + QEMU_FALLTHROUGH; + case INDEX_op_ext32s_i64: + sign = INT32_MIN; + z_mask = (uint32_t)z_mask; + break; + default: + g_assert_not_reached(); + } + + if (z_mask & sign) { + z_mask |= sign; + } else if (!type_change) { + ctx->a_mask = z_mask_old ^ z_mask; + } + ctx->z_mask = z_mask; + + return fold_masks(ctx, op); } static bool fold_extu(OptContext *ctx, TCGOp *op) { - return fold_const1(ctx, op); + uint64_t z_mask_old, z_mask; + bool type_change = false; + + if (fold_const1(ctx, op)) { + return true; + } + + z_mask_old = z_mask = arg_info(op->args[1])->z_mask; + + switch (op->opc) { + CASE_OP_32_64(ext8u): + z_mask = (uint8_t)z_mask; + break; + CASE_OP_32_64(ext16u): + z_mask = (uint16_t)z_mask; + break; + case INDEX_op_extrl_i64_i32: + case INDEX_op_extu_i32_i64: + type_change = true; + QEMU_FALLTHROUGH; + case INDEX_op_ext32u_i64: + z_mask = (uint32_t)z_mask; + break; + case INDEX_op_extrh_i64_i32: + type_change = true; + z_mask >>= 32; + break; + default: + g_assert_not_reached(); + } + + ctx->z_mask = z_mask; + if (!type_change) { + ctx->a_mask = z_mask_old ^ z_mask; + } + return fold_masks(ctx, op); } static bool fold_mb(OptContext *ctx, TCGOp *op) @@ -1149,6 +1359,9 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]); } + ctx->z_mask = arg_info(op->args[3])->z_mask + | arg_info(op->args[4])->z_mask; + if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { uint64_t tv = arg_info(op->args[3])->val; uint64_t fv = arg_info(op->args[4])->val; @@ -1214,9 +1427,16 @@ static bool fold_nand(OptContext *ctx, TCGOp *op) static bool fold_neg(OptContext *ctx, TCGOp *op) { + uint64_t z_mask; + if (fold_const1(ctx, op)) { return true; } + + /* Set to 1 all bits to the left of the rightmost. */ + z_mask = arg_info(op->args[1])->z_mask; + ctx->z_mask = -(z_mask & -z_mask); + /* * Because of fold_sub_to_neg, we want to always return true, * via finish_folding. @@ -1252,7 +1472,10 @@ static bool fold_or(OptContext *ctx, TCGOp *op) fold_xx_to_x(ctx, op)) { return true; } - return false; + + ctx->z_mask = arg_info(op->args[1])->z_mask + | arg_info(op->args[2])->z_mask; + return fold_masks(ctx, op); } static bool fold_orc(OptContext *ctx, TCGOp *op) @@ -1266,6 +1489,15 @@ static bool fold_orc(OptContext *ctx, TCGOp *op) static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) { + const TCGOpDef *def = &tcg_op_defs[op->opc]; + MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs]; + MemOp mop = get_memop(oi); + int width = 8 << (mop & MO_SIZE); + + if (!(mop & MO_SIGN) && width < 64) { + ctx->z_mask = MAKE_64BIT_MASK(0, width); + } + /* Opcodes that touch guest memory stop the mb optimization. */ ctx->prev_mb = NULL; return false; @@ -1286,6 +1518,8 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) if (i >= 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } + + ctx->z_mask = 1; return false; } @@ -1352,6 +1586,8 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) op->opc = INDEX_op_setcond_i32; break; } + + ctx->z_mask = 1; return false; do_setcond_const: @@ -1360,6 +1596,8 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) static bool fold_sextract(OptContext *ctx, TCGOp *op) { + int64_t z_mask_old, z_mask; + if (arg_is_const(op->args[1])) { uint64_t t; @@ -1367,7 +1605,15 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) t = sextract64(t, op->args[2], op->args[3]); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } - return false; + + z_mask_old = arg_info(op->args[1])->z_mask; + z_mask = sextract64(z_mask_old, op->args[2], op->args[3]); + if (op->args[2] == 0 && z_mask >= 0) { + ctx->a_mask = z_mask_old ^ z_mask; + } + ctx->z_mask = z_mask; + + return fold_masks(ctx, op); } static bool fold_shift(OptContext *ctx, TCGOp *op) @@ -1377,6 +1623,13 @@ static bool fold_shift(OptContext *ctx, TCGOp *op) fold_xi_to_x(ctx, op, 0)) { return true; } + + if (arg_is_const(op->args[2])) { + ctx->z_mask = do_constant_folding(op->opc, ctx->type, + arg_info(op->args[1])->z_mask, + arg_info(op->args[2])->val); + return fold_masks(ctx, op); + } return false; } @@ -1432,6 +1685,25 @@ static bool fold_sub2_i32(OptContext *ctx, TCGOp *op) return fold_addsub2_i32(ctx, op, false); } +static bool fold_tcg_ld(OptContext *ctx, TCGOp *op) +{ + /* We can't do any folding with a load, but we can record bits. */ + switch (op->opc) { + CASE_OP_32_64(ld8u): + ctx->z_mask = 0xff; + break; + CASE_OP_32_64(ld16u): + ctx->z_mask = 0xffff; + break; + case INDEX_op_ld32u_i64: + ctx->z_mask = 0xffffffffu; + break; + default: + g_assert_not_reached(); + } + return false; +} + static bool fold_xor(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || @@ -1440,7 +1712,10 @@ static bool fold_xor(OptContext *ctx, TCGOp *op) fold_xi_to_not(ctx, op, -1)) { return true; } - return false; + + ctx->z_mask = arg_info(op->args[1])->z_mask + | arg_info(op->args[2])->z_mask; + return fold_masks(ctx, op); } /* Propagate constants and copies, fold constant expressions. */ @@ -1461,7 +1736,6 @@ void tcg_optimize(TCGContext *s) } QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { - uint64_t z_mask, partmask, affected, tmp; TCGOpcode opc = op->opc; const TCGOpDef *def; bool done = false; @@ -1542,245 +1816,9 @@ void tcg_optimize(TCGContext *s) break; } - /* Simplify using known-zero bits. Currently only ops with a single - output argument is supported. */ - z_mask = -1; - affected = -1; - switch (opc) { - CASE_OP_32_64(ext8s): - if ((arg_info(op->args[1])->z_mask & 0x80) != 0) { - break; - } - QEMU_FALLTHROUGH; - CASE_OP_32_64(ext8u): - z_mask = 0xff; - goto and_const; - CASE_OP_32_64(ext16s): - if ((arg_info(op->args[1])->z_mask & 0x8000) != 0) { - break; - } - QEMU_FALLTHROUGH; - CASE_OP_32_64(ext16u): - z_mask = 0xffff; - goto and_const; - case INDEX_op_ext32s_i64: - if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { - break; - } - QEMU_FALLTHROUGH; - case INDEX_op_ext32u_i64: - z_mask = 0xffffffffU; - goto and_const; - - CASE_OP_32_64(and): - z_mask = arg_info(op->args[2])->z_mask; - if (arg_is_const(op->args[2])) { - and_const: - affected = arg_info(op->args[1])->z_mask & ~z_mask; - } - z_mask = arg_info(op->args[1])->z_mask & z_mask; - break; - - case INDEX_op_ext_i32_i64: - if ((arg_info(op->args[1])->z_mask & 0x80000000) != 0) { - break; - } - QEMU_FALLTHROUGH; - case INDEX_op_extu_i32_i64: - /* We do not compute affected as it is a size changing op. */ - z_mask = (uint32_t)arg_info(op->args[1])->z_mask; - break; - - CASE_OP_32_64(andc): - /* Known-zeros does not imply known-ones. Therefore unless - op->args[2] is constant, we can't infer anything from it. */ - if (arg_is_const(op->args[2])) { - z_mask = ~arg_info(op->args[2])->z_mask; - goto and_const; - } - /* But we certainly know nothing outside args[1] may be set. */ - z_mask = arg_info(op->args[1])->z_mask; - break; - - case INDEX_op_sar_i32: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 31; - z_mask = (int32_t)arg_info(op->args[1])->z_mask >> tmp; - } - break; - case INDEX_op_sar_i64: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 63; - z_mask = (int64_t)arg_info(op->args[1])->z_mask >> tmp; - } - break; - - case INDEX_op_shr_i32: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 31; - z_mask = (uint32_t)arg_info(op->args[1])->z_mask >> tmp; - } - break; - case INDEX_op_shr_i64: - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & 63; - z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> tmp; - } - break; - - case INDEX_op_extrl_i64_i32: - z_mask = (uint32_t)arg_info(op->args[1])->z_mask; - break; - case INDEX_op_extrh_i64_i32: - z_mask = (uint64_t)arg_info(op->args[1])->z_mask >> 32; - break; - - CASE_OP_32_64(shl): - if (arg_is_const(op->args[2])) { - tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1); - z_mask = arg_info(op->args[1])->z_mask << tmp; - } - break; - - CASE_OP_32_64(neg): - /* Set to 1 all bits to the left of the rightmost. */ - z_mask = -(arg_info(op->args[1])->z_mask - & -arg_info(op->args[1])->z_mask); - break; - - CASE_OP_32_64(deposit): - z_mask = deposit64(arg_info(op->args[1])->z_mask, - op->args[3], op->args[4], - arg_info(op->args[2])->z_mask); - break; - - CASE_OP_32_64(extract): - z_mask = extract64(arg_info(op->args[1])->z_mask, - op->args[2], op->args[3]); - if (op->args[2] == 0) { - affected = arg_info(op->args[1])->z_mask & ~z_mask; - } - break; - CASE_OP_32_64(sextract): - z_mask = sextract64(arg_info(op->args[1])->z_mask, - op->args[2], op->args[3]); - if (op->args[2] == 0 && (tcg_target_long)z_mask >= 0) { - affected = arg_info(op->args[1])->z_mask & ~z_mask; - } - break; - - CASE_OP_32_64(or): - CASE_OP_32_64(xor): - z_mask = arg_info(op->args[1])->z_mask - | arg_info(op->args[2])->z_mask; - break; - - case INDEX_op_clz_i32: - case INDEX_op_ctz_i32: - z_mask = arg_info(op->args[2])->z_mask | 31; - break; - - case INDEX_op_clz_i64: - case INDEX_op_ctz_i64: - z_mask = arg_info(op->args[2])->z_mask | 63; - break; - - case INDEX_op_ctpop_i32: - z_mask = 32 | 31; - break; - case INDEX_op_ctpop_i64: - z_mask = 64 | 63; - break; - - CASE_OP_32_64(setcond): - case INDEX_op_setcond2_i32: - z_mask = 1; - break; - - CASE_OP_32_64(movcond): - z_mask = arg_info(op->args[3])->z_mask - | arg_info(op->args[4])->z_mask; - break; - - CASE_OP_32_64(ld8u): - z_mask = 0xff; - break; - CASE_OP_32_64(ld16u): - z_mask = 0xffff; - break; - case INDEX_op_ld32u_i64: - z_mask = 0xffffffffu; - break; - - CASE_OP_32_64(qemu_ld): - { - MemOpIdx oi = op->args[def->nb_oargs + def->nb_iargs]; - MemOp mop = get_memop(oi); - if (!(mop & MO_SIGN)) { - z_mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; - } - } - break; - - CASE_OP_32_64(bswap16): - z_mask = arg_info(op->args[1])->z_mask; - if (z_mask <= 0xffff) { - op->args[2] |= TCG_BSWAP_IZ; - } - z_mask = bswap16(z_mask); - switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { - case TCG_BSWAP_OZ: - break; - case TCG_BSWAP_OS: - z_mask = (int16_t)z_mask; - break; - default: /* undefined high bits */ - z_mask |= MAKE_64BIT_MASK(16, 48); - break; - } - break; - - case INDEX_op_bswap32_i64: - z_mask = arg_info(op->args[1])->z_mask; - if (z_mask <= 0xffffffffu) { - op->args[2] |= TCG_BSWAP_IZ; - } - z_mask = bswap32(z_mask); - switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { - case TCG_BSWAP_OZ: - break; - case TCG_BSWAP_OS: - z_mask = (int32_t)z_mask; - break; - default: /* undefined high bits */ - z_mask |= MAKE_64BIT_MASK(32, 32); - break; - } - break; - - default: - break; - } - - /* 32-bit ops generate 32-bit results. For the result is zero test - below, we can ignore high bits, but for further optimizations we - need to record that the high bits contain garbage. */ - partmask = z_mask; - if (ctx.type == TCG_TYPE_I32) { - z_mask |= ~(tcg_target_ulong)0xffffffffu; - partmask &= 0xffffffffu; - affected &= 0xffffffffu; - } - ctx.z_mask = z_mask; - - if (partmask == 0) { - tcg_opt_gen_movi(&ctx, op, op->args[0], 0); - continue; - } - if (affected == 0) { - tcg_opt_gen_mov(&ctx, op, op->args[0], op->args[1]); - continue; - } + /* Assume all bits affected, and no bits known zero. */ + ctx.a_mask = -1; + ctx.z_mask = -1; /* * Process each opcode. @@ -1853,6 +1891,11 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extrh_i64_i32: done = fold_extu(&ctx, op); break; + CASE_OP_32_64(ld8u): + CASE_OP_32_64(ld16u): + case INDEX_op_ld32u_i64: + done = fold_tcg_ld(&ctx, op); + break; case INDEX_op_mb: done = fold_mb(&ctx, op); break; From patchwork Thu Oct 21 21:05:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516104 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp349424imj; Thu, 21 Oct 2021 14:36:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytGBrF0/cmaUXkdillUXpiLxe29fPD3DDFwE8tPq/7AzXfk5fBDGutWxU4Cuk6koVinl30 X-Received: by 2002:a05:6830:356:: with SMTP id h22mr6500950ote.110.1634852214646; Thu, 21 Oct 2021 14:36:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852214; cv=none; d=google.com; s=arc-20160816; b=ghWw475PG49fggawSiWzr1yHH1O7uevgBHlIP7m1VPtW0zb2+k/SUKcljWH4jLwQ5A CNYcLLFK07cXsxC2JtMjJ43tvCcBlCPuIEpaTdNkxwCUEmFOfmtMyNw7dKsdcG35mEBe JPZubIvGZaXl6ixVG0jZZZjwbswxBpOmB5u/Oj3N7zF5CE6vrx/vybHAKUpVqHja0hjQ jlBFojUdKuHRMsFONOTdW1/vo6AYE20+N37unTPn8wByFO91/B6re/fiohNKP4z763Eq fLT8vSW0VCD2DAWBmWr0vYe39gTjgZfpU4CHeMr2xhInNHSznKJs3yUaeQ5+hghGkxTF ahWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bbujJ/Gml0vlPkv2W75zfuI+JolLNfHI4JOjGTTLUJ4=; b=pLHSgMIK4gvC/puMffciuB0jHdQyDgG8yAiEWTVYDSc0QFfpMwcsHbd3P+O84HXqaj /ySM/0INxzi8eeBHy88W5pPSo7Tful239wiu9J2Bl2zat8rPjVmTiqEMPFgvNIkvd7sd GJ6l0QHldGJmRDRopxJIocGcCpfzaG5Wt/2VYCymUoPUD6NJmHwzsjImRnk6oL82Lj7l IiVjyLE29dqE8Gn6AG/mIswSI9DWCiiwHMVenttQwkEsxkpg/TFz/jKgxH7Cv8iMJ1eG /P0SJcjyyQQGCyk9EMjaLHiYwabotn/xagFYTpEoSrPQQXD8TFdC/r5JQMmmsZOwOfg1 /xhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NyC7rn3F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/optimize.c | 44 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/optimize.c b/tcg/optimize.c index f0086ee789..efd5f58137 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1398,19 +1398,44 @@ static bool fold_multiply(OptContext *ctx, TCGOp *op) return false; } -static bool fold_mulu2_i32(OptContext *ctx, TCGOp *op) +static bool fold_multiply2(OptContext *ctx, TCGOp *op) { if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { - uint32_t a = arg_info(op->args[2])->val; - uint32_t b = arg_info(op->args[3])->val; - uint64_t r = (uint64_t)a * b; + uint64_t a = arg_info(op->args[2])->val; + uint64_t b = arg_info(op->args[3])->val; + uint64_t h, l; TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32); + TCGOp *op2; + + switch (op->opc) { + case INDEX_op_mulu2_i32: + l = (uint64_t)(uint32_t)a * (uint32_t)b; + h = (int32_t)(l >> 32); + l = (int32_t)l; + break; + case INDEX_op_muls2_i32: + l = (int64_t)(int32_t)a * (int32_t)b; + h = l >> 32; + l = (int32_t)l; + break; + case INDEX_op_mulu2_i64: + mulu64(&l, &h, a, b); + break; + case INDEX_op_muls2_i64: + muls64(&l, &h, a, b); + break; + default: + g_assert_not_reached(); + } rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(ctx, op, rl, (int32_t)r); - tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(r >> 32)); + + /* The proper opcode is supplied by tcg_opt_gen_mov. */ + op2 = tcg_op_insert_before(ctx->tcg, op, 0); + + tcg_opt_gen_movi(ctx, op, rl, l); + tcg_opt_gen_movi(ctx, op2, rh, h); return true; } return false; @@ -1910,8 +1935,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(muluh): done = fold_multiply(&ctx, op); break; - case INDEX_op_mulu2_i32: - done = fold_mulu2_i32(&ctx, op); + CASE_OP_32_64(muls2): + CASE_OP_32_64(mulu2): + done = fold_multiply2(&ctx, op); break; CASE_OP_32_64(nand): done = fold_nand(&ctx, op); From patchwork Thu Oct 21 21:05:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516108 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp352454imj; Thu, 21 Oct 2021 14:40:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2N7d0ym25DKv7x3BK3LRsbF5R61/whyZf9oh23RSTPXswQHTDOYpa6XoNoOGX843aan++ X-Received: by 2002:a9d:4c98:: with SMTP id m24mr6707290otf.48.1634852457722; Thu, 21 Oct 2021 14:40:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852457; cv=none; d=google.com; s=arc-20160816; b=enJtSbMEpFYlvGZWZ/xBxBOPo6BfDScVObfsWcR1/Da0Dz9clEDGELDx19LXITZKcb Arn4Y7A9SRzjIf4ITWE1Kh2lBjfq+PUT0yGEZR43bExfzBwPUCehsOyfRvdfijCSHBjb gNnmIvd2kB6hzkryzInMMXBtLI8gmmcJoU6DxQE56iIv0Cf/uDTGl8TkvixJEc1ODN66 tua9x8KoiDAuehPCREuR6kmHchfSXmM7KTNyalaE7re94ieiunwmNzT1BSKk7pf1eali F9/HtkQuvjaCFDceDrX77UdiYKMvOJgedCG+rzTdQW9hCroDbLCv+hx4vRqcgsoQCNyr +lzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4peLAaBX1JXxddh7SAc9adEMPD07opOaRpK6mFtuTqo=; b=d1ZuL4TMHHHAIxtCjaIiGMExmwCUfMyK/YTiXunwPzEEzlr7LUQnNPywNeDd70Vyfy T7Wr0QkXfNVGvrdNm0baTG6MajE22sk4K+quVLwWoDmupf6AYV+W5LoJ4AwYdHG5PbtG QTJc8UOy8zbtlRWg5dSVjjoLUqV/ppNTLUwstijhYWd7r6EcaG4aHCCrnvIDWSWx6heF q7xO4bOrbeJKmEmUNaTBhCwsg+F5A2a539BVOwKUTQg0Ll1qT9gFJhE94Z9qSQulU78Q 4Y5AYj7st0O3zkwKwEm3KNUEiHv3MSQP284kDocCfy5NGOtmG26jV69H1C3+qSCSwjbC fX0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rrI0kpXT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e25si9027104oti.277.2021.10.21.14.40.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:40:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rrI0kpXT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfo1-0007Mv-0T for patch@linaro.org; Thu, 21 Oct 2021 17:40:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfJK-0003nI-TZ for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:14 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:45867) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfJI-0008VT-Mz for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:14 -0400 Received: by mail-pj1-x102c.google.com with SMTP id ls14-20020a17090b350e00b001a00e2251c8so1493130pjb.4 for ; Thu, 21 Oct 2021 14:09:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4peLAaBX1JXxddh7SAc9adEMPD07opOaRpK6mFtuTqo=; b=rrI0kpXTC/serDI1fdq17NKpYJODjInJ3HW5/Aqpb7ileSsNTT9E0/vQFF7BhjfwQY TzlldF4aYVCNCEQggVoIDKcbSTLemNp0lh5ip0+x3r9ttf7TcbXeENHUSaaitmZBKKgM oSBjZkqVfg8W62seX1K3zqM8Cr3VKJB/JsYly/NrneyQJcJjGlT0cvwDrHkACOujGJ// 3hfpqCgxkB4iTNuUZa6BEgXgzOHUFzKu83DxeyGneMYNOYVjBc4OMX0AqpEAwnnmAIc/ 5smOUughKIeSnYQDtBDUeWroNhL/IujhmWjs62yRGaujGM/NncAbXa0PSTF+04wjjomg DG4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4peLAaBX1JXxddh7SAc9adEMPD07opOaRpK6mFtuTqo=; b=r4DhQo+u79Pg2ucroX6TmB+oxisN/iUhD2pblDuLgI8zYW8lvwU4XgUKM8mFH/i+R8 pJw25GD2K+sQ/+H+v/J8SxSR579u78hTzG1JP3mFAnaTUaUGQks8ga7kABFpj281TeWp STp7RQ0Sx/ygthgpW2d77+Bt4h8LVbiY9A82mgHjVgdZYlTzbaMXUg2FUie1ECTrHMha GI+aOYcYu6ZosZgcmdMdb7rH9bOd45emRWpNiCCtUcbsb0Ov5UWu8Nc+sMm7Ni1VQkgI 6APDkFN49L63zPpC90T1uWQF/kGjfknSrp2tUE69xNXZM+yshltZO8y6g6kC3n5b2d0V vzxA== X-Gm-Message-State: AOAM531oTdjrRvoP1I3mNqADO0wkDnOql1oDJqQmXkcn6hIWgM/R6Hul Gw4cHrYY/G7eXoYkYeNFMS84/Vw5pKHJhQ== X-Received: by 2002:a17:90b:1e01:: with SMTP id pg1mr9572088pjb.73.1634850551306; Thu, 21 Oct 2021 14:09:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i5sm6258856pgo.36.2021.10.21.14.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:09:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops Date: Thu, 21 Oct 2021 14:05:31 -0700 Message-Id: <20211021210539.825582-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org, =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to fold_addsub2. Use Int128 to implement the wider operation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 65 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index efd5f58137..ba068e7d3e 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -24,6 +24,7 @@ */ #include "qemu/osdep.h" +#include "qemu/int128.h" #include "tcg/tcg-op.h" #include "tcg-internal.h" @@ -838,37 +839,59 @@ static bool fold_add(OptContext *ctx, TCGOp *op) return false; } -static bool fold_addsub2_i32(OptContext *ctx, TCGOp *op, bool add) +static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add) { if (arg_is_const(op->args[2]) && arg_is_const(op->args[3]) && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) { - uint32_t al = arg_info(op->args[2])->val; - uint32_t ah = arg_info(op->args[3])->val; - uint32_t bl = arg_info(op->args[4])->val; - uint32_t bh = arg_info(op->args[5])->val; - uint64_t a = ((uint64_t)ah << 32) | al; - uint64_t b = ((uint64_t)bh << 32) | bl; + uint64_t al = arg_info(op->args[2])->val; + uint64_t ah = arg_info(op->args[3])->val; + uint64_t bl = arg_info(op->args[4])->val; + uint64_t bh = arg_info(op->args[5])->val; TCGArg rl, rh; - TCGOp *op2 = tcg_op_insert_before(ctx->tcg, op, INDEX_op_mov_i32); + TCGOp *op2; - if (add) { - a += b; + if (ctx->type == TCG_TYPE_I32) { + uint64_t a = deposit64(al, 32, 32, ah); + uint64_t b = deposit64(bl, 32, 32, bh); + + if (add) { + a += b; + } else { + a -= b; + } + + al = sextract64(a, 0, 32); + ah = sextract64(a, 32, 32); } else { - a -= b; + Int128 a = int128_make128(al, ah); + Int128 b = int128_make128(bl, bh); + + if (add) { + a = int128_add(a, b); + } else { + a = int128_sub(a, b); + } + + al = int128_getlo(a); + ah = int128_gethi(a); } rl = op->args[0]; rh = op->args[1]; - tcg_opt_gen_movi(ctx, op, rl, (int32_t)a); - tcg_opt_gen_movi(ctx, op2, rh, (int32_t)(a >> 32)); + + /* The proper opcode is supplied by tcg_opt_gen_mov. */ + op2 = tcg_op_insert_before(ctx->tcg, op, 0); + + tcg_opt_gen_movi(ctx, op, rl, al); + tcg_opt_gen_movi(ctx, op2, rh, ah); return true; } return false; } -static bool fold_add2_i32(OptContext *ctx, TCGOp *op) +static bool fold_add2(OptContext *ctx, TCGOp *op) { - return fold_addsub2_i32(ctx, op, true); + return fold_addsub2(ctx, op, true); } static bool fold_and(OptContext *ctx, TCGOp *op) @@ -1705,9 +1728,9 @@ static bool fold_sub(OptContext *ctx, TCGOp *op) return false; } -static bool fold_sub2_i32(OptContext *ctx, TCGOp *op) +static bool fold_sub2(OptContext *ctx, TCGOp *op) { - return fold_addsub2_i32(ctx, op, false); + return fold_addsub2(ctx, op, false); } static bool fold_tcg_ld(OptContext *ctx, TCGOp *op) @@ -1853,8 +1876,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(add): done = fold_add(&ctx, op); break; - case INDEX_op_add2_i32: - done = fold_add2_i32(&ctx, op); + CASE_OP_32_64(add2): + done = fold_add2(&ctx, op); break; CASE_OP_32_64_VEC(and): done = fold_and(&ctx, op); @@ -1989,8 +2012,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(sub): done = fold_sub(&ctx, op); break; - case INDEX_op_sub2_i32: - done = fold_sub2_i32(&ctx, op); + CASE_OP_32_64(sub2): + done = fold_sub2(&ctx, op); break; CASE_OP_32_64_VEC(xor): done = fold_xor(&ctx, op); From patchwork Thu Oct 21 21:05:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516113 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp356925imj; Thu, 21 Oct 2021 14:47:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJiWifrTU0QfR48wImc+q+q5+Rxscggb0VlNd1WIWx0ebskq0y8OOK/MtLRg2FVQAAfqNz X-Received: by 2002:a05:6808:7c8:: with SMTP id f8mr6658062oij.146.1634852853259; Thu, 21 Oct 2021 14:47:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852853; cv=none; d=google.com; s=arc-20160816; b=YvgLUxy/ec04y3yYNtSkaLWqpNNIOsNiMEmj4WDxLObqLwXBWldhmaBkbJQcveQv9J Dz5xLyhmVTjfefSW4HHdSNKcGpGiSWUiq9XsrjdoubX9ZZ1CZFK70KExogiqnELDtTxr JFWkDXbxirGhwqdoLxEx+Kz5g3mZeXCSwiC/KrO55ZX5tQMbYVlBBAr73G6nUjj9z53+ WIcux6OTzsKUp65QGWN92yjNG/1nEIcngz+2VEdc3cy5lIpt6Ji9MogbwgCvjJpy8/a4 I82BYIYVqcBG9U0nzVX08BOBO/fv+6BZoCsfOhnGdwIIJD1hPf9+/IL5GtVe5rc/0UGA KUfA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id w83si6270723oig.218.2021.10.21.14.47.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:47:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ky+kErUK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfuO-0001qo-Ff for patch@linaro.org; Thu, 21 Oct 2021 17:47:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfJN-0003vv-An for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:17 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:36699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfJJ-0008Vs-Ao for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:16 -0400 Received: by mail-pf1-x433.google.com with SMTP id m26so1774621pff.3 for ; Thu, 21 Oct 2021 14:09:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hLET9P+4Q8tOpGhlnq30E50IovzdBUmNq96PBkRmeZA=; b=Ky+kErUKaLqOwT1sdKwrB7MpyWYV1zOKM95lh/COywgVj6pkW1x54+RKoycQmtIJGf 4C33eh9dqUdFgVzTrQJs0MI+B5vSeHVTxyMqI41faEI2vbU+W1vT8xMkOMdAOUiPocaO yZBIPPa0OpgTKqvGS5+NSoGKdTxYHHAiGn7bbsJdhvjYH1xO7yGXxZlcfamRB2pAXpKq vgQ5h+yRhu6+5932sSst+qzPmVrSBNEIJJx3zIFTFSUgQhrWPZ8Xl+DkrVYRUJYZjMD2 oWZrc3TiNIz0bXgdL6fz3NXZlQ54xLySCucPQhKyscRwZJ+Me95pYfCuUDu8+1vYJmDS MEfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hLET9P+4Q8tOpGhlnq30E50IovzdBUmNq96PBkRmeZA=; b=E+0ID8R7VlxZkca7ZHsdVCx3okjA5qAcPcKc0TK7dpsg+8lQ4fxGeUpeMftEgRtduU OPAwnQkSQsgqDosxazlQnzU4d3g5nHCBdTYczbB+KKuUm5OUPqLJfnwOSNfyVdDRbSRw ub70UGmWhHqzgYIBrYEwOOpA+rnJISajNLrd27Id6JgKi+oWrdU1dL7fUWt2o0JOHa1e 0MyKS3jE7DZ3ro2fT1rJdpKULPsfp9rWkN1A2H8rVoGhRCxx0zixeAi6Ont+S/R73qiy SRteH0sKz9gZLqkn/g8gPI9nRxPegYo8PJZmonesdQNX7aK7HAGmn6zLg16ixKMQ7h3W sgDw== X-Gm-Message-State: AOAM531zt29G/JLZvOX7yJBBf/JVMKHc4tIjG3E8SJqaUc981AQ/nxhf lLDbnwtO7P0EDULtjuXqXH7S4nn+r6Stuw== X-Received: by 2002:aa7:8243:0:b0:44e:599:bfe8 with SMTP id e3-20020aa78243000000b0044e0599bfe8mr8080790pfn.36.1634850552005; Thu, 21 Oct 2021 14:09:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i5sm6258856pgo.36.2021.10.21.14.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:09:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 41/48] tcg/optimize: Sink commutative operand swapping into fold functions Date: Thu, 21 Oct 2021 14:05:32 -0700 Message-Id: <20211021210539.825582-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most of these are handled by creating a fold_const2_commutative to handle all of the binary operators. The rest were already handled on a case-by-case basis in the switch, and have their own fold function in which to place the call. We now have only one major switch on TCGOpcode. Signed-off-by: Richard Henderson --- tcg/optimize.c | 128 ++++++++++++++++++++++--------------------------- 1 file changed, 56 insertions(+), 72 deletions(-) -- 2.25.1 diff --git a/tcg/optimize.c b/tcg/optimize.c index ba068e7d3e..92b35a8c3f 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -696,6 +696,12 @@ static bool fold_const2(OptContext *ctx, TCGOp *op) return false; } +static bool fold_const2_commutative(OptContext *ctx, TCGOp *op) +{ + swap_commutative(op->args[0], &op->args[1], &op->args[2]); + return fold_const2(ctx, op); +} + static bool fold_masks(OptContext *ctx, TCGOp *op) { uint64_t a_mask = ctx->a_mask; @@ -832,7 +838,7 @@ static bool fold_xx_to_x(OptContext *ctx, TCGOp *op) static bool fold_add(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_x(ctx, op, 0)) { return true; } @@ -891,6 +897,9 @@ static bool fold_addsub2(OptContext *ctx, TCGOp *op, bool add) static bool fold_add2(OptContext *ctx, TCGOp *op) { + swap_commutative(op->args[0], &op->args[2], &op->args[4]); + swap_commutative(op->args[1], &op->args[3], &op->args[5]); + return fold_addsub2(ctx, op, true); } @@ -898,7 +907,7 @@ static bool fold_and(OptContext *ctx, TCGOp *op) { uint64_t z1, z2; - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, -1) || fold_xx_to_x(ctx, op)) { @@ -950,8 +959,13 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) static bool fold_brcond(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[2]; - int i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond); + int i; + if (swap_commutative(-1, &op->args[0], &op->args[1])) { + op->args[2] = cond = tcg_swap_cond(cond); + } + + i = do_constant_folding_cond(ctx->type, op->args[0], op->args[1], cond); if (i == 0) { tcg_op_remove(ctx->tcg, op); return true; @@ -966,10 +980,14 @@ static bool fold_brcond(OptContext *ctx, TCGOp *op) static bool fold_brcond2(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[4]; - int i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond); TCGArg label = op->args[5]; - int inv = 0; + int i, inv = 0; + if (swap_commutative2(&op->args[0], &op->args[2])) { + op->args[4] = cond = tcg_swap_cond(cond); + } + + i = do_constant_folding_cond2(&op->args[0], &op->args[2], cond); if (i >= 0) { goto do_brcond_const; } @@ -1214,7 +1232,7 @@ static bool fold_dup2(OptContext *ctx, TCGOp *op) static bool fold_eqv(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_x(ctx, op, -1) || fold_xi_to_not(ctx, op, 0)) { return true; @@ -1376,8 +1394,20 @@ static bool fold_mov(OptContext *ctx, TCGOp *op) static bool fold_movcond(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[5]; - int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); + int i; + if (swap_commutative(-1, &op->args[1], &op->args[2])) { + op->args[5] = cond = tcg_swap_cond(cond); + } + /* + * Canonicalize the "false" input reg to match the destination reg so + * that the tcg backend can implement a "move if true" operation. + */ + if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { + op->args[5] = cond = tcg_invert_cond(cond); + } + + i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); if (i >= 0) { return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[4 - i]); } @@ -1414,7 +1444,7 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) static bool fold_multiply(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_i(ctx, op, 0)) { return true; } @@ -1423,6 +1453,8 @@ static bool fold_multiply(OptContext *ctx, TCGOp *op) static bool fold_multiply2(OptContext *ctx, TCGOp *op) { + swap_commutative(op->args[0], &op->args[2], &op->args[3]); + if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { uint64_t a = arg_info(op->args[2])->val; uint64_t b = arg_info(op->args[3])->val; @@ -1466,7 +1498,7 @@ static bool fold_multiply2(OptContext *ctx, TCGOp *op) static bool fold_nand(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_not(ctx, op, -1)) { return true; } @@ -1495,7 +1527,7 @@ static bool fold_neg(OptContext *ctx, TCGOp *op) static bool fold_nor(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_not(ctx, op, 0)) { return true; } @@ -1515,7 +1547,7 @@ static bool fold_not(OptContext *ctx, TCGOp *op) static bool fold_or(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xi_to_x(ctx, op, 0) || fold_xx_to_x(ctx, op)) { return true; @@ -1561,8 +1593,13 @@ static bool fold_qemu_st(OptContext *ctx, TCGOp *op) static bool fold_setcond(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[3]; - int i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); + int i; + if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { + op->args[3] = cond = tcg_swap_cond(cond); + } + + i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); if (i >= 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } @@ -1574,9 +1611,13 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) static bool fold_setcond2(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[5]; - int i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond); - int inv = 0; + int i, inv = 0; + if (swap_commutative2(&op->args[1], &op->args[3])) { + op->args[5] = cond = tcg_swap_cond(cond); + } + + i = do_constant_folding_cond2(&op->args[1], &op->args[3], cond); if (i >= 0) { goto do_setcond_const; } @@ -1754,7 +1795,7 @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op) static bool fold_xor(OptContext *ctx, TCGOp *op) { - if (fold_const2(ctx, op) || + if (fold_const2_commutative(ctx, op) || fold_xx_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, 0) || fold_xi_to_not(ctx, op, -1)) { @@ -1807,63 +1848,6 @@ void tcg_optimize(TCGContext *s) ctx.type = TCG_TYPE_I32; } - /* For commutative operations make constant second argument */ - switch (opc) { - CASE_OP_32_64_VEC(add): - CASE_OP_32_64_VEC(mul): - CASE_OP_32_64_VEC(and): - CASE_OP_32_64_VEC(or): - CASE_OP_32_64_VEC(xor): - CASE_OP_32_64(eqv): - CASE_OP_32_64(nand): - CASE_OP_32_64(nor): - CASE_OP_32_64(muluh): - CASE_OP_32_64(mulsh): - swap_commutative(op->args[0], &op->args[1], &op->args[2]); - break; - CASE_OP_32_64(brcond): - if (swap_commutative(-1, &op->args[0], &op->args[1])) { - op->args[2] = tcg_swap_cond(op->args[2]); - } - break; - CASE_OP_32_64(setcond): - if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { - op->args[3] = tcg_swap_cond(op->args[3]); - } - break; - CASE_OP_32_64(movcond): - if (swap_commutative(-1, &op->args[1], &op->args[2])) { - op->args[5] = tcg_swap_cond(op->args[5]); - } - /* For movcond, we canonicalize the "false" input reg to match - the destination reg so that the tcg backend can implement - a "move if true" operation. */ - if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) { - op->args[5] = tcg_invert_cond(op->args[5]); - } - break; - CASE_OP_32_64(add2): - swap_commutative(op->args[0], &op->args[2], &op->args[4]); - swap_commutative(op->args[1], &op->args[3], &op->args[5]); - break; - CASE_OP_32_64(mulu2): - CASE_OP_32_64(muls2): - swap_commutative(op->args[0], &op->args[2], &op->args[3]); - break; - case INDEX_op_brcond2_i32: - if (swap_commutative2(&op->args[0], &op->args[2])) { - op->args[4] = tcg_swap_cond(op->args[4]); - } - break; - case INDEX_op_setcond2_i32: - if (swap_commutative2(&op->args[1], &op->args[3])) { - op->args[5] = tcg_swap_cond(op->args[5]); - } - break; - default: - break; - } - /* Assume all bits affected, and no bits known zero. */ ctx.a_mask = -1; ctx.z_mask = -1; From patchwork Thu Oct 21 21:05:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516110 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp353736imj; Thu, 21 Oct 2021 14:43:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjmsQURJrVe6f5swD5UytEqO3LMuXtt/v+AqzlBkriGR9FkXIfppnMzNXzK3D9tZ0SQd0T X-Received: by 2002:a9d:458d:: with SMTP id x13mr6606082ote.290.1634852584769; Thu, 21 Oct 2021 14:43:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852584; cv=none; d=google.com; s=arc-20160816; b=duNcnao9e6ZouR6NXQkkMpUqScecGmvghVkRs9CXEQK9eyfIAEjeWuC61gE8KV9lyN mtiSnfB0nusDMqmDSf2igePGlUIFu8rwmfiTGNpJc/yFz34WzC9lk2wf4dTTVFRSPwK3 yOBJ5uY+c/5rP8A+VqnPp3qxOQN5jpKc1GInf6Ph8jmwcXENdPqdZ3IKJW6GHpxA4lkY WXWtGgSf2V1Z/+S3lYUxsY6jgRLqlGchiFItFmqMJBMA7nHuMLcvbdgcQFRJwLUFxX+C yKvJAawUBaKfhLq1Qp8C6qwRuTrRnscIg/kBY0FH2RLuJRV/i4QJKKeWtOsI80/O5q7k WdDg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id a6si7348262otl.90.2021.10.21.14.43.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:43:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=N29pthoM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdfq4-0002ER-7R for patch@linaro.org; Thu, 21 Oct 2021 17:43:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49238) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfJM-0003tn-Nk for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:16 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:46672) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfJK-00005i-3A for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:16 -0400 Received: by mail-pl1-x633.google.com with SMTP id i1so1260300plr.13 for ; Thu, 21 Oct 2021 14:09:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jhxCxDORBWFlpLFFFW8AXdB1GybQS0psT2aJJV5BQRM=; b=N29pthoMXmOqz68v+3SMzBPcn2qtDZXIDUYPEaAu5omWZj2+vQUB1KS/WcXSRyIQAX YEpFAjTgTJVduKhS/iCThZ+3568A6rOZ6+ZflAft/nFN2Kp73sR1mX8Iu+0NuqXPxSuN TLyOFRvA3vpLvHscRyei/vQy4UtWH2butXRr78vFkUkPUnlZQk28GJIrBzJ2x24EBLpP 7ZPf/8ut31EeK2UhAhexVV+/whyK/xtqZd6JSAy3Q7kXDl+/+Kr8q4+OpwEjqqOAI1lp sJXFWhUzaM48m+c/7HTWxqhQI8BgJyj9WFu3ccO/hvlvJOTnmKiYCKypbmr6o8GnlXn3 GVyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jhxCxDORBWFlpLFFFW8AXdB1GybQS0psT2aJJV5BQRM=; b=VwnRsGR5s76KiaH4VyGqy3bFkdvqoTzfsbStpGMLw9H51ofHq1+4qGlE5AjiKS8MfJ ldhrmuyAMeX10q2zjlH/i2Xk0tnGciq6DsxaFPQD5H+oPYBvddDG0tZtGAvQV0vE2rBD WwiXS11Qz9nD+RpaGjoj7rCPXOOJ7g864CEoDNMA3otl/EE8WMdiG++BtN2OjgcZfSiz /GHMDCnfZFqrtfO3rKc5qn+R+ZKAMso03hYj5lYYBXKs+WELXfkgo5yKExMi/RdUn46v v1bb0C/4bGK2HR+ddgbwvjmQMkemmTZq/MzHvlyOzfovYj784FSNrCLFhxBwO18hh4uZ ZwyA== X-Gm-Message-State: AOAM531lqKs61dknTYxZRwtJBiqJbz7kVTVSWrcqYKTFksc+2OVWyUqi HXEL/jFvY3Ke7dP0i74EdGZ2jm066nI6nA== X-Received: by 2002:a17:902:bb81:b0:12d:a7ec:3d85 with SMTP id m1-20020a170902bb8100b0012da7ec3d85mr7544088pls.17.1634850552663; Thu, 21 Oct 2021 14:09:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i5sm6258856pgo.36.2021.10.21.14.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:09:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 42/48] tcg/optimize: Add more simplifications for orc Date: Thu, 21 Oct 2021 14:05:33 -0700 Message-Id: <20211021210539.825582-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Two simplifications that were missing from before the split to fold functions, and are now easy to provide. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 92b35a8c3f..dc7744d41a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1561,6 +1561,8 @@ static bool fold_or(OptContext *ctx, TCGOp *op) static bool fold_orc(OptContext *ctx, TCGOp *op) { if (fold_const2(ctx, op) || + fold_xx_to_i(ctx, op, -1) || + fold_xi_to_x(ctx, op, -1) || fold_xi_to_not(ctx, op, 0)) { return true; } From patchwork Thu Oct 21 21:05:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516106 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp350456imj; Thu, 21 Oct 2021 14:38:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3FnUUP14m2opKZ+Y41cetiQc4uOM5SMZGXICu9q3Eg88PlGmKj/toIbQ7paGKZSUoIeeq X-Received: by 2002:a05:6830:233a:: with SMTP id q26mr7004552otg.245.1634852292736; Thu, 21 Oct 2021 14:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852292; cv=none; d=google.com; s=arc-20160816; b=0pxmwNolkgbXxlHELJQ4aT55PQCajcsCOErVzDVRZlNzZrzF2GhSAdRsrADH2X0Q56 A8RHO/syywirMq5HCmUO2ttd4iTxa7uYuhc2bbMwz/vqcG+aqL2T0Ei8YJIMgOBxwdg5 8SBT+FMPHQxBrQmNIsB3go+e2ksgNBJlxNfT6dtg3TIxB8lx8OUBAW/7f1k8JwcrhuiW opLvPPpMIZW+nc6Fj9OP8fcsPF1jSyQrx1yz5IaLSa3td7ZYiXFyiwwc4TL1C28eBtnK n0hWlF6w6Njsts/Bavwfu5Mvu4chNECPGZovd2/cQ1fs+xEja0CnRZsA241i8q7czy16 JREg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JQeaF7dr//8ZGCludsintmyDL9Pclz06Mhriys2K3H8=; b=KhDP6b3WYozJnZBtS7Z8A4+qAEUoBc9XdMrzMGigO6cWn3asBA7GPBFuPEeTn/EXtA CcyoIhvMAmTZEsDuJCoJxfAtsbdCacL05cEij4/ge5WrcveZG7mJ0LMHzFhoEZyQkE0g lp54mTzsRGDGiugrXqvNDcKg1AOA7jjY3eOBOQuyzCClVcg+ONMa3CufyuDTY0MGdiqf BSqfa+queP1POSEhdVlF9o6SN5FCFR6oDQNoKkdEgDeQ1/3s65ECxUv3KkfOXnh2iwyp Ik595NEG+67l0tp7cCDG3Ykg+5SWdpnJATzXqRgDCaNYgySFculxKW8cmwF+RyHMAnDw /POA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vwOrU4uH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j17si10154048otu.222.2021.10.21.14.38.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:38:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vwOrU4uH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdflM-0003eL-2a for patch@linaro.org; Thu, 21 Oct 2021 17:38:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49252) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfJO-0003wz-Ik for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:18 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:46856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfJL-00006N-2T for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:17 -0400 Received: by mail-pj1-x1032.google.com with SMTP id pi19-20020a17090b1e5300b0019fdd3557d3so1487733pjb.5 for ; Thu, 21 Oct 2021 14:09:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JQeaF7dr//8ZGCludsintmyDL9Pclz06Mhriys2K3H8=; b=vwOrU4uH4VYZgdI8Sd1Qo+USSiXpe5e5jbkXY2zzqx6Fry5G3gi2b/wtcdhYkN7MfY KWS0wexPW8SpWMGEOko2hOYP15OJOjaL8dwr0SxAEvKUWu279/sPDt0w6A0nYmSdPljl 33TIjYIQA+FNIsNLmCJfkalQVZqldJnWkEclbI39WgO92dAaOQNxqDQcdeOd/8oe8lGc taMcTKleRez8L2rVo5Zns2OYEfnijMagYC4IkofjCcPBeoGJNjU+sWfrejxol0NO0ipu OZm5yk4K1valyCkxg0jQjdjSFNp4CFqAZjN5UfMcrN/TpKM6yg1RCj5RDcu2OOO5cBPy MZLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JQeaF7dr//8ZGCludsintmyDL9Pclz06Mhriys2K3H8=; b=z9i08bYBKzPc2erJnnY+MmVmxSrY4pZ0+GLTtnqjneMWW/w8CSCTshYKqtwQXX5axG OU8Y5+yShZtOyKoLLEefBKXt2cxDv/KLyQqZgAnR/CkEsuMhoeFcTYua9d47x3hIdsWg YXCQtQMjyqZ23jn3bzBTXu5Rd/jAfi65tSI0n5jERVI34WfyFxOQsTB1hdofKlUI+e29 V04hdpWCA4VcccDzWMv7Vj0pQNKWam9oPH/Lv/S/cSQj4p6ff09cPw0mZg0H8jQ9lm7i 1G1r/fyF5zQ1TEqHOJYndg9p1gqSZH7/XOOjT0OdYStqEvuy2DP9hMHswmjAdKoC8U+m BIYA== X-Gm-Message-State: AOAM530ngvQ8SSZc2UxyJlqXj/GFRIXqpKZ2u5uoagU39uxGKC41r2X/ ng9ppACdub3z0yJMS5+ehy6DOzw0N46o+Q== X-Received: by 2002:a17:90b:1646:: with SMTP id il6mr9132066pjb.129.1634850553762; Thu, 21 Oct 2021 14:09:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i5sm6258856pgo.36.2021.10.21.14.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:09:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 43/48] tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values Date: Thu, 21 Oct 2021 14:05:34 -0700 Message-Id: <20211021210539.825582-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "garbage" setting pre-dates the addition of the type changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64, and INDEX_op_extr{l,h}_i64_i32. So now we have a definitive points at which to adjust z_mask to eliminate such bits from the 32-bit operands. Signed-off-by: Richard Henderson --- tcg/optimize.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index dc7744d41a..89117dd420 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -124,10 +124,6 @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts) ti->is_const = true; ti->val = ts->val; ti->z_mask = ts->val; - if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) { - /* High bits of a 32-bit quantity are garbage. */ - ti->z_mask |= ~0xffffffffull; - } } else { ti->is_const = false; ti->z_mask = -1; @@ -192,7 +188,6 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) TCGTemp *src_ts = arg_temp(src); TempOptInfo *di; TempOptInfo *si; - uint64_t z_mask; TCGOpcode new_op; if (ts_are_copies(dst_ts, src_ts)) { @@ -224,12 +219,7 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) op->args[0] = dst; op->args[1] = src; - z_mask = si->z_mask; - if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { - /* High bits of the destination are now garbage. */ - z_mask |= ~0xffffffffull; - } - di->z_mask = z_mask; + di->z_mask = si->z_mask; if (src_ts->type == dst_ts->type) { TempOptInfo *ni = ts_info(si->next_copy); @@ -247,9 +237,14 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) static bool tcg_opt_gen_movi(OptContext *ctx, TCGOp *op, TCGArg dst, uint64_t val) { - /* Convert movi to mov with constant temp. */ - TCGTemp *tv = tcg_constant_internal(ctx->type, val); + TCGTemp *tv; + if (ctx->type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + /* Convert movi to mov with constant temp. */ + tv = tcg_constant_internal(ctx->type, val); init_ts_info(ctx, tv); return tcg_opt_gen_mov(ctx, op, dst, temp_arg(tv)); } @@ -708,14 +703,16 @@ static bool fold_masks(OptContext *ctx, TCGOp *op) uint64_t z_mask = ctx->z_mask; /* - * 32-bit ops generate 32-bit results. For the result is zero test - * below, we can ignore high bits, but for further optimizations we - * need to record that the high bits contain garbage. + * 32-bit ops generate 32-bit results, which for the purpose of + * simplifying tcg are sign-extended. Certainly that's how we + * represent our constants elsewhere. Note that the bits will + * be reset properly for a 64-bit value when encountering the + * type changing opcodes. */ if (ctx->type == TCG_TYPE_I32) { - ctx->z_mask |= MAKE_64BIT_MASK(32, 32); - a_mask &= MAKE_64BIT_MASK(0, 32); - z_mask &= MAKE_64BIT_MASK(0, 32); + a_mask = (int32_t)a_mask; + z_mask = (int32_t)z_mask; + ctx->z_mask = z_mask; } if (z_mask == 0) { From patchwork Thu Oct 21 21:05:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516109 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp353344imj; Thu, 21 Oct 2021 14:42:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy/TLVvOtHTuEIE0ZhQnOpN1rsqD6WBej2I8ukb+jYdHGcJz+9a0eZAKx6nIGfFCrPPSaep X-Received: by 2002:a9d:6c4b:: with SMTP id g11mr7211969otq.122.1634852551080; Thu, 21 Oct 2021 14:42:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852551; cv=none; d=google.com; s=arc-20160816; b=L4sKGVmAdTlTdYFck7xutMCjwLT6h0EUU2etjFb3Kyb1O2OWXMAF6amJTrikyIXrKT DSVvgAcCy+XlegzMuBTtXg4flXG3Hp0GU2MqsaYruyf1DtHp6kO2VcUc5RHORPF1esTs sTA5/pe9bM/E50ZgOHZXUIzBE7lajNS5CFnhQItoJQmPklqsi/Bhtwi5p6AP7iNgZ01F 4S9NL/OrX0yFpGhWFHt/AwUNnJYCou28fOoZPXWNDtDJKbOV5q48FHoI9WTGiaUwUE4m DyDs/hab/6LZyhh5fQa7UqlaJUiaG5prfrT3yRSs66CtiFjboL4cO662CjIzMysT6BKx VJRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6Z5ejrZT676sLwMlzFe91VFmxn5RszfR6WUEnHfTEzM=; b=dVlR0NH4sDSMXLSuhcq4UPKYaX0coBs2dx70YQWfrHaxwgebhGwDXytS4/QTwmWfJj OT8GdiLA9UdKnpWpUXOXp8IgiH9EKff+1AFvzsNbNtHmOSZlJcimy0/3s/8hHLYpbvDl FkMN5DEinY3EmGQQ+7CfqyeyRmqJSTlSgztUdBitr2/RpRo+7Twszz8ejN+01EIr6yYR 39ku1soemKKKiXQdr5/t39CnfwtLjokKZrUwuuqkAxu7g+RMUgv39LjvgXwTRaSizUZw oVP3kUUFs9jiOgFeAGtZSEc6YBh8XGwrmIABa3IiV47lJ3/swUMLbgIejjyoFcRVqubk 4xUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="XQVIUVc/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This can lead to lots of redundant extensions as values are manipulated. Begin by tracking only the obvious sign-extensions, and converting them to simple copies when possible. Signed-off-by: Richard Henderson --- tcg/optimize.c | 129 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 105 insertions(+), 24 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 89117dd420..cf3c9d6b12 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -43,6 +43,7 @@ typedef struct TempOptInfo { TCGTemp *next_copy; uint64_t val; uint64_t z_mask; /* mask bit is 0 if and only if value bit is 0 */ + uint64_t s_mask; /* a left-aligned mask of clrsb(value) bits. */ } TempOptInfo; typedef struct OptContext { @@ -53,9 +54,37 @@ typedef struct OptContext { /* In flight values from optimization. */ uint64_t a_mask; /* mask bit is 0 iff value identical to first input */ uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ + uint64_t s_mask; /* mask of clrsb(value) bits */ TCGType type; } OptContext; +/* Calculate the smask for a specific value. */ +static uint64_t smask_from_value(uint64_t value) +{ + int rep = clrsb64(value); + return ~(~0ull >> rep); +} + +/* + * Calculate the smask for a given set of known-zeros. + * If there are lots of zeros on the left, we can consider the remainder + * an unsigned field, and thus the corresponding signed field is one bit + * larger. + */ +static uint64_t smask_from_zmask(uint64_t zmask) +{ + /* + * Only the 0 bits are significant for zmask, thus the msb itself + * must be zero, else we have no sign information. + */ + int rep = clz64(zmask); + if (rep == 0) { + return 0; + } + rep -= 1; + return ~(~0ull >> rep); +} + static inline TempOptInfo *ts_info(TCGTemp *ts) { return ts->state_ptr; @@ -94,6 +123,7 @@ static void reset_ts(TCGTemp *ts) ti->prev_copy = ts; ti->is_const = false; ti->z_mask = -1; + ti->s_mask = 0; } static void reset_temp(TCGArg arg) @@ -124,9 +154,11 @@ static void init_ts_info(OptContext *ctx, TCGTemp *ts) ti->is_const = true; ti->val = ts->val; ti->z_mask = ts->val; + ti->s_mask = smask_from_value(ts->val); } else { ti->is_const = false; ti->z_mask = -1; + ti->s_mask = 0; } } @@ -220,6 +252,7 @@ static bool tcg_opt_gen_mov(OptContext *ctx, TCGOp *op, TCGArg dst, TCGArg src) op->args[1] = src; di->z_mask = si->z_mask; + di->s_mask = si->s_mask; if (src_ts->type == dst_ts->type) { TempOptInfo *ni = ts_info(si->next_copy); @@ -645,13 +678,15 @@ static void finish_folding(OptContext *ctx, TCGOp *op) nb_oargs = def->nb_oargs; for (i = 0; i < nb_oargs; i++) { - reset_temp(op->args[i]); + TCGTemp *ts = arg_temp(op->args[i]); + reset_ts(ts); /* - * Save the corresponding known-zero bits mask for the + * Save the corresponding known-zero/sign bits mask for the * first output argument (only one supported so far). */ if (i == 0) { - arg_info(op->args[i])->z_mask = ctx->z_mask; + ts_info(ts)->z_mask = ctx->z_mask; + ts_info(ts)->s_mask = ctx->s_mask; } } } @@ -701,6 +736,7 @@ static bool fold_masks(OptContext *ctx, TCGOp *op) { uint64_t a_mask = ctx->a_mask; uint64_t z_mask = ctx->z_mask; + uint64_t s_mask = ctx->s_mask; /* * 32-bit ops generate 32-bit results, which for the purpose of @@ -712,7 +748,9 @@ static bool fold_masks(OptContext *ctx, TCGOp *op) if (ctx->type == TCG_TYPE_I32) { a_mask = (int32_t)a_mask; z_mask = (int32_t)z_mask; + s_mask |= MAKE_64BIT_MASK(32, 32); ctx->z_mask = z_mask; + ctx->s_mask = s_mask; } if (z_mask == 0) { @@ -1058,7 +1096,7 @@ static bool fold_brcond2(OptContext *ctx, TCGOp *op) static bool fold_bswap(OptContext *ctx, TCGOp *op) { - uint64_t z_mask, sign; + uint64_t z_mask, s_mask, sign; if (arg_is_const(op->args[1])) { uint64_t t = arg_info(op->args[1])->val; @@ -1068,6 +1106,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) } z_mask = arg_info(op->args[1])->z_mask; + switch (op->opc) { case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -1086,6 +1125,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) default: g_assert_not_reached(); } + s_mask = smask_from_zmask(z_mask); switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) { case TCG_BSWAP_OZ: @@ -1094,14 +1134,17 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op) /* If the sign bit may be 1, force all the bits above to 1. */ if (z_mask & sign) { z_mask |= sign; + s_mask = sign << 1; } break; default: /* The high bits are undefined: force all bits above the sign to 1. */ z_mask |= sign << 1; + s_mask = 0; break; } ctx->z_mask = z_mask; + ctx->s_mask = s_mask; return fold_masks(ctx, op); } @@ -1240,21 +1283,24 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) static bool fold_extract(OptContext *ctx, TCGOp *op) { uint64_t z_mask_old, z_mask; + int pos = op->args[2]; + int len = op->args[3]; if (arg_is_const(op->args[1])) { uint64_t t; t = arg_info(op->args[1])->val; - t = extract64(t, op->args[2], op->args[3]); + t = extract64(t, pos, len); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } z_mask_old = arg_info(op->args[1])->z_mask; - z_mask = sextract64(z_mask_old, op->args[2], op->args[3]); - if (op->args[2] == 0) { + z_mask = extract64(z_mask_old, pos, len); + if (pos == 0) { ctx->a_mask = z_mask_old ^ z_mask; } ctx->z_mask = z_mask; + ctx->s_mask = smask_from_zmask(z_mask); return fold_masks(ctx, op); } @@ -1280,14 +1326,16 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op) static bool fold_exts(OptContext *ctx, TCGOp *op) { - uint64_t z_mask_old, z_mask, sign; + uint64_t s_mask_old, s_mask, z_mask, sign; bool type_change = false; if (fold_const1(ctx, op)) { return true; } - z_mask_old = z_mask = arg_info(op->args[1])->z_mask; + z_mask = arg_info(op->args[1])->z_mask; + s_mask = arg_info(op->args[1])->s_mask; + s_mask_old = s_mask; switch (op->opc) { CASE_OP_32_64(ext8s): @@ -1311,10 +1359,14 @@ static bool fold_exts(OptContext *ctx, TCGOp *op) if (z_mask & sign) { z_mask |= sign; - } else if (!type_change) { - ctx->a_mask = z_mask_old ^ z_mask; } + s_mask |= sign << 1; + ctx->z_mask = z_mask; + ctx->s_mask = s_mask; + if (!type_change) { + ctx->a_mask = s_mask & ~s_mask_old; + } return fold_masks(ctx, op); } @@ -1353,6 +1405,7 @@ static bool fold_extu(OptContext *ctx, TCGOp *op) } ctx->z_mask = z_mask; + ctx->s_mask = smask_from_zmask(z_mask); if (!type_change) { ctx->a_mask = z_mask_old ^ z_mask; } @@ -1573,8 +1626,12 @@ static bool fold_qemu_ld(OptContext *ctx, TCGOp *op) MemOp mop = get_memop(oi); int width = 8 << (mop & MO_SIZE); - if (!(mop & MO_SIGN) && width < 64) { - ctx->z_mask = MAKE_64BIT_MASK(0, width); + if (width < 64) { + ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width); + if (!(mop & MO_SIGN)) { + ctx->z_mask = MAKE_64BIT_MASK(0, width); + ctx->s_mask <<= 1; + } } /* Opcodes that touch guest memory stop the mb optimization. */ @@ -1684,23 +1741,31 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) static bool fold_sextract(OptContext *ctx, TCGOp *op) { - int64_t z_mask_old, z_mask; + uint64_t z_mask, s_mask, s_mask_old; + int pos = op->args[2]; + int len = op->args[3]; if (arg_is_const(op->args[1])) { uint64_t t; t = arg_info(op->args[1])->val; - t = sextract64(t, op->args[2], op->args[3]); + t = sextract64(t, pos, len); return tcg_opt_gen_movi(ctx, op, op->args[0], t); } - z_mask_old = arg_info(op->args[1])->z_mask; - z_mask = sextract64(z_mask_old, op->args[2], op->args[3]); - if (op->args[2] == 0 && z_mask >= 0) { - ctx->a_mask = z_mask_old ^ z_mask; - } + z_mask = arg_info(op->args[1])->z_mask; + z_mask = sextract64(z_mask, pos, len); ctx->z_mask = z_mask; + s_mask_old = arg_info(op->args[1])->s_mask; + s_mask = sextract64(s_mask_old, pos, len); + s_mask |= MAKE_64BIT_MASK(len, 64 - len); + ctx->s_mask = s_mask; + + if (pos == 0) { + ctx->a_mask = s_mask & ~s_mask_old; + } + return fold_masks(ctx, op); } @@ -1777,14 +1842,26 @@ static bool fold_tcg_ld(OptContext *ctx, TCGOp *op) { /* We can't do any folding with a load, but we can record bits. */ switch (op->opc) { + CASE_OP_32_64(ld8s): + ctx->s_mask = MAKE_64BIT_MASK(8, 56); + break; CASE_OP_32_64(ld8u): - ctx->z_mask = 0xff; + ctx->z_mask = MAKE_64BIT_MASK(0, 8); + ctx->s_mask = MAKE_64BIT_MASK(9, 55); + break; + CASE_OP_32_64(ld16s): + ctx->s_mask = MAKE_64BIT_MASK(16, 48); break; CASE_OP_32_64(ld16u): - ctx->z_mask = 0xffff; + ctx->z_mask = MAKE_64BIT_MASK(0, 16); + ctx->s_mask = MAKE_64BIT_MASK(17, 47); + break; + case INDEX_op_ld32s_i64: + ctx->s_mask = MAKE_64BIT_MASK(32, 32); break; case INDEX_op_ld32u_i64: - ctx->z_mask = 0xffffffffu; + ctx->z_mask = MAKE_64BIT_MASK(0, 32); + ctx->s_mask = MAKE_64BIT_MASK(33, 31); break; default: g_assert_not_reached(); @@ -1847,9 +1924,10 @@ void tcg_optimize(TCGContext *s) ctx.type = TCG_TYPE_I32; } - /* Assume all bits affected, and no bits known zero. */ + /* Assume all bits affected, no bits known zero, no sign reps. */ ctx.a_mask = -1; ctx.z_mask = -1; + ctx.s_mask = 0; /* * Process each opcode. @@ -1922,8 +2000,11 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extrh_i64_i32: done = fold_extu(&ctx, op); break; + CASE_OP_32_64(ld8s): CASE_OP_32_64(ld8u): + CASE_OP_32_64(ld16s): CASE_OP_32_64(ld16u): + case INDEX_op_ld32s_i64: case INDEX_op_ld32u_i64: done = fold_tcg_ld(&ctx, op); break; From patchwork Thu Oct 21 21:05:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516114 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp359628imj; Thu, 21 Oct 2021 14:51:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOceUjyHBjkluhUOQtHs1Kjb8neDKAg4/7eFCG7IBbVjIr9/x0AKEbSLFLTYmgC5cH/K0S X-Received: by 2002:a05:6808:10ca:: with SMTP id s10mr6183229ois.62.1634853067030; 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Bitwise operations preserve the relative quantity of the repetitions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index cf3c9d6b12..d08cf7e4eb 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -953,6 +953,13 @@ static bool fold_and(OptContext *ctx, TCGOp *op) z2 = arg_info(op->args[2])->z_mask; ctx->z_mask = z1 & z2; + /* + * Sign repetitions are perforce all identical, whether they are 1 or 0. + * Bitwise operations preserve the relative quantity of the repetitions. + */ + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; + /* * Known-zeros does not imply known-ones. Therefore unless * arg2 is constant, we can't infer affected bits from it. @@ -988,6 +995,8 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) } ctx->z_mask = z1; + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return fold_masks(ctx, op); } @@ -1277,6 +1286,9 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) fold_xi_to_not(ctx, op, 0)) { return true; } + + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return false; } @@ -1464,6 +1476,8 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) ctx->z_mask = arg_info(op->args[3])->z_mask | arg_info(op->args[4])->z_mask; + ctx->s_mask = arg_info(op->args[3])->s_mask + & arg_info(op->args[4])->s_mask; if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { uint64_t tv = arg_info(op->args[3])->val; @@ -1552,6 +1566,9 @@ static bool fold_nand(OptContext *ctx, TCGOp *op) fold_xi_to_not(ctx, op, -1)) { return true; } + + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return false; } @@ -1581,6 +1598,9 @@ static bool fold_nor(OptContext *ctx, TCGOp *op) fold_xi_to_not(ctx, op, 0)) { return true; } + + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return false; } @@ -1590,6 +1610,8 @@ static bool fold_not(OptContext *ctx, TCGOp *op) return true; } + ctx->s_mask = arg_info(op->args[1])->s_mask; + /* Because of fold_to_not, we want to always return true, via finish. */ finish_folding(ctx, op); return true; @@ -1605,6 +1627,8 @@ static bool fold_or(OptContext *ctx, TCGOp *op) ctx->z_mask = arg_info(op->args[1])->z_mask | arg_info(op->args[2])->z_mask; + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return fold_masks(ctx, op); } @@ -1616,6 +1640,9 @@ static bool fold_orc(OptContext *ctx, TCGOp *op) fold_xi_to_not(ctx, op, 0)) { return true; } + + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return false; } @@ -1880,6 +1907,8 @@ static bool fold_xor(OptContext *ctx, TCGOp *op) ctx->z_mask = arg_info(op->args[1])->z_mask | arg_info(op->args[2])->z_mask; + ctx->s_mask = arg_info(op->args[1])->s_mask + & arg_info(op->args[2])->s_mask; return fold_masks(ctx, op); } From patchwork Thu Oct 21 21:05:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516116 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp363189imj; Thu, 21 Oct 2021 14:56:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwaJKjrT+8WUfVMK+5Bg6YU2n3sHuKnl6wawlGDs6IBnySwCdrc7nolB/F3SyZ/TBBlryK5 X-Received: by 2002:aca:e142:: with SMTP id y63mr6942183oig.112.1634853391360; Thu, 21 Oct 2021 14:56:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634853391; cv=none; d=google.com; s=arc-20160816; b=L7ko1RKmb60HyTlqg/pVPdUBJSxwrRALiHhEd8LYI3OwYITa9vQhqSZ5eRUmSj4brR Gv4+82CBgDCLoMnwBU5jj0DK9i8pptOFQhWc6URQqYj4a0q89ZScxezjT6cDFpsSQ+m3 Civ4yds4I8Da+9WlNABnbsMMD7coeKlS8zKdoJ3tDXXB3nG1TpTD9eCN5AHc4NBcrxkE vL6nLJ4oQsXGdEkt4dHH3jVV/cmJKXp0OACWH+lGgGJMK3BWcvIrcYUbYt8qsSjX9/21 bdSTrY5PyqB8s5HrZhvphFT7eJE3rVuluEsUPHUr2GEFhEbc3e74nMuUEb9IqQSZ5xeH yhfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6WqZ25wFq09ydrDs8rqLqB/wSl97QtTO4lZCT5y2bsY=; b=H8rdwUcKL5uUIjYd+Lr5JthphUPNRUvRHIHjqVFEW7hNvbRHXOArszqVFFkzGv8EWc oRKnP4D4AWH/4HZ9Jb/AEOtzhxhMbwi0mrCfXNeWFP32rTDMJlzWxchxXdgfTSAa509p 5D/otA4YA3POhDZpR0k6gSckrRz64tb8H5kI4vcbbFDAV6MoGfFXIUuY1mwbLcUrVfPp ZmN+qPRD0ewoI8LstA3PAYotfZWPYW97O33lKmtSdWfM9KCzQ6nHH1j4n3MtEnmcBgw4 4VGQm9gXmVCoIoO0p/62r8c7NmnoX3b8GPRlD6nnWTdd832bbJbTOdoeqfP+P4PWU3FF RyBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="dhVJ/Xlc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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For clarity, use the smask_from_zmask function. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index d08cf7e4eb..64d3256bbc 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1688,6 +1688,7 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) } ctx->z_mask = 1; + ctx->s_mask = smask_from_zmask(1); return false; } @@ -1760,6 +1761,7 @@ static bool fold_setcond2(OptContext *ctx, TCGOp *op) } ctx->z_mask = 1; + ctx->s_mask = smask_from_zmask(1); return false; do_setcond_const: From patchwork Thu Oct 21 21:05:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516112 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp354781imj; Thu, 21 Oct 2021 14:44:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgaGDfkDn8PyowUoCu8ZY9oaPEbceGGhOusrJYyIJCuNn4X5gQ88NQvpN25WiiMoFLEbBJ X-Received: by 2002:a05:6830:147:: with SMTP id j7mr6723279otp.67.1634852680056; Thu, 21 Oct 2021 14:44:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634852680; cv=none; d=google.com; s=arc-20160816; b=LibfuZbLoWBPrwpOJe6WS7FWhtiOeSxKfd4VrD5GzHTbcP4CQCY3B/x1+CJuW1vveD W8q0n9uEhexPrWVrGWurR99AEX0sisTs6KsprSHQO7HacCyP1jxAUxWV5hiopEkI5noa V3i7dnLLmj6IfvIzQDlDDp9t1eH4VkHfYTHBBPt9l0NnFYt/BuOKcBMXVrJAGjVk617Y pR3rerSdTYeh1UJd1q5fHVrWFW+xoLYazuuqd1BnvaRfvPOa64cnePNDZSYrcyzq+8zw FZ5hgChhW9XQE1qPzT7blktNazu15YaILJgJMXH7aS0OCqkhdhHxE1eXYR4pWI0bW4nK Z5YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5G0K+H2e7otmmKQ9zQj4DbcKrZpcr7GS6k3OOPhe8m0=; b=b1HUt1y8rlKoyWDepUzGsmfikIu52bxf1sm7sdSSyDuGUmSYFr3QAoJWvcdy17TdL2 nAN9H06Nljm29idc/tjO8/W0QwlkFK5sJVVPHc8GYeI6VIc4NzSfbfYB8YJZLZqCkJZM 2a+RkOZg3SzkC4Xamzy9gfBF3OT29XGbEtFnbA5AUl9e/bnX03OM2V3fqdQNzzSxqjM/ ujJqPS9J6dEVBoQWoeRnANzoeN1O57LMUVjxSriWNy1CQY6yOpo5vww4gJdJPzvEpXeW loBLXyzR5GynOJqIJkJoWdh/CsSg4tg7mKCJ1YkgPWUmvOV1gJQXr5SrWFYkqqTSEOVp q8ZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vCm+AY8X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 64d3256bbc..3dd9219d69 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1215,7 +1215,7 @@ static bool fold_count_zeros(OptContext *ctx, TCGOp *op) g_assert_not_reached(); } ctx->z_mask = arg_info(op->args[2])->z_mask | z_mask; - + ctx->s_mask = smask_from_zmask(ctx->z_mask); return false; } @@ -1235,6 +1235,7 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) default: g_assert_not_reached(); } + ctx->s_mask = smask_from_zmask(ctx->z_mask); return false; } From patchwork Thu Oct 21 21:05:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516115 Delivered-To: patch@linaro.org Received: by 2002:ac0:bf50:0:0:0:0:0 with SMTP id o16csp361372imj; Thu, 21 Oct 2021 14:53:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxLW6xaxXHlthCh6j3VsdJO4K+4bSjGvvVS8IjndylVGZ2UzPMnlqbZ9HPMzeZQYbUmsu0G X-Received: by 2002:aca:ba04:: with SMTP id k4mr6461656oif.76.1634853218873; Thu, 21 Oct 2021 14:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634853218; cv=none; d=google.com; s=arc-20160816; b=sliuqm5D314EyHx2J/sa45dfnGxelivuKw+D6SBtW4rjvYieRIQ1qxpLNJou2ThJjY wmoOENPH430yr2kQ34iYhYJTKH0PEOrtYw21v2xCYjlTCqn2U1jYiA7tRp7hM40XnhKu mJqO2FH2BIukkXdD2ATMQrfNe6esvOB5ZrTmEtQwr93Lop0ODQunhAyl7oWBsmQWZRNZ RYrL4eIjetRsbrp2H6IjsFQDu6io3z9IVyz+Irj2HoUxTvPN1PWADpoCHE0UvuMbi+5T xzyJZqUA+xh0JxGd+cpg0Gx5PVKQFntUjd6ZIazDtOwgltIxpAcvYw4qjuEFn/iOCvsE VI4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IOs5dk/JjBB+U1kfM4iGuyzcyV6uCGa5kiLeJfswCh8=; b=r0n5u9hwCCWAUGyi5mD5K1bx53GvHqoG3V8VCQ2/BRTE9UEWuLzo/pvU4LJlQcO2wY 2Yjz6JOOeylC+LTVczTne603OuOns5SyG/3ykKL2iC9dY14coaOEqncrKlXneo6LE2+m 6ULtZngbGiBV6DEegMwrNHlwzjL7jLHg+HQgQbvLy4q7h6bj8HA2Vcn0E6bnAIvYeZ3Z 1AmZz3X+X7ztfLRwcuMpU1Qyw6S+V41/xGqf7+F8Biz3g7l7usjJSTbnMHhJqPdgUvF+ dNBG+drBmSQ2s2hpgcVkjzUssE6V405lxO0Dqi0l9hLX9HzW7mLf4rciwXUVK1Xf8sIe VLFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=p2Z55PxB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w65si6884339oib.291.2021.10.21.14.53.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 14:53:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=p2Z55PxB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdg0I-0005Pk-73 for patch@linaro.org; Thu, 21 Oct 2021 17:53:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49312) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdfJQ-00045O-Pc for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:24 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:42574) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdfJO-0000A2-T8 for qemu-devel@nongnu.org; Thu, 21 Oct 2021 17:09:20 -0400 Received: by mail-pl1-x62e.google.com with SMTP id w17so1280459plg.9 for ; Thu, 21 Oct 2021 14:09:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IOs5dk/JjBB+U1kfM4iGuyzcyV6uCGa5kiLeJfswCh8=; b=p2Z55PxB+CCq278VYHceK6G6MwhAVqzaD4o+Xyg3FAk/pucA3qObjv9qncqwL8BuX5 DFdc5+PYdLMnOg2Gnvtehq6q1mitzWLVQ8NBCHR3qmWJwkyzZbPUG2FAvtnk28RCXhWS pU2AAvfewzjoFB5rV6S5CGPozyFSofpRr5LsFSkYX7NmTyBHKyXFH2QFk1/YJFLkexmM MEDHzCKfhc9hvT7CDjA9sbT89Fm6y+5cHC/J/vnVdbhkg8AJn3YLqOqTqauFqk20pbp1 9nsgTRhoTToucuZW8fXpqIopgXPCle7mX6d42jF5Ux/AXTVUaz2djDMyEUIY61xP+jo9 +2NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IOs5dk/JjBB+U1kfM4iGuyzcyV6uCGa5kiLeJfswCh8=; b=gjbz5haoeMyLoXdoQhcCmI/iOQhDONO7rl4gTJYd3RcIGJTWUnbKTAgmCwPEjotsDh JYL4SMf/omoVW/w+LVeOwPCs4440gljOYWX4LPhKhV2BQi5JKP8azcS45M8w+gcEUayo L1A5zWhs0YTmp9H8Ea/CmSxqhfNo3rMlo1ri5cW8sSSK6OOqtQJtPqPbKyM/sja7k9DB y6ti2ifcezzGIeCDWEjwK9tCepmDyulV+XAAr52xnxjyuHZroFK2NiYkf3YIWHawCOR6 TFSpQ999Q85uMcSZriut0GFcEkdjZVPiWclhZsIFYLSg2c/E+6GwG7Ev9G5R1aKQucxj qZzg== X-Gm-Message-State: AOAM533zD0fIZYc9ScAfwFb3RwwRDDURQQ5E3yPl8KAQuz/xoiSzGd32 OuWyrYzfEXwJuQyafR13+5a+JbwXfQeXug== X-Received: by 2002:a17:902:c950:b0:13e:fbf9:7939 with SMTP id i16-20020a170902c95000b0013efbf97939mr7339824pla.65.1634850557442; Thu, 21 Oct 2021 14:09:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id i5sm6258856pgo.36.2021.10.21.14.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 14:09:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 48/48] tcg/optimize: Propagate sign info for shifting Date: Thu, 21 Oct 2021 14:05:39 -0700 Message-Id: <20211021210539.825582-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211021210539.825582-1-richard.henderson@linaro.org> References: <20211021210539.825582-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: luis.pires@eldorado.org.br, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For constant shifts, we can simply shift the s_mask. For variable shifts, we know that sar does not reduce the s_mask, which helps for sequences like ext32s_i64 t, in sar_i64 t, t, v ext32s_i64 out, t allowing the final extend to be eliminated. Signed-off-by: Richard Henderson --- tcg/optimize.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tcg/optimize.c b/tcg/optimize.c index 3dd9219d69..5e239e00ee 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -85,6 +85,18 @@ static uint64_t smask_from_zmask(uint64_t zmask) return ~(~0ull >> rep); } +/* + * Recreate a properly left-aligned smask after manipulation. + * Some bit-shuffling, particularly shifts and rotates, may + * retain sign bits on the left, but may scatter disconnected + * sign bits on the right. Retain only what remains to the left. + */ +static uint64_t smask_from_smask(int64_t smask) +{ + /* Only the 1 bits are significant for smask */ + return smask_from_zmask(~smask); +} + static inline TempOptInfo *ts_info(TCGTemp *ts) { return ts->state_ptr; @@ -1801,18 +1813,50 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) static bool fold_shift(OptContext *ctx, TCGOp *op) { + uint64_t s_mask, z_mask, sign; + if (fold_const2(ctx, op) || fold_ix_to_i(ctx, op, 0) || fold_xi_to_x(ctx, op, 0)) { return true; } + s_mask = arg_info(op->args[1])->s_mask; + z_mask = arg_info(op->args[1])->z_mask; + if (arg_is_const(op->args[2])) { - ctx->z_mask = do_constant_folding(op->opc, ctx->type, - arg_info(op->args[1])->z_mask, - arg_info(op->args[2])->val); + int sh = arg_info(op->args[2])->val; + + ctx->z_mask = do_constant_folding(op->opc, ctx->type, z_mask, sh); + + s_mask = do_constant_folding(op->opc, ctx->type, s_mask, sh); + ctx->s_mask = smask_from_smask(s_mask); + return fold_masks(ctx, op); } + + switch (op->opc) { + CASE_OP_32_64(sar): + /* + * Arithmetic right shift will not reduce the number of + * input sign repetitions. + */ + ctx->s_mask = s_mask; + break; + CASE_OP_32_64(shr): + /* + * If the sign bit is known zero, then logical right shift + * will not reduced the number of input sign repetitions. + */ + sign = (s_mask & -s_mask) >> 1; + if (!(z_mask & sign)) { + ctx->s_mask = s_mask; + } + break; + default: + break; + } + return false; }