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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/10] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn Date: Wed, 3 Nov 2021 00:03:43 -0400 Message-Id: <20211103040352.373688-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cec672f229..9c4258ccac 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14750,6 +14750,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint64_t pc = s->base.pc_next; uint32_t insn; if (s->ss_active && !s->pstate_ss) { @@ -14769,10 +14770,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) return; } - s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); + s->pc_curr = pc; + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; - s->base.pc_next += 4; + s->base.pc_next = pc + 4; s->fp_access_checked = false; s->sve_access_checked = false; From patchwork Wed Nov 3 04:03:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516706 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp178684iml; Tue, 2 Nov 2021 21:06:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxR4hQPycxeMBHVRB6JdE2yTIgDybVlgbSz8oL/VfL0LsgEULMLdty7FtocclY4hKtwKMPl X-Received: by 2002:a05:6808:18a7:: with SMTP id bi39mr8580940oib.136.1635912363549; Tue, 02 Nov 2021 21:06:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912363; cv=none; d=google.com; s=arc-20160816; b=lLWdNM5BeAxTD5+wK5iZcpiFBxmGVljbSXT6cNuxAs7jx6qdmkdSs2xSDxG90TmULf 59YLHjK/wyEs9Nr5NXIXyZvIVNh4mOf1PPEQPiIno2A9BZaWinvD4em1/BB40+DUesof 4euaF9TgiV+rfoASzA7DCQ6mX46A6CiyeAG+OCfrWkJzwxDgLdlGIi7N2w+0uAJjaTCz QolgCp6EWw/4gcJ32zSY8Pfh9TVRh3fAgMcxSNwrSb7WQTx/7pWj/LpDc74fC1WUk9h4 8WHzYfyR9YYFzUw6b3J9vGx6DdGr5V6AoqRmYd9ElVyscv3B0Pa3WUGQoH5bv0pU/cC5 ma5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rD85GE1yJzMtNOUqHAoor4VFksIyrwnTsoaHAPCG9mI=; b=p1UgYB90VmHohHFKZBUj46Ql+6xk4U0+SSu67fRLEr6JQbAi3mlp7uB1vMxePZwqA4 rQhJxU2cXCrU7L2qEY18ZfjG54UKhpBCBw9jTsp97LEHuGj+T3sUz0HRdnYYbYiMi3TB 9FQhQWgLbQcwRxxo+5SnYG3j/1pxt6U70jVJvC0Sz0J4pqD0027h81KlasCZNReATYg/ tWvQTjnG9S1t5lgcjF3yTAg6bEDkGQgXnZLY2CrXt50fODSjTB1Ao8uJks7jS86XaBhL VNP800AopsX7YwDZ/y47vDFdxCJKnKi+0Wha0qJj9jxFyQ/s5AuvD7B+1bm1bQ1tA5P9 A/ZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GoIZq52T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/10] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn Date: Wed, 3 Nov 2021 00:03:44 -0400 Message-Id: <20211103040352.373688-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d6af5b1b03..ead77e9006 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9559,17 +9559,18 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; unsigned int insn; if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); dc->insn = insn; - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; disas_arm_insn(dc, insn); arm_post_translate_insn(dc); From patchwork Wed Nov 3 04:03:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516711 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp180543iml; Tue, 2 Nov 2021 21:08:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFgLMEtI9AIPFLSOpaVVbFmJyroFsyG4Ys54dXunh+lqZeE1BWYbpOAFc5YjRertvzpJ1c X-Received: by 2002:aca:3788:: with SMTP id e130mr8833652oia.90.1635912513511; Tue, 02 Nov 2021 21:08:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912513; cv=none; d=google.com; s=arc-20160816; b=AEV6eayedaRtdUcQQsLmz9vTkxjV5GK9ejP0m6ceIGAvqAXTz/n+qc5V8VUgDYhNL2 yGXHPRh1yZRauOO01s49yYwv1OHPxJMviNQV3uyUjky56OSXzFchKriuv0orIMpKBV2f eEny6dZE4zKdlKnP2sN1MJWP8FPMGvqWkm5K12l6o8XC7qQZKkmZD523Z0VWSWcxvviD J2TLDZWhBpQwxLtFdSErY979tz303qb0daFLAzqG63Z4pyA7GTW+0qJltx0+rDZP8zgc xeJ6Svbpl31AEKFgtYqCtU41aIjSwfH0ucF2E5pauNHyL8Fy8cydJQXuMrFQ4b7M9Vk5 Rd8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pKojDLUB4PcjfS7SRPDbZQq3hYacmhCQrpop1lkMtjQ=; b=k+7pv8+nu9fdX+V7bHx1WG7G0mVJHSLNYofq+kIdKZP09nVptazTiDB1nRdH/TlPyN BsbxWKcFbBI64WLKN/c1+XfOhSpf88FEKOasnERxydexSq/eeoeDDfoq4Gk2Uy7cTQrG kdDWaUL5orYEq/qAsQatUTrDsg5ZtvGKfhMQZs7ah9K/sY8I1XnX/LCetkzSVaF0YMSr jwG36QKCXTDd2/hxHjZB0Chx2/GedywvVz62+6gFMSWORPjh4iyrkZsv5h4H8XeiyY1B /TAhMXdHRaZpYf+xUQAHev3quUhfOp4JzDxfImrbIhREJanXVPaMd8ufcelZX6XV/kDM JrgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ToJypVBw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/10] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn Date: Wed, 3 Nov 2021 00:03:45 -0400 Message-Id: <20211103040352.373688-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index ead77e9006..a39456ea98 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9629,25 +9629,25 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; uint32_t insn; bool is_16bit; if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 2; + dc->base.pc_next = pc + 2; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); - dc->base.pc_next += 2; + pc += 2; if (!is_16bit) { - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, - dc->sctlr_b); - + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); insn = insn << 16 | insn2; - dc->base.pc_next += 2; + pc += 2; } + dc->base.pc_next = pc; dc->insn = insn; if (dc->pstate_il) { From patchwork Wed Nov 3 04:03:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516707 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp179120iml; Tue, 2 Nov 2021 21:06:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZRFh+xAdV+uwStDR7JjJjPbnMuIb1xtvyIk8dOvYdPiCTljGSfXUxgPFZZHzwwBK1fmXG X-Received: by 2002:a05:6830:448e:: with SMTP id r14mr18936888otv.171.1635912398984; Tue, 02 Nov 2021 21:06:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912398; cv=none; d=google.com; s=arc-20160816; b=lBsIoz76C0Bfi2Rrd7dCHVLG9dmXSOIdTh4WnTjq2y28LpygKRoJXtZoQ5hSqXNHEP UeJwfVxxP5BtE5ziI8zONJe48WMxMImdXU6/Rk0JqupgXoJ098gwhFidfKkgSwfGCPp/ Z2w0R4WX49OD6I9h1Re1f3dJerWTWxb/m6666BvMUmriY6ILMBBiuvcyEIU4rjqbYpoE iywbMMmwnIU9Z1Vl+pv/BKqKCpRX1ziUMOKJ3JeazNTUDl0FdVoLj/ZMQtwgQP0acDGH wP19CmiHbND9bnOwDP4YfKnrMn9CTGaMS93W7Pu8S0qttXpwDbxL8/HtHby2MSPlRrOf 4Vgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ztwm/zJmHHIzh4HcML3vD8itiNyqlXeIngv750qW5RU=; b=VbJvGJ4oBFfoKEdbL9idXX06QA8+MAKOQFwDIV8xiKAEQfWb9KtHL86pxsGs/raQnn Bfv8/bvXLJ0F0NcGu4d0BPa1+0ndWL7ZdBgmK06vhP+R8/gSYSswRDNvzkfbTAJF6ClA OZXdvA1RdZOsSPtqdur3b+B+NtQWHkb2p586eAOXx4Sc/m6YQI0e2l0ENnThLphkkVns 40PvJA1osICnOMgmHVUGi9AFSj0P8UE/5mJcK+3QEyH93IAOjNv0X29vk+p3C09vO1ph HF0OvoHLEmdh5ZC/I2UUMNAkxujPTI3PqHC0wBnKWllti/5i0iGZ+AH2zFDB2VmHuqiT jNTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wKWi/ht9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/10] target/arm: Split arm_pre_translate_insn Date: Wed, 3 Nov 2021 00:03:46 -0400 Message-Id: <20211103040352.373688-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f32; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create arm_check_ss_active and arm_check_kernelpage. Reverse the order of the tests. While it doesn't matter in practice, because only user-only has a kernel page and user-only never sets ss_active, ss_active has priority over execution exceptions and it is best to keep them in the proper order. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a39456ea98..82d4e24c27 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9513,7 +9513,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9525,7 +9525,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9562,7 +9566,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 4; return; } @@ -9633,7 +9637,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 2; return; } From patchwork Wed Nov 3 04:03:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516712 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp180784iml; Tue, 2 Nov 2021 21:08:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdkDl8DoKT1Z0z8lOEm5iyny/ntz+JZ/p0dPVkjopi3O3x9PpWQpe+xoJ1L9pkXxRe1DKG X-Received: by 2002:a05:6830:55b:: with SMTP id l27mr30488121otb.309.1635912534511; Tue, 02 Nov 2021 21:08:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912534; cv=none; d=google.com; s=arc-20160816; b=IQn7KHDZWiYRyD2F50+uTfq6YlhtdvKrFR7UyzIHgBAlyeFmXcZMLvSPUXwAKocltE p12BEYDnV85KcnRQkhiUVlwSrj4GIE4PW0bHBsPSVS0LtiLzWKzPernmE5mLXzy+lInJ U6mUlovG1JdkRtsgeAABotS44qofjbSSJ3HAmix2oPLuHUsTvdo8WZE2BgpfQPspusOh LBcDypk1/2M4enJiRPfGaDlzzAiWs9zkCdfIWAhs1oOsKQBWe/BjSUzVDC2nBogcyXq8 /fR9LR81a9T6iwVSRkhZqwauli158jx5RflFwB4xY4fw8qJCbkVlSkMfJKlYspCxDtbr VsWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cJZzHtETyU7Abpg6jDwficUEI9QcLIESqh5Jw1opJKw=; b=s0bFbhhNl6MHaYi3dUBUZIu5m+raycLZIpGw5lx+bllcBC4kBmj6ar1vAi+eTsIUFI ovSHZtslllT+x2rAG4zxHbENt7CJZcBVFraWaxSXA7ZPDKbVZXjPb0FnI+wPa9acAmUI +orRGuOM96MCzm4HNRkakyM84zx0MXxWMwAuMAwki8e5E0KJiw3CAj1DAgabsXvl4V/Z N7iyfi36zw1DJ4DOGBKVSVtEQDis/9mxoT5/2QMjv618RDBcDDEgJSnzhcJDZPuJ926X RWg1P4HKmMIQqNjKLj8uVkpcoSl/f/OQGnfGObfOHN1i6fudho3JOlkgwofEKyKmvAv3 SR3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HiDMshOr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/10] target/arm: Advance pc for arch single-step exception Date: Wed, 3 Nov 2021 00:03:47 -0400 Message-Id: <20211103040352.373688-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f33; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The size of the code covered by a TranslationBlock cannot be 0; this is checked via assert in tb_gen_code. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) -- 2.25.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c4258ccac..2986fe1393 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; } From patchwork Wed Nov 3 04:03:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516715 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp182434iml; Tue, 2 Nov 2021 21:10:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4N/PFQpFVP59fKjd/BBM+os26AzY1oIIvP3xbmI1JIQJnxyQaYO8xzEFLo2RojnHpac1w X-Received: by 2002:a9d:70c9:: with SMTP id w9mr29420893otj.243.1635912654576; Tue, 02 Nov 2021 21:10:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912654; cv=none; d=google.com; s=arc-20160816; b=oQr4YB+2HVq7by2NaKRzkmr258G4A5yz3NReRpM7yCLYsB3SjMewBeOVsuUC1XRDT0 lDpbA2SGlAwZ52ZGVtbghigZ+N7Li746rcvN2FMaisNluvq4uhsvu9wajM2HGlg1BZwt fnK7Z0Wl/ALt4DeYDJAi1t6KEXr2XRCsEy8eIRnzrHZiYlTXTNTtPRiI2ic14tTwjwRr oqqvZk/iTmkRmy1+FfRofJDE1ybdPuuWmqGsRsSSkaABM+0JMAZ0vOyeB0kNzVZXzZ54 h119fTv2LjtQ3f6/50NBOb676ucJR6Cb+FmZBmerC57hsD+Kv6znsVb50gxIxZdeCsYQ eTVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ML6fKNTEkgsDPbAJVxy09+sBxdECZjbfdFlmno/fZac=; b=BGoCOxTTk5+jarRynqbWtY90hToAcojoQvxrEfl/hOQiZw/sxbSLlyOHZfj4zpxahy 3TLRz8g1Hw6MKl7fURHxVPWgjMYE0zzQLqmzGI1nlGpoFuA7NTjkN9hyGkQB2NJELWTB /86YA6Iwzr4yBYaMbJuRd1wGo+FjP+2I3OI5qINghwgFGMDUYEiAdnBboCx2Kyz8CDzT VYnMbJPI/wwHfvaM90goI5H6pNLbuctHGIh+SPvoyl+hBEjssuAhezzSnlZ6lwFegxJa QuCn1qkePJkFaLdfcjWZ0KDp5wdVW6ypsb2YZ+34JUP+6UvJUO6oY2dLxtGQhAs6ssjD f0vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Xcg/YGsm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/10] target/arm: Split compute_fsr_fsc out of arm_deliver_fault Date: Wed, 3 Nov 2021 00:03:48 -0400 Message-Id: <20211103040352.373688-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2b; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will reuse this section of arm_deliver_fault for raising pc alignment faults. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 12a934e924..4cacb9658f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, + int target_el, int mmu_idx, uint32_t *ret_fsc) { - CPUARMState *env = &cpu->env; - int target_el; - bool same_el; - uint32_t syn, exc, fsr, fsc; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); - - target_el = exception_target_el(env); - if (fi->stage2) { - target_el = 2; - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; - if (arm_is_secure_below_el3(env) && fi->s1ns) { - env->cp15.hpfar_el2 |= HPFAR_NS; - } - } - same_el = (arm_current_el(env) == target_el); + uint32_t fsr, fsc; if (target_el == 2 || arm_el_is_aa64(env, target_el) || arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { @@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, fsc = 0x3f; } + *ret_fsc = fsc; + return fsr; +} + +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) +{ + CPUARMState *env = &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc, fsr, fsc; + + target_el = exception_target_el(env); + if (fi->stage2) { + target_el = 2; + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi->s1ns) { + env->cp15.hpfar_el2 |= HPFAR_NS; + } + } + same_el = (arm_current_el(env) == target_el); + + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + if (access_type == MMU_INST_FETCH) { syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; From patchwork Wed Nov 3 04:03:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516713 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp182112iml; Tue, 2 Nov 2021 21:10:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2D9NBeBsFCNhJBfH1CyZUtKqlgcZgiMsX3gwwHg1CjBWk/bHdUcz6tKhDLQbyunVXCKZv X-Received: by 2002:aca:60c1:: with SMTP id u184mr8614681oib.50.1635912634163; Tue, 02 Nov 2021 21:10:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912634; cv=none; d=google.com; s=arc-20160816; b=N88Z0SkVJzWzf/kUZIm9FAmK6Fljghq3zGv+3I/4wkgRY12fqrF2x60m5GcpqBTmd+ YJCkC6nKKRPbVm+HuRHINCjaYBMmNgGgMHQrDufSUCwtRYMTcGEmdl1JeXDz1pr7heJv 9E7C6rllvevEW5UuczSuv3jG2HF32wt+M3a/k4oFEf9OnqEs+QA+ugmtwOQer1WhMBVU ifvZvO84OITzMkbcB5XT9Z+ATPietswZwXahapQ1gNkd1U/MB3pauO5GRhUUXduY+IZg UA5WdQuqdTgRmtC/hLneUsWmgw+VWLO3KUR4rliBICkECLrha6uUlEBDSDU0bwYLmXbV AwOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=baj/I/Bz1wNfmusOUpoAH2XUyOJ1rLb4eb+amBeVoKQ=; b=B+bUGHFLEM0xfyL2FXD1Ac2rrE5SAxUb+Gc+QSSfHKvh7OduDIqzsmdkd2BpCl298w kNYEKRq2jkbyK8ukCdkDx9OHbeAmZxsX7Wxw/y0c2bpvHZQd8U6NiPkEYbljKjje3H8e H0YrsPLfxR8TmFhR2jdxTcVwdHo5Afo/K7WpLGHUIXXw58AxRK1S92MuUclupuXgRWuW NanDVG9/u3jRMAJheMIEH6203fqL72Av1xVeWhKpwtP5DiZxUXy1AR5YKsSuwqRuChAz lZl3IMW6k2VvmjrhxpxAsCJomY6TUZ8zH3Ba3gl3z1SiLv+i1Ad29jGai9674UoNUVvB ZhTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NmUMYFsf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/10] target/arm: Take an exception if PC is misaligned Date: Wed, 3 Nov 2021 00:03:49 -0400 Message-Id: <20211103040352.373688-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::733; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x733.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/syndrome.h | 5 ++++ linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++--------------- target/arm/tlb_helper.c | 18 ++++++++++++++ target/arm/translate-a64.c | 15 ++++++++++++ target/arm/translate.c | 22 ++++++++++++++++- 6 files changed, 87 insertions(+), 20 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.h b/target/arm/helper.h index 448a86edfd..b463d9343b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index f30f4130a2..8cde8e7243 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 97e0728b67..f9f3473288 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ ec = syn_get_ec(env->exception.syndrome); - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc = extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MTESERR; + break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MTESERR; - break; - case 0x21: /* Alignment fault */ + case EC_PCALIGNMENT: si_signo = TARGET_SIGBUS; si_code = TARGET_BUS_ADRALN; break; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 4cacb9658f..b79004e0cc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -134,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; + int target_el = exception_target_el(env); + int mmu_idx = cpu_mmu_index(env, true); + uint32_t fsc; + + env->exception.vaddress = pc; + + /* + * Note that the fsc is not applicable to this exception, + * since any syndrome is pcalignment not insn_abort. + */ + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); +} + #if !defined(CONFIG_USER_ONLY) /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2986fe1393..130a9ff8d5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14753,6 +14753,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint64_t pc = s->base.pc_next; uint32_t insn; + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14771,6 +14772,20 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) return; } + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + s->pc_curr = pc; insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; diff --git a/target/arm/translate.c b/target/arm/translate.c index 82d4e24c27..828fb328ee 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9566,7 +9566,27 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next = pc + 4; + return; + } + + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should only + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp = DISAS_NORETURN; + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 4; return; } From patchwork Wed Nov 3 04:03:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516708 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp179430iml; Tue, 2 Nov 2021 21:07:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyi1/47tRz55jxxBXKsN6jWdIyJQ7qFYE5mkMs/3xuKExbrAkQaERxMmxFjVXWnbuFtzMgP X-Received: by 2002:a05:6808:1814:: with SMTP id bh20mr8927214oib.0.1635912425925; Tue, 02 Nov 2021 21:07:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912425; cv=none; d=google.com; s=arc-20160816; b=WEXwtXliL/lFP4LxB595qH3FnbPMYu9W4O8LkNTVCJf8tg2j5jMI/toGNOesMnY3iK UjaqjRDbsucBzu6YuX1uKW6X3WeS11kJUPW2+NRCVoTxgbzmmBqRkA72/8HBgAGcp7aE 6r5BQMblQFOybgEyHse4DDrcqktW1fOV9CT2/WGB9Ip/mtOw0aj/87Ksc0wOncwuXWmS R9OVYVsDeHV6Xr3Z8d2FlXQ343xaZbnzIJ0PR2l7OtUk6c7sNI4QZjt2TeDew8FhnNQP fhSP12ynGwuJ4rTfUcjt3eQ3wc3PbAj5d1VlpxHavemkJXfImEUwE8WIvUv5UOHqjDmF N7bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FTtJgfAjhjyjpChmV21pyJSxrF1nuLy+//JpsWJ6z/k=; b=Z38HCewQAJZJ2ABFSNYGQ19mO+0LReID0+gaHAQnzz4xCM7dEI+suiNHksfhySMyPE 7J2EIlk1NAOoIe7zXS0gJ18HWLcUOMDrrN9kM0uQGcANWc5mIA0XTQKBpF/WYajY0AP9 VpjFGlTIJVnam21qTJ0z25e9EcVeEWIFEU2dr9XIlgQh+WUBjOAA4IWoRvFImZ4AnNyV JWTj+6NvexOnJG6wRcUiQAMdEJSUvcUJ/sLRx/6h8bo+ka61C3SexR/MCFb9zLyTylIO 79vId/fvvdxL+83ys/FWj+g2McijeSTuE7zL8VZBX6oJ3T0rq/sXFrwiCF2yLIUH2yL2 Ydkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g1E1hcAc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/10] target/arm: Assert thumb pc is aligned Date: Wed, 3 Nov 2021 00:03:50 -0400 Message-Id: <20211103040352.373688-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub.c | 9 +++++++-- target/arm/machine.c | 10 ++++++++++ target/arm/translate.c | 3 +++ 3 files changed, 20 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index e0dcb33e32..90bf803be2 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n == 15) { tmp &= ~1; } diff --git a/target/arm/machine.c b/target/arm/machine.c index c74d8c3f4b..135d2420b5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } } + + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 828fb328ee..9ac4292cfb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9657,6 +9657,9 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) == 0); + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 2; return; From patchwork Wed Nov 3 04:03:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516714 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp182333iml; Tue, 2 Nov 2021 21:10:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz20KgKsrfo1JE/DrIU0GqOdU4nr0/bQ9n4KmoRbvDjj5tlHsc0IKrpV20/rinAO9VEGKn8 X-Received: by 2002:a9d:6c0c:: with SMTP id f12mr28980227otq.275.1635912647997; Tue, 02 Nov 2021 21:10:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912647; cv=none; d=google.com; s=arc-20160816; b=CA9Enf7XSXTDBBOONdIqi2vRAymMZJytQ50q6dmvgY7k7S2GbxV2XhXWHk7BhJX/YU nbBOWVFUMc+cDd8mLzAWoFFYrG53FT7Cxl9ZynD8hEtH3ZEZWcbEvaPZM/4IXu5CDs23 69l1v0ddm6Q+riDYztjs/3KYuz/I0kpNh01q+nRInqeuP2PNyMIpPcWibnVX+rrItCRD pzrDN4ZxHiecqgvafqWttDg5xJDWWafV0Rxmf6bdVKqOFligtXHjdLnNVkU7iRbgccd0 iq20+tMhofv8nNxwBNH1eP97gcDVtKgXrbiicWNoDjv1+jBRDjjHrSFtXbr83Yuzhxso 9WWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1GwQXaikJPOnXJQIMQ/JzNg2jCKDE196b7cKL2erVtk=; b=vfEyJwiu6PtRnKLU6FEF/wbVKD48vmQhBIKGGUzCpFfj/dyem1V9Rm8N0k+JFfxozm pALEH04lqF8GhbO507gmUvP4ql1iPoPKhJYqAxmPebXoE9j7oUmiXGG4/WXkGEZnqBpu +b8CaZqH0YSkDT3NPLyXSh9rculrWLYL99yd9AzX5nZEtOBQ7uwwPgR11dkAEUBek3cT Mfd3vMhrGJrOwA4dmE0YjkM61KqlN8i24kii2p9DAjEkWHwsq19VY/2Hbe20QXysuBLX dXzmxPI/kLCdcDIzw8TR3RanVAlgJgMZSEXH/v8aVlACI1xmpRs/Kt4ytGfK472lXmLj NPtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eoMwY3zX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/10] target/arm: Suppress bp for exceptions with more priority Date: Wed, 3 Nov 2021 00:03:51 -0400 Message-Id: <20211103040352.373688-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both single-step and pc alignment faults have priority over breakpoint exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.25.1 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..32f3caec23 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + target_ulong pc; int n; /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc = is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; From patchwork Wed Nov 3 04:03:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 516709 Delivered-To: patch@linaro.org Received: by 2002:ad5:5208:0:0:0:0:0 with SMTP id p8csp180325iml; Tue, 2 Nov 2021 21:08:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx655XOhrthWW+l3bv+6AneI2mtsCOk5TmqQ4zpRnB7UY3FUZcv/5ZGkfK1/4LEqZvVyLwd X-Received: by 2002:aca:5bd6:: with SMTP id p205mr8406777oib.35.1635912497486; Tue, 02 Nov 2021 21:08:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635912497; cv=none; d=google.com; s=arc-20160816; b=MT86lS5RJs6DzhHxF0Cf+LwDTWgUnTqaOp2W+yXavYsjJ08Lqwq+J+tnqAnYxW2/zb MCZMrFf1SoPwG6dD44GLqCs9tnGie8Cxa+OTbds8s1yYVbU+kXMvU99zzDreqZN0euYa Xy6TXjY4VmprDbLN0S65iUDs2m6sQDG9FoLuwG1lCVw4AZy9JTF9DTWu7r8yoElrdmW3 jA/zdfjPrRPyZyCUq+d28Ofl5dHKDlpbWBk1xqoY5c3PfJFCsNL3RyvrgXj52JVl9SRd wZFrnyXRtKFYPKXR1r4QbbiiJZ9ZaKFpxwMKXqwR+JKoYNInU1d3k66vs6I/JdS6bNGO SP6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=j3xcIy2m2TMlH3aTyvVTXEM5j7IHz1QAadoWnnY7f2s=; b=MmVTd0mFC9TR8sRyqFkHAJ2QA5Id2Du91hdJhBaWiUs8G2Omtic6vnhpQP2lCsy4Pi V99NIWbPZ4mB55rclK9/30PTFj2Yuj4u/mzwOD6Mb3fU3J//+w41W7tcT8aJVtqoD2bk 1Wwmyz6Bnut2j1hBNHpPrbJXiwereD52bb5xRDq5ZHvpSqTUmlA2wW4A5WtRoYxVmW8i eoS7fpDrLoemS9ju+ETvqRmcvCFg0opIkA+TC7A+OXKktowVRT8UYQ8g6lAUeszQ3wkQ vC3rK3KMmzGp4KdUzy/cnMcxajce9IvhgqNtL0NEKdeg+D8CjuhMK9VrrHxFsJXqsa1B iIaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JeL6e5zC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:04:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/10] tests/tcg: Add arm and aarch64 pc alignment tests Date: Wed, 3 Nov 2021 00:03:52 -0400 Message-Id: <20211103040352.373688-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org> References: <20211103040352.373688-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +-- tests/tcg/arm/Makefile.target | 4 +++ 4 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c -- 2.25.1 diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c new file mode 100644 index 0000000000..6b9277f919 --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + abort(); +} diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 0000000000..3c9c8cc97b --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2c05c90d17..1d967901bd 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# Float-convert Tests -AARCH64_TESTS=fcvt +# Base architecture tests +AARCH64_TESTS=fcvt pcalign-a64 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce..f509d823d4 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# PC alignment test +ARM_TESTS += pcalign-a32 +pcalign-a32: CFLAGS+=-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) # Semihosting smoke test for linux-user