From patchwork Mon Nov 5 15:11:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 150193 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2718640ljp; Mon, 5 Nov 2018 07:11:36 -0800 (PST) X-Google-Smtp-Source: AJdET5eFH6B7szMpGpCwFLNEQnEQGTgkYzFWCnx5zsRoVsrfEEjNMoO2qaeIfudNWN6D2wrtC8KM X-Received: by 2002:adf:e983:: with SMTP id h3-v6mr7019776wrm.58.1541430696773; Mon, 05 Nov 2018 07:11:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541430696; cv=none; d=google.com; s=arc-20160816; b=s70xbtjJXsPKSAYMgAj2zCaomn3Uleb6kqxVHiN6JHeK2csEOj8L8Ojh1WfEB9bLmc UgSzA6kOePyV9y0XLgy+JjhCx/6PsiUemlW30D9HNqc0lv60IL/UiVIgg6zKAhhszqds cgCctmvYJ66kc+8aUUKzODsVVIop548BrzItbNs8kPilPyIMaoRgOPCVfQ5dfYyVVmWh 31tqPnlh888qJJlCKV4t4gzJ6995kPlmP1TVe+kKjetPRShlO8v+kf3EBn2BMA3BPVF+ r0ilAKIjobkD2wC9z/Bn0jpmkP1NAIp+9FShOm/Ydyy1kuoo071UzwtrdQMSM0pFq0DV 3cUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from; bh=KOH+SCAfduq0uFXDMHk05ZCfASxwmfBMLvhPu+KASTU=; b=wRuQijshLPAJbcII7k1VN/YLuPcRPG8NzX2S2O1jPEKneCgCgqqe5J3fLuvVbNgJ6j NGmZ3jWrp0ZUCnjhtJedTW5SK6dBKtVZA+SbudpHOgeqdcHA0gWa3yiMa6HJd/FYOtTs MgLZvBXdfsVwcPFOkROAlrN/jT1vhw8aqFuopvwCir5JWAE7MOEWQe87YqjJLmtZMqS6 3VSucDsNAIjE0dwo9VOsYw+N+FgPHrLZEHqaCAAiRmk67pWFVXsKeaWIeaQys3vWgw/R 5EtwfYqDKOUeGwWOx6x/yIMZI2PtHmwWjiLicPiA5zqA/Oq27eNigFQt4OmLs9hcWifS 870A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c2-v6si25977514wrw.86.2018.11.05.07.11.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Nov 2018 07:11:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gJgXP-0006MU-35; Mon, 05 Nov 2018 15:11:35 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mitsyanko , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= Subject: [PATCH for-3.1] hw/arm/exynos4210: Zero memory allocated for Exynos4210State Date: Mon, 5 Nov 2018 15:11:32 +0000 Message-Id: <20181105151132.13884-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 In exynos4210_init() we allocate memory for an Exynos4210State struct. Generally devices can assume that the memory allocated for their state struct is zero-initialized; we broke that assumption here by using g_new(). Use g_new0() instead. (In particular, some code assumes that the various irq arrays in the Exynos4210Irq sub-struct are zero-initialized.) In the longer term, this code should be QOMified, and then the struct memory will be allocated elsewhere and by functions which always zero-initalize it; but for 3.1 this is a simple fix. Signed-off-by: Peter Maydell --- I suggested this fix the other day: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg00135.html so here it is as an actual patch. Probably we should go through other uses of g_new() in board/device code at some point. hw/arm/exynos4210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.19.1 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 827318a0036..af82e955421 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -162,7 +162,7 @@ static uint64_t exynos4210_calc_affinity(int cpu) Exynos4210State *exynos4210_init(MemoryRegion *system_mem) { - Exynos4210State *s = g_new(Exynos4210State, 1); + Exynos4210State *s = g_new0(Exynos4210State, 1); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; SysBusDevice *busdev; DeviceState *dev;