From patchwork Mon Nov 22 16:04:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 518810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BF7CC433EF for ; Mon, 22 Nov 2021 16:04:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240156AbhKVQHm (ORCPT ); Mon, 22 Nov 2021 11:07:42 -0500 Received: from mail.kernel.org ([198.145.29.99]:55104 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240150AbhKVQHl (ORCPT ); Mon, 22 Nov 2021 11:07:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 11632604DA; Mon, 22 Nov 2021 16:04:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637597074; bh=oIlj4AL4IkCRUuzrCaLfIWpzkAppKN5eC4wr2r2aMik=; h=From:To:Cc:Subject:Date:From; b=Mi64BkkKrOi9QplUhK0D+jtOhf2QRDjjlICR/A4WI/6ZBFozME24+EFD4wdjIYYKU 2vv0nsQRtAg7VX7V/Hjtjaiw+4vUPgU5bNIeFeDDtdGZE/S52Zd4d5h4D/hyft4lGL YCxf2dYGCa5z7YUHVVEgexBUmBHYZG1VtPFZUM7mOtEIyFM4GJI8ir3C7k+9uDKWl/ 9cRc/NYND8AJI7VpOYSkjbA3BNv1/rttM+GJgq+3LW6AIyDgp6LCi1REyHDN15Y7Dl QQkBVSPVP7AME+BZ16StMinl/m+/Fn/TydZhK5wbYojwwRNtgWh40W/F4wxnyAKyFZ i69c0phr/2ouQ== From: Dinh Nguyen To: broonie@kernel.org Cc: dinguyen@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Date: Mon, 22 Nov 2021 10:04:26 -0600 Message-Id: <20211122160427.2808342-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register regardless of any condition. Well, the Cadence QuadSPI controller on Intel's SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash! So starting with v5.16, I introduced the patch 98d948eb833 ("spi: cadence-quadspi: fix write completion support"), which adds the dts property "intel,socfpga-qspi" that is specific for the QSPI on SoCFPGA that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 0b021eef0b53..108c3610bf52 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -782,7 +782,7 @@ ocram: sram@ffff0000 { }; qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qpsi"; #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index a574ea91d9d3..e1a70f3a641d 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -756,7 +756,7 @@ usb0-ecc@ff8c8800 { }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index d301ac0d406b..d391153c9e6d 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -594,7 +594,7 @@ emac0-tx-ecc@ff8c0400 { }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 163f33b46e4f..de6dd2189e74 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -628,7 +628,7 @@ sdmmca-ecc@ff8c8c00 { }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, From patchwork Mon Nov 22 16:04:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 517718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AD3FC433F5 for ; Mon, 22 Nov 2021 16:04:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240061AbhKVQHm (ORCPT ); Mon, 22 Nov 2021 11:07:42 -0500 Received: from mail.kernel.org ([198.145.29.99]:55122 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239994AbhKVQHm (ORCPT ); Mon, 22 Nov 2021 11:07:42 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id C9EE160524; Mon, 22 Nov 2021 16:04:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637597075; bh=7su5gVKoU6LxfqwsdkPAzegniwM93fqsZvNA4Sk4ACw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UOX6ARW1xXFQRPRHt2euwA7dN4QMa97W+iQQPNdZrrMjPJx+aiRXglxfyYITn8+cy /w4Q3iUJIGAvzZ63GbBvi3MG9bw5xqm1t4jyk2hco3/3E0Nkbgtx8L0DxUTh7tQcG8 fs5Y3y73XrfEbAeUMSrfvd2wucc9afLF0F1gbjlVUCTv2GXgtmyDa1nQ0IXctX11id 6XXbf9lMGCIEEKYVi+fnkn7dhUu15B5m8+ozzXVG5kXr0QgKNpvndA4dNkiwHF4lcT XQO1C5WLiuuvJUD8jWG/FKaTEW+mQWy3L4lyMM4bHYS8rxXv1uJaHf0gQsDizVi49e 47D3ZAgllcifg== From: Dinh Nguyen To: broonie@kernel.org Cc: dinguyen@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Date: Mon, 22 Nov 2021 10:04:27 -0600 Message-Id: <20211122160427.2808342-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211122160427.2808342-1-dinguyen@kernel.org> References: <20211122160427.2808342-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The QSPI controller on Intel's SoCFPGA platform does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash. Introduce the dts binding "intel,socfpga-qspi" to differentiate the hardware. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index ca155abbda7a..037f41f58503 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -29,6 +29,7 @@ properties: - ti,am654-ospi - intel,lgm-qspi - xlnx,versal-ospi-1.0 + - intel,socfpga-qspi - const: cdns,qspi-nor - const: cdns,qspi-nor