From patchwork Tue Jan 24 10:39:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 92332 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1649045qgi; Tue, 24 Jan 2017 02:44:50 -0800 (PST) X-Received: by 10.84.216.30 with SMTP id m30mr10954960pli.72.1485254690689; Tue, 24 Jan 2017 02:44:50 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si18643651pll.246.2017.01.24.02.44.50; Tue, 24 Jan 2017 02:44:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750775AbdAXKou (ORCPT + 7 others); Tue, 24 Jan 2017 05:44:50 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:28117 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750781AbdAXKot (ORCPT ); Tue, 24 Jan 2017 05:44:49 -0500 Received: from 172.24.1.47 (EHLO szxeml428-hub.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DTT06293; Tue, 24 Jan 2017 18:43:33 +0800 (CST) Received: from linux-ibm.site (10.175.102.37) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Jan 2017 18:43:20 +0800 From: Hanjun Guo To: Mark Rutland , Marc Zyngier , Will Deacon , Daniel Lezcano CC: "Rafael J. Wysocki" , Lorenzo Pieralisi , Fu Wei , Ding Tianhong , , , , Hanjun Guo Subject: [PATCH 1/2] arm64: arch_timer: acpi: Introduce a generic aquirk framework for erratum Date: Tue, 24 Jan 2017 18:39:50 +0800 Message-ID: <1485254391-51551-2-git-send-email-guohanjun@huawei.com> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1485254391-51551-1-git-send-email-guohanjun@huawei.com> References: <1485254391-51551-1-git-send-email-guohanjun@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.102.37] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.58872FD8.0018, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9142eecde5e5777ecc9115c9b2ed67ee Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: Hanjun Guo Introduce a general quirk framework for arch timer erratum in ACPI, which use the oem information in GTDT table for platform specific erratums. The struct gtdt_arch_timer_fixup is introduced to record the oem information to match the quirk and handle the erratum. Signed-off-by: Hanjun Guo --- drivers/clocksource/arm_arch_timer.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 1.7.12.4 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 2dc571d..80d6f76 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1146,6 +1146,39 @@ static int __init arch_timer_mem_of_init(struct device_node *np) arch_timer_mem_of_init); #ifdef CONFIG_ACPI_GTDT +struct gtdt_arch_timer_fixup { + char oem_id[ACPI_OEM_ID_SIZE + 1]; + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; + u32 oem_revision; + + /* quirk handler for arch timer erratum */ + void (*handler)(void *context); + void *context; +}; + +/* note: this needs to be updated according to the doc of OEM ID + * and TABLE ID for different board. + */ +static struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = { +}; + +static void __init arch_timer_acpi_quirks_handler(char *oem_id, + char *oem_table_id, + u32 oem_revision) +{ + struct gtdt_arch_timer_fixup *quirks = arch_timer_quirks; + int i; + + for (i = 0; i < ARRAY_SIZE(arch_timer_quirks); i++, quirks++) { + if (!memcmp(quirks->oem_id, oem_id, ACPI_OEM_ID_SIZE) && + !memcmp(quirks->oem_table_id, oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && + quirks->oem_revision == oem_revision) { + if (quirks->handler && quirks->context) + quirks->handler(quirks->context); + } + } +} + static int __init arch_timer_mem_acpi_init(int platform_timer_count) { struct arch_timer_mem *timer_mem; @@ -1182,6 +1215,9 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) return -EINVAL; } + arch_timer_acpi_quirks_handler(table->oem_id, table->oem_table_id, + table->oem_revision); + arch_timers_present |= ARCH_TIMER_TYPE_CP15; ret = acpi_gtdt_init(table, &platform_timer_count); From patchwork Tue Jan 24 10:39:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 92331 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1649038qgi; Tue, 24 Jan 2017 02:44:49 -0800 (PST) X-Received: by 10.98.223.66 with SMTP id u63mr37790881pfg.39.1485254689430; Tue, 24 Jan 2017 02:44:49 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si18643651pll.246.2017.01.24.02.44.49; Tue, 24 Jan 2017 02:44:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750791AbdAXKos (ORCPT + 7 others); Tue, 24 Jan 2017 05:44:48 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:28109 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750775AbdAXKor (ORCPT ); Tue, 24 Jan 2017 05:44:47 -0500 Received: from 172.24.1.47 (EHLO szxeml428-hub.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DTT06294; Tue, 24 Jan 2017 18:43:33 +0800 (CST) Received: from linux-ibm.site (10.175.102.37) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.235.1; Tue, 24 Jan 2017 18:43:21 +0800 From: Hanjun Guo To: Mark Rutland , Marc Zyngier , Will Deacon , Daniel Lezcano CC: "Rafael J. Wysocki" , Lorenzo Pieralisi , Fu Wei , Ding Tianhong , , , , Hanjun Guo Subject: [PATCH 2/2] arch_timer: acpi: add hisi timer erratum data Date: Tue, 24 Jan 2017 18:39:51 +0800 Message-ID: <1485254391-51551-3-git-send-email-guohanjun@huawei.com> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1485254391-51551-1-git-send-email-guohanjun@huawei.com> References: <1485254391-51551-1-git-send-email-guohanjun@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.102.37] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.58872FD7.009A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 879f98702beefa7a2e241a3691616ab3 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: Hanjun Guo Add hisilicon timer specific erratum fixes. Signed-off-by: Hanjun Guo --- drivers/clocksource/arm_arch_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 1.7.12.4 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Signed-off-by: Marc Zyngier Signed-off-by: Marc Zyngier diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 80d6f76..3e62a09 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1156,10 +1156,32 @@ struct gtdt_arch_timer_fixup { void *context; }; +#ifdef CONFIG_HISILICON_ERRATUM_161010101 +static void __init hisi_erratum_workaroud_enable(void *context) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { + if (!strcmp(context, ool_workarounds[i].id)) { + timer_unstable_counter_workaround = &ool_workarounds[i]; + static_branch_enable(&arch_timer_read_ool_enabled); + pr_info("arch_timer: Enabling workaround for %s\n", + timer_unstable_counter_workaround->id); + break; + } + } +} +#endif + /* note: this needs to be updated according to the doc of OEM ID * and TABLE ID for different board. */ static struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = { +#ifdef CONFIG_HISILICON_ERRATUM_161010101 + {"HISI ", "HIP05 ", 0, &hisi_erratum_workaroud_enable, "hisilicon,erratum-161010101"}, + {"HISI ", "HIP06 ", 0, &hisi_erratum_workaroud_enable, "hisilicon,erratum-161010101"}, + {"HISI ", "HIP07 ", 0, &hisi_erratum_workaroud_enable, "hisilicon,erratum-161010101"}, +#endif }; static void __init arch_timer_acpi_quirks_handler(char *oem_id,