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The tile size is 8x128 Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 15 +++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 19 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst index 3a09d93d405b..fc3baa2753ab 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst @@ -257,6 +257,8 @@ of the luma plane. .. _V4L2-PIX-FMT-NV12-4L4: .. _V4L2-PIX-FMT-NV12-16L16: .. _V4L2-PIX-FMT-NV12-32L32: +.. _V4L2_PIX_FMT_NV12MT_8L128: +.. _V4L2_PIX_FMT_NV12MT_10BE_8L128: Tiled NV12 ---------- @@ -296,6 +298,19 @@ tiles linearly in memory. The line stride and image height must be aligned to a multiple of 32. The layouts of the luma and chroma planes are identical. +``V4L2_PIX_FMT_NV12MT_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores +pixel in 2D 8x128 tiles, and stores tiles linearly in memory. +The image height must be aligned to a multiple of 128. +The layouts of the luma and chroma planes are identical. + +``V4L2_PIX_FMT_NV12MT_10BE_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores +10 bits pixel in 2D 8x128 tiles, and stores tiles linearly in memory. +the data is arranged at the big end. +The image height must be aligned to a multiple of 128. +The layouts of the luma and chroma planes are identical. +Note the tile size is 8bytes multiplied by 128 bytes, +it means that the low bits and high bits of one pixel may be in differnt tiles. + .. _nv12mt: .. kernel-figure:: nv12mt.svg diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 69b74d0e8a90..400eec0157a7 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1388,6 +1388,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_META_FMT_VIVID: descr = "Vivid Metadata"; break; case V4L2_META_FMT_RK_ISP1_PARAMS: descr = "Rockchip ISP1 3A Parameters"; break; case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A Statistics"; break; + case V4L2_PIX_FMT_NV12MT_8L128: descr = "NV12M (8x128 Linear)"; break; + case V4L2_PIX_FMT_NV12MT_10BE_8L128: descr = "NV12M 10BE(8x128 Linear)"; break; default: /* Compressed formats */ diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index f118fe7a9f58..9443c3109928 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -632,6 +632,8 @@ struct v4l2_pix_format { /* Tiled YUV formats, non contiguous planes */ #define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 tiles */ #define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 tiles */ +#define V4L2_PIX_FMT_NV12MT_8L128 v4l2_fourcc('N', 'A', '1', '2') /* Y/CbCr 4:2:0 8x128 tiles */ +#define V4L2_PIX_FMT_NV12MT_10BE_8L128 v4l2_fourcc('N', 'T', '1', '2') /* Y/CbCr 4:2:0 10-bit 8x128 tiles */ /* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */ #define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. 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CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM6PR04MB6341.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(83380400001)(5660300002)(52116002)(8936002)(6666004)(508600001)(66556008)(7416002)(316002)(86362001)(6486002)(26005)(186003)(956004)(36756003)(2906002)(8676002)(7696005)(44832011)(66476007)(4326008)(38350700002)(30864003)(2616005)(38100700002)(66946007)(559001)(579004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BKNeZ/gitXIXUdlFOgvLAewzXLxTY60hehS3j3lmWTcoDBKXS5dNnuRAwPUmBcFhl00YAylGYNQQMDzEY9IcLF3oAogK3WGwKb3M6XaP7o13elZEiEBCtTpCe9qfcizb3Nr2BLedGZcvYCr7oK/s9tT+OgdbS7cfXiaSlV3xLhaNYCJMjOhYFuX5RVx/vqQjisqf5LnoAj+BP3METXldy6eU0NslxityneSAXhQhp6vQCnJWcvfwWQcgWXxgmhlZQxpdxxJTixAO8JXTHNz15VG2Po1DCOWXcPr5GhIYVF7HRLeAuNApY4xk9F3arYPLCvJObnCotnU18n3tY+zc7aQLrOjFJcKWy5DEK/KDMP0O8GLzKv2IBqE9Ms1HQAsGTXU6usOUkA1aqPxk1+IxIcNYpEtMQF4GYmztfi0Uv5zACU5fdxaIZq9y6uaQAHZaGEqT+ebCny9KsN5riT5bYwOmAhwtTtphhlR0g3ruQrudBvbBADLZSjxvfgRdbtcoZ4pHPpsRKH2W7hVclIaAGPozXK/LYb/dDkgi2tmxImMvo0sTUn82xHGL/ouLoEAz0tsFRcXfZ3D+KJhFD2BlJa0fKCU4II/uV+PzLz4cVAlxF+W1sr6duhj0CdCnfxY9523lYXiPXUwBpAFkN4hkBpEaVsMWJGG/eK+3A/1h1TpP03DaK4wABaktAHCIpW/edF0aSXunybO10LuelKTv2HrtZ6e/K01FoXC4Wkj4O74YnqOc22y7oNyqv/zusNRHJjiAkEUPCwyFan8NxyMlZVbwSk3Ji2+SDQMGOMUidBTN66L2hTa8zI7REVfRV6aOxPVKKYdnrKGrB7ZVg27LGrc/ULPMWUiVVVbX1KZhIsKdorkBGb08CCK49hd0WrOAay+0ayE1Fp5UvgsY909trqbMiboh9dsvdPJ8fRkhP+ct75RBISO6edpWt2e0PS0aeQUWEYivSjai8LkDzdgCcdSfSNeJapYTZUKD5rq7v6rH8PbCzJcsJuEIuRnimsvIN5Kxdos0GTFM+Iw2q8zFT1r7xjJ5PUhUD3bM9RYwAC3xaIrSbxFVY8LTWsV6pk9RkER97N+BOryTv2RJFhWeud63siHO0KYzh0kFlLe0YHInzn97ODFqgiXuZWQTSACfKiZzhavoAslJquMFRcM3torRLIlaq3QW5QdSwj4gyY9IVCUY437ipYlnb+KiJz4kUQbzMPGD9J36SvA6CFSOY9miGRrigaKNig67RO1q6vN6XkmttnKmj4bC417VS7RNO9kyNylL6cEUxt4Pr19XeKvcIwOEN9gpeLNkaGXsNik6BFdIW4elBKcGtQUoqgWP7UPXljUZshQIZK943mob6c34oQMK0efzw6cXH6RvP8PKlvF+v6CYJKaIIABGBrWuXexgi/H+rhFBmceaJKGf7MJWWQeb1cu4WxwRezlJTeEEMHAXO3dzpN+y4KIsmmpBk3HbrRTCDpagZ2q85GjqrPYFj3PyP3dTzfy2hwvI4ZFlJQFoKgQAftI9KNE5mY/naMgNyqcWUTW8Uk9OSDC3hUX/zUuQ6TkNV97COp2hZ6VaVX66Wif3WgaytSZ2PHFpYa9lCGEwOP2xCo/kVEljW6cZQKrpOV+8v/PFdLf5sOE= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4d187d1c-3848-4106-e3f0-08d9b3e69e5b X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 09:48:53.7673 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: U4ITa54wvV+q9GUZB3enq0sKNtVQ4A4ekB50tSCLugu87mLIX1ZqcePbQ/QRyy71AD6azxWBIKfh/23MQtsEcQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3925 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The vpu supports encoder and decoder. it needs mu core to handle it. core will run either encoder or decoder firmware. This driver is for support the vpu core. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/media/platform/amphion/vpu_codec.h | 67 ++ drivers/media/platform/amphion/vpu_core.c | 906 +++++++++++++++++++++ drivers/media/platform/amphion/vpu_core.h | 15 + drivers/media/platform/amphion/vpu_dbg.c | 495 +++++++++++ drivers/media/platform/amphion/vpu_rpc.c | 279 +++++++ drivers/media/platform/amphion/vpu_rpc.h | 464 +++++++++++ 6 files changed, 2226 insertions(+) create mode 100644 drivers/media/platform/amphion/vpu_codec.h create mode 100644 drivers/media/platform/amphion/vpu_core.c create mode 100644 drivers/media/platform/amphion/vpu_core.h create mode 100644 drivers/media/platform/amphion/vpu_dbg.c create mode 100644 drivers/media/platform/amphion/vpu_rpc.c create mode 100644 drivers/media/platform/amphion/vpu_rpc.h diff --git a/drivers/media/platform/amphion/vpu_codec.h b/drivers/media/platform/amphion/vpu_codec.h new file mode 100644 index 000000000000..bf8920e9f6d7 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_codec.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_CODEC_H +#define _AMPHION_VPU_CODEC_H + +struct vpu_encode_params { + u32 input_format; + u32 codec_format; + u32 profile; + u32 tier; + u32 level; + struct v4l2_fract frame_rate; + u32 src_stride; + u32 src_width; + u32 src_height; + struct v4l2_rect crop; + u32 out_width; + u32 out_height; + + u32 gop_length; + u32 bframes; + + u32 rc_mode; + u32 bitrate; + u32 bitrate_min; + u32 bitrate_max; + + u32 i_frame_qp; + u32 p_frame_qp; + u32 b_frame_qp; + u32 qp_min; + u32 qp_max; + u32 qp_min_i; + u32 qp_max_i; + + struct { + u32 enable; + u32 idc; + u32 width; + u32 height; + } sar; + + struct { + u32 primaries; + u32 transfer; + u32 matrix; + u32 full_range; + } color; +}; + +struct vpu_decode_params { + u32 codec_format; + u32 output_format; + u32 b_dis_reorder; + u32 b_non_frame; + u32 frame_count; + u32 end_flag; + struct { + u32 base; + u32 size; + } udata; +}; + +#endif diff --git a/drivers/media/platform/amphion/vpu_core.c b/drivers/media/platform/amphion/vpu_core.c new file mode 100644 index 000000000000..0dbfd1c84f75 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_core.c @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_core.h" +#include "vpu_mbox.h" +#include "vpu_msgs.h" +#include "vpu_rpc.h" +#include "vpu_cmds.h" + +void csr_writel(struct vpu_core *core, u32 reg, u32 val) +{ + writel(val, core->base + reg); +} + +u32 csr_readl(struct vpu_core *core, u32 reg) +{ + return readl(core->base + reg); +} + +static int vpu_core_load_firmware(struct vpu_core *core) +{ + const struct firmware *pfw = NULL; + int ret = 0; + + WARN_ON(!core || !core->res || !core->res->fwname); + if (!core->fw.virt) { + dev_err(core->dev, "firmware buffer is not ready\n"); + return -EINVAL; + } + + ret = request_firmware(&pfw, core->res->fwname, core->dev); + dev_dbg(core->dev, "request_firmware %s : %d\n", core->res->fwname, ret); + if (ret) { + dev_err(core->dev, "request firmware %s failed, ret = %d\n", + core->res->fwname, ret); + return ret; + } + + if (core->fw.length < pfw->size) { + dev_err(core->dev, "firmware buffer size want %zu, but %d\n", + pfw->size, core->fw.length); + ret = -EINVAL; + goto exit; + } + + memset_io(core->fw.virt, 0, core->fw.length); + memcpy(core->fw.virt, pfw->data, pfw->size); + core->fw.bytesused = pfw->size; + ret = vpu_iface_on_firmware_loaded(core); +exit: + release_firmware(pfw); + pfw = NULL; + + return ret; +} + +static int vpu_core_boot_done(struct vpu_core *core) +{ + u32 fw_version; + + fw_version = vpu_iface_get_version(core); + dev_info(core->dev, "%s firmware version : %d.%d.%d\n", + vpu_core_type_desc(core->type), + (fw_version >> 16) & 0xff, + (fw_version >> 8) & 0xff, + fw_version & 0xff); + core->supported_instance_count = vpu_iface_get_max_instance_count(core); + if (core->res->act_size) { + u32 count = core->act.length / core->res->act_size; + + core->supported_instance_count = min(core->supported_instance_count, count); + } + core->fw_version = fw_version; + core->state = VPU_CORE_ACTIVE; + + return 0; +} + +static int vpu_core_wait_boot_done(struct vpu_core *core) +{ + int ret; + + ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT); + if (!ret) { + dev_err(core->dev, "boot timeout\n"); + return -EINVAL; + } + return vpu_core_boot_done(core); +} + +static int vpu_core_boot(struct vpu_core *core, bool load) +{ + int ret; + + WARN_ON(!core); + + if (!core->res->standalone) + return 0; + + reinit_completion(&core->cmp); + if (load) { + ret = vpu_core_load_firmware(core); + if (ret) + return ret; + } + + vpu_iface_boot_core(core); + return vpu_core_wait_boot_done(core); +} + +static int vpu_core_shutdown(struct vpu_core *core) +{ + if (!core->res->standalone) + return 0; + return vpu_iface_shutdown_core(core); +} + +static int vpu_core_restore(struct vpu_core *core) +{ + int ret; + + if (!core->res->standalone) + return 0; + ret = vpu_core_sw_reset(core); + if (ret) + return ret; + + vpu_core_boot_done(core); + return vpu_iface_restore_core(core); +} + +static int __vpu_alloc_dma(struct device *dev, struct vpu_buffer *buf) +{ + gfp_t gfp = GFP_KERNEL | GFP_DMA32; + + WARN_ON(!dev || !buf); + + if (!buf->length) + return 0; + + buf->virt = dma_alloc_coherent(dev, buf->length, &buf->phys, gfp); + if (!buf->virt) + return -ENOMEM; + + buf->dev = dev; + + return 0; +} + +void vpu_free_dma(struct vpu_buffer *buf) +{ + WARN_ON(!buf); + + if (!buf->virt || !buf->dev) + return; + + dma_free_coherent(buf->dev, buf->length, buf->virt, buf->phys); + buf->virt = NULL; + buf->phys = 0; + buf->length = 0; + buf->bytesused = 0; + buf->dev = NULL; +} + +int vpu_alloc_dma(struct vpu_core *core, struct vpu_buffer *buf) +{ + WARN_ON(!core || !buf); + + return __vpu_alloc_dma(core->dev, buf); +} + +static void vpu_core_check_hang(struct vpu_core *core) +{ + if (core->hang_mask) + core->state = VPU_CORE_HANG; +} + +static struct vpu_core *vpu_core_find_proper_by_type(struct vpu_dev *vpu, u32 type) +{ + struct vpu_core *core = NULL; + int request_count = INT_MAX; + struct vpu_core *c; + + WARN_ON(!vpu); + + list_for_each_entry(c, &vpu->cores, list) { + dev_dbg(c->dev, "instance_mask = 0x%lx, state = %d\n", + c->instance_mask, + c->state); + if (c->type != type) + continue; + if (c->state == VPU_CORE_DEINIT) { + core = c; + break; + } + vpu_core_check_hang(c); + if (c->state != VPU_CORE_ACTIVE) + continue; + if (c->request_count < request_count) { + request_count = c->request_count; + core = c; + } + if (!request_count) + break; + } + + return core; +} + +static bool vpu_core_is_exist(struct vpu_dev *vpu, struct vpu_core *core) +{ + struct vpu_core *c; + + list_for_each_entry(c, &vpu->cores, list) { + if (c == core) + return true; + } + + return false; +} + +static void vpu_core_get_vpu(struct vpu_core *core) +{ + core->vpu->get_vpu(core->vpu); + if (core->type == VPU_CORE_TYPE_ENC) + core->vpu->get_enc(core->vpu); + if (core->type == VPU_CORE_TYPE_DEC) + core->vpu->get_dec(core->vpu); +} + +static int vpu_core_register(struct device *dev, struct vpu_core *core) +{ + struct vpu_dev *vpu = dev_get_drvdata(dev); + int ret = 0; + + dev_dbg(core->dev, "register core %s\n", vpu_core_type_desc(core->type)); + if (vpu_core_is_exist(vpu, core)) + return 0; + + core->workqueue = alloc_workqueue("vpu", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (!core->workqueue) { + dev_err(core->dev, "fail to alloc workqueue\n"); + return -ENOMEM; + } + INIT_WORK(&core->msg_work, vpu_msg_run_work); + INIT_DELAYED_WORK(&core->msg_delayed_work, vpu_msg_delayed_work); + core->msg_buffer_size = roundup_pow_of_two(VPU_MSG_BUFFER_SIZE); + core->msg_buffer = vzalloc(core->msg_buffer_size); + if (!core->msg_buffer) { + dev_err(core->dev, "failed allocate buffer for fifo\n"); + ret = -ENOMEM; + goto error; + } + ret = kfifo_init(&core->msg_fifo, core->msg_buffer, core->msg_buffer_size); + if (ret) { + dev_err(core->dev, "failed init kfifo\n"); + goto error; + } + + list_add_tail(&core->list, &vpu->cores); + + vpu_core_get_vpu(core); + + if (vpu_iface_get_power_state(core)) + ret = vpu_core_restore(core); + if (ret) + goto error; + + return 0; +error: + if (core->msg_buffer) { + vfree(core->msg_buffer); + core->msg_buffer = NULL; + } + if (core->workqueue) { + destroy_workqueue(core->workqueue); + core->workqueue = NULL; + } + return ret; +} + +static void vpu_core_put_vpu(struct vpu_core *core) +{ + if (core->type == VPU_CORE_TYPE_ENC) + core->vpu->put_enc(core->vpu); + if (core->type == VPU_CORE_TYPE_DEC) + core->vpu->put_dec(core->vpu); + core->vpu->put_vpu(core->vpu); +} + +static int vpu_core_unregister(struct device *dev, struct vpu_core *core) +{ + list_del_init(&core->list); + + vpu_core_put_vpu(core); + core->vpu = NULL; + vfree(core->msg_buffer); + core->msg_buffer = NULL; + + if (core->workqueue) { + cancel_work_sync(&core->msg_work); + cancel_delayed_work_sync(&core->msg_delayed_work); + destroy_workqueue(core->workqueue); + core->workqueue = NULL; + } + + return 0; +} + +static int vpu_core_acquire_instance(struct vpu_core *core) +{ + int id; + + WARN_ON(!core); + + id = ffz(core->instance_mask); + if (id >= core->supported_instance_count) + return -EINVAL; + + set_bit(id, &core->instance_mask); + + return id; +} + +static void vpu_core_release_instance(struct vpu_core *core, int id) +{ + WARN_ON(!core); + + if (id < 0 || id >= core->supported_instance_count) + return; + + clear_bit(id, &core->instance_mask); +} + +struct vpu_inst *vpu_inst_get(struct vpu_inst *inst) +{ + if (!inst) + return NULL; + + atomic_inc(&inst->ref_count); + + return inst; +} + +void vpu_inst_put(struct vpu_inst *inst) +{ + if (!inst) + return; + if (atomic_dec_and_test(&inst->ref_count)) { + if (inst->release) + inst->release(inst); + } +} + +struct vpu_core *vpu_request_core(struct vpu_dev *vpu, enum vpu_core_type type) +{ + struct vpu_core *core = NULL; + int ret; + + mutex_lock(&vpu->lock); + + core = vpu_core_find_proper_by_type(vpu, type); + if (!core) + goto exit; + + mutex_lock(&core->lock); + pm_runtime_get_sync(core->dev); + + if (core->state == VPU_CORE_DEINIT) { + ret = vpu_core_boot(core, true); + if (ret) { + pm_runtime_put_sync(core->dev); + mutex_unlock(&core->lock); + core = NULL; + goto exit; + } + } + + core->request_count++; + + mutex_unlock(&core->lock); +exit: + mutex_unlock(&vpu->lock); + + return core; +} + +void vpu_release_core(struct vpu_core *core) +{ + if (!core) + return; + + mutex_lock(&core->lock); + pm_runtime_put_sync(core->dev); + if (core->request_count) + core->request_count--; + mutex_unlock(&core->lock); +} + +int vpu_inst_register(struct vpu_inst *inst) +{ + struct vpu_dev *vpu; + struct vpu_core *core; + int ret = 0; + + WARN_ON(!inst || !inst->vpu); + + vpu = inst->vpu; + core = inst->core; + if (!core) { + core = vpu_request_core(vpu, inst->type); + if (!core) { + dev_err(vpu->dev, "there is no vpu core for %s\n", + vpu_core_type_desc(inst->type)); + return -EINVAL; + } + inst->core = core; + inst->dev = get_device(core->dev); + } + + mutex_lock(&core->lock); + if (inst->id >= 0 && inst->id < core->supported_instance_count) + goto exit; + + ret = vpu_core_acquire_instance(core); + if (ret < 0) + goto exit; + + vpu_trace(inst->dev, "[%d] %p\n", ret, inst); + inst->id = ret; + list_add_tail(&inst->list, &core->instances); + ret = 0; + if (core->res->act_size) { + inst->act.phys = core->act.phys + core->res->act_size * inst->id; + inst->act.virt = core->act.virt + core->res->act_size * inst->id; + inst->act.length = core->res->act_size; + } + vpu_inst_create_dbgfs_file(inst); +exit: + mutex_unlock(&core->lock); + + if (ret) + dev_err(core->dev, "register instance fail\n"); + return ret; +} + +int vpu_inst_unregister(struct vpu_inst *inst) +{ + struct vpu_core *core; + + WARN_ON(!inst); + + if (!inst->core) + return 0; + + core = inst->core; + vpu_clear_request(inst); + mutex_lock(&core->lock); + if (inst->id >= 0 && inst->id < core->supported_instance_count) { + vpu_inst_remove_dbgfs_file(inst); + list_del_init(&inst->list); + vpu_core_release_instance(core, inst->id); + inst->id = VPU_INST_NULL_ID; + } + vpu_core_check_hang(core); + if (core->state == VPU_CORE_HANG && !core->instance_mask) { + dev_info(core->dev, "reset hang core\n"); + if (!vpu_core_sw_reset(core)) { + core->state = VPU_CORE_ACTIVE; + core->hang_mask = 0; + } + } + mutex_unlock(&core->lock); + + return 0; +} + +struct vpu_inst *vpu_core_find_instance(struct vpu_core *core, u32 index) +{ + struct vpu_inst *inst = NULL; + struct vpu_inst *tmp; + + mutex_lock(&core->lock); + if (!test_bit(index, &core->instance_mask)) + goto exit; + list_for_each_entry(tmp, &core->instances, list) { + if (tmp->id == index) { + inst = vpu_inst_get(tmp); + break; + } + } +exit: + mutex_unlock(&core->lock); + + return inst; +} + +const struct vpu_core_resources *vpu_get_resource(struct vpu_inst *inst) +{ + struct vpu_dev *vpu; + struct vpu_core *core = NULL; + const struct vpu_core_resources *res = NULL; + + if (!inst || !inst->vpu) + return NULL; + + if (inst->core && inst->core->res) + return inst->core->res; + + vpu = inst->vpu; + mutex_lock(&vpu->lock); + list_for_each_entry(core, &vpu->cores, list) { + if (core->type == inst->type) { + res = core->res; + break; + } + } + mutex_unlock(&vpu->lock); + + return res; +} + +static int vpu_core_parse_dt(struct vpu_core *core, struct device_node *np) +{ + struct device_node *node; + struct resource res; + + if (of_count_phandle_with_args(np, "memory-region", NULL) < 2) { + dev_err(core->dev, "need 2 memory-region for boot and rpc\n"); + return -ENODEV; + } + + node = of_parse_phandle(np, "memory-region", 0); + if (!node) { + dev_err(core->dev, "boot-region of_parse_phandle error\n"); + return -ENODEV; + } + if (of_address_to_resource(node, 0, &res)) { + dev_err(core->dev, "boot-region of_address_to_resource error\n"); + return -EINVAL; + } + core->fw.phys = res.start; + core->fw.length = resource_size(&res); + + node = of_parse_phandle(np, "memory-region", 1); + if (!node) { + dev_err(core->dev, "rpc-region of_parse_phandle error\n"); + return -ENODEV; + } + if (of_address_to_resource(node, 0, &res)) { + dev_err(core->dev, "rpc-region of_address_to_resource error\n"); + return -EINVAL; + } + core->rpc.phys = res.start; + core->rpc.length = resource_size(&res); + + if (core->rpc.length < core->res->rpc_size + core->res->fwlog_size) { + dev_err(core->dev, "the rpc-region <%pad, 0x%x> is not enough\n", + &core->rpc.phys, core->rpc.length); + return -EINVAL; + } + + core->fw.virt = ioremap_wc(core->fw.phys, core->fw.length); + core->rpc.virt = ioremap_wc(core->rpc.phys, core->rpc.length); + memset_io(core->rpc.virt, 0, core->rpc.length); + + if (vpu_iface_check_memory_region(core, + core->rpc.phys, + core->rpc.length) != VPU_CORE_MEMORY_UNCACHED) { + dev_err(core->dev, "rpc region<%pad, 0x%x> isn't uncached\n", + &core->rpc.phys, core->rpc.length); + return -EINVAL; + } + + core->log.phys = core->rpc.phys + core->res->rpc_size; + core->log.virt = core->rpc.virt + core->res->rpc_size; + core->log.length = core->res->fwlog_size; + core->act.phys = core->log.phys + core->log.length; + core->act.virt = core->log.virt + core->log.length; + core->act.length = core->rpc.length - core->res->rpc_size - core->log.length; + core->rpc.length = core->res->rpc_size; + + return 0; +} + +static int vpu_core_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct vpu_core *core; + struct vpu_dev *vpu = dev_get_drvdata(dev->parent); + struct vpu_shared_addr *iface; + u32 iface_data_size; + int ret; + + dev_dbg(dev, "probe\n"); + if (!vpu) + return -EINVAL; + core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL); + if (!core) + return -ENOMEM; + + core->pdev = pdev; + core->dev = dev; + platform_set_drvdata(pdev, core); + core->vpu = vpu; + INIT_LIST_HEAD(&core->instances); + mutex_init(&core->lock); + mutex_init(&core->cmd_lock); + init_completion(&core->cmp); + init_waitqueue_head(&core->ack_wq); + core->state = VPU_CORE_DEINIT; + + core->res = of_device_get_match_data(dev); + if (!core->res) + return -ENODEV; + + core->type = core->res->type; + core->id = of_alias_get_id(dev->of_node, "vpu_core"); + if (core->id < 0) { + dev_err(dev, "can't get vpu core id\n"); + return core->id; + } + dev_info(core->dev, "[%d] = %s\n", core->id, vpu_core_type_desc(core->type)); + ret = vpu_core_parse_dt(core, dev->of_node); + if (ret) + return ret; + + core->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(core->base)) + return PTR_ERR(core->base); + + if (!vpu_iface_check_codec(core)) { + dev_err(core->dev, "is not supported\n"); + return -EINVAL; + } + + ret = vpu_mbox_init(core); + if (ret) + return ret; + + iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL); + if (!iface) + return -ENOMEM; + + iface_data_size = vpu_iface_get_data_size(core); + if (iface_data_size) { + iface->priv = devm_kzalloc(dev, iface_data_size, GFP_KERNEL); + if (!iface->priv) + return -ENOMEM; + } + + ret = vpu_iface_init(core, iface, &core->rpc, core->fw.phys); + if (ret) { + dev_err(core->dev, "init iface fail, ret = %d\n", ret); + return ret; + } + + vpu_iface_config_system(core, vpu->res->mreg_base, vpu->base); + vpu_iface_set_log_buf(core, &core->log); + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret) { + pm_runtime_put_noidle(dev); + pm_runtime_set_suspended(dev); + goto err_runtime_disable; + } + + ret = vpu_core_register(dev->parent, core); + if (ret) + goto err_core_register; + core->parent = dev->parent; + + pm_runtime_put_sync(dev); + vpu_core_create_dbgfs_file(core); + + return 0; + +err_core_register: + pm_runtime_put_sync(dev); +err_runtime_disable: + pm_runtime_disable(dev); + + return ret; +} + +static int vpu_core_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct vpu_core *core = platform_get_drvdata(pdev); + int ret; + + vpu_core_remove_dbgfs_file(core); + ret = pm_runtime_get_sync(dev); + WARN_ON(ret < 0); + + vpu_core_shutdown(core); + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + + vpu_core_unregister(core->parent, core); + iounmap(core->fw.virt); + iounmap(core->rpc.virt); + mutex_destroy(&core->lock); + mutex_destroy(&core->cmd_lock); + + return 0; +} + +static int __maybe_unused vpu_core_runtime_resume(struct device *dev) +{ + struct vpu_core *core = dev_get_drvdata(dev); + + return vpu_mbox_request(core); +} + +static int __maybe_unused vpu_core_runtime_suspend(struct device *dev) +{ + struct vpu_core *core = dev_get_drvdata(dev); + + vpu_mbox_free(core); + return 0; +} + +static void vpu_core_cancel_work(struct vpu_core *core) +{ + struct vpu_inst *inst = NULL; + + cancel_work_sync(&core->msg_work); + cancel_delayed_work_sync(&core->msg_delayed_work); + + mutex_lock(&core->lock); + list_for_each_entry(inst, &core->instances, list) + cancel_work_sync(&inst->msg_work); + mutex_unlock(&core->lock); +} + +static void vpu_core_resume_work(struct vpu_core *core) +{ + struct vpu_inst *inst = NULL; + unsigned long delay = msecs_to_jiffies(10); + + queue_work(core->workqueue, &core->msg_work); + queue_delayed_work(core->workqueue, &core->msg_delayed_work, delay); + + mutex_lock(&core->lock); + list_for_each_entry(inst, &core->instances, list) + queue_work(inst->workqueue, &inst->msg_work); + mutex_unlock(&core->lock); +} + +static int __maybe_unused vpu_core_resume(struct device *dev) +{ + struct vpu_core *core = dev_get_drvdata(dev); + int ret = 0; + + if (!core->res->standalone) + return 0; + + mutex_lock(&core->lock); + pm_runtime_get_sync(dev); + vpu_core_get_vpu(core); + if (core->state != VPU_CORE_SNAPSHOT) + goto exit; + + if (!vpu_iface_get_power_state(core)) { + if (!list_empty(&core->instances)) { + ret = vpu_core_boot(core, false); + if (ret) { + dev_err(core->dev, "%s boot fail\n", __func__); + core->state = VPU_CORE_DEINIT; + goto exit; + } + } else { + core->state = VPU_CORE_DEINIT; + } + } else { + if (!list_empty(&core->instances)) { + ret = vpu_core_sw_reset(core); + if (ret) { + dev_err(core->dev, "%s sw_reset fail\n", __func__); + core->state = VPU_CORE_HANG; + goto exit; + } + } + core->state = VPU_CORE_ACTIVE; + } + +exit: + pm_runtime_put_sync(dev); + mutex_unlock(&core->lock); + + vpu_core_resume_work(core); + return ret; +} + +static int __maybe_unused vpu_core_suspend(struct device *dev) +{ + struct vpu_core *core = dev_get_drvdata(dev); + int ret = 0; + + if (!core->res->standalone) + return 0; + + mutex_lock(&core->lock); + if (core->state == VPU_CORE_ACTIVE) { + if (!list_empty(&core->instances)) { + ret = vpu_core_snapshot(core); + if (ret) { + mutex_unlock(&core->lock); + return ret; + } + } + + core->state = VPU_CORE_SNAPSHOT; + } + mutex_unlock(&core->lock); + + vpu_core_cancel_work(core); + + mutex_lock(&core->lock); + vpu_core_put_vpu(core); + mutex_unlock(&core->lock); + return ret; +} + +static const struct dev_pm_ops vpu_core_pm_ops = { + SET_RUNTIME_PM_OPS(vpu_core_runtime_suspend, vpu_core_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(vpu_core_suspend, vpu_core_resume) +}; + +static struct vpu_core_resources imx8q_enc = { + .type = VPU_CORE_TYPE_ENC, + .fwname = "vpu/vpu_fw_imx8_enc.bin", + .stride = 16, + .max_width = 1920, + .max_height = 1920, + .min_width = 64, + .min_height = 48, + .step_width = 2, + .step_height = 2, + .rpc_size = 0x80000, + .fwlog_size = 0x80000, + .act_size = 0xc0000, + .standalone = true, +}; + +static struct vpu_core_resources imx8q_dec = { + .type = VPU_CORE_TYPE_DEC, + .fwname = "vpu/vpu_fw_imx8_dec.bin", + .stride = 256, + .max_width = 8188, + .max_height = 8188, + .min_width = 16, + .min_height = 16, + .step_width = 1, + .step_height = 1, + .rpc_size = 0x80000, + .fwlog_size = 0x80000, + .standalone = true, +}; + +static const struct of_device_id vpu_core_dt_match[] = { + { .compatible = "nxp,imx8q-vpu-encoder", .data = &imx8q_enc }, + { .compatible = "nxp,imx8q-vpu-decoder", .data = &imx8q_dec }, + {} +}; +MODULE_DEVICE_TABLE(of, vpu_core_dt_match); + +static struct platform_driver amphion_vpu_core_driver = { + .probe = vpu_core_probe, + .remove = vpu_core_remove, + .driver = { + .name = "amphion-vpu-core", + .of_match_table = vpu_core_dt_match, + .pm = &vpu_core_pm_ops, + }, +}; + +int __init vpu_core_driver_init(void) +{ + return platform_driver_register(&hion_vpu_core_driver); +} + +void __exit vpu_core_driver_exit(void) +{ + platform_driver_unregister(&hion_vpu_core_driver); +} diff --git a/drivers/media/platform/amphion/vpu_core.h b/drivers/media/platform/amphion/vpu_core.h new file mode 100644 index 000000000000..00a662997da4 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_core.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_CORE_H +#define _AMPHION_VPU_CORE_H + +void csr_writel(struct vpu_core *core, u32 reg, u32 val); +u32 csr_readl(struct vpu_core *core, u32 reg); +int vpu_alloc_dma(struct vpu_core *core, struct vpu_buffer *buf); +void vpu_free_dma(struct vpu_buffer *buf); +struct vpu_inst *vpu_core_find_instance(struct vpu_core *core, u32 index); + +#endif diff --git a/drivers/media/platform/amphion/vpu_dbg.c b/drivers/media/platform/amphion/vpu_dbg.c new file mode 100644 index 000000000000..2e7e11101f99 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_dbg.c @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_helpers.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" + +struct print_buf_desc { + u32 start_h_phy; + u32 start_h_vir; + u32 start_m; + u32 bytes; + u32 read; + u32 write; + char buffer[0]; +}; + +static char *vb2_stat_name[] = { + [VB2_BUF_STATE_DEQUEUED] = "dequeued", + [VB2_BUF_STATE_IN_REQUEST] = "in_request", + [VB2_BUF_STATE_PREPARING] = "preparing", + [VB2_BUF_STATE_QUEUED] = "queued", + [VB2_BUF_STATE_ACTIVE] = "active", + [VB2_BUF_STATE_DONE] = "done", + [VB2_BUF_STATE_ERROR] = "error", +}; + +static char *vpu_stat_name[] = { + [VPU_BUF_STATE_IDLE] = "idle", + [VPU_BUF_STATE_INUSE] = "inuse", + [VPU_BUF_STATE_DECODED] = "decoded", + [VPU_BUF_STATE_READY] = "ready", + [VPU_BUF_STATE_SKIP] = "skip", + [VPU_BUF_STATE_ERROR] = "error", +}; + +static int vpu_dbg_instance(struct seq_file *s, void *data) +{ + struct vpu_inst *inst = s->private; + char str[128]; + int num; + struct vb2_queue *vq; + int i; + + num = scnprintf(str, sizeof(str), "[%s]\n", vpu_core_type_desc(inst->type)); + if (seq_write(s, str, num)) + return 0; + + num = scnprintf(str, sizeof(str), "tgig = %d,pid = %d\n", inst->tgid, inst->pid); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), "state = %d\n", inst->state); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), + "min_buffer_out = %d, min_buffer_cap = %d\n", + inst->min_buffer_out, inst->min_buffer_cap); + if (seq_write(s, str, num)) + return 0; + + + vq = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx); + num = scnprintf(str, sizeof(str), + "output (%2d, %2d): fmt = %c%c%c%c %d x %d, %d;", + vb2_is_streaming(vq), + vq->num_buffers, + inst->out_format.pixfmt, + inst->out_format.pixfmt >> 8, + inst->out_format.pixfmt >> 16, + inst->out_format.pixfmt >> 24, + inst->out_format.width, + inst->out_format.height, + vq->last_buffer_dequeued); + if (seq_write(s, str, num)) + return 0; + for (i = 0; i < inst->out_format.num_planes; i++) { + num = scnprintf(str, sizeof(str), " %d(%d)", + inst->out_format.sizeimage[i], + inst->out_format.bytesperline[i]); + if (seq_write(s, str, num)) + return 0; + } + if (seq_write(s, "\n", 1)) + return 0; + + vq = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); + num = scnprintf(str, sizeof(str), + "capture(%2d, %2d): fmt = %c%c%c%c %d x %d, %d;", + vb2_is_streaming(vq), + vq->num_buffers, + inst->cap_format.pixfmt, + inst->cap_format.pixfmt >> 8, + inst->cap_format.pixfmt >> 16, + inst->cap_format.pixfmt >> 24, + inst->cap_format.width, + inst->cap_format.height, + vq->last_buffer_dequeued); + if (seq_write(s, str, num)) + return 0; + for (i = 0; i < inst->cap_format.num_planes; i++) { + num = scnprintf(str, sizeof(str), " %d(%d)", + inst->cap_format.sizeimage[i], + inst->cap_format.bytesperline[i]); + if (seq_write(s, str, num)) + return 0; + } + if (seq_write(s, "\n", 1)) + return 0; + num = scnprintf(str, sizeof(str), "crop: (%d, %d) %d x %d\n", + inst->crop.left, + inst->crop.top, + inst->crop.width, + inst->crop.height); + if (seq_write(s, str, num)) + return 0; + + vq = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx); + for (i = 0; i < vq->num_buffers; i++) { + struct vb2_buffer *vb = vq->bufs[i]; + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf); + + if (vb->state == VB2_BUF_STATE_DEQUEUED) + continue; + num = scnprintf(str, sizeof(str), + "output [%2d] state = %10s, %8s\n", + i, vb2_stat_name[vb->state], + vpu_stat_name[vpu_buf->state]); + if (seq_write(s, str, num)) + return 0; + } + + vq = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); + for (i = 0; i < vq->num_buffers; i++) { + struct vb2_buffer *vb = vq->bufs[i]; + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_vb2_buffer *vpu_buf = to_vpu_vb2_buffer(vbuf); + + if (vb->state == VB2_BUF_STATE_DEQUEUED) + continue; + num = scnprintf(str, sizeof(str), + "capture[%2d] state = %10s, %8s\n", + i, vb2_stat_name[vb->state], + vpu_stat_name[vpu_buf->state]); + if (seq_write(s, str, num)) + return 0; + } + + num = scnprintf(str, sizeof(str), "sequence = %d\n", inst->sequence); + if (seq_write(s, str, num)) + return 0; + + if (inst->use_stream_buffer) { + num = scnprintf(str, sizeof(str), "stream_buffer = %d / %d, <%pad, 0x%x>\n", + vpu_helper_get_used_space(inst), + inst->stream_buffer.length, + &inst->stream_buffer.phys, + inst->stream_buffer.length); + if (seq_write(s, str, num)) + return 0; + } + num = scnprintf(str, sizeof(str), "kfifo len = 0x%x\n", kfifo_len(&inst->msg_fifo)); + if (seq_write(s, str, num)) + return 0; + + num = scnprintf(str, sizeof(str), "flow :\n"); + if (seq_write(s, str, num)) + return 0; + + mutex_lock(&inst->core->cmd_lock); + for (i = 0; i < ARRAY_SIZE(inst->flows); i++) { + u32 idx = (inst->flow_idx + i) % (ARRAY_SIZE(inst->flows)); + + if (!inst->flows[idx]) + continue; + num = scnprintf(str, sizeof(str), "\t[%s]0x%x\n", + inst->flows[idx] >= VPU_MSG_ID_NOOP ? "M" : "C", + inst->flows[idx]); + if (seq_write(s, str, num)) { + mutex_unlock(&inst->core->cmd_lock); + return 0; + } + } + mutex_unlock(&inst->core->cmd_lock); + + i = 0; + while (true) { + num = call_vop(inst, get_debug_info, str, sizeof(str), i++); + if (num <= 0) + break; + if (seq_write(s, str, num)) + return 0; + } + + return 0; +} + +static int vpu_dbg_core(struct seq_file *s, void *data) +{ + struct vpu_core *core = s->private; + struct vpu_shared_addr *iface = core->iface; + char str[128]; + int num; + + num = scnprintf(str, sizeof(str), "[%s]\n", vpu_core_type_desc(core->type)); + if (seq_write(s, str, num)) + return 0; + + num = scnprintf(str, sizeof(str), "boot_region = <%pad, 0x%x>\n", + &core->fw.phys, core->fw.length); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), "rpc_region = <%pad, 0x%x> used = 0x%x\n", + &core->rpc.phys, core->rpc.length, core->rpc.bytesused); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), "fwlog_region = <%pad, 0x%x>\n", + &core->log.phys, core->log.length); + if (seq_write(s, str, num)) + return 0; + + num = scnprintf(str, sizeof(str), "state = %d\n", core->state); + if (seq_write(s, str, num)) + return 0; + if (core->state == VPU_CORE_DEINIT) + return 0; + num = scnprintf(str, sizeof(str), "fw version = %d.%d.%d\n", + (core->fw_version >> 16) & 0xff, + (core->fw_version >> 8) & 0xff, + core->fw_version & 0xff); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), "instances = %d/%d (0x%02lx), %d\n", + hweight32(core->instance_mask), + core->supported_instance_count, + core->instance_mask, + core->request_count); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), "kfifo len = 0x%x\n", kfifo_len(&core->msg_fifo)); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), + "cmd_buf:[0x%x, 0x%x], wptr = 0x%x, rptr = 0x%x\n", + iface->cmd_desc->start, + iface->cmd_desc->end, + iface->cmd_desc->wptr, + iface->cmd_desc->rptr); + if (seq_write(s, str, num)) + return 0; + num = scnprintf(str, sizeof(str), + "msg_buf:[0x%x, 0x%x], wptr = 0x%x, rptr = 0x%x\n", + iface->msg_desc->start, + iface->msg_desc->end, + iface->msg_desc->wptr, + iface->msg_desc->rptr); + if (seq_write(s, str, num)) + return 0; + + return 0; +} + +static int vpu_dbg_fwlog(struct seq_file *s, void *data) +{ + struct vpu_core *core = s->private; + struct print_buf_desc *print_buf; + int length; + u32 rptr; + u32 wptr; + int ret = 0; + + if (!core->log.virt || core->state == VPU_CORE_DEINIT) + return 0; + + print_buf = core->log.virt; + rptr = print_buf->read; + wptr = print_buf->write; + + if (rptr == wptr) + return 0; + else if (rptr < wptr) + length = wptr - rptr; + else + length = print_buf->bytes + wptr - rptr; + + if (s->count + length >= s->size) { + s->count = s->size; + return 0; + } + + if (rptr + length >= print_buf->bytes) { + int num = print_buf->bytes - rptr; + + if (seq_write(s, print_buf->buffer + rptr, num)) + ret = -1; + length -= num; + rptr = 0; + } + + if (length) { + if (seq_write(s, print_buf->buffer + rptr, length)) + ret = -1; + rptr += length; + } + if (!ret) + print_buf->read = rptr; + + return 0; +} + +static int vpu_dbg_inst_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, vpu_dbg_instance, inode->i_private); +} + +static ssize_t vpu_dbg_inst_write(struct file *file, + const char __user *user_buf, size_t size, loff_t *ppos) +{ + struct seq_file *s = file->private_data; + struct vpu_inst *inst = s->private; + + vpu_session_debug(inst); + + return size; +} + +static ssize_t vpu_dbg_core_write(struct file *file, + const char __user *user_buf, size_t size, loff_t *ppos) +{ + struct seq_file *s = file->private_data; + struct vpu_core *core = s->private; + + pm_runtime_get_sync(core->dev); + mutex_lock(&core->lock); + if (core->state != VPU_CORE_DEINIT && !core->instance_mask) { + dev_info(core->dev, "reset\n"); + if (!vpu_core_sw_reset(core)) { + core->state = VPU_CORE_ACTIVE; + core->hang_mask = 0; + } + } + mutex_unlock(&core->lock); + pm_runtime_put_sync(core->dev); + + return size; +} + +static int vpu_dbg_core_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, vpu_dbg_core, inode->i_private); +} + +static int vpu_dbg_fwlog_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, vpu_dbg_fwlog, inode->i_private); +} + +static const struct file_operations vpu_dbg_inst_fops = { + .owner = THIS_MODULE, + .open = vpu_dbg_inst_open, + .release = single_release, + .read = seq_read, + .write = vpu_dbg_inst_write, +}; + +static const struct file_operations vpu_dbg_core_fops = { + .owner = THIS_MODULE, + .open = vpu_dbg_core_open, + .release = single_release, + .read = seq_read, + .write = vpu_dbg_core_write, +}; + +static const struct file_operations vpu_dbg_fwlog_fops = { + .owner = THIS_MODULE, + .open = vpu_dbg_fwlog_open, + .release = single_release, + .read = seq_read, +}; + +int vpu_inst_create_dbgfs_file(struct vpu_inst *inst) +{ + struct vpu_dev *vpu; + char name[64]; + + if (!inst || !inst->core || !inst->core->vpu) + return -EINVAL; + + vpu = inst->core->vpu; + if (!vpu->debugfs) + return -EINVAL; + + if (inst->debugfs) + return 0; + + scnprintf(name, sizeof(name), "instance.%d.%d", + inst->core->id, inst->id); + inst->debugfs = debugfs_create_file((const char *)name, + VERIFY_OCTAL_PERMISSIONS(0644), + vpu->debugfs, + inst, + &vpu_dbg_inst_fops); + if (!inst->debugfs) { + dev_err(inst->dev, "vpu create debugfs %s fail\n", name); + return -EINVAL; + } + + return 0; +} + +int vpu_inst_remove_dbgfs_file(struct vpu_inst *inst) +{ + if (!inst) + return 0; + + debugfs_remove(inst->debugfs); + inst->debugfs = NULL; + + return 0; +} + +int vpu_core_create_dbgfs_file(struct vpu_core *core) +{ + struct vpu_dev *vpu; + char name[64]; + + if (!core || !core->vpu) + return -EINVAL; + + vpu = core->vpu; + if (!vpu->debugfs) + return -EINVAL; + + if (!core->debugfs) { + scnprintf(name, sizeof(name), "core.%d", core->id); + core->debugfs = debugfs_create_file((const char *)name, + VERIFY_OCTAL_PERMISSIONS(0644), + vpu->debugfs, + core, + &vpu_dbg_core_fops); + if (!core->debugfs) { + dev_err(core->dev, "vpu create debugfs %s fail\n", name); + return -EINVAL; + } + } + if (!core->debugfs_fwlog) { + scnprintf(name, sizeof(name), "fwlog.%d", core->id); + core->debugfs_fwlog = debugfs_create_file((const char *)name, + VERIFY_OCTAL_PERMISSIONS(0444), + vpu->debugfs, + core, + &vpu_dbg_fwlog_fops); + if (!core->debugfs_fwlog) { + dev_err(core->dev, "vpu create debugfs %s fail\n", name); + return -EINVAL; + } + } + + return 0; +} + +int vpu_core_remove_dbgfs_file(struct vpu_core *core) +{ + if (!core) + return 0; + debugfs_remove(core->debugfs); + core->debugfs = NULL; + debugfs_remove(core->debugfs_fwlog); + core->debugfs_fwlog = NULL; + + return 0; +} + +void vpu_inst_record_flow(struct vpu_inst *inst, u32 flow) +{ + if (!inst) + return; + + inst->flows[inst->flow_idx] = flow; + inst->flow_idx = (inst->flow_idx + 1) % (ARRAY_SIZE(inst->flows)); +} diff --git a/drivers/media/platform/amphion/vpu_rpc.c b/drivers/media/platform/amphion/vpu_rpc.c new file mode 100644 index 000000000000..7b5e9177e010 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_rpc.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_rpc.h" +#include "vpu_imx8q.h" +#include "vpu_windsor.h" +#include "vpu_malone.h" + +u32 vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->check_memory_region) + return VPU_CORE_MEMORY_INVALID; + + return ops->check_memory_region(core->fw.phys, addr, size); +} + +static u32 vpu_rpc_check_buffer_space(struct vpu_rpc_buffer_desc *desc, bool write) +{ + u32 ptr1; + u32 ptr2; + u32 size; + + WARN_ON(!desc); + + size = desc->end - desc->start; + if (write) { + ptr1 = desc->wptr; + ptr2 = desc->rptr; + } else { + ptr1 = desc->rptr; + ptr2 = desc->wptr; + } + + if (ptr1 == ptr2) { + if (!write) + return 0; + else + return size; + } + + return (ptr2 + size - ptr1) % size; +} + +static int vpu_rpc_send_cmd_buf(struct vpu_shared_addr *shared, + struct vpu_rpc_event *cmd) +{ + struct vpu_rpc_buffer_desc *desc; + u32 space = 0; + u32 *data; + u32 wptr; + u32 i; + + WARN_ON(!shared || !shared->cmd_mem_vir || !cmd); + + desc = shared->cmd_desc; + space = vpu_rpc_check_buffer_space(desc, true); + if (space < (((cmd->hdr.num + 1) << 2) + 16)) { + pr_err("Cmd Buffer is no space for [%d] %d\n", + cmd->hdr.index, cmd->hdr.id); + return -EINVAL; + } + wptr = desc->wptr; + data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start); + *data = 0; + *data |= ((cmd->hdr.index & 0xff) << 24); + *data |= ((cmd->hdr.num & 0xff) << 16); + *data |= (cmd->hdr.id & 0x3fff); + wptr += 4; + data++; + if (wptr >= desc->end) { + wptr = desc->start; + data = shared->cmd_mem_vir; + } + + for (i = 0; i < cmd->hdr.num; i++) { + *data = cmd->data[i]; + wptr += 4; + data++; + if (wptr >= desc->end) { + wptr = desc->start; + data = shared->cmd_mem_vir; + } + } + + /*update wptr after data is written*/ + mb(); + desc->wptr = wptr; + + return 0; +} + +static bool vpu_rpc_check_msg(struct vpu_shared_addr *shared) +{ + struct vpu_rpc_buffer_desc *desc; + u32 space = 0; + u32 msgword; + u32 msgnum; + + WARN_ON(!shared || !shared->msg_desc); + + desc = shared->msg_desc; + space = vpu_rpc_check_buffer_space(desc, 0); + space = (space >> 2); + + if (space) { + msgword = *(u32 *)(shared->msg_mem_vir + desc->rptr - desc->start); + msgnum = (msgword & 0xff0000) >> 16; + if (msgnum <= space) + return true; + } + + return false; +} + +static int vpu_rpc_receive_msg_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *msg) +{ + struct vpu_rpc_buffer_desc *desc; + u32 *data; + u32 msgword; + u32 rptr; + u32 i; + + WARN_ON(!shared || !shared->msg_desc || !msg); + + if (!vpu_rpc_check_msg(shared)) + return -EINVAL; + + desc = shared->msg_desc; + data = (u32 *)(shared->msg_mem_vir + desc->rptr - desc->start); + rptr = desc->rptr; + msgword = *data; + data++; + rptr += 4; + if (rptr >= desc->end) { + rptr = desc->start; + data = shared->msg_mem_vir; + } + + msg->hdr.index = (msgword >> 24) & 0xff; + msg->hdr.num = (msgword >> 16) & 0xff; + msg->hdr.id = msgword & 0x3fff; + + if (msg->hdr.num > ARRAY_SIZE(msg->data)) { + pr_err("msg(%d) data length(%d) is out of range\n", + msg->hdr.id, msg->hdr.num); + return -EINVAL; + } + + for (i = 0; i < msg->hdr.num; i++) { + msg->data[i] = *data; + data++; + rptr += 4; + if (rptr >= desc->end) { + rptr = desc->start; + data = shared->msg_mem_vir; + } + } + + /*update rptr after data is read*/ + mb(); + desc->rptr = rptr; + + return 0; +} + +struct vpu_iface_ops imx8q_rpc_ops[] = { + [VPU_CORE_TYPE_ENC] = { + .check_codec = vpu_imx8q_check_codec, + .check_fmt = vpu_imx8q_check_fmt, + .boot_core = vpu_imx8q_boot_core, + .get_power_state = vpu_imx8q_get_power_state, + .on_firmware_loaded = vpu_imx8q_on_firmware_loaded, + .get_data_size = vpu_windsor_get_data_size, + .check_memory_region = vpu_imx8q_check_memory_region, + .init_rpc = vpu_windsor_init_rpc, + .set_log_buf = vpu_windsor_set_log_buf, + .set_system_cfg = vpu_windsor_set_system_cfg, + .get_version = vpu_windsor_get_version, + .send_cmd_buf = vpu_rpc_send_cmd_buf, + .receive_msg_buf = vpu_rpc_receive_msg_buf, + .pack_cmd = vpu_windsor_pack_cmd, + .convert_msg_id = vpu_windsor_convert_msg_id, + .unpack_msg_data = vpu_windsor_unpack_msg_data, + .config_memory_resource = vpu_windsor_config_memory_resource, + .get_stream_buffer_size = vpu_windsor_get_stream_buffer_size, + .config_stream_buffer = vpu_windsor_config_stream_buffer, + .get_stream_buffer_desc = vpu_windsor_get_stream_buffer_desc, + .update_stream_buffer = vpu_windsor_update_stream_buffer, + .set_encode_params = vpu_windsor_set_encode_params, + .input_frame = vpu_windsor_input_frame, + .get_max_instance_count = vpu_windsor_get_max_instance_count, + }, + [VPU_CORE_TYPE_DEC] = { + .check_codec = vpu_imx8q_check_codec, + .check_fmt = vpu_imx8q_check_fmt, + .boot_core = vpu_imx8q_boot_core, + .get_power_state = vpu_imx8q_get_power_state, + .on_firmware_loaded = vpu_imx8q_on_firmware_loaded, + .get_data_size = vpu_malone_get_data_size, + .check_memory_region = vpu_imx8q_check_memory_region, + .init_rpc = vpu_malone_init_rpc, + .set_log_buf = vpu_malone_set_log_buf, + .set_system_cfg = vpu_malone_set_system_cfg, + .get_version = vpu_malone_get_version, + .send_cmd_buf = vpu_rpc_send_cmd_buf, + .receive_msg_buf = vpu_rpc_receive_msg_buf, + .get_stream_buffer_size = vpu_malone_get_stream_buffer_size, + .config_stream_buffer = vpu_malone_config_stream_buffer, + .set_decode_params = vpu_malone_set_decode_params, + .pack_cmd = vpu_malone_pack_cmd, + .convert_msg_id = vpu_malone_convert_msg_id, + .unpack_msg_data = vpu_malone_unpack_msg_data, + .get_stream_buffer_desc = vpu_malone_get_stream_buffer_desc, + .update_stream_buffer = vpu_malone_update_stream_buffer, + .add_scode = vpu_malone_add_scode, + .input_frame = vpu_malone_input_frame, + .pre_send_cmd = vpu_malone_pre_cmd, + .post_send_cmd = vpu_malone_post_cmd, + .init_instance = vpu_malone_init_instance, + .get_max_instance_count = vpu_malone_get_max_instance_count, + }, +}; + + +static struct vpu_iface_ops *vpu_get_iface(struct vpu_dev *vpu, enum vpu_core_type type) +{ + struct vpu_iface_ops *rpc_ops = NULL; + u32 size = 0; + + WARN_ON(!vpu || !vpu->res); + + switch (vpu->res->plat_type) { + case IMX8QXP: + case IMX8QM: + rpc_ops = imx8q_rpc_ops; + size = ARRAY_SIZE(imx8q_rpc_ops); + break; + default: + return NULL; + } + + if (type >= size) + return NULL; + + return &rpc_ops[type]; +} + +struct vpu_iface_ops *vpu_core_get_iface(struct vpu_core *core) +{ + WARN_ON(!core || !core->vpu); + + return vpu_get_iface(core->vpu, core->type); +} + +struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst) +{ + WARN_ON(!inst || !inst->vpu); + + if (inst->core) + return vpu_core_get_iface(inst->core); + + return vpu_get_iface(inst->vpu, inst->type); +} diff --git a/drivers/media/platform/amphion/vpu_rpc.h b/drivers/media/platform/amphion/vpu_rpc.h new file mode 100644 index 000000000000..abe998e5a5be --- /dev/null +++ b/drivers/media/platform/amphion/vpu_rpc.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_RPC_H +#define _AMPHION_VPU_RPC_H + +#include +#include "vpu_codec.h" + +struct vpu_rpc_buffer_desc { + u32 wptr; + u32 rptr; + u32 start; + u32 end; +}; + +struct vpu_shared_addr { + void *iface; + struct vpu_rpc_buffer_desc *cmd_desc; + void *cmd_mem_vir; + struct vpu_rpc_buffer_desc *msg_desc; + void *msg_mem_vir; + + unsigned long boot_addr; + struct vpu_core *core; + void *priv; +}; + +struct vpu_rpc_event_header { + u32 index; + u32 id; + u32 num; +}; + +struct vpu_rpc_event { + struct vpu_rpc_event_header hdr; + u32 data[128]; +}; + +struct vpu_iface_ops { + bool (*check_codec)(enum vpu_core_type type); + bool (*check_fmt)(enum vpu_core_type type, u32 pixelfmt); + u32 (*get_data_size)(void); + u32 (*check_memory_region)(dma_addr_t base, dma_addr_t addr, u32 size); + int (*boot_core)(struct vpu_core *core); + int (*shutdown_core)(struct vpu_core *core); + int (*restore_core)(struct vpu_core *core); + int (*get_power_state)(struct vpu_core *core); + int (*on_firmware_loaded)(struct vpu_core *core); + void (*init_rpc)(struct vpu_shared_addr *shared, + struct vpu_buffer *rpc, dma_addr_t boot_addr); + void (*set_log_buf)(struct vpu_shared_addr *shared, + struct vpu_buffer *log); + void (*set_system_cfg)(struct vpu_shared_addr *shared, + u32 regs_base, void __iomem *regs, u32 index); + void (*set_stream_cfg)(struct vpu_shared_addr *shared, u32 index); + u32 (*get_version)(struct vpu_shared_addr *shared); + u32 (*get_max_instance_count)(struct vpu_shared_addr *shared); + int (*get_stream_buffer_size)(struct vpu_shared_addr *shared); + int (*send_cmd_buf)(struct vpu_shared_addr *shared, + struct vpu_rpc_event *cmd); + int (*receive_msg_buf)(struct vpu_shared_addr *shared, + struct vpu_rpc_event *msg); + int (*pack_cmd)(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data); + int (*convert_msg_id)(u32 msg_id); + int (*unpack_msg_data)(struct vpu_rpc_event *pkt, void *data); + int (*input_frame)(struct vpu_shared_addr *shared, + struct vpu_inst *inst, struct vb2_buffer *vb); + int (*config_memory_resource)(struct vpu_shared_addr *shared, + u32 instance, + u32 type, + u32 index, + struct vpu_buffer *buf); + int (*config_stream_buffer)(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_buffer *buf); + int (*update_stream_buffer)(struct vpu_shared_addr *shared, + u32 instance, u32 ptr, bool write); + int (*get_stream_buffer_desc)(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_rpc_buffer_desc *desc); + int (*set_encode_params)(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_encode_params *params, u32 update); + int (*set_decode_params)(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_decode_params *params, u32 update); + int (*add_scode)(struct vpu_shared_addr *shared, + u32 instance, + struct vpu_buffer *stream_buffer, + u32 pixelformat, + u32 scode_type); + int (*pre_send_cmd)(struct vpu_shared_addr *shared, u32 instance); + int (*post_send_cmd)(struct vpu_shared_addr *shared, u32 instance); + int (*init_instance)(struct vpu_shared_addr *shared, u32 instance); +}; + +enum { + VPU_CORE_MEMORY_INVALID = 0, + VPU_CORE_MEMORY_CACHED, + VPU_CORE_MEMORY_UNCACHED +}; + +struct vpu_rpc_region_t { + dma_addr_t start; + dma_addr_t end; + dma_addr_t type; +}; + +struct vpu_iface_ops *vpu_core_get_iface(struct vpu_core *core); +struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst); +u32 vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size); + +static inline bool vpu_iface_check_codec(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (ops && ops->check_codec) + return ops->check_codec(core->type); + + return true; +} + +static inline bool vpu_iface_check_format(struct vpu_inst *inst, u32 pixelfmt) +{ + struct vpu_iface_ops *ops = vpu_inst_get_iface(inst); + + if (ops && ops->check_fmt) + return ops->check_fmt(inst->type, pixelfmt); + + return true; +} + +static inline int vpu_iface_boot_core(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (ops && ops->boot_core) + return ops->boot_core(core); + return 0; +} + +static inline int vpu_iface_get_power_state(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (ops && ops->get_power_state) + return ops->get_power_state(core); + return 1; +} + +static inline int vpu_iface_shutdown_core(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (ops && ops->shutdown_core) + return ops->shutdown_core(core); + return 0; +} + +static inline int vpu_iface_restore_core(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (ops && ops->restore_core) + return ops->restore_core(core); + return 0; +} + +static inline int vpu_iface_on_firmware_loaded(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (ops && ops->on_firmware_loaded) + return ops->on_firmware_loaded(core); + + return 0; +} + +static inline u32 vpu_iface_get_data_size(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->get_data_size) + return 0; + + return ops->get_data_size(); +} + +static inline int vpu_iface_init(struct vpu_core *core, + struct vpu_shared_addr *shared, + struct vpu_buffer *rpc, + dma_addr_t boot_addr) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->init_rpc) + return -EINVAL; + + ops->init_rpc(shared, rpc, boot_addr); + core->iface = shared; + shared->core = core; + if (rpc->bytesused > rpc->length) + return -ENOSPC; + return 0; +} + +static inline int vpu_iface_set_log_buf(struct vpu_core *core, + struct vpu_buffer *log) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops) + return -EINVAL; + + if (ops->set_log_buf) + ops->set_log_buf(core->iface, log); + + return 0; +} + +static inline int vpu_iface_config_system(struct vpu_core *core, + u32 regs_base, void __iomem *regs) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops) + return -EINVAL; + if (ops->set_system_cfg) + ops->set_system_cfg(core->iface, regs_base, regs, core->id); + + return 0; +} + +static inline int vpu_iface_get_stream_buffer_size(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->get_stream_buffer_size) + return 0; + + return ops->get_stream_buffer_size(core->iface); +} + +static inline int vpu_iface_config_stream(struct vpu_inst *inst) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops) + return -EINVAL; + if (ops->set_stream_cfg) + ops->set_stream_cfg(inst->core->iface, inst->id); + return 0; +} + +static inline int vpu_iface_send_cmd(struct vpu_core *core, struct vpu_rpc_event *cmd) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->send_cmd_buf) + return -EINVAL; + + return ops->send_cmd_buf(core->iface, cmd); +} + +static inline int vpu_iface_receive_msg(struct vpu_core *core, struct vpu_rpc_event *msg) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->receive_msg_buf) + return -EINVAL; + + return ops->receive_msg_buf(core->iface, msg); +} + +static inline int vpu_iface_pack_cmd(struct vpu_core *core, + struct vpu_rpc_event *pkt, + u32 index, u32 id, void *data) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->pack_cmd) + return -EINVAL; + return ops->pack_cmd(pkt, index, id, data); +} + +static inline int vpu_iface_convert_msg_id(struct vpu_core *core, u32 msg_id) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->convert_msg_id) + return -EINVAL; + + return ops->convert_msg_id(msg_id); +} + +static inline int vpu_iface_unpack_msg_data(struct vpu_core *core, + struct vpu_rpc_event *pkt, void *data) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->unpack_msg_data) + return -EINVAL; + + return ops->unpack_msg_data(pkt, data); +} + +static inline int vpu_iface_input_frame(struct vpu_inst *inst, + struct vb2_buffer *vb) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + if (!ops || !ops->input_frame) + return -EINVAL; + + return ops->input_frame(inst->core->iface, inst, vb); +} + +static inline int vpu_iface_config_memory_resource(struct vpu_inst *inst, + u32 type, u32 index, struct vpu_buffer *buf) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->config_memory_resource) + return -EINVAL; + + return ops->config_memory_resource(inst->core->iface, + inst->id, + type, index, buf); +} + +static inline int vpu_iface_config_stream_buffer(struct vpu_inst *inst, + struct vpu_buffer *buf) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->config_stream_buffer) + return -EINVAL; + + return ops->config_stream_buffer(inst->core->iface, inst->id, buf); +} + +static inline int vpu_iface_update_stream_buffer(struct vpu_inst *inst, + u32 ptr, bool write) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->update_stream_buffer) + return -EINVAL; + + return ops->update_stream_buffer(inst->core->iface, inst->id, ptr, write); +} + +static inline int vpu_iface_get_stream_buffer_desc(struct vpu_inst *inst, + struct vpu_rpc_buffer_desc *desc) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->get_stream_buffer_desc) + return -EINVAL; + + if (!desc) + return 0; + + return ops->get_stream_buffer_desc(inst->core->iface, inst->id, desc); +} + +static inline u32 vpu_iface_get_version(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->get_version) + return 0; + + return ops->get_version(core->iface); +} + +static inline u32 vpu_iface_get_max_instance_count(struct vpu_core *core) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(core); + + if (!ops || !ops->get_max_instance_count) + return 0; + + return ops->get_max_instance_count(core->iface); +} + +static inline int vpu_iface_set_encode_params(struct vpu_inst *inst, + struct vpu_encode_params *params, u32 update) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->set_encode_params) + return -EINVAL; + + return ops->set_encode_params(inst->core->iface, inst->id, params, update); +} + +static inline int vpu_iface_set_decode_params(struct vpu_inst *inst, + struct vpu_decode_params *params, u32 update) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->set_decode_params) + return -EINVAL; + + return ops->set_decode_params(inst->core->iface, inst->id, params, update); +} + +static inline int vpu_iface_add_scode(struct vpu_inst *inst, u32 scode_type) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (!ops || !ops->add_scode) + return -EINVAL; + + return ops->add_scode(inst->core->iface, inst->id, + &inst->stream_buffer, + inst->out_format.pixfmt, + scode_type); +} + +static inline int vpu_iface_pre_send_cmd(struct vpu_inst *inst) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (ops && ops->pre_send_cmd) + return ops->pre_send_cmd(inst->core->iface, inst->id); + return 0; +} + +static inline int vpu_iface_post_send_cmd(struct vpu_inst *inst) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (ops && ops->post_send_cmd) + return ops->post_send_cmd(inst->core->iface, inst->id); + return 0; +} + +static inline int vpu_iface_init_instance(struct vpu_inst *inst) +{ + struct vpu_iface_ops *ops = vpu_core_get_iface(inst->core); + + WARN_ON(inst->id < 0); + if (ops && ops->init_instance) + return ops->init_instance(inst->core->iface, inst->id); + + return 0; +} + +#endif From patchwork Tue Nov 30 09:48:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 519529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54BDAC4332F for ; Tue, 30 Nov 2021 09:49:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240465AbhK3Jwk (ORCPT ); Tue, 30 Nov 2021 04:52:40 -0500 Received: from mail-eopbgr30067.outbound.protection.outlook.com ([40.107.3.67]:9460 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240473AbhK3JwU (ORCPT ); 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Tue, 30 Nov 2021 09:48:58 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v13 05/13] media: amphion: implement vpu core communication based on mailbox Date: Tue, 30 Nov 2021 17:48:06 +0800 Message-Id: X-Mailer: git-send-email 2.33.0 In-Reply-To: References: X-ClientProxiedBy: SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; Tue, 30 Nov 2021 09:48:54 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fe048e27-75d1-4a3f-3706-08d9b3e6a11d X-MS-TrafficTypeDiagnostic: AM6PR0402MB3592: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:94; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng Reported-by: kernel test robot --- drivers/media/platform/amphion/vpu_cmds.c | 439 ++++++++++++++++++++++ drivers/media/platform/amphion/vpu_cmds.h | 25 ++ drivers/media/platform/amphion/vpu_mbox.c | 124 ++++++ drivers/media/platform/amphion/vpu_mbox.h | 16 + drivers/media/platform/amphion/vpu_msgs.c | 414 ++++++++++++++++++++ drivers/media/platform/amphion/vpu_msgs.h | 14 + 6 files changed, 1032 insertions(+) create mode 100644 drivers/media/platform/amphion/vpu_cmds.c create mode 100644 drivers/media/platform/amphion/vpu_cmds.h create mode 100644 drivers/media/platform/amphion/vpu_mbox.c create mode 100644 drivers/media/platform/amphion/vpu_mbox.h create mode 100644 drivers/media/platform/amphion/vpu_msgs.c create mode 100644 drivers/media/platform/amphion/vpu_msgs.h diff --git a/drivers/media/platform/amphion/vpu_cmds.c b/drivers/media/platform/amphion/vpu_cmds.c new file mode 100644 index 000000000000..3cfe08f9c19d --- /dev/null +++ b/drivers/media/platform/amphion/vpu_cmds.c @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" +#include "vpu_mbox.h" + +struct vpu_cmd_request { + u32 request; + u32 response; + u32 handled; +}; + +struct vpu_cmd_t { + struct list_head list; + u32 id; + struct vpu_cmd_request *request; + struct vpu_rpc_event *pkt; + unsigned long key; +}; + +static struct vpu_cmd_request vpu_cmd_requests[] = { + { + .request = VPU_CMD_ID_CONFIGURE_CODEC, + .response = VPU_MSG_ID_MEM_REQUEST, + .handled = 1, + }, + { + .request = VPU_CMD_ID_START, + .response = VPU_MSG_ID_START_DONE, + .handled = 0, + }, + { + .request = VPU_CMD_ID_STOP, + .response = VPU_MSG_ID_STOP_DONE, + .handled = 0, + }, + { + .request = VPU_CMD_ID_ABORT, + .response = VPU_MSG_ID_ABORT_DONE, + .handled = 0, + }, + { + .request = VPU_CMD_ID_RST_BUF, + .response = VPU_MSG_ID_BUF_RST, + .handled = 1, + }, +}; + +static int vpu_cmd_send(struct vpu_core *core, struct vpu_rpc_event *pkt) +{ + int ret = 0; + + WARN_ON(!core || !pkt); + + ret = vpu_iface_send_cmd(core, pkt); + if (ret) + return ret; + + /*write cmd data to cmd buffer before trigger a cmd interrupt*/ + mb(); + vpu_mbox_send_type(core, COMMAND); + + return ret; +} + +static struct vpu_cmd_t *vpu_alloc_cmd(struct vpu_inst *inst, u32 id, void *data) +{ + struct vpu_cmd_t *cmd; + int i; + int ret; + + cmd = vzalloc(sizeof(*cmd)); + if (!cmd) + return NULL; + + cmd->pkt = vzalloc(sizeof(*cmd->pkt)); + if (!cmd->pkt) { + vfree(cmd); + return NULL; + } + + cmd->id = id; + ret = vpu_iface_pack_cmd(inst->core, cmd->pkt, inst->id, id, data); + if (ret) { + dev_err(inst->dev, "iface pack cmd(%d) fail\n", id); + vfree(cmd->pkt); + vfree(cmd); + return NULL; + } + for (i = 0; i < ARRAY_SIZE(vpu_cmd_requests); i++) { + if (vpu_cmd_requests[i].request == id) { + cmd->request = &vpu_cmd_requests[i]; + break; + } + } + + return cmd; +} + +static void vpu_free_cmd(struct vpu_cmd_t *cmd) +{ + if (!cmd) + return; + if (cmd->pkt) + vfree(cmd->pkt); + vfree(cmd); +} + +static int vpu_session_process_cmd(struct vpu_inst *inst, struct vpu_cmd_t *cmd) +{ + int ret; + + if (!inst || !cmd || !cmd->pkt) + return -EINVAL; + + dev_dbg(inst->dev, "[%d]send cmd(0x%x)\n", inst->id, cmd->id); + vpu_iface_pre_send_cmd(inst); + ret = vpu_cmd_send(inst->core, cmd->pkt); + if (!ret) { + vpu_iface_post_send_cmd(inst); + vpu_inst_record_flow(inst, cmd->id); + } else + dev_err(inst->dev, "[%d] iface send cmd(0x%x) fail\n", inst->id, cmd->id); + + return ret; +} + +static void vpu_process_cmd_request(struct vpu_inst *inst) +{ + struct vpu_cmd_t *cmd; + struct vpu_cmd_t *tmp; + + if (!inst || inst->pending) + return; + + list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) { + list_del_init(&cmd->list); + if (vpu_session_process_cmd(inst, cmd)) + dev_err(inst->dev, "[%d] process cmd(%d) fail\n", inst->id, cmd->id); + if (cmd->request) { + inst->pending = (void *)cmd; + break; + } + vpu_free_cmd(cmd); + } +} + +static int vpu_request_cmd(struct vpu_inst *inst, u32 id, void *data, + unsigned long *key, int *sync) +{ + struct vpu_core *core; + struct vpu_cmd_t *cmd; + + if (!inst || !inst->core) + return -EINVAL; + + core = inst->core; + cmd = vpu_alloc_cmd(inst, id, data); + if (!cmd) + return -ENOMEM; + + mutex_lock(&core->cmd_lock); + cmd->key = core->cmd_seq++; + if (key) + *key = cmd->key; + if (sync) + *sync = cmd->request ? true : false; + list_add_tail(&cmd->list, &inst->cmd_q); + vpu_process_cmd_request(inst); + mutex_unlock(&core->cmd_lock); + + return 0; +} + +static void vpu_clear_pending(struct vpu_inst *inst) +{ + if (!inst || !inst->pending) + return; + + vpu_free_cmd(inst->pending); + wake_up_all(&inst->core->ack_wq); + inst->pending = NULL; +} + +static bool vpu_check_response(struct vpu_cmd_t *cmd, u32 response, u32 handled) +{ + struct vpu_cmd_request *request; + + if (!cmd || !cmd->request) + return false; + + request = cmd->request; + if (request->response != response) + return false; + if (request->handled != handled) + return false; + + return true; +} + +int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled) +{ + struct vpu_core *core; + + if (!inst || !inst->core) + return -EINVAL; + + core = inst->core; + mutex_lock(&core->cmd_lock); + if (vpu_check_response(inst->pending, response, handled)) + vpu_clear_pending(inst); + + vpu_process_cmd_request(inst); + mutex_unlock(&core->cmd_lock); + + return 0; +} + +void vpu_clear_request(struct vpu_inst *inst) +{ + struct vpu_cmd_t *cmd; + struct vpu_cmd_t *tmp; + + mutex_lock(&inst->core->cmd_lock); + if (inst->pending) + vpu_clear_pending(inst); + + list_for_each_entry_safe(cmd, tmp, &inst->cmd_q, list) { + list_del_init(&cmd->list); + vpu_free_cmd(cmd); + } + mutex_unlock(&inst->core->cmd_lock); +} + +static bool check_is_responsed(struct vpu_inst *inst, unsigned long key) +{ + struct vpu_core *core = inst->core; + struct vpu_cmd_t *cmd; + bool flag = true; + + mutex_lock(&core->cmd_lock); + cmd = inst->pending; + if (cmd && key == cmd->key) { + flag = false; + goto exit; + } + list_for_each_entry(cmd, &inst->cmd_q, list) { + if (key == cmd->key) { + flag = false; + break; + } + } +exit: + mutex_unlock(&core->cmd_lock); + + return flag; +} + +static int sync_session_response(struct vpu_inst *inst, unsigned long key) +{ + struct vpu_core *core; + + if (!inst || !inst->core) + return -EINVAL; + + core = inst->core; + + call_vop(inst, wait_prepare); + wait_event_timeout(core->ack_wq, + check_is_responsed(inst, key), + VPU_TIMEOUT); + call_vop(inst, wait_finish); + + if (!check_is_responsed(inst, key)) { + dev_err(inst->dev, "[%d] sync session timeout\n", inst->id); + set_bit(inst->id, &core->hang_mask); + mutex_lock(&inst->core->cmd_lock); + vpu_clear_pending(inst); + mutex_unlock(&inst->core->cmd_lock); + return -EINVAL; + } + + return 0; +} + +static int vpu_session_send_cmd(struct vpu_inst *inst, u32 id, void *data) +{ + unsigned long key; + int sync = false; + int ret = -EINVAL; + + WARN_ON(!inst || !inst->core || inst->id < 0); + + ret = vpu_request_cmd(inst, id, data, &key, &sync); + if (!ret && sync) + ret = sync_session_response(inst, key); + + if (ret) + dev_err(inst->dev, "[%d] send cmd(0x%x) fail\n", inst->id, id); + + return ret; +} + +int vpu_session_configure_codec(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_CONFIGURE_CODEC, NULL); +} + +int vpu_session_start(struct vpu_inst *inst) +{ + vpu_trace(inst->dev, "[%d]\n", inst->id); + + return vpu_session_send_cmd(inst, VPU_CMD_ID_START, NULL); +} + +int vpu_session_stop(struct vpu_inst *inst) +{ + int ret; + + vpu_trace(inst->dev, "[%d]\n", inst->id); + + ret = vpu_session_send_cmd(inst, VPU_CMD_ID_STOP, NULL); + /* workaround for a firmware bug, + * if the next command is too close after stop cmd, + * the firmware may enter wfi wrongly. + */ + usleep_range(3000, 5000); + return ret; +} + +int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_FRAME_ENCODE, ×tamp); +} + +int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_ALLOC, fs); +} + +int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_FS_RELEASE, fs); +} + +int vpu_session_abort(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_ABORT, NULL); +} + +int vpu_session_rst_buf(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_RST_BUF, NULL); +} + +int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_TIMESTAMP, info); +} + +int vpu_session_update_parameters(struct vpu_inst *inst, void *arg) +{ + if (inst->type & VPU_CORE_TYPE_DEC) + vpu_iface_set_decode_params(inst, arg, 1); + else + vpu_iface_set_encode_params(inst, arg, 1); + + return vpu_session_send_cmd(inst, VPU_CMD_ID_UPDATE_PARAMETER, arg); +} + +int vpu_session_debug(struct vpu_inst *inst) +{ + return vpu_session_send_cmd(inst, VPU_CMD_ID_DEBUG, NULL); +} + +int vpu_core_snapshot(struct vpu_core *core) +{ + struct vpu_inst *inst; + int ret; + + WARN_ON(!core || list_empty(&core->instances)); + + inst = list_first_entry(&core->instances, struct vpu_inst, list); + + reinit_completion(&core->cmp); + ret = vpu_session_send_cmd(inst, VPU_CMD_ID_SNAPSHOT, NULL); + if (ret) + return ret; + ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT); + if (!ret) { + dev_err(core->dev, "snapshot timeout\n"); + return -EINVAL; + } + + return 0; +} + +int vpu_core_sw_reset(struct vpu_core *core) +{ + struct vpu_rpc_event pkt; + int ret; + + WARN_ON(!core); + + memset(&pkt, 0, sizeof(pkt)); + vpu_iface_pack_cmd(core, &pkt, 0, VPU_CMD_ID_FIRM_RESET, NULL); + + reinit_completion(&core->cmp); + mutex_lock(&core->cmd_lock); + ret = vpu_cmd_send(core, &pkt); + mutex_unlock(&core->cmd_lock); + if (ret) + return ret; + ret = wait_for_completion_timeout(&core->cmp, VPU_TIMEOUT); + if (!ret) { + dev_err(core->dev, "sw reset timeout\n"); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_cmds.h b/drivers/media/platform/amphion/vpu_cmds.h new file mode 100644 index 000000000000..bc538d277bc9 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_cmds.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_CMDS_H +#define _AMPHION_VPU_CMDS_H + +int vpu_session_configure_codec(struct vpu_inst *inst); +int vpu_session_start(struct vpu_inst *inst); +int vpu_session_stop(struct vpu_inst *inst); +int vpu_session_abort(struct vpu_inst *inst); +int vpu_session_rst_buf(struct vpu_inst *inst); +int vpu_session_encode_frame(struct vpu_inst *inst, s64 timestamp); +int vpu_session_alloc_fs(struct vpu_inst *inst, struct vpu_fs_info *fs); +int vpu_session_release_fs(struct vpu_inst *inst, struct vpu_fs_info *fs); +int vpu_session_fill_timestamp(struct vpu_inst *inst, struct vpu_ts_info *info); +int vpu_session_update_parameters(struct vpu_inst *inst, void *arg); +int vpu_core_snapshot(struct vpu_core *core); +int vpu_core_sw_reset(struct vpu_core *core); +int vpu_response_cmd(struct vpu_inst *inst, u32 response, u32 handled); +void vpu_clear_request(struct vpu_inst *inst); +int vpu_session_debug(struct vpu_inst *inst); + +#endif diff --git a/drivers/media/platform/amphion/vpu_mbox.c b/drivers/media/platform/amphion/vpu_mbox.c new file mode 100644 index 000000000000..87f8743bedea --- /dev/null +++ b/drivers/media/platform/amphion/vpu_mbox.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_mbox.h" +#include "vpu_msgs.h" + +static void vpu_mbox_rx_callback(struct mbox_client *cl, void *msg) +{ + struct vpu_mbox *rx = container_of(cl, struct vpu_mbox, cl); + struct vpu_core *core = container_of(rx, struct vpu_core, rx); + + vpu_isr(core, *(u32 *)msg); +} + +static int vpu_mbox_request_channel(struct device *dev, struct vpu_mbox *mbox) +{ + struct mbox_chan *ch; + struct mbox_client *cl; + + if (!dev || !mbox) + return -EINVAL; + if (mbox->ch) + return 0; + + cl = &mbox->cl; + cl->dev = dev; + if (mbox->block) { + cl->tx_block = true; + cl->tx_tout = 1000; + } else { + cl->tx_block = false; + } + cl->knows_txdone = false; + cl->rx_callback = vpu_mbox_rx_callback; + + ch = mbox_request_channel_byname(cl, mbox->name); + if (IS_ERR(ch)) { + dev_err(dev, "Failed to request mbox chan %s, ret : %ld\n", + mbox->name, PTR_ERR(ch)); + return PTR_ERR(ch); + } + + mbox->ch = ch; + return 0; +} + +int vpu_mbox_init(struct vpu_core *core) +{ + WARN_ON(!core); + + scnprintf(core->tx_type.name, sizeof(core->tx_type.name) - 1, "tx0"); + core->tx_type.block = true; + + scnprintf(core->tx_data.name, sizeof(core->tx_data.name) - 1, "tx1"); + core->tx_data.block = false; + + scnprintf(core->rx.name, sizeof(core->rx.name) - 1, "rx"); + core->rx.block = true; + + return 0; +} + +int vpu_mbox_request(struct vpu_core *core) +{ + int ret; + + WARN_ON(!core); + + ret = vpu_mbox_request_channel(core->dev, &core->tx_type); + if (ret) + goto error; + ret = vpu_mbox_request_channel(core->dev, &core->tx_data); + if (ret) + goto error; + ret = vpu_mbox_request_channel(core->dev, &core->rx); + if (ret) + goto error; + + dev_dbg(core->dev, "%s request mbox\n", vpu_core_type_desc(core->type)); + return 0; +error: + vpu_mbox_free(core); + return ret; +} + +void vpu_mbox_free(struct vpu_core *core) +{ + WARN_ON(!core); + + mbox_free_channel(core->tx_type.ch); + mbox_free_channel(core->tx_data.ch); + mbox_free_channel(core->rx.ch); + core->tx_type.ch = NULL; + core->tx_data.ch = NULL; + core->rx.ch = NULL; + dev_dbg(core->dev, "%s free mbox\n", vpu_core_type_desc(core->type)); +} + +void vpu_mbox_send_type(struct vpu_core *core, u32 type) +{ + mbox_send_message(core->tx_type.ch, &type); +} + +void vpu_mbox_send_msg(struct vpu_core *core, u32 type, u32 data) +{ + mbox_send_message(core->tx_data.ch, &data); + mbox_send_message(core->tx_type.ch, &type); +} + +void vpu_mbox_enable_rx(struct vpu_dev *dev) +{ +} diff --git a/drivers/media/platform/amphion/vpu_mbox.h b/drivers/media/platform/amphion/vpu_mbox.h new file mode 100644 index 000000000000..79cfd874e92b --- /dev/null +++ b/drivers/media/platform/amphion/vpu_mbox.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_MBOX_H +#define _AMPHION_VPU_MBOX_H + +int vpu_mbox_init(struct vpu_core *core); +int vpu_mbox_request(struct vpu_core *core); +void vpu_mbox_free(struct vpu_core *core); +void vpu_mbox_send_msg(struct vpu_core *core, u32 type, u32 data); +void vpu_mbox_send_type(struct vpu_core *core, u32 type); +void vpu_mbox_enable_rx(struct vpu_dev *dev); + +#endif diff --git a/drivers/media/platform/amphion/vpu_msgs.c b/drivers/media/platform/amphion/vpu_msgs.c new file mode 100644 index 000000000000..34d3da4d1a57 --- /dev/null +++ b/drivers/media/platform/amphion/vpu_msgs.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_core.h" +#include "vpu_rpc.h" +#include "vpu_mbox.h" +#include "vpu_defs.h" +#include "vpu_cmds.h" +#include "vpu_msgs.h" +#include "vpu_v4l2.h" + +#define VPU_PKT_HEADER_LENGTH 3 + +struct vpu_msg_handler { + u32 id; + void (*done)(struct vpu_inst *inst, struct vpu_rpc_event *pkt); +}; + +static void vpu_session_handle_start_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + WARN_ON(!inst || !inst->core); + + vpu_trace(inst->dev, "[%d]\n", inst->id); +} + +static void vpu_session_handle_mem_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_pkt_mem_req_data req_data; + + WARN_ON(!inst || !inst->core || !inst->ops); + + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&req_data); + vpu_trace(inst->dev, "[%d] %d:%d %d:%d %d:%d\n", + inst->id, + req_data.enc_frame_size, + req_data.enc_frame_num, + req_data.ref_frame_size, + req_data.ref_frame_num, + req_data.act_buf_size, + req_data.act_buf_num); + call_vop(inst, mem_request, + req_data.enc_frame_size, + req_data.enc_frame_num, + req_data.ref_frame_size, + req_data.ref_frame_num, + req_data.act_buf_size, + req_data.act_buf_num); +} + +static void vpu_session_handle_stop_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + WARN_ON(!inst || !inst->core); + + vpu_trace(inst->dev, "[%d]\n", inst->id); + + call_vop(inst, stop_done); +} + +static void vpu_session_handle_seq_hdr(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_dec_codec_info info; + const struct vpu_core_resources *res; + + WARN_ON(!inst || !inst->core); + + memset(&info, 0, sizeof(info)); + res = vpu_get_resource(inst); + info.stride = res ? res->stride : 1; + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + call_vop(inst, event_notify, VPU_MSG_ID_SEQ_HDR_FOUND, &info); +} + +static void vpu_session_handle_resolution_change(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + WARN_ON(!inst || !inst->core); + + call_vop(inst, event_notify, VPU_MSG_ID_RES_CHANGE, NULL); +} + +static void vpu_session_handle_enc_frame_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_enc_pic_info info; + + WARN_ON(!inst || !inst->core); + + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + dev_dbg(inst->dev, "[%d] frame id = %d, wptr = 0x%x, size = %d\n", + inst->id, info.frame_id, info.wptr, info.frame_size); + call_vop(inst, get_one_frame, &info); +} + +static void vpu_session_handle_frame_request(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_fs_info fs; + + vpu_iface_unpack_msg_data(inst->core, pkt, &fs); + call_vop(inst, event_notify, VPU_MSG_ID_FRAME_REQ, &fs); +} + +static void vpu_session_handle_frame_release(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + + WARN_ON(!inst || !inst->core); + + if (inst->core->type == VPU_CORE_TYPE_ENC) { + struct vpu_frame_info info; + + memset(&info, 0, sizeof(info)); + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info.sequence); + dev_dbg(inst->dev, "[%d] %d\n", inst->id, info.sequence); + info.type = inst->out_format.type; + call_vop(inst, buf_done, &info); + } else if (inst->core->type == VPU_CORE_TYPE_DEC) { + struct vpu_fs_info fs; + + vpu_iface_unpack_msg_data(inst->core, pkt, &fs); + call_vop(inst, event_notify, VPU_MSG_ID_FRAME_RELEASE, &fs); + } +} + +static void vpu_session_handle_input_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + + WARN_ON(!inst || !inst->core); + + dev_dbg(inst->dev, "[%d]\n", inst->id); + call_vop(inst, input_done); +} + +static void vpu_session_handle_pic_decoded(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_dec_pic_info info; + + WARN_ON(!inst || !inst->core); + + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + call_vop(inst, get_one_frame, &info); +} + +static void vpu_session_handle_pic_done(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + struct vpu_dec_pic_info info; + struct vpu_frame_info frame; + + WARN_ON(!inst || !inst->core); + + memset(&frame, 0, sizeof(frame)); + vpu_iface_unpack_msg_data(inst->core, pkt, (void *)&info); + if (inst->core->type == VPU_CORE_TYPE_DEC) + frame.type = inst->cap_format.type; + frame.id = info.id; + frame.luma = info.luma; + frame.skipped = info.skipped; + frame.timestamp = info.timestamp; + + call_vop(inst, buf_done, &frame); +} + +static void vpu_session_handle_eos(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + call_vop(inst, event_notify, VPU_MSG_ID_PIC_EOS, NULL); +} + +static void vpu_session_handle_error(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + dev_err(inst->dev, "unsupported stream\n"); + call_vop(inst, event_notify, VPU_MSG_ID_UNSUPPORTED, NULL); + vpu_v4l2_set_error(inst); +} + +static void vpu_session_handle_firmware_xcpt(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + char *str = (char *)pkt->data; + + dev_err(inst->dev, "%s firmware xcpt: %s\n", + vpu_core_type_desc(inst->core->type), str); + call_vop(inst, event_notify, VPU_MSG_ID_FIRMWARE_XCPT, NULL); + set_bit(inst->id, &inst->core->hang_mask); + vpu_v4l2_set_error(inst); +} + +struct vpu_msg_handler handlers[] = { + {VPU_MSG_ID_START_DONE, vpu_session_handle_start_done}, + {VPU_MSG_ID_STOP_DONE, vpu_session_handle_stop_done}, + {VPU_MSG_ID_MEM_REQUEST, vpu_session_handle_mem_request}, + {VPU_MSG_ID_SEQ_HDR_FOUND, vpu_session_handle_seq_hdr}, + {VPU_MSG_ID_RES_CHANGE, vpu_session_handle_resolution_change}, + {VPU_MSG_ID_FRAME_INPUT_DONE, vpu_session_handle_input_done}, + {VPU_MSG_ID_FRAME_REQ, vpu_session_handle_frame_request}, + {VPU_MSG_ID_FRAME_RELEASE, vpu_session_handle_frame_release}, + {VPU_MSG_ID_ENC_DONE, vpu_session_handle_enc_frame_done}, + {VPU_MSG_ID_PIC_DECODED, vpu_session_handle_pic_decoded}, + {VPU_MSG_ID_DEC_DONE, vpu_session_handle_pic_done}, + {VPU_MSG_ID_PIC_EOS, vpu_session_handle_eos}, + {VPU_MSG_ID_UNSUPPORTED, vpu_session_handle_error}, + {VPU_MSG_ID_FIRMWARE_XCPT, vpu_session_handle_firmware_xcpt}, +}; + +static int vpu_session_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *msg) +{ + int ret; + u32 msg_id; + struct vpu_msg_handler *handler = NULL; + unsigned int i; + + ret = vpu_iface_convert_msg_id(inst->core, msg->hdr.id); + if (ret < 0) + return -EINVAL; + + msg_id = ret; + dev_dbg(inst->dev, "[%d] receive event(0x%x)\n", inst->id, msg_id); + + for (i = 0; i < ARRAY_SIZE(handlers); i++) { + if (handlers[i].id == msg_id) { + handler = &handlers[i]; + break; + } + } + + if (handler && handler->done) + handler->done(inst, msg); + + vpu_response_cmd(inst, msg_id, 1); + + return 0; +} + +static bool vpu_inst_receive_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + u32 bytes = sizeof(struct vpu_rpc_event_header); + u32 ret; + + memset(pkt, 0, sizeof(*pkt)); + if (kfifo_len(&inst->msg_fifo) < bytes) + return false; + + ret = kfifo_out(&inst->msg_fifo, pkt, bytes); + if (ret != bytes) + return false; + + if (pkt->hdr.num > 0) { + bytes = pkt->hdr.num * sizeof(u32); + ret = kfifo_out(&inst->msg_fifo, pkt->data, bytes); + if (ret != bytes) + return false; + } + + return true; +} + +void vpu_inst_run_work(struct work_struct *work) +{ + struct vpu_inst *inst = container_of(work, struct vpu_inst, msg_work); + struct vpu_rpc_event pkt; + + while (vpu_inst_receive_msg(inst, &pkt)) + vpu_session_handle_msg(inst, &pkt); +} + +static void vpu_inst_handle_msg(struct vpu_inst *inst, struct vpu_rpc_event *pkt) +{ + u32 bytes; + u32 id = pkt->hdr.id; + int ret; + + if (!inst->workqueue) { + vpu_session_handle_msg(inst, pkt); + return; + } + + bytes = sizeof(pkt->hdr) + pkt->hdr.num * sizeof(u32); + ret = kfifo_in(&inst->msg_fifo, pkt, bytes); + if (ret != bytes) + dev_err(inst->dev, "[%d:%d]overflow: %d\n", inst->core->id, inst->id, id); + queue_work(inst->workqueue, &inst->msg_work); +} + +static int vpu_handle_msg(struct vpu_core *core) +{ + struct vpu_rpc_event pkt; + struct vpu_inst *inst; + int ret; + + memset(&pkt, 0, sizeof(pkt)); + while (!vpu_iface_receive_msg(core, &pkt)) { + dev_dbg(core->dev, "event index = %d, id = %d, num = %d\n", + pkt.hdr.index, pkt.hdr.id, pkt.hdr.num); + + ret = vpu_iface_convert_msg_id(core, pkt.hdr.id); + if (ret < 0) + continue; + + inst = vpu_core_find_instance(core, pkt.hdr.index); + if (inst) { + vpu_response_cmd(inst, ret, 0); + mutex_lock(&core->cmd_lock); + vpu_inst_record_flow(inst, ret); + mutex_unlock(&core->cmd_lock); + + vpu_inst_handle_msg(inst, &pkt); + vpu_inst_put(inst); + } + memset(&pkt, 0, sizeof(pkt)); + } + + return 0; +} + +static int vpu_isr_thread(struct vpu_core *core, u32 irq_code) +{ + WARN_ON(!core); + + dev_dbg(core->dev, "irq code = 0x%x\n", irq_code); + switch (irq_code) { + case VPU_IRQ_CODE_SYNC: + vpu_mbox_send_msg(core, PRC_BUF_OFFSET, core->rpc.phys - core->fw.phys); + vpu_mbox_send_msg(core, BOOT_ADDRESS, core->fw.phys); + vpu_mbox_send_msg(core, INIT_DONE, 2); + break; + case VPU_IRQ_CODE_BOOT_DONE: + break; + case VPU_IRQ_CODE_SNAPSHOT_DONE: + break; + default: + vpu_handle_msg(core); + break; + } + + return 0; +} + +static void vpu_core_run_msg_work(struct vpu_core *core) +{ + const unsigned int SIZE = sizeof(u32); + + while (kfifo_len(&core->msg_fifo) >= SIZE) { + u32 data; + + if (kfifo_out(&core->msg_fifo, &data, SIZE) == SIZE) + vpu_isr_thread(core, data); + } +} + +void vpu_msg_run_work(struct work_struct *work) +{ + struct vpu_core *core = container_of(work, struct vpu_core, msg_work); + unsigned long delay = msecs_to_jiffies(10); + + vpu_core_run_msg_work(core); + queue_delayed_work(core->workqueue, &core->msg_delayed_work, delay); +} + +void vpu_msg_delayed_work(struct work_struct *work) +{ + struct vpu_core *core; + struct delayed_work *dwork; + u32 bytes = sizeof(bytes); + u32 i; + + if (!work) + return; + + dwork = to_delayed_work(work); + core = container_of(dwork, struct vpu_core, msg_delayed_work); + if (kfifo_len(&core->msg_fifo) >= bytes) + vpu_core_run_msg_work(core); + + bytes = sizeof(struct vpu_rpc_event_header); + for (i = 0; i < core->supported_instance_count; i++) { + struct vpu_inst *inst = vpu_core_find_instance(core, i); + + if (!inst) + continue; + + if (inst->workqueue && kfifo_len(&inst->msg_fifo) >= bytes) + queue_work(inst->workqueue, &inst->msg_work); + + vpu_inst_put(inst); + } +} + + +int vpu_isr(struct vpu_core *core, u32 irq) +{ + WARN_ON(!core); + + switch (irq) { + case VPU_IRQ_CODE_SYNC: + break; + case VPU_IRQ_CODE_BOOT_DONE: + complete(&core->cmp); + break; + case VPU_IRQ_CODE_SNAPSHOT_DONE: + complete(&core->cmp); + break; + default: + break; + } + + if (kfifo_in(&core->msg_fifo, &irq, sizeof(irq)) != sizeof(irq)) + dev_err(core->dev, "[%d]overflow: %d\n", core->id, irq); + queue_work(core->workqueue, &core->msg_work); + + return 0; +} diff --git a/drivers/media/platform/amphion/vpu_msgs.h b/drivers/media/platform/amphion/vpu_msgs.h new file mode 100644 index 000000000000..c466b4f62aad --- /dev/null +++ b/drivers/media/platform/amphion/vpu_msgs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020-2021 NXP + */ + +#ifndef _AMPHION_VPU_MSGS_H +#define _AMPHION_VPU_MSGS_H + +int vpu_isr(struct vpu_core *core, u32 irq); +void vpu_inst_run_work(struct work_struct *work); +void vpu_msg_run_work(struct work_struct *work); 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/media/platform/amphion/vdec.c | 1680 +++++++++++++++++++++++++ 1 file changed, 1680 insertions(+) create mode 100644 drivers/media/platform/amphion/vdec.c diff --git a/drivers/media/platform/amphion/vdec.c b/drivers/media/platform/amphion/vdec.c new file mode 100644 index 000000000000..a66d34d02a50 --- /dev/null +++ b/drivers/media/platform/amphion/vdec.c @@ -0,0 +1,1680 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_core.h" +#include "vpu_helpers.h" +#include "vpu_v4l2.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" + +#define VDEC_FRAME_DEPTH 256 +#define VDEC_MIN_BUFFER_CAP 8 + +struct vdec_fs_info { + char name[8]; + u32 type; + u32 max_count; + u32 req_count; + u32 count; + u32 index; + u32 size; + struct vpu_buffer buffer[32]; + u32 tag; +}; + +struct vdec_t { + u32 seq_hdr_found; + struct vpu_buffer udata; + struct vpu_decode_params params; + struct vpu_dec_codec_info codec_info; + enum vpu_codec_state state; + + struct vpu_vb2_buffer *slots[VB2_MAX_FRAME]; + u32 req_frame_count; + struct vdec_fs_info mbi; + struct vdec_fs_info dcp; + u32 seq_tag; + + bool reset_codec; + bool fixed_fmt; + u32 decoded_frame_count; + u32 display_frame_count; + u32 sequence; + u32 eos_received; + bool is_source_changed; + u32 source_change; + u32 drain; + u32 ts_pre_count; + u32 frame_depth; + s64 ts_start; + s64 ts_input; + s64 timestamp; +}; + +static const struct vpu_format vdec_formats[] = { + { + .pixfmt = V4L2_PIX_FMT_NV12MT_8L128, + .num_planes = 2, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, + }, + { + .pixfmt = V4L2_PIX_FMT_NV12MT_10BE_8L128, + .num_planes = 2, + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, + }, + { + .pixfmt = V4L2_PIX_FMT_H264, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_H264_MVC, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_HEVC, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_G, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_MPEG2, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_MPEG4, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_XVID, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_VP8, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt = V4L2_PIX_FMT_H263, + .num_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION + }, + {0, 0, 0, 0}, +}; + +static const struct v4l2_ctrl_ops vdec_ctrl_ops = { + .g_volatile_ctrl = vpu_helper_g_volatile_ctrl, +}; + +static int vdec_ctrl_init(struct vpu_inst *inst) +{ + struct v4l2_ctrl *ctrl; + int ret; + + ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20); + if (ret) + return ret; + + ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 2); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; + + ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 2); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; + + ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler); + if (ret) { + dev_err(inst->dev, "[%d] setup ctrls fail, ret = %d\n", inst->id, ret); + v4l2_ctrl_handler_free(&inst->ctrl_handler); + return ret; + } + + return 0; +} + +static void vdec_set_last_buffer_dequeued(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + if (vdec->eos_received) { + if (!vpu_set_last_buffer_dequeued(inst)) + vdec->eos_received--; + } +} + +static void vdec_handle_resolution_change(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + struct vb2_queue *q; + + if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + return; + if (!vdec->source_change) + return; + + q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); + if (!list_empty(&q->done_list)) + return; + + vdec->source_change--; + vpu_notify_source_change(inst); +} + +static int vdec_update_state(struct vpu_inst *inst, + enum vpu_codec_state state, u32 force) +{ + struct vdec_t *vdec = inst->priv; + enum vpu_codec_state pre_state = inst->state; + + if (state == VPU_CODEC_STATE_SEEK) { + if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + vdec->state = inst->state; + else + vdec->state = VPU_CODEC_STATE_ACTIVE; + } + if (inst->state != VPU_CODEC_STATE_SEEK || force) + inst->state = state; + else if (state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + vdec->state = VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE; + + if (inst->state != pre_state) + vpu_trace(inst->dev, "[%d] %d -> %d\n", inst->id, pre_state, inst->state); + + if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + vdec_handle_resolution_change(inst); + + return 0; +} + +static int vdec_querycap(struct file *file, void *fh, struct v4l2_capability *cap) +{ + strscpy(cap->driver, "amphion-vpu", sizeof(cap->driver)); + strscpy(cap->card, "amphion vpu decoder", sizeof(cap->card)); + strscpy(cap->bus_info, "platform: amphion-vpu", sizeof(cap->bus_info)); + + return 0; +} + +static int vdec_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f) +{ + struct vpu_inst *inst = to_inst(file); + struct vdec_t *vdec = inst->priv; + const struct vpu_format *fmt; + int ret = -EINVAL; + + vpu_inst_lock(inst); + if (!V4L2_TYPE_IS_OUTPUT(f->type) && vdec->fixed_fmt) { + if (f->index == 0) { + f->pixelformat = inst->cap_format.pixfmt; + f->flags = inst->cap_format.flags; + ret = 0; + } + } else { + fmt = vpu_helper_enum_format(inst, f->type, f->index); + memset(f->reserved, 0, sizeof(f->reserved)); + if (!fmt) + goto exit; + + f->pixelformat = fmt->pixfmt; + f->flags = fmt->flags; + ret = 0; + } + +exit: + vpu_inst_unlock(inst); + return ret; +} + +static int vdec_g_fmt(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_inst *inst = to_inst(file); + struct vdec_t *vdec = inst->priv; + struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; + struct vpu_format *cur_fmt; + int i; + + cur_fmt = vpu_get_format(inst, f->type); + + pixmp->pixelformat = cur_fmt->pixfmt; + pixmp->num_planes = cur_fmt->num_planes; + pixmp->width = cur_fmt->width; + pixmp->height = cur_fmt->height; + pixmp->field = cur_fmt->field; + pixmp->flags = cur_fmt->flags; + for (i = 0; i < pixmp->num_planes; i++) { + pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; + pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i]; + } + + f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; + f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; + f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; + f->fmt.pix_mp.quantization = vdec->codec_info.full_range; + + return 0; +} + +static int vdec_try_fmt(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_inst *inst = to_inst(file); + struct vdec_t *vdec = inst->priv; + + vpu_try_fmt_common(inst, f); + + vpu_inst_lock(inst); + if (vdec->fixed_fmt) { + f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; + f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; + f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; + f->fmt.pix_mp.quantization = vdec->codec_info.full_range; + } else { + f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_DEFAULT; + f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; + f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; + } + vpu_inst_unlock(inst); + + return 0; +} + +static int vdec_s_fmt_common(struct vpu_inst *inst, struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; + const struct vpu_format *fmt; + struct vpu_format *cur_fmt; + struct vb2_queue *q; + struct vdec_t *vdec = inst->priv; + int i; + + q = v4l2_m2m_get_vq(inst->fh.m2m_ctx, f->type); + if (!q) + return -EINVAL; + if (vb2_is_streaming(q)) + return -EBUSY; + + fmt = vpu_try_fmt_common(inst, f); + if (!fmt) + return -EINVAL; + + cur_fmt = vpu_get_format(inst, f->type); + if (V4L2_TYPE_IS_OUTPUT(f->type) && inst->state != VPU_CODEC_STATE_DEINIT) { + if (cur_fmt->pixfmt != fmt->pixfmt || + (pixmp->width && cur_fmt->width != pixmp->width) || + (pixmp->height && cur_fmt->height != pixmp->height)) { + vdec->reset_codec = true; + vdec->fixed_fmt = false; + } + } + cur_fmt->pixfmt = fmt->pixfmt; + if (V4L2_TYPE_IS_OUTPUT(f->type) || !vdec->fixed_fmt) { + cur_fmt->num_planes = fmt->num_planes; + cur_fmt->flags = fmt->flags; + cur_fmt->width = pixmp->width; + cur_fmt->height = pixmp->height; + for (i = 0; i < fmt->num_planes; i++) { + cur_fmt->sizeimage[i] = pixmp->plane_fmt[i].sizeimage; + cur_fmt->bytesperline[i] = pixmp->plane_fmt[i].bytesperline; + } + if (pixmp->field != V4L2_FIELD_ANY) + cur_fmt->field = pixmp->field; + } else { + pixmp->num_planes = cur_fmt->num_planes; + pixmp->width = cur_fmt->width; + pixmp->height = cur_fmt->height; + for (i = 0; i < pixmp->num_planes; i++) { + pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; + pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i]; + } + pixmp->field = cur_fmt->field; + } + + if (!vdec->fixed_fmt) { + if (V4L2_TYPE_IS_OUTPUT(f->type)) { + vdec->params.codec_format = cur_fmt->pixfmt; + vdec->codec_info.color_primaries = f->fmt.pix_mp.colorspace; + vdec->codec_info.transfer_chars = f->fmt.pix_mp.xfer_func; + vdec->codec_info.matrix_coeffs = f->fmt.pix_mp.ycbcr_enc; + vdec->codec_info.full_range = f->fmt.pix_mp.quantization; + } else { + vdec->params.output_format = cur_fmt->pixfmt; + inst->crop.left = 0; + inst->crop.top = 0; + inst->crop.width = cur_fmt->width; + inst->crop.height = cur_fmt->height; + } + } + + return 0; +} + +static int vdec_s_fmt(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_inst *inst = to_inst(file); + struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; + struct vdec_t *vdec = inst->priv; + int ret = 0; + + vpu_inst_lock(inst); + ret = vdec_s_fmt_common(inst, f); + if (ret) + goto exit; + + if (V4L2_TYPE_IS_OUTPUT(f->type) && !vdec->fixed_fmt) { + struct v4l2_format fc; + + memset(&fc, 0, sizeof(fc)); + fc.type = inst->cap_format.type; + fc.fmt.pix_mp.pixelformat = inst->cap_format.pixfmt; + fc.fmt.pix_mp.width = pixmp->width; + fc.fmt.pix_mp.height = pixmp->height; + vdec_s_fmt_common(inst, &fc); + } + + f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; + f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; + f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; + f->fmt.pix_mp.quantization = vdec->codec_info.full_range; + +exit: + vpu_inst_unlock(inst); + return ret; +} + +static int vdec_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct vpu_inst *inst = to_inst(file); + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + return -EINVAL; + + switch (s->target) { + case V4L2_SEL_TGT_COMPOSE: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_PADDED: + s->r = inst->crop; + break; + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->cap_format.width; + s->r.height = inst->cap_format.height; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int vdec_drain(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + if (!vdec->drain) + return 0; + + if (v4l2_m2m_num_src_bufs_ready(inst->fh.m2m_ctx)) + return 0; + + if (!vdec->params.frame_count) { + vpu_set_last_buffer_dequeued(inst); + return 0; + } + + vpu_iface_add_scode(inst, SCODE_PADDING_EOS); + vdec->params.end_flag = 1; + vpu_iface_set_decode_params(inst, &vdec->params, 1); + vdec->drain = 0; + vpu_trace(inst->dev, "[%d] frame_count = %d\n", inst->id, vdec->params.frame_count); + + return 0; +} + +static int vdec_cmd_start(struct vpu_inst *inst) +{ + if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0); + vpu_process_capture_buffer(inst); + return 0; +} + +static int vdec_cmd_stop(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + vpu_trace(inst->dev, "[%d]\n", inst->id); + + if (inst->state == VPU_CODEC_STATE_DEINIT) { + vpu_set_last_buffer_dequeued(inst); + } else { + vdec->drain = 1; + vdec_drain(inst); + } + + return 0; +} + +static int vdec_decoder_cmd(struct file *file, + void *fh, + struct v4l2_decoder_cmd *cmd) +{ + struct vpu_inst *inst = to_inst(file); + int ret; + + ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, cmd); + if (ret) + return ret; + + vpu_inst_lock(inst); + switch (cmd->cmd) { + case V4L2_DEC_CMD_START: + vdec_cmd_start(inst); + break; + case V4L2_DEC_CMD_STOP: + vdec_cmd_stop(inst); + break; + default: + break; + } + vpu_inst_unlock(inst); + + return 0; +} + +static int vdec_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_EOS: + return v4l2_event_subscribe(fh, sub, 0, NULL); + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_src_change_event_subscribe(fh, sub); + case V4L2_EVENT_CTRL: + return v4l2_ctrl_subscribe_event(fh, sub); + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ioctl_ops vdec_ioctl_ops = { + .vidioc_querycap = vdec_querycap, + .vidioc_enum_fmt_vid_cap = vdec_enum_fmt, + .vidioc_enum_fmt_vid_out = vdec_enum_fmt, + .vidioc_g_fmt_vid_cap_mplane = vdec_g_fmt, + .vidioc_g_fmt_vid_out_mplane = vdec_g_fmt, + .vidioc_try_fmt_vid_cap_mplane = vdec_try_fmt, + .vidioc_try_fmt_vid_out_mplane = vdec_try_fmt, + .vidioc_s_fmt_vid_cap_mplane = vdec_s_fmt, + .vidioc_s_fmt_vid_out_mplane = vdec_s_fmt, + .vidioc_g_selection = vdec_g_selection, + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, + .vidioc_decoder_cmd = vdec_decoder_cmd, + .vidioc_subscribe_event = vdec_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, +}; + +static bool vdec_check_ready(struct vpu_inst *inst, unsigned int type) +{ + struct vdec_t *vdec = inst->priv; + + if (V4L2_TYPE_IS_OUTPUT(type)) { + if (vdec->ts_pre_count >= vdec->frame_depth) + return false; + return true; + } + + if (vdec->req_frame_count) + return true; + + return false; +} + +static int vdec_frame_decoded(struct vpu_inst *inst, void *arg) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_dec_pic_info *info = arg; + struct vpu_vb2_buffer *vpu_buf; + int ret = 0; + + if (!info || info->id >= ARRAY_SIZE(vdec->slots)) + return -EINVAL; + + vpu_inst_lock(inst); + vpu_buf = vdec->slots[info->id]; + if (!vpu_buf) { + dev_err(inst->dev, "[%d] decoded invalid frame[%d]\n", inst->id, info->id); + ret = -EINVAL; + goto exit; + } + if (vpu_buf->state == VPU_BUF_STATE_DECODED) + dev_info(inst->dev, "[%d] buf[%d] has been decoded\n", inst->id, info->id); + vpu_buf->state = VPU_BUF_STATE_DECODED; + vdec->decoded_frame_count++; + if (vdec->ts_pre_count >= info->consumed_count) + vdec->ts_pre_count -= info->consumed_count; + else + vdec->ts_pre_count = 0; +exit: + vpu_inst_unlock(inst); + + return ret; +} + +static struct vpu_vb2_buffer *vdec_find_buffer(struct vpu_inst *inst, u32 luma) +{ + struct vdec_t *vdec = inst->priv; + int i; + + for (i = 0; i < ARRAY_SIZE(vdec->slots); i++) { + if (!vdec->slots[i]) + continue; + if (luma == vdec->slots[i]->luma) + return vdec->slots[i]; + } + + return NULL; +} + +static void vdec_buf_done(struct vpu_inst *inst, struct vpu_frame_info *frame) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_vb2_buffer *vpu_buf; + struct vb2_v4l2_buffer *vbuf; + u32 sequence; + + if (!frame) + return; + + vpu_inst_lock(inst); + sequence = vdec->sequence++; + vpu_buf = vdec_find_buffer(inst, frame->luma); + vpu_inst_unlock(inst); + if (!vpu_buf) { + dev_err(inst->dev, "[%d] can't find buffer, id = %d, addr = 0x%x\n", + inst->id, frame->id, frame->luma); + return; + } + if (frame->skipped) { + dev_dbg(inst->dev, "[%d] frame skip\n", inst->id); + return; + } + + vbuf = &vpu_buf->m2m_buf.vb; + if (vbuf->vb2_buf.index != frame->id) + dev_err(inst->dev, "[%d] buffer id(%d, %d) dismatch\n", + inst->id, vbuf->vb2_buf.index, frame->id); + + if (vpu_buf->state != VPU_BUF_STATE_DECODED) + dev_err(inst->dev, "[%d] buffer(%d) ready without decoded\n", + inst->id, frame->id); + vpu_buf->state = VPU_BUF_STATE_READY; + vb2_set_plane_payload(&vbuf->vb2_buf, 0, inst->cap_format.sizeimage[0]); + vb2_set_plane_payload(&vbuf->vb2_buf, 1, inst->cap_format.sizeimage[1]); + vbuf->vb2_buf.timestamp = frame->timestamp; + vbuf->field = inst->cap_format.field; + vbuf->sequence = sequence; + dev_dbg(inst->dev, "[%d][OUTPUT TS]%32lld\n", inst->id, frame->timestamp); + + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); + vpu_inst_lock(inst); + vdec->timestamp = frame->timestamp; + vdec->display_frame_count++; + vpu_inst_unlock(inst); + dev_dbg(inst->dev, "[%d] decoded : %d, display : %d, sequence : %d\n", + inst->id, + vdec->decoded_frame_count, + vdec->display_frame_count, + vdec->sequence); +} + +static void vdec_stop_done(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + vpu_inst_lock(inst); + vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 0); + vdec->seq_hdr_found = 0; + vdec->req_frame_count = 0; + vdec->reset_codec = false; + vdec->fixed_fmt = false; + vdec->params.end_flag = 0; + vdec->drain = 0; + vdec->ts_pre_count = 0; + vdec->timestamp = VPU_INVALID_TIMESTAMP; + vdec->ts_start = VPU_INVALID_TIMESTAMP; + vdec->ts_input = VPU_INVALID_TIMESTAMP; + vdec->params.frame_count = 0; + vdec->decoded_frame_count = 0; + vdec->display_frame_count = 0; + vdec->sequence = 0; + vdec->eos_received = 0; + vdec->is_source_changed = false; + vdec->source_change = 0; + vpu_inst_unlock(inst); +} + +static bool vdec_check_source_change(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + const struct vpu_format *fmt; + int i; + + if (!vb2_is_streaming(v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx))) + return true; + fmt = vpu_helper_find_format(inst, inst->cap_format.type, vdec->codec_info.pixfmt); + if (inst->cap_format.pixfmt != vdec->codec_info.pixfmt) + return true; + if (inst->cap_format.width != vdec->codec_info.decoded_width) + return true; + if (inst->cap_format.height != vdec->codec_info.decoded_height) + return true; + if (vpu_get_num_buffers(inst, inst->cap_format.type) < inst->min_buffer_cap) + return true; + if (inst->crop.left != vdec->codec_info.offset_x) + return true; + if (inst->crop.top != vdec->codec_info.offset_y) + return true; + if (inst->crop.width != vdec->codec_info.width) + return true; + if (inst->crop.height != vdec->codec_info.height) + return true; + if (fmt && inst->cap_format.num_planes != fmt->num_planes) + return true; + for (i = 0; i < inst->cap_format.num_planes; i++) { + if (inst->cap_format.bytesperline[i] != vdec->codec_info.bytesperline[i]) + return true; + if (inst->cap_format.sizeimage[i] != vdec->codec_info.sizeimage[i]) + return true; + } + + return false; +} + +static void vdec_init_fmt(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + const struct vpu_format *fmt; + int i; + + fmt = vpu_helper_find_format(inst, inst->cap_format.type, vdec->codec_info.pixfmt); + inst->out_format.width = vdec->codec_info.width; + inst->out_format.height = vdec->codec_info.height; + inst->cap_format.width = vdec->codec_info.decoded_width; + inst->cap_format.height = vdec->codec_info.decoded_height; + inst->cap_format.pixfmt = vdec->codec_info.pixfmt; + if (fmt) { + inst->cap_format.num_planes = fmt->num_planes; + inst->cap_format.flags = fmt->flags; + } + for (i = 0; i < inst->cap_format.num_planes; i++) { + inst->cap_format.bytesperline[i] = vdec->codec_info.bytesperline[i]; + inst->cap_format.sizeimage[i] = vdec->codec_info.sizeimage[i]; + } + if (vdec->codec_info.progressive) + inst->cap_format.field = V4L2_FIELD_NONE; + else + inst->cap_format.field = V4L2_FIELD_INTERLACED; + if (vdec->codec_info.color_primaries == V4L2_COLORSPACE_DEFAULT) + vdec->codec_info.color_primaries = V4L2_COLORSPACE_REC709; + if (vdec->codec_info.transfer_chars == V4L2_XFER_FUNC_DEFAULT) + vdec->codec_info.transfer_chars = V4L2_XFER_FUNC_709; + if (vdec->codec_info.matrix_coeffs == V4L2_YCBCR_ENC_DEFAULT) + vdec->codec_info.matrix_coeffs = V4L2_YCBCR_ENC_709; + if (vdec->codec_info.full_range == V4L2_QUANTIZATION_DEFAULT) + vdec->codec_info.full_range = V4L2_QUANTIZATION_LIM_RANGE; +} + +static void vdec_init_crop(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + inst->crop.left = vdec->codec_info.offset_x; + inst->crop.top = vdec->codec_info.offset_y; + inst->crop.width = vdec->codec_info.width; + inst->crop.height = vdec->codec_info.height; +} + +static void vdec_init_mbi(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + vdec->mbi.size = vdec->codec_info.mbi_size; + vdec->mbi.max_count = ARRAY_SIZE(vdec->mbi.buffer); + scnprintf(vdec->mbi.name, sizeof(vdec->mbi.name), "mbi"); + vdec->mbi.type = MEM_RES_MBI; + vdec->mbi.tag = vdec->seq_tag; +} + +static void vdec_init_dcp(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + vdec->dcp.size = vdec->codec_info.dcp_size; + vdec->dcp.max_count = ARRAY_SIZE(vdec->dcp.buffer); + scnprintf(vdec->dcp.name, sizeof(vdec->dcp.name), "dcp"); + vdec->dcp.type = MEM_RES_DCP; + vdec->dcp.tag = vdec->seq_tag; +} + +static void vdec_request_one_fs(struct vdec_fs_info *fs) +{ + WARN_ON(!fs); + + fs->req_count++; + if (fs->req_count > fs->max_count) + fs->req_count = fs->max_count; +} + +static int vdec_alloc_fs_buffer(struct vpu_inst *inst, struct vdec_fs_info *fs) +{ + struct vpu_buffer *buffer; + + if (!inst || !fs || !fs->size) + return -EINVAL; + + if (fs->count >= fs->req_count) + return -EINVAL; + + buffer = &fs->buffer[fs->count]; + if (buffer->virt && buffer->length >= fs->size) + return 0; + + vpu_free_dma(buffer); + buffer->length = fs->size; + return vpu_alloc_dma(inst->core, buffer); +} + +static void vdec_alloc_fs(struct vpu_inst *inst, struct vdec_fs_info *fs) +{ + int ret; + + while (fs->count < fs->req_count) { + ret = vdec_alloc_fs_buffer(inst, fs); + if (ret) + break; + fs->count++; + } +} + +static void vdec_clear_fs(struct vdec_fs_info *fs) +{ + u32 i; + + if (!fs) + return; + + for (i = 0; i < ARRAY_SIZE(fs->buffer); i++) + vpu_free_dma(&fs->buffer[i]); + memset(fs, 0, sizeof(*fs)); +} + +static int vdec_response_fs(struct vpu_inst *inst, struct vdec_fs_info *fs) +{ + struct vpu_fs_info info; + int ret; + + if (fs->index >= fs->count) + return 0; + + memset(&info, 0, sizeof(info)); + info.id = fs->index; + info.type = fs->type; + info.tag = fs->tag; + info.luma_addr = fs->buffer[fs->index].phys; + info.luma_size = fs->buffer[fs->index].length; + ret = vpu_session_alloc_fs(inst, &info); + if (ret) + return ret; + + fs->index++; + return 0; +} + +static int vdec_response_frame_abnormal(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_fs_info info; + + if (!vdec->req_frame_count) + return 0; + + memset(&info, 0, sizeof(info)); + info.type = MEM_RES_FRAME; + info.tag = vdec->seq_tag + 0xf0; + vpu_session_alloc_fs(inst, &info); + vdec->req_frame_count--; + + return 0; +} + +static int vdec_response_frame(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_vb2_buffer *vpu_buf; + struct vpu_fs_info info; + int ret; + + if (inst->state != VPU_CODEC_STATE_ACTIVE) + return -EINVAL; + + if (!vdec->req_frame_count) + return -EINVAL; + + if (!vbuf) + return -EINVAL; + + if (vdec->slots[vbuf->vb2_buf.index]) { + dev_err(inst->dev, "[%d] repeat alloc fs %d\n", + inst->id, vbuf->vb2_buf.index); + return -EINVAL; + } + + dev_dbg(inst->dev, "[%d] state = %d, alloc fs %d, tag = 0x%x\n", + inst->id, inst->state, vbuf->vb2_buf.index, vdec->seq_tag); + vpu_buf = to_vpu_vb2_buffer(vbuf); + + memset(&info, 0, sizeof(info)); + info.id = vbuf->vb2_buf.index; + info.type = MEM_RES_FRAME; + info.tag = vdec->seq_tag; + info.luma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 0); + info.luma_size = inst->cap_format.sizeimage[0]; + info.chroma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 1); + info.chromau_size = inst->cap_format.sizeimage[1]; + info.bytesperline = inst->cap_format.bytesperline[0]; + ret = vpu_session_alloc_fs(inst, &info); + if (ret) + return ret; + + vpu_buf->tag = info.tag; + vpu_buf->luma = info.luma_addr; + vpu_buf->chroma_u = info.chromau_size; + vpu_buf->chroma_v = 0; + vpu_buf->state = VPU_BUF_STATE_INUSE; + vdec->slots[info.id] = vpu_buf; + vdec->req_frame_count--; + + return 0; +} + +static void vdec_response_fs_request(struct vpu_inst *inst, bool force) +{ + struct vdec_t *vdec = inst->priv; + int i; + int ret; + + if (force) { + for (i = vdec->req_frame_count; i > 0; i--) + vdec_response_frame_abnormal(inst); + return; + } + + for (i = vdec->req_frame_count; i > 0; i--) { + ret = vpu_process_capture_buffer(inst); + if (ret) + break; + if (vdec->eos_received) + break; + } + + for (i = vdec->mbi.index; i < vdec->mbi.count; i++) { + if (vdec_response_fs(inst, &vdec->mbi)) + break; + if (vdec->eos_received) + break; + } + for (i = vdec->dcp.index; i < vdec->dcp.count; i++) { + if (vdec_response_fs(inst, &vdec->dcp)) + break; + if (vdec->eos_received) + break; + } +} + +static void vdec_response_fs_release(struct vpu_inst *inst, u32 id, u32 tag) +{ + struct vpu_fs_info info; + + memset(&info, 0, sizeof(info)); + info.id = id; + info.tag = tag; + vpu_session_release_fs(inst, &info); +} + +static void vdec_recycle_buffer(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf) +{ + if (!inst || !vbuf) + return; + + if (vbuf->vb2_buf.state != VB2_BUF_STATE_ACTIVE) + return; + if (vpu_find_buf_by_idx(inst, vbuf->vb2_buf.type, vbuf->vb2_buf.index)) + return; + v4l2_m2m_buf_queue(inst->fh.m2m_ctx, vbuf); +} + +static void vdec_clear_slots(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_vb2_buffer *vpu_buf; + struct vb2_v4l2_buffer *vbuf; + int i; + + for (i = 0; i < ARRAY_SIZE(vdec->slots); i++) { + if (!vdec->slots[i]) + continue; + + vpu_buf = vdec->slots[i]; + vbuf = &vpu_buf->m2m_buf.vb; + + vdec_response_fs_release(inst, i, vpu_buf->tag); + vdec_recycle_buffer(inst, vbuf); + vdec->slots[i]->state = VPU_BUF_STATE_IDLE; + vdec->slots[i] = NULL; + } +} + +static void vdec_event_seq_hdr(struct vpu_inst *inst, + struct vpu_dec_codec_info *hdr) +{ + struct vdec_t *vdec = inst->priv; + + vpu_inst_lock(inst); + memcpy(&vdec->codec_info, hdr, sizeof(vdec->codec_info)); + + vpu_trace(inst->dev, "[%d] %d x %d, crop : (%d, %d) %d x %d, %d, %d\n", + inst->id, + vdec->codec_info.decoded_width, + vdec->codec_info.decoded_height, + vdec->codec_info.offset_x, + vdec->codec_info.offset_y, + vdec->codec_info.width, + vdec->codec_info.height, + hdr->num_ref_frms, + hdr->num_dpb_frms); + inst->min_buffer_cap = hdr->num_ref_frms + hdr->num_dpb_frms; + vdec->is_source_changed = vdec_check_source_change(inst); + vdec_init_fmt(inst); + vdec_init_crop(inst); + vdec_init_mbi(inst); + vdec_init_dcp(inst); + if (!vdec->seq_hdr_found) { + vdec->seq_tag = vdec->codec_info.tag; + if (vdec->is_source_changed) { + vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0); + vpu_notify_source_change(inst); + vdec->is_source_changed = false; + } + } + if (vdec->seq_tag != vdec->codec_info.tag) { + vdec_response_fs_request(inst, true); + vpu_trace(inst->dev, "[%d] seq tag change: %d -> %d\n", + inst->id, vdec->seq_tag, vdec->codec_info.tag); + } + vdec->seq_hdr_found++; + vdec->fixed_fmt = true; + vpu_inst_unlock(inst); +} + +static void vdec_event_resolution_change(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + vpu_trace(inst->dev, "[%d]\n", inst->id); + vpu_inst_lock(inst); + vdec->seq_tag = vdec->codec_info.tag; + vdec_clear_fs(&vdec->mbi); + vdec_clear_fs(&vdec->dcp); + vdec_clear_slots(inst); + vdec_init_mbi(inst); + vdec_init_dcp(inst); + if (vdec->is_source_changed) { + vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0); + vdec->source_change++; + vdec_handle_resolution_change(inst); + vdec->is_source_changed = false; + } + vpu_inst_unlock(inst); +} + +static void vdec_event_req_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) +{ + struct vdec_t *vdec = inst->priv; + + if (!fs) + return; + + vpu_inst_lock(inst); + + switch (fs->type) { + case MEM_RES_FRAME: + vdec->req_frame_count++; + break; + case MEM_RES_MBI: + vdec_request_one_fs(&vdec->mbi); + break; + case MEM_RES_DCP: + vdec_request_one_fs(&vdec->dcp); + break; + default: + break; + } + + vdec_alloc_fs(inst, &vdec->mbi); + vdec_alloc_fs(inst, &vdec->dcp); + + vdec_response_fs_request(inst, false); + + vpu_inst_unlock(inst); +} + +static void vdec_evnet_rel_fs(struct vpu_inst *inst, struct vpu_fs_info *fs) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_vb2_buffer *vpu_buf; + struct vb2_v4l2_buffer *vbuf; + + if (!fs || fs->id >= ARRAY_SIZE(vdec->slots)) + return; + if (fs->type != MEM_RES_FRAME) + return; + + if (fs->id >= vpu_get_num_buffers(inst, inst->cap_format.type)) { + dev_err(inst->dev, "[%d] invalid fs(%d) to release\n", inst->id, fs->id); + return; + } + + vpu_inst_lock(inst); + vpu_buf = vdec->slots[fs->id]; + vdec->slots[fs->id] = NULL; + + if (!vpu_buf) { + dev_dbg(inst->dev, "[%d] fs[%d] has bee released\n", inst->id, fs->id); + goto exit; + } + + if (vpu_buf->state == VPU_BUF_STATE_DECODED) { + dev_dbg(inst->dev, "[%d] frame skip\n", inst->id); + vdec->sequence++; + } + + vdec_response_fs_release(inst, fs->id, vpu_buf->tag); + vbuf = &vpu_buf->m2m_buf.vb; + if (vpu_buf->state != VPU_BUF_STATE_READY) + vdec_recycle_buffer(inst, vbuf); + + vpu_buf->state = VPU_BUF_STATE_IDLE; + vpu_process_capture_buffer(inst); + +exit: + vpu_inst_unlock(inst); +} + +static void vdec_event_eos(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + + vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n", + inst->id, + vdec->params.frame_count, + vdec->decoded_frame_count, + vdec->display_frame_count, + vdec->sequence); + vpu_inst_lock(inst); + vdec->eos_received++; + vdec->fixed_fmt = false; + inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP; + vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0); + vdec_set_last_buffer_dequeued(inst); + vpu_inst_unlock(inst); +} + +static void vdec_event_notify(struct vpu_inst *inst, u32 event, void *data) +{ + switch (event) { + case VPU_MSG_ID_SEQ_HDR_FOUND: + vdec_event_seq_hdr(inst, data); + break; + case VPU_MSG_ID_RES_CHANGE: + vdec_event_resolution_change(inst); + break; + case VPU_MSG_ID_FRAME_REQ: + vdec_event_req_fs(inst, data); + break; + case VPU_MSG_ID_FRAME_RELEASE: + vdec_evnet_rel_fs(inst, data); + break; + case VPU_MSG_ID_PIC_EOS: + vdec_event_eos(inst); + break; + default: + break; + } +} + +static int vdec_process_output(struct vpu_inst *inst, struct vb2_buffer *vb) +{ + struct vdec_t *vdec = inst->priv; + struct vb2_v4l2_buffer *vbuf; + struct vpu_vb2_buffer *vpu_buf; + struct vpu_rpc_buffer_desc desc; + s64 timestamp; + u32 free_space; + int ret; + + vbuf = to_vb2_v4l2_buffer(vb); + vpu_buf = to_vpu_vb2_buffer(vbuf); + dev_dbg(inst->dev, "[%d] dec output [%d] %d : %ld\n", + inst->id, vbuf->sequence, vb->index, vb2_get_plane_payload(vb, 0)); + + if (inst->state == VPU_CODEC_STATE_DEINIT) + return -EINVAL; + if (vdec->reset_codec) + return -EINVAL; + + if (inst->state == VPU_CODEC_STATE_STARTED) + vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0); + + ret = vpu_iface_get_stream_buffer_desc(inst, &desc); + if (ret) + return ret; + + free_space = vpu_helper_get_free_space(inst); + if (free_space < vb2_get_plane_payload(vb, 0) + 0x40000) + return -ENOMEM; + + timestamp = vb->timestamp; + if (timestamp >= 0 && vdec->ts_start < 0) + vdec->ts_start = timestamp; + if (vdec->ts_input < timestamp) + vdec->ts_input = timestamp; + + ret = vpu_iface_input_frame(inst, vb); + if (ret < 0) + return -ENOMEM; + + dev_dbg(inst->dev, "[%d][INPUT TS]%32lld\n", inst->id, vb->timestamp); + vdec->ts_pre_count++; + vdec->params.frame_count++; + + v4l2_m2m_src_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf); + vpu_buf->state = VPU_BUF_STATE_IDLE; + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); + + if (vdec->drain) + vdec_drain(inst); + + return 0; +} + +static int vdec_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb) +{ + struct vdec_t *vdec = inst->priv; + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + int ret; + + if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + return -EINVAL; + if (vdec->reset_codec) + return -EINVAL; + + ret = vdec_response_frame(inst, vbuf); + if (ret) + return ret; + v4l2_m2m_dst_buf_remove_by_buf(inst->fh.m2m_ctx, vbuf); + return 0; +} + +static void vdec_on_queue_empty(struct vpu_inst *inst, u32 type) +{ + struct vdec_t *vdec = inst->priv; + + if (V4L2_TYPE_IS_OUTPUT(type)) + return; + + vdec_handle_resolution_change(inst); + if (vdec->eos_received) + vdec_set_last_buffer_dequeued(inst); +} + +static void vdec_abort(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + struct vpu_rpc_buffer_desc desc; + int ret; + + vpu_trace(inst->dev, "[%d] state = %d\n", inst->id, inst->state); + vpu_iface_add_scode(inst, SCODE_PADDING_ABORT); + vdec->params.end_flag = 1; + vpu_iface_set_decode_params(inst, &vdec->params, 1); + + vpu_session_abort(inst); + + ret = vpu_iface_get_stream_buffer_desc(inst, &desc); + if (!ret) + vpu_iface_update_stream_buffer(inst, desc.rptr, 1); + + vpu_session_rst_buf(inst); + vpu_trace(inst->dev, "[%d] input : %d, decoded : %d, display : %d, sequence : %d\n", + inst->id, + vdec->params.frame_count, + vdec->decoded_frame_count, + vdec->display_frame_count, + vdec->sequence); + vdec->params.end_flag = 0; + vdec->drain = 0; + vdec->ts_pre_count = 0; + vdec->timestamp = VPU_INVALID_TIMESTAMP; + vdec->ts_start = VPU_INVALID_TIMESTAMP; + vdec->ts_input = VPU_INVALID_TIMESTAMP; + vdec->params.frame_count = 0; + vdec->decoded_frame_count = 0; + vdec->display_frame_count = 0; + vdec->sequence = 0; +} + +static void vdec_stop(struct vpu_inst *inst, bool free) +{ + struct vdec_t *vdec = inst->priv; + + vdec_clear_slots(inst); + if (inst->state != VPU_CODEC_STATE_DEINIT) + vpu_session_stop(inst); + vdec_clear_fs(&vdec->mbi); + vdec_clear_fs(&vdec->dcp); + if (free) { + vpu_free_dma(&vdec->udata); + vpu_free_dma(&inst->stream_buffer); + } + vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 1); + vdec->reset_codec = false; +} + +static void vdec_release(struct vpu_inst *inst) +{ + if (inst->id != VPU_INST_NULL_ID) + vpu_trace(inst->dev, "[%d]\n", inst->id); + vpu_inst_lock(inst); + vdec_stop(inst, true); + vpu_inst_unlock(inst); +} + +static void vdec_cleanup(struct vpu_inst *inst) +{ + struct vdec_t *vdec; + + if (!inst) + return; + + vdec = inst->priv; + if (vdec) + vfree(vdec); + inst->priv = NULL; + vfree(inst); +} + +static void vdec_init_params(struct vdec_t *vdec) +{ + vdec->params.frame_count = 0; + vdec->params.end_flag = 0; +} + +static int vdec_start(struct vpu_inst *inst) +{ + struct vdec_t *vdec = inst->priv; + int stream_buffer_size; + int ret; + + if (inst->state != VPU_CODEC_STATE_DEINIT) + return 0; + + vpu_trace(inst->dev, "[%d]\n", inst->id); + if (!vdec->udata.virt) { + vdec->udata.length = 0x1000; + ret = vpu_alloc_dma(inst->core, &vdec->udata); + if (ret) { + dev_err(inst->dev, "[%d] alloc udata fail\n", inst->id); + goto error; + } + } + + if (!inst->stream_buffer.virt) { + stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core); + if (stream_buffer_size > 0) { + inst->stream_buffer.length = stream_buffer_size; + ret = vpu_alloc_dma(inst->core, &inst->stream_buffer); + if (ret) { + dev_err(inst->dev, "[%d] alloc stream buffer fail\n", inst->id); + goto error; + } + inst->use_stream_buffer = true; + } + } + + if (inst->use_stream_buffer) + vpu_iface_config_stream_buffer(inst, &inst->stream_buffer); + vpu_iface_init_instance(inst); + vdec->params.udata.base = vdec->udata.phys; + vdec->params.udata.size = vdec->udata.length; + ret = vpu_iface_set_decode_params(inst, &vdec->params, 0); + if (ret) { + dev_err(inst->dev, "[%d] set decode params fail\n", inst->id); + goto error; + } + + vdec_init_params(vdec); + ret = vpu_session_start(inst); + if (ret) { + dev_err(inst->dev, "[%d] start fail\n", inst->id); + goto error; + } + + vdec_update_state(inst, VPU_CODEC_STATE_STARTED, 0); + + return 0; +error: + vpu_free_dma(&vdec->udata); + vpu_free_dma(&inst->stream_buffer); + return ret; +} + +static int vdec_start_session(struct vpu_inst *inst, u32 type) +{ + struct vdec_t *vdec = inst->priv; + int ret = 0; + + if (V4L2_TYPE_IS_OUTPUT(type)) { + if (vdec->reset_codec) + vdec_stop(inst, false); + if (inst->state == VPU_CODEC_STATE_DEINIT) { + ret = vdec_start(inst); + if (ret) + return ret; + } + } + + if (V4L2_TYPE_IS_OUTPUT(type)) { + if (inst->state == VPU_CODEC_STATE_SEEK) + vdec_update_state(inst, vdec->state, 1); + vdec->eos_received = 0; + vpu_process_output_buffer(inst); + } else { + vdec_cmd_start(inst); + } + if (inst->state == VPU_CODEC_STATE_ACTIVE) + vdec_response_fs_request(inst, false); + + return ret; +} + +static int vdec_stop_session(struct vpu_inst *inst, u32 type) +{ + struct vdec_t *vdec = inst->priv; + + if (inst->state == VPU_CODEC_STATE_DEINIT) + return 0; + + if (V4L2_TYPE_IS_OUTPUT(type)) { + vdec_update_state(inst, VPU_CODEC_STATE_SEEK, 0); + vdec->drain = 0; + } else { + if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE) + vdec_abort(inst); + + vdec->eos_received = 0; + vdec_clear_slots(inst); + } + + return 0; +} + +static int vdec_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i) +{ + struct vdec_t *vdec = inst->priv; + int num = -1; + + switch (i) { + case 0: + num = scnprintf(str, size, + "req_frame_count = %d\ninterlaced = %d\n", + vdec->req_frame_count, + vdec->codec_info.progressive ? 0 : 1); + break; + case 1: + num = scnprintf(str, size, + "mbi: size = 0x%x request = %d, alloc = %d, response = %d\n", + vdec->mbi.size, + vdec->mbi.req_count, + vdec->mbi.count, + vdec->mbi.index); + break; + case 2: + num = scnprintf(str, size, + "dcp: size = 0x%x request = %d, alloc = %d, response = %d\n", + vdec->dcp.size, + vdec->dcp.req_count, + vdec->dcp.count, + vdec->dcp.index); + break; + case 3: + num = scnprintf(str, size, "input_frame_count = %d\n", vdec->params.frame_count); + break; + case 4: + num = scnprintf(str, size, "decoded_frame_count = %d\n", vdec->decoded_frame_count); + break; + case 5: + num = scnprintf(str, size, "display_frame_count = %d\n", vdec->display_frame_count); + break; + case 6: + num = scnprintf(str, size, "sequence = %d\n", vdec->sequence); + break; + case 7: + num = scnprintf(str, size, "drain = %d, eos = %d, source_change = %d\n", + vdec->drain, vdec->eos_received, vdec->source_change); + break; + case 8: + num = scnprintf(str, size, "ts_pre_count = %d, frame_depth = %d\n", + vdec->ts_pre_count, vdec->frame_depth); + break; + case 9: + num = scnprintf(str, size, "fps = %d/%d\n", + vdec->codec_info.frame_rate.numerator, + vdec->codec_info.frame_rate.denominator); + break; + case 10: + { + s64 timestamp = vdec->timestamp; + s64 ts_start = vdec->ts_start; + s64 ts_input = vdec->ts_input; + + num = scnprintf(str, size, "timestamp = %9lld.%09lld(%9lld.%09lld, %9lld.%09lld)\n", + timestamp / NSEC_PER_SEC, + timestamp % NSEC_PER_SEC, + ts_start / NSEC_PER_SEC, + ts_start % NSEC_PER_SEC, + ts_input / NSEC_PER_SEC, + ts_input % NSEC_PER_SEC); + } + break; + default: + break; + } + + return num; +} + +static struct vpu_inst_ops vdec_inst_ops = { + .ctrl_init = vdec_ctrl_init, + .check_ready = vdec_check_ready, + .buf_done = vdec_buf_done, + .get_one_frame = vdec_frame_decoded, + .stop_done = vdec_stop_done, + .event_notify = vdec_event_notify, + .release = vdec_release, + .cleanup = vdec_cleanup, + .start = vdec_start_session, + .stop = vdec_stop_session, + .process_output = vdec_process_output, + .process_capture = vdec_process_capture, + .on_queue_empty = vdec_on_queue_empty, + .get_debug_info = vdec_get_debug_info, + .wait_prepare = vpu_inst_unlock, + .wait_finish = vpu_inst_lock, +}; + +static void vdec_init(struct file *file) +{ + struct vpu_inst *inst = to_inst(file); + struct vdec_t *vdec; + struct v4l2_format f; + + vdec = inst->priv; + vdec->frame_depth = VDEC_FRAME_DEPTH; + vdec->timestamp = VPU_INVALID_TIMESTAMP; + vdec->ts_start = VPU_INVALID_TIMESTAMP; + vdec->ts_input = VPU_INVALID_TIMESTAMP; + + memset(&f, 0, sizeof(f)); + f.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264; + f.fmt.pix_mp.width = 1280; + f.fmt.pix_mp.height = 720; + f.fmt.pix_mp.field = V4L2_FIELD_NONE; + vdec_s_fmt(file, &inst->fh, &f); + + memset(&f, 0, sizeof(f)); + f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12MT_8L128; + f.fmt.pix_mp.width = 1280; + f.fmt.pix_mp.height = 720; + f.fmt.pix_mp.field = V4L2_FIELD_NONE; + vdec_s_fmt(file, &inst->fh, &f); +} + +static int vdec_open(struct file *file) +{ + struct vpu_inst *inst; + struct vdec_t *vdec; + int ret; + + inst = vzalloc(sizeof(*inst)); + if (!inst) + return -ENOMEM; + + vdec = vzalloc(sizeof(*vdec)); + if (!vdec) { + vfree(inst); + return -ENOMEM; + } + + inst->ops = &vdec_inst_ops; + inst->formats = vdec_formats; + inst->type = VPU_CORE_TYPE_DEC; + inst->priv = vdec; + + ret = vpu_v4l2_open(file, inst); + if (ret) + return ret; + + vdec->fixed_fmt = false; + inst->min_buffer_cap = VDEC_MIN_BUFFER_CAP; + vdec_init(file); + + return 0; +} + +static __poll_t vdec_poll(struct file *file, poll_table *wait) +{ + struct vpu_inst *inst = to_inst(file); + struct vb2_queue *src_q, *dst_q; + __poll_t ret; + + ret = v4l2_m2m_fop_poll(file, wait); + src_q = v4l2_m2m_get_src_vq(inst->fh.m2m_ctx); + dst_q = v4l2_m2m_get_dst_vq(inst->fh.m2m_ctx); + if (vb2_is_streaming(src_q) && !vb2_is_streaming(dst_q)) + ret &= (~EPOLLERR); + if (!src_q->error && !dst_q->error && + (vb2_is_streaming(src_q) && list_empty(&src_q->queued_list)) && + (vb2_is_streaming(dst_q) && list_empty(&dst_q->queued_list))) + ret &= (~EPOLLERR); + + return ret; +} + +static const struct v4l2_file_operations vdec_fops = { + .owner = THIS_MODULE, + .open = vdec_open, + .release = vpu_v4l2_close, + .unlocked_ioctl = video_ioctl2, + .poll = vdec_poll, + .mmap = v4l2_m2m_fop_mmap, +}; + +const struct v4l2_ioctl_ops *vdec_get_ioctl_ops(void) +{ + return &vdec_ioctl_ops; +} + +const struct v4l2_file_operations *vdec_get_fops(void) +{ + return &vdec_fops; +} From patchwork Tue Nov 30 09:48:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 519527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 228E4C4167B for ; Tue, 30 Nov 2021 09:49:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240569AbhK3Jwy (ORCPT ); Tue, 30 Nov 2021 04:52:54 -0500 Received: from mail-eopbgr50049.outbound.protection.outlook.com ([40.107.5.49]:37188 "EHLO EUR03-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S240476AbhK3Jwu (ORCPT ); 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Tue, 30 Nov 2021 09:49:24 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v13 11/13] ARM64: dts: freescale: imx8q: add imx vpu codec entries Date: Tue, 30 Nov 2021 17:48:12 +0800 Message-Id: <7330d63786ab3f580ffde5a214b1c1e6613e72b7.1638263914.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: References: X-ClientProxiedBy: SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 +++++++ 3 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100644 index 000000000000..f2dde6d14ca3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng + */ + +vpu: vpu@2c000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "okay"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "okay"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu_core@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + status = "disabled"; + }; + vpu_core1: vpu_core@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + status = "disabled"; + }; + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 863232a47004..05495b60beb8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -196,6 +196,23 @@ &usdhc2 { status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 617618edf77e..6b6d3c71632b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,6 +46,9 @@ aliases { serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus { @@ -134,10 +137,30 @@ reserved-memory { #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + + encoder_rpc: encoder-rpc@0x94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; }; pmu { @@ -259,6 +282,7 @@ map0 { /* sorted in register address */ #include "imx8-ss-img.dtsi" + #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" From patchwork Tue Nov 30 09:48:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 519525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C16D7C433EF for ; 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Received: from AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) by AM5PR0402MB2884.eurprd04.prod.outlook.com (2603:10a6:203:94::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4734.23; Tue, 30 Nov 2021 09:49:28 +0000 Received: from AM6PR04MB6341.eurprd04.prod.outlook.com ([fe80::fc3a:8aea:2c92:3886]) by AM6PR04MB6341.eurprd04.prod.outlook.com ([fe80::fc3a:8aea:2c92:3886%5]) with mapi id 15.20.4734.024; Tue, 30 Nov 2021 09:49:28 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v13 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Tue, 30 Nov 2021 17:48:13 +0800 Message-Id: <92ff12d58d0ae8aa1d09c30dcb5e163a0592f7be.1638263914.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: References: X-ClientProxiedBy: SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SI2P153CA0025.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::12) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; 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Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index ff6569c4a53b..af3d057e6421 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },