From patchwork Thu Dec 9 14:15:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 522573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EFD3C433F5 for ; Thu, 9 Dec 2021 14:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238420AbhLIOUD (ORCPT ); Thu, 9 Dec 2021 09:20:03 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:61611 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230048AbhLIOUD (ORCPT ); Thu, 9 Dec 2021 09:20:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1639059390; x=1670595390; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=AzPD1WoFBGnMhjs5plCLFR7JEN6Rj7aU/8x0LI3lULk=; b=vcEi8RHk/j+KbxBAkO4rxgtyf0JYW31//lSXTEfk1F+hJNhuj274rlB4 xVgb9dgnNLD3USoI0QPQ9J5Tic4JyitWfpX9027h/qnSxj9vpnT8hLGQs bf/a/ioK2mPNX0dJqlt8Vq/7WKuOwonGC7mjPDtWXSqLhIhZA6RH8gowT 4=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 09 Dec 2021 06:16:29 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 06:16:29 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:29 -0800 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:25 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Subject: [PATCH v2 1/9] Use IDR to maintain all the enabled sources' paths. Date: Thu, 9 Dec 2021 22:15:35 +0800 Message-ID: <20211209141543.21314-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209141543.21314-1-quic_jinlmao@quicinc.com> References: <20211209141543.21314-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use hash length of the source's device name to map to the pointer of the enabled path. Using IDR will be more efficient than using the list. And there could be other sources except STM and CPU etms in the new HWs. It is better to maintain all the paths together. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-core.c | 76 +++++++------------- 1 file changed, 26 insertions(+), 50 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 8a18c71df37a..cc6b6cabf85f 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,12 @@ static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); +/* + * Use IDR to map the hash length of the source's device name + * to the pointer of path for the source + */ +static DEFINE_IDR(path_idr); + /** * struct coresight_node - elements of a path, from source to sink * @csdev: Address of an element. @@ -36,20 +43,6 @@ struct coresight_node { struct list_head link; }; -/* - * When operating Coresight drivers from the sysFS interface, only a single - * path can exist from a tracer (associated to a CPU) to a sink. - */ -static DEFINE_PER_CPU(struct list_head *, tracer_path); - -/* - * As of this writing only a single STM can be found in CS topologies. Since - * there is no way to know if we'll ever see more and what kind of - * configuration they will enact, for the time being only define a single path - * for STM. - */ -static struct list_head *stm_path; - /* * When losing synchronisation a new barrier packet needs to be inserted at the * beginning of the data collected in a buffer. That way the decoder knows that @@ -1088,10 +1081,11 @@ static int coresight_validate_source(struct coresight_device *csdev, int coresight_enable(struct coresight_device *csdev) { - int cpu, ret = 0; + int ret = 0; struct coresight_device *sink; struct list_head *path; enum coresight_dev_subtype_source subtype; + u32 hash; subtype = csdev->subtype.source_subtype; @@ -1133,26 +1127,14 @@ int coresight_enable(struct coresight_device *csdev) if (ret) goto err_source; - switch (subtype) { - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: - /* - * When working from sysFS it is important to keep track - * of the paths that were created so that they can be - * undone in 'coresight_disable()'. Since there can only - * be a single session per tracer (when working from sysFS) - * a per-cpu variable will do just fine. - */ - cpu = source_ops(csdev)->cpu_id(csdev); - per_cpu(tracer_path, cpu) = path; - break; - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - stm_path = path; - break; - default: - /* We can't be here */ - break; - } - + /* + * Use the hash length of source's device name as ID + * and map the ID to the pointer of the path. + */ + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL); + if (ret) + goto err_source; out: mutex_unlock(&coresight_mutex); return ret; @@ -1168,8 +1150,9 @@ EXPORT_SYMBOL_GPL(coresight_enable); void coresight_disable(struct coresight_device *csdev) { - int cpu, ret; + int ret; struct list_head *path = NULL; + u32 hash; mutex_lock(&coresight_mutex); @@ -1180,21 +1163,13 @@ void coresight_disable(struct coresight_device *csdev) if (!csdev->enable || !coresight_disable_source(csdev)) goto out; - switch (csdev->subtype.source_subtype) { - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: - cpu = source_ops(csdev)->cpu_id(csdev); - path = per_cpu(tracer_path, cpu); - per_cpu(tracer_path, cpu) = NULL; - break; - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - path = stm_path; - stm_path = NULL; - break; - default: - /* We can't be here */ - break; - } + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + /* Find the path by the hash length. */ + path = idr_find(&path_idr, hash); + if (path == NULL) + return; + idr_remove(&path_idr, hash); coresight_disable_path(path); coresight_release_path(path); @@ -1779,6 +1754,7 @@ static int __init coresight_init(void) static void __exit coresight_exit(void) { + idr_destroy(&path_idr); cscfg_exit(); etm_perf_exit(); bus_unregister(&coresight_bustype); From patchwork Thu Dec 9 14:15:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 522572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39E33C433F5 for ; Thu, 9 Dec 2021 14:16:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238470AbhLIOUO (ORCPT ); Thu, 9 Dec 2021 09:20:14 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:35093 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238461AbhLIOUN (ORCPT ); Thu, 9 Dec 2021 09:20:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1639059400; x=1670595400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=nhu/DRtvsNP69U2TczNII5EIaKqMthBCJ+8MxNclmJ0=; b=evQpZirtDf9FKE17dV9GwPh0fBoziPbiX8IiDFGGRmS/LZ4hmrsEOdGi YRKuqGQ2adsWxzlkkuHV/fnjbukFhbEj9VZxoleFU32k2JD+87D2oQz2E 3DhHytfdbUaMld8c3ndtufU1p4y+tv4Sljxx+I9QYAP3yAEYFIC78jtxI U=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 09 Dec 2021 06:16:40 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 06:16:40 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:39 -0800 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:36 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Subject: [PATCH v2 3/9] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Date: Thu, 9 Dec 2021 22:15:37 +0800 Message-ID: <20211209141543.21314-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209141543.21314-1-quic_jinlmao@quicinc.com> References: <20211209141543.21314-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds new coresight-tpdm.yaml file describing the bindings required to define tpdm in the device trees. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/coresight-tpdm.yaml | 83 +++++++++++++++++++ .../devicetree/bindings/arm/coresight.txt | 7 ++ MAINTAINERS | 1 + 3 files changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml new file mode 100644 index 000000000000..63b0583afcfc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Monitor - TPDM + +description: | + The TPDM or Monitor serves as data collection component for various dataset + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef), + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete + Single Bit (DSB). It performs data collection in the data producing clock + domain and transfers it to the data collection time domain, generally ATB + clock domain. + + The primary use case of the TPDM is to collect data from different data + sources and send it to a TPDA for packetization, timestamping, and funneling. + +maintainers: + - Tao Zhang + - Mao Jinlong + - Suzuki K Poulose + - Mathieu Poirier + +properties: + $nodename: + pattern: "^tpdm(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpdm + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + out-ports: + description: | + Output connections from the TPDM to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + properties: + port: + description: Output connection from the TPDM to legacy CoreSight + Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum TPDM definition. + - | + tpdm@6980000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x6980000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index c68d93a35b6c..f7ce8af48574 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -52,6 +52,10 @@ its hardware characteristcs. "arm,coresight-cti", "arm,primecell"; See coresight-cti.yaml for full CTI definitions. + - Trace, Profiling and Diagnostics Monitor (TPDM): + "qcom,coresight-tpdm", "arm,primecell"; + See coresight-tpdm.yaml for full TPDM definitions. + * reg: physical base address and length of the register set(s) of the component. @@ -82,6 +86,9 @@ its hardware characteristcs. * Required properties for Coresight Cross Trigger Interface (CTI) See coresight-cti.yaml for full CTI definitions. +* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM) + See coresight-tpdm.yaml for full TPDM definitions. + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators and non-configurable funnels: diff --git a/MAINTAINERS b/MAINTAINERS index 59f39b3194f6..d763ba684b99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15566,6 +15566,7 @@ M: Jinlong Mao M: Mathieu Poirier M: Suzuki K Poulose S: Maintained +F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml F: drivers/hwtracing/coresight/coresight-tpdm.c QEMU MACHINE EMULATOR AND VIRTUALIZER SUPPORT From patchwork Thu Dec 9 14:15:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 522571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D6D0C433FE for ; Thu, 9 Dec 2021 14:16:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238503AbhLIOUZ (ORCPT ); Thu, 9 Dec 2021 09:20:25 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:61662 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238495AbhLIOUY (ORCPT ); Thu, 9 Dec 2021 09:20:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1639059411; x=1670595411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=xqJAJ9D7+IA8ZR9lL4oi9H+spKYV1MaDmW9XUuI/wcI=; b=zU+i/QhP63opHPDuE9hxautDSXmOcW+DPeY1mG25YbfKs2OHLuWjJp2W 91FfBM9l3FW9QVD+eu6kZrVfpKjBU7FvHMND0qkZoW/FSfQvAb7iarN6Y sC9R9k7SL8iOP3eSRfll3kgUrCUzxh+duUdQ968MIBNDfxtBnJ3Wd3xO0 c=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 09 Dec 2021 06:16:51 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 06:16:46 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:45 -0800 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:41 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Subject: [PATCH v2 4/9] coresight-tpdm: Add DSB dataset support Date: Thu, 9 Dec 2021 22:15:38 +0800 Message-ID: <20211209141543.21314-5-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209141543.21314-1-quic_jinlmao@quicinc.com> References: <20211209141543.21314-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org TPDM serves as data collection component for various dataset types. DSB(Discrete Single Bit) is one of the dataset types. DSB subunit can be enabled for data collection by writing 1 to the first bit of DSB_CR register. This change is to add enable/disable function for DSB dataset by writing DSB_CR register. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 56 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 23 ++++++++ 2 files changed, 79 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f494cef4fb24..c0dd216f70eb 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,6 +20,27 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val = val | BIT(0); + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + +static void _tpdm_enable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) + tpdm_enable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { @@ -31,6 +52,7 @@ static int tpdm_enable(struct coresight_device *csdev, return -EBUSY; } + _tpdm_enable(drvdata); drvdata->enable = true; mutex_unlock(&drvdata->lock); @@ -38,6 +60,28 @@ static int tpdm_enable(struct coresight_device *csdev, return 0; } +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 0 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val = val & ~BIT(0); + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + +static void _tpdm_disable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) + tpdm_disable_dsb(drvdata); + + CS_LOCK(drvdata->base); + +} + static void tpdm_disable(struct coresight_device *csdev, struct perf_event *event) { @@ -49,6 +93,7 @@ static void tpdm_disable(struct coresight_device *csdev, return; } + _tpdm_disable(drvdata); drvdata->enable = false; mutex_unlock(&drvdata->lock); @@ -75,8 +120,19 @@ static const struct coresight_ops tpdm_cs_ops = { static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) { static int traceid = TPDM_TRACE_ID_START; + int i; + u32 pidr; + CS_UNLOCK(drvdata->base); drvdata->traceid = traceid++; + + /* Get the datasets present on the TPDM. */ + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); + for (i = 0; i < TPDM_DATASETS; i++) { + if (pidr & BIT(i)) + __set_bit(i, drvdata->datasets); + } + CS_LOCK(drvdata->base); } static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 980ae90ff1c8..ba99c20e12bb 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -8,6 +8,27 @@ /* Default value of the traceid */ #define TPDM_TRACE_ID_START 128 +/* The max number of the datasets that TPDM supports */ +#define TPDM_DATASETS 7 + +/* DSB Subunit Registers */ +#define TPDM_DSB_CR (0x780) + +/** + * This enum is for PERIPHIDR0 register of TPDM. + * The fields [6:0] of PERIPHIDR0 are used to determine what + * interfaces and subunits are present on a given TPDM. + * + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0. + * No TPDM supports ImplDef subunit now. But + * the first bit of PERIPHIDR0 is for ImplDef + * subunit for initial design. + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0. + */ +enum tpdm_dataset { + TPDM_DS_IMPLDEF, + TPDM_DS_DSB, +}; /** * struct tpdm_drvdata - specifics associated to an TPDM component @@ -16,6 +37,7 @@ * @csdev: component vitals needed by the framework. * @lock: lock for the enable value. * @enable: enable status of the component. + * @datasets: The datasets types present of the TPDM. * @traceid: value of the current ID for this component. */ @@ -25,6 +47,7 @@ struct tpdm_drvdata { struct coresight_device *csdev; struct mutex lock; bool enable; + DECLARE_BITMAP(datasets, TPDM_DATASETS); int traceid; }; From patchwork Thu Dec 9 14:15:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 522570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 905C4C433F5 for ; Thu, 9 Dec 2021 14:17:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238546AbhLIOUi (ORCPT ); Thu, 9 Dec 2021 09:20:38 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:61677 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238495AbhLIOUe (ORCPT ); Thu, 9 Dec 2021 09:20:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1639059421; x=1670595421; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Tsb8Ukn+VNxBthIIOk431AQ0YerI8izT+fR5DeXUq4c=; b=zNOZHvUiF9rD3mYpD1leMghzEeImmM+nMNmieMr8vValDcNxqwKH+JqP NAzkzH+J6U9P2XnRs5PF/akRgeb/S5VDEwNakSPJ6VImKPlWjRg8Pr2E9 XF+FHKgLbJGHEnLEd1R+fNZS8RpOq7SHNT2u1E2pXlMORsMGgeXx6TFNt 4=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 09 Dec 2021 06:17:00 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 06:17:00 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:17:00 -0800 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:16:57 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Subject: [PATCH v2 7/9] Coresight: Add TPDA link driver Date: Thu, 9 Dec 2021 22:15:41 +0800 Message-ID: <20211209141543.21314-8-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209141543.21314-1-quic_jinlmao@quicinc.com> References: <20211209141543.21314-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org TPDA(Trace, Profiling and Diagnostics Aggregator) is to provide packetization, funneling and timestamping of TPDM data. Multiple monitors are connected to different input ports of TPDA.This change is to add tpda enable/disable/probe functions for coresight tpda driver. - - - - - - - - - - - - | TPDM 0| | TPDM 1 | | TPDM 2| - - - - - - - - - - - - | | | |_ _ _ _ _ _ | _ _ _ _ | | | | | | | ------------------ | TPDA | ------------------ | | ------------------ | Trace Funnel | ------------------ Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- MAINTAINERS | 1 + drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 201 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 33 +++ 5 files changed, 247 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h diff --git a/MAINTAINERS b/MAINTAINERS index 7e2898f1550b..12e4e56a252c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15568,6 +15568,7 @@ M: Suzuki K Poulose S: Maintained F: Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml +F: drivers/hwtracing/coresight/coresight-tpda.c F: drivers/hwtracing/coresight/coresight-tpdm.c QEMU MACHINE EMULATOR AND VIRTUALIZER SUPPORT diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 60248fef4089..317c5e7f4819 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -223,4 +223,15 @@ config CORESIGHT_TPDM_INTEGRATION_TEST operation to facilitate integration testing and software bringup and/or to instrument topology discovery. The TPDM utilizes integration mode to accomplish integration testing and software bringup. + +config CORESIGHT_TPDA + tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver" + help + This driver provides support for configuring aggregator. This is + primarily useful for pulling the data sets from one or more + attached monitors and pushing the resultant data out. Multiple + monitors are connected on different input ports of TPDA. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpda. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index e7392a0dddeb..cd8079ec276d 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o +obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c new file mode 100644 index 000000000000..e51624fac567 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpda.h" + +DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); + +/* Settings pre enabling port control register */ +static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_CR); + val |= (drvdata->atid << 6); + writel_relaxed(val, drvdata->base + TPDA_CR); +} + +static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* Enable the port */ + val = val | BIT(0); + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +} + +/* Settings post enabling port control register */ +static void tpda_enable_post_port(struct tpda_drvdata *drvdata) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_SYNCR); + /* Clear the mode */ + val = val & ~BIT(12); + /* Program the counter value */ + val = val | 0xFFF; + writel_relaxed(val, drvdata->base + TPDA_SYNCR); +} + +static void _tpda_enable(struct tpda_drvdata *drvdata, int port) +{ + CS_UNLOCK(drvdata->base); + + if (!drvdata->enable) + tpda_enable_pre_port(drvdata); + + tpda_enable_port(drvdata, port); + + if (!drvdata->enable) + tpda_enable_post_port(drvdata); + + CS_LOCK(drvdata->base); +} + +static int tpda_enable(struct coresight_device *csdev, int inport, int outport) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + mutex_lock(&drvdata->lock); + _tpda_enable(drvdata, inport); + drvdata->enable = true; + mutex_unlock(&drvdata->lock); + + dev_info(drvdata->dev, "TPDA inport %d enabled\n", inport); + return 0; +} + +static void _tpda_disable(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + val = val & ~BIT(0); + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); + + CS_LOCK(drvdata->base); +} + +static void tpda_disable(struct coresight_device *csdev, int inport, + int outport) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + mutex_lock(&drvdata->lock); + _tpda_disable(drvdata, inport); + drvdata->enable = false; + mutex_unlock(&drvdata->lock); + + dev_info(drvdata->dev, "TPDA inport %d disabled\n", inport); +} + +static const struct coresight_ops_link tpda_link_ops = { + .enable = tpda_enable, + .disable = tpda_disable, +}; + +static const struct coresight_ops tpda_cs_ops = { + .link_ops = &tpda_link_ops, +}; + +static int tpda_parse_of_data(struct tpda_drvdata *drvdata) +{ + int ret; + struct device_node *node = drvdata->dev->of_node; + + ret = of_property_read_u32(node, "qcom,tpda-atid", &drvdata->atid); + if (ret) { + dev_err(drvdata->dev, "TPDA ATID is not specified\n"); + return -EINVAL; + } + return 0; +} + +static int tpda_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct tpda_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + + desc.name = coresight_alloc_device_name(&tpda_devs, dev); + if (!desc.name) + return -ENOMEM; + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base = devm_ioremap_resource(dev, &adev->res); + if (!drvdata->base) + return -ENOMEM; + + mutex_init(&drvdata->lock); + + ret = tpda_parse_of_data(drvdata); + if (ret) + return ret; + + desc.type = CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops = &tpda_cs_ops; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + pm_runtime_put(&adev->dev); + + dev_dbg(drvdata->dev, "TPDA initialized\n"); + return 0; +} + +static struct amba_id tpda_ids[] = { + { + .id = 0x000f0f00, + .mask = 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpda_driver = { + .drv = { + .name = "coresight-tpda", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = tpda_probe, + .id_table = tpda_ids, +}; + +module_amba_driver(tpda_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h new file mode 100644 index 000000000000..35723571ea13 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDA_H +#define _CORESIGHT_CORESIGHT_TPDA_H + +#define TPDA_CR (0x000) +#define TPDA_Pn_CR(n) (0x004 + (n * 4)) +#define TPDA_SYNCR (0x08C) + +#define TPDA_MAX_INPORTS 32 + +/** + * struct tpda_drvdata - specifics associated to an TPDA component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @lock: lock for the enable value. + * @enable: enable status of the component. + * @traceid: trace source identification for the data packet by TPDA. + */ +struct tpda_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + struct mutex lock; + bool enable; + u32 atid; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDA_H */ From patchwork Thu Dec 9 14:15:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 522569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 436C8C433F5 for ; Thu, 9 Dec 2021 14:17:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238569AbhLIOUv (ORCPT ); Thu, 9 Dec 2021 09:20:51 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:5132 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238549AbhLIOUl (ORCPT ); Thu, 9 Dec 2021 09:20:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1639059428; x=1670595428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+gEGiTe5F7Hgf4jkiA8JEJg9Ffn33edoUDRll/gXJQY=; b=pmqcco2QuYm/tljfPExhT/XEqgZW2r/dh1gQhQvAFq4GOQGmuXIpQKBI BT/OgLni/hSU+ksiPBMsPw1RXxg6LSPuK2KmCRwSeU3gzWPs5x8r4VW4m JwakKJmFGchxsWO0P2o3wu3NkVga4DbqjYoFRCJR1p5M3lQkg2MPafKeA U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 09 Dec 2021 06:17:08 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 06:17:08 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:17:07 -0800 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 9 Dec 2021 06:17:04 -0800 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Subject: [PATCH v2 8/9] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Date: Thu, 9 Dec 2021 22:15:42 +0800 Message-ID: <20211209141543.21314-9-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209141543.21314-1-quic_jinlmao@quicinc.com> References: <20211209141543.21314-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds new coresight-tpda.yaml file describing the bindings required to define tpda in the device trees. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/coresight-tpda.yaml | 131 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml new file mode 100644 index 000000000000..4ce8c81a109a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Aggregator - TPDA + +description: | + TPDAs are responsible for packetization and timestamping of data sets + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or + more attached TPDM and pushing the resultant (packetized) data out a + master ATB interface. Performing an arbitrated ATB interleaving (funneling) + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). + +maintainers: + - Tao Zhang + - Mao Jinlong + - Suzuki K Poulose + - Mathieu Poirier + +properties: + $nodename: + pattern: "^tpda(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpda + - const: arm,primecell + + reg: + maxItems: 1 + + qcom,tpda-atid: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 + description: | + Use the ATID field for trace source identification. This allows + multiple TPDMs to be interleaved and formatted via the Coresight + trace formatter framing protocol and de-formatted/parsed on a host + or debugger. + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + type: object + description: | + Input connections from TPDM to TPDA + $ref: /schemas/graph.yaml#/properties/ports + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^port@[0-9a-f]+$": + type: object + required: + - reg + + required: + - '#size-cells' + - '#address-cells' + + out-ports: + type: object + description: | + Output connections from the TPDA to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: + Output connection from the TPDA to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - qcom,tpda-atid + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + # minimum tpda definition. + - | + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x6004000 0x1000>; + + qcom,tpda-atid = <65>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 12e4e56a252c..d3b7ce75ba9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15567,6 +15567,7 @@ M: Mathieu Poirier M: Suzuki K Poulose S: Maintained F: Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +F: Documentation/devicetree/bindings/arm/coresight-tpda.yaml F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml F: drivers/hwtracing/coresight/coresight-tpda.c F: drivers/hwtracing/coresight/coresight-tpdm.c