From patchwork Wed Dec 15 00:54:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9A20C4332F for ; Wed, 15 Dec 2021 00:54:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238668AbhLOAys (ORCPT ); Tue, 14 Dec 2021 19:54:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235240AbhLOAyr (ORCPT ); Tue, 14 Dec 2021 19:54:47 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70EA8C061574 for ; Tue, 14 Dec 2021 16:54:47 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id l7so30910251lja.2 for ; Tue, 14 Dec 2021 16:54:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YjtmLC1Vf5ZIFfw4f99ohhNZHTDpH6wpJkebrivmqJA=; b=OyH9U1gGbntZOkZXCtT7+E/3yTS+Qhuyxt+ccmKoawGIGLsl6DRVVaQIXux+0ALTs0 wqIOOnGn4vNbVjbZJosGajKGcYgwBHS3B1GS5+KXuuzW68AQS1iLVsiGJyWW47iybmR4 Y9/E9ZbRYTDoMThfAugVy04eTu10tasLV4IEJxcNpr0s1iFDkvcSe5Wf1q0q5RgTcyFV CdI6dtMuvhDjhvsVVvwXRslXt8SiFp5Ga20NKz3Sy22tyF6F/gJJDUeOUa7jW1egUZHm YVp4A7Trm21CNggBIAGOGZ2PcIZmz8Dt2Nk8Ozbl1yOuQlK0CW+JAjkeTfQQcq5CEHB0 RUfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YjtmLC1Vf5ZIFfw4f99ohhNZHTDpH6wpJkebrivmqJA=; b=ENv/3LY10OaGmQuvw8yJJVi2aMPqHIfCKREWLJ4NmINMLLzzNLVPpTtSyPHxcI+c9+ WxUSU7Q0qyjECgDT2ZmpinpFGXX1XuJL7VUVL1AAkvxReW1wrVv1tmO1Y/z4xCb0PIpu eG3MkvG8Pac6wZZgtSpD1eMIHqDL8BP2ckH3pbJESKzA3RL7UJSJRUAti0ZoaPqPhndW Xk4R+P77qU/HJzK+TG27NaW9qmLhUu8G275hg6CFRwL1jE7nR53BTRUyM93w0MJXa9YI R8aODI5VOeCLRFwNJpxc0NxcebcsgbZ72Fb52pykLyzAlvcf7njvnDYI8ZDHpbfNptO+ bJQQ== X-Gm-Message-State: AOAM532jid2cOLPSF1LFOgMH2Zq6nICp+B73AnnjY9kz97SpaiZq2Yi6 BVJqTI/d/BzeQucnJn0MOePxuA== X-Google-Smtp-Source: ABdhPJww3rA5+O62rNKiakFtKOUXQ0lIqvsxa0/up8nvRlkxdqL1UY+xjUAtOe9IyOcRvCrd0Pt0UA== X-Received: by 2002:a2e:b6c5:: with SMTP id m5mr8080780ljo.220.1639529685691; Tue, 14 Dec 2021 16:54:45 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id b12sm53022lfb.146.2021.12.14.16.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 16:54:45 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 01/15] clk: qcom: gpucc-sdm660: fix two clocks with parent_names Date: Wed, 15 Dec 2021 03:54:09 +0300 Message-Id: <20211215005423.2114261-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Two clocks are still using parent_names, use parent_hws instead. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gpucc-sdm660.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 41bba96a08b3..7c07b0979aea 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -204,8 +204,8 @@ static struct clk_branch gpucc_rbbmtimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_rbbmtimer_clk", - .parent_names = (const char *[]){ - "rbbmtimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &rbbmtimer_clk_src.clr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -222,8 +222,8 @@ static struct clk_branch gpucc_rbcpr_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_rbcpr_clk", - .parent_names = (const char *[]){ - "rbcpr_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &rbcpr_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Wed Dec 15 00:54:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF009C433F5 for ; Wed, 15 Dec 2021 00:54:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238674AbhLOAyv (ORCPT ); Tue, 14 Dec 2021 19:54:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235240AbhLOAyv (ORCPT ); Tue, 14 Dec 2021 19:54:51 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DF75C061574 for ; Tue, 14 Dec 2021 16:54:50 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id bi37so40093411lfb.5 for ; Tue, 14 Dec 2021 16:54:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SKTQi2EJrKx0JbO96uoXGThEUfmCNmO0OSGslUkg3+8=; b=K5FGKst7dMMN9k3UnVPyFWAjwF+MGr7RrxFOqBUeyuQUvyQ20/vcsp6s8HtfsD1fPn R7BYzukh4qzVylXoglKBQzBBYG6FT9Vk0FAA6Cim+UBQygBK0ewabEH7LmrAC6XGKD3D qMJi1kyPP11OBsg8rHtxbl2ucwgPenLtLiTtMz/VIaIpV5TmpWt/cYJ66t6Sf/iufRnj D2MBQzj2/MgAgJ2a7DfZP/E6W4x14A/JPwEv2fV/BTPyvMOJmbFaTy05HPaqCRMgu1Gw JyR613gPi6VDATsMFao7XMh7qm7AXJCAyPeTKhtbhHB+Xdp+SVnYCR/d5WWj+BW1o3Mi xzaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SKTQi2EJrKx0JbO96uoXGThEUfmCNmO0OSGslUkg3+8=; b=e99U+dFcmv2KSbOwBbDChwPQvGwn5zClXlpo7MaLvXxOWGCc+7ggs/HjloAetIHTVb 34Vf+d5lhffcOXvoVm5E8B8UfTQIvNrtY3M7Kntv8ZZwAVRUYjKmAGhgvnb+HB1To7Jn G/n7K6ZW1c23ZO59lOfSQQzvVjCPMu6iKpE6zfIsPcJwmJnhvtZT9BnGPOOnUzdplRdk EiobJVw2FHBzv/kOA4ON70Xf/umYCPiYyWKFv4E9iQkaHPsABxEHFfro7EpBFpsG+RkG 7sXnaB/0XEVe1rRx2Xaa9LAL42x87foZL6C+2OxuKaE1Z3KLaPtMqWFFvQs+tmwrsj3q sdew== X-Gm-Message-State: AOAM533GEeBmXpWcgiNBaZAk7MFFHF+2N2O/t1BLor9LBIrYxdimdBaW +c/3EAmqUOizUipfVKnlsJ0JOg== X-Google-Smtp-Source: ABdhPJwKnBx7GnKjM0XHrWQqG4sNKQCHPc53Zycg8vjofIYcVAqKBGlDwFV6JA99UBuFas3ex1KP2w== X-Received: by 2002:a05:6512:114a:: with SMTP id m10mr7550783lfg.54.1639529688931; Tue, 14 Dec 2021 16:54:48 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id b12sm53022lfb.146.2021.12.14.16.54.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 16:54:48 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Marijn Suijten , Stephen Boyd Subject: [PATCH v2 03/15] clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data Date: Wed, 15 Dec 2021 03:54:11 +0300 Message-Id: <20211215005423.2114261-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd --- drivers/clk/qcom/gpucc-sdm660.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 71a1ee05e822..dfb3902186e1 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -65,8 +65,8 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = { .num_vco = ARRAY_SIZE(gpu_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_pll0_pll_out_main", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpucc_cxo_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpucc_cxo_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -80,8 +80,8 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = { .num_vco = ARRAY_SIZE(gpu_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_pll1_pll_out_main", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpucc_cxo_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpucc_cxo_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -134,8 +134,8 @@ static struct clk_branch gpucc_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_gfx3d_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gfx3d_clk_src.rcg.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gfx3d_clk_src.rcg.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, From patchwork Wed Dec 15 00:54:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72528C433EF for ; Wed, 15 Dec 2021 00:54:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238679AbhLOAyy (ORCPT ); Tue, 14 Dec 2021 19:54:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235240AbhLOAyy (ORCPT ); Tue, 14 Dec 2021 19:54:54 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B52F1C061574 for ; Tue, 14 Dec 2021 16:54:53 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id d10so40061718lfg.6 for ; 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Tue, 14 Dec 2021 16:54:51 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id b12sm53022lfb.146.2021.12.14.16.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 16:54:51 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 05/15] clk: qcom: camcc-sc7180: get rid of the test clock Date: Wed, 15 Dec 2021 03:54:13 +0300 Message-Id: <20211215005423.2114261-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/camcc-sc7180.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index f6e303976a0d..3c15e551419f 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -29,7 +29,6 @@ enum { P_CAM_CC_PLL2_OUT_AUX, P_CAM_CC_PLL2_OUT_EARLY, P_CAM_CC_PLL3_OUT_MAIN, - P_CORE_BI_PLL_TEST_SE, }; static const struct pll_vco agera_vco[] = { @@ -187,26 +186,22 @@ static const struct parent_map cam_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll1.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_AUX, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll2_out_aux.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_2[] = { @@ -214,7 +209,6 @@ static const struct parent_map cam_cc_parent_map_2[] = { { P_CAM_CC_PLL2_OUT_EARLY, 4 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_2[] = { @@ -222,7 +216,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = { { .hw = &cam_cc_pll2_out_early.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_3[] = { @@ -231,7 +224,6 @@ static const struct parent_map cam_cc_parent_map_3[] = { { P_CAM_CC_PLL2_OUT_EARLY, 4 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_3[] = { @@ -240,33 +232,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = { { .hw = &cam_cc_pll2_out_early.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_6[] = { @@ -274,7 +261,6 @@ static const struct parent_map cam_cc_parent_map_6[] = { { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_6[] = { @@ -282,7 +268,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = { { .hw = &cam_cc_pll1.clkr.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { From patchwork Wed Dec 15 00:54:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E546C4332F for ; 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Tue, 14 Dec 2021 16:54:53 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Marijn Suijten , Stephen Boyd Subject: [PATCH v2 06/15] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data Date: Wed, 15 Dec 2021 03:54:14 +0300 Message-Id: <20211215005423.2114261-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd --- drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++---------------- 1 file changed, 79 insertions(+), 77 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index 3c15e551419f..e2b4804695f3 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_early", - .parent_names = (const char *[]){ "cam_cc_pll2" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_aux", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_pll2.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_bps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_core_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_icp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ipe_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_jpeg_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_lrme_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_lrme_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Wed Dec 15 00:54:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E9A9C4321E for ; Wed, 15 Dec 2021 00:55:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238689AbhLOAzA (ORCPT ); Tue, 14 Dec 2021 19:55:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238685AbhLOAy6 (ORCPT ); Tue, 14 Dec 2021 19:54:58 -0500 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D535C061574 for ; Tue, 14 Dec 2021 16:54:58 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id m12so30891263ljj.6 for ; Tue, 14 Dec 2021 16:54:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k0ce96TstsYTrbqj0IC60xk9afyHKUuCVQ7+9L71RNk=; b=ZXsf3cufSuOiAaD7yd8wOf+OwL55oAMdTXR6e8kx440S4uMYF4YavvgotWU87tLtet 1O4WtrMADEMSXBuLdJdASGHArDFWHitZzvPEVlOq/KPLi6Z6TQvP8LVc/CRTNkPYtdzC CusD8O+2HkSB0o0KBe/56Vj3UBTjqT201ViszZP7aJJlHcfQHTdDfaWCd8xQEyPN6oTF HzTPA6u3uXYsIkyRdHR8GYfDyIlotPQ0y46Sl/0lH9wGtwD9XqrIeQlNWQDgDA4UfRud y9zlAdhTeBvhl62FO7Q+0Z40K8LyW/9f0fOA0T3qsd1Lwq1Dj0VtY2Br1C8P7iL+9tEY m2Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k0ce96TstsYTrbqj0IC60xk9afyHKUuCVQ7+9L71RNk=; b=l3tQoeX5F4ccNuDKCPFhNC6answAAzokoqmGREbjwEK5MuTZdXF3nvwbnlUgotVoLw LYjKv8WI8G6+PSH/sSXX/zizspV4ykB1msgxbjAvtK3p5R9Wuf3SBbbD6ptvqVrTKnVF 25UfMTUsSFbvNP6tlYFcNPV7bOKFzYRvrhZ2JZKBFQdc7LROTnPLzxygX3VOlgTvAACe 81Cz5ZQM6hInYPm5C00Hx8BhXz05bMGN25RzDE0QcDi9/T4ZUmWdB5THBUSGuTySy5b4 YMPq6cvNfSqHjBLMHGTQqs+cLRUeZBqLc40IJS6EIcQZuIhUfQlrynbGV29kbp551RVw PuhA== X-Gm-Message-State: AOAM533VhcQ3TpMQ24xykfU5qWb0XlObSapriOOsxsJULFSS5Dfr3C4h 6/VBWDfELjPNLHXut7J6xedbTw== X-Google-Smtp-Source: ABdhPJyh1ku3OlGmEGFW/enyG3onTT+fFDBKY/9W/Xzh8Vj8Hh5ZG8CYd0IG+livKdZ8OV9AI+nmRQ== X-Received: by 2002:a2e:874b:: with SMTP id q11mr7862082ljj.194.1639529696618; Tue, 14 Dec 2021 16:54:56 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id b12sm53022lfb.146.2021.12.14.16.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 16:54:56 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 08/15] clk: qcom: camcc-sdm845: move clock parent tables down Date: Wed, 15 Dec 2021 03:54:16 +0300 Message-Id: <20211215005423.2114261-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/camcc-sdm845.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index 545c288a7f98..f5b43dce3295 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -25,22 +25,6 @@ enum { P_CAM_CC_PLL3_OUT_EVEN, }; -static const struct parent_map cam_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL2_OUT_EVEN, 1 }, - { P_CAM_CC_PLL1_OUT_EVEN, 2 }, - { P_CAM_CC_PLL3_OUT_EVEN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, -}; - -static const char * const cam_cc_parent_names_0[] = { - "bi_tcxo", - "cam_cc_pll2_out_even", - "cam_cc_pll1_out_even", - "cam_cc_pll3_out_even", - "cam_cc_pll0_out_even", -}; - static struct clk_alpha_pll cam_cc_pll0 = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], @@ -159,6 +143,22 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { }, }; +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 1 }, + { P_CAM_CC_PLL1_OUT_EVEN, 2 }, + { P_CAM_CC_PLL3_OUT_EVEN, 5 }, + { P_CAM_CC_PLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &cam_cc_pll2_out_even.clkr.hw }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, +}; + static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), From patchwork Wed Dec 15 00:54:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A129AC433F5 for ; Wed, 15 Dec 2021 00:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238693AbhLOAzD (ORCPT ); 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Tue, 14 Dec 2021 16:55:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Marijn Suijten , Stephen Boyd Subject: [PATCH v2 11/15] clk: qcom: videocc-sc7180: use parent_hws instead of parent_data Date: Wed, 15 Dec 2021 03:54:19 +0300 Message-Id: <20211215005423.2114261-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd --- drivers/clk/qcom/videocc-sc7180.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index ed57bbb19f88..5b9b54f616b8 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -99,8 +99,8 @@ static struct clk_branch video_cc_vcodec0_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_vcodec0_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_venus_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -143,8 +143,8 @@ static struct clk_branch video_cc_venus_ctl_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_venus_ctl_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_venus_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Wed Dec 15 00:54:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B7F3C43219 for ; Wed, 15 Dec 2021 00:55:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238694AbhLOAzF (ORCPT ); Tue, 14 Dec 2021 19:55:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238680AbhLOAzF (ORCPT ); Tue, 14 Dec 2021 19:55:05 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61507C06173E for ; Tue, 14 Dec 2021 16:55:04 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id b40so40009492lfv.10 for ; Tue, 14 Dec 2021 16:55:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+amuZGSFWXVVm3r5rOaOAfThglCaL2AfSDBWBPHb7hY=; b=WJlZYO6EfephluW3tv81/WAWSdkjw5QjtrM8+BNo0goHhXFoxp5w6hx7yPR75iC07S wJFj7OjtuDOCXHXalbIsfa1MKDb9we3Myom2Y4fchybkW+/0VOb46fWH6gGx6/SwjiFN U55/UuT3DeO19Nc7/u+f3KuTH634YyHjyGoeCOcONXcrW3JS6C0naNSL+qBdqmhuk7uQ q5XICjJRkuusWW/yBBhLHYo29lV/zhiy50McV8KcV2Paf+LODMzsC+EBRE0A/yXI71PJ HnGRob3G9IPi/lXCdtSDJiDM/D2USMAnGGUyqjL0PTbM041IHuD9mt5FIllnwagPKD6m eiLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+amuZGSFWXVVm3r5rOaOAfThglCaL2AfSDBWBPHb7hY=; b=vEFR1B8sSwYXgD4VeZS1Jmf7kwHRzVAzuhZmD58qJP6h1yS+13+fSZiLeA5qSQXeRe tKUG7rGGPGI7EbdXvt46008uAj/AYi5sGrJSk5LxIa9yqAv41cXogTC5NRYrQv4xMwxt NbpMEy9PC7P74o2kjJZ8h5hJWktmofFl+TSsxznmWDjzuKpv9RkCIo4Ma8mH7cJpS1tt PfMOJy+cld8mBBJVfriNULnSXl7rkHGzhd2OrrK+e0OGutsskPUp41X0HjgdhnC5fKDl 00/YZthuOGtiBkFCkqFpG59wH/ZgpPU7GfweHLiNYagI+HNORYxJYtQ1COUpSRQik+8g Xydw== X-Gm-Message-State: AOAM530Ta2akkCm3ddP0HxwFDYhyB8Iresg9CxLe2xqTLReLIUBzmPKI Ixt+/N0wl7wEaavL7dJXCuuHLvLPdOWrBXU5 X-Google-Smtp-Source: ABdhPJz8XYNVy1dwECA06h4gtfDWpkcbp0PHy+zhi8F62J+ADpX+sY2+aUjliwC85YEA/aa0HvMCIg== X-Received: by 2002:ac2:4c4e:: with SMTP id o14mr7804415lfk.148.1639529702589; Tue, 14 Dec 2021 16:55:02 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id b12sm53022lfb.146.2021.12.14.16.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 16:55:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 12/15] clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents Date: Wed, 15 Dec 2021 03:54:20 +0300 Message-Id: <20211215005423.2114261-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++----------------- 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 9b1674b28d45..d95814025c65 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -290,7 +290,7 @@ static struct clk_rcg2 system_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -310,7 +310,7 @@ static struct clk_rcg2 config_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "config_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -332,7 +332,7 @@ static struct clk_rcg2 periph_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "periph_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -353,7 +353,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -371,7 +371,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -389,7 +389,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_names = gcc_xo_sleep_clk, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -408,7 +408,7 @@ static struct clk_rcg2 usb20_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_master_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -421,7 +421,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -447,7 +447,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_floor_ops, }, }; @@ -467,7 +467,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -492,7 +492,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, }; @@ -506,7 +506,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc3_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, }; @@ -530,7 +530,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, }; @@ -555,7 +555,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -574,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -634,7 +634,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -675,7 +675,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -716,7 +716,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -757,7 +757,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -798,7 +798,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -812,7 +812,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -839,7 +839,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -880,7 +880,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -921,7 +921,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -962,7 +962,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1003,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart5_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1044,7 +1044,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1058,7 +1058,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart6_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1076,7 +1076,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1095,7 +1095,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", .parent_names = gcc_xo_gpll0_aud_ref_clk, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), .ops = &clk_rcg2_ops, }, }; @@ -1107,7 +1107,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sleep_clk_src", .parent_names = gcc_sleep_clk, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -1120,7 +1120,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1132,7 +1132,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1153,7 +1153,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1167,7 +1167,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1181,7 +1181,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1200,7 +1200,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_aux_clk_src", .parent_names = gcc_xo_sleep_clk, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -1221,7 +1221,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1241,7 +1241,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1262,7 +1262,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; From patchwork Wed Dec 15 00:54:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 524651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30E19C433FE for ; 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Tue, 14 Dec 2021 16:55:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 15/15] clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names Date: Wed, 15 Dec 2021 03:54:23 +0300 Message-Id: <20211215005423.2114261-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> References: <20211215005423.2114261-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++----------- 1 file changed, 463 insertions(+), 215 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 8531f2f3665f..204c1f4c68c4 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = { .div = 1, .hw.init = &(struct clk_init_data){ .name = "xo", - .parent_names = (const char *[]){ "xo_board" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo", .name = "xo_board", + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_early", - .parent_names = (const char *[]){ "xo" }, + .parent_hws = (const struct clk_hw*[]){ + &xo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_early_div", - .parent_names = (const char *[]){ "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", - .parent_names = (const char *[]){ "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_gpll0_div_clk", - .parent_names = (const char *[]){ "gpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_gpll0_div_clk", - .parent_names = (const char *[]){ "gpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops @@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4_early", - .parent_names = (const char *[]){ "xo" }, + .parent_hws = (const struct clk_hw*[]){ + &xo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", - .parent_names = (const char *[]){ "gpll4_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll4_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = { { P_SLEEP_CLK, 5 } }; -static const char * const gcc_sleep_clk[] = { - "sleep_clk" +static const struct clk_parent_data gcc_sleep_clk[] = { + { .fw_name = "sleep_clk", .name = "sleep_clk" } }; static const struct parent_map gcc_xo_gpll0_map[] = { @@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = { { P_GPLL0, 1 } }; -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0" +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw } }; static const struct parent_map gcc_xo_sleep_clk_map[] = { @@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = { { P_SLEEP_CLK, 5 } }; -static const char * const gcc_xo_sleep_clk[] = { - "xo", - "sleep_clk" +static const struct clk_parent_data gcc_xo_sleep_clk[] = { + { .hw = &xo.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" } }; static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { @@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { { P_GPLL0_EARLY_DIV, 6 } }; -static const char * const gcc_xo_gpll0_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll0_early_div" +static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_early_div.hw } }; static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { @@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { { P_GPLL4, 5 } }; -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0", - "gpll4" +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw } }; static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { @@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { { P_AUD_REF_CLK, 2 } }; -static const char * const gcc_xo_gpll0_aud_ref_clk[] = { - "xo", - "gpll0", - "aud_ref_clk" +static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" } }; static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { @@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { { P_GPLL0_EARLY_DIV, 6 } }; -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { - "xo", - "gpll0", - "sleep_clk", - "gpll0_early_div" +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, + { .hw = &gpll0_early_div.hw } }; static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { @@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { { P_GPLL0_EARLY_DIV, 6 } }; -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll4", - "gpll0_early_div" +static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0_early_div.hw } }; static const struct freq_tbl ftbl_system_noc_clk_src[] = { @@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = { .freq_tbl = ftbl_system_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = { .freq_tbl = ftbl_config_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "config_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = { .freq_tbl = ftbl_periph_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "periph_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .freq_tbl = ftbl_usb30_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .freq_tbl = ftbl_usb3_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_xo_sleep_clk, + .parent_data = gcc_xo_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, @@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = { .freq_tbl = ftbl_usb20_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_master_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .freq_tbl = ftbl_sdcc1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_floor_ops, }, @@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .freq_tbl = ftbl_sdcc1_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4, + .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, @@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc3_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4, + .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, @@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .freq_tbl = ftbl_sdcc4_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, @@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = { .freq_tbl = ftbl_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { .freq_tbl = ftbl_tsif_ref_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", - .parent_names = gcc_xo_gpll0_aud_ref_clk, + .parent_data = gcc_xo_gpll0_aud_ref_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), .ops = &clk_rcg2_ops, }, @@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = { .parent_map = gcc_sleep_clk_map, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sleep_clk_src", - .parent_names = gcc_sleep_clk, + .parent_data = gcc_sleep_clk, .num_parents = ARRAY_SIZE(gcc_sleep_clk), .ops = &clk_rcg2_ops, }, @@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { .freq_tbl = ftbl_pcie_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_aux_clk_src", - .parent_names = gcc_xo_sleep_clk, + .parent_data = gcc_xo_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, @@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { .freq_tbl = ftbl_ufs_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { .freq_tbl = ftbl_ufs_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { .freq_tbl = ftbl_qspi_ser_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_axi_clk", - .parent_names = (const char *[]){ "usb30_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_ufs_axi_clk", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_periph_noc_usb20_ahb_clk", - .parent_names = (const char *[]){ "usb20_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb20_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .ops = &clk_branch2_ops, @@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ "usb30_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_mock_utmi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb3_phy_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_pipe_clk", - .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_master_clk", - .parent_names = (const char *[]){ "usb20_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb20_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb20_mock_utmi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_phy_cfg_ahb2phy_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ "sdcc1_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc1_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc1_ice_core_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ "sdcc2_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc2_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_apps_clk", - .parent_names = (const char *[]){ "sdcc3_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc3_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", - .parent_names = (const char *[]){ "sdcc4_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc4_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart1_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup2_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart2_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup3_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart3_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart3_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup4_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart4_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart4_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup5_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart5_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart5_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup6_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart6_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart6_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup1_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart1_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup2_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart2_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup3_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart3_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart3_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart4_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart4_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup5_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup5_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart5_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart5_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup6_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup6_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart6_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart6_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ "pdm2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pdm2_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_prng_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_inactivity_timers_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_boot_rom_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_rbcpr_clk", - .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &hmss_rbcpr_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ "gp1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp1_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ "gp2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp2_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ "gp3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp3_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_slv_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_mstr_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_slv_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_mstr_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", - .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_slv_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_mstr_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_pipe_clk", - .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_axi_clk", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = { .div = 16, .hw.init = &(struct clk_init_data){ .name = "ufs_tx_cfg_clk_src", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, @@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_cfg_clk", - .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_tx_cfg_clk_src.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = { .div = 16, .hw.init = &(struct clk_init_data){ .name = "ufs_rx_cfg_clk_src", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, @@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_cfg_clk", - .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_rx_cfg_clk_src.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_0_clk", - .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_0_clk", - .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_1_clk", - .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_postdiv_clk_src", - .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_ice_core_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, @@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_unipro_core_clk", - .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_ice_core_postdiv_clk_src.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ice_core_clk", - .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_ice_core_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre0_snoc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre0_cnoc_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_smmu_aggre0_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_smmu_aggre0_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre2_ufs_axi_clk", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre2_usb3_axi_clk", - .parent_names = (const char *[]){ "usb30_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_dcc_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_ser_clk", - .parent_names = (const char *[]){ "qspi_ser_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &qspi_ser_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_mnoc_bimc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_snoc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, },