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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id z17-v6sm13747187wrm.65.2018.11.12.02.36.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 02:36:57 -0800 (PST) From: Srinivas Kandagatla To: marc.zyngier@arm.com Cc: sudeep.holla@arm.com, tglx@linutronix.de, jason@lakedaemon.net, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, sboyd@kernel.org, srini@kernel.org, bjorn.andersson@linaro.org, nicolas.dechesne@linaro.org, ctatlor97@gmail.com, vkoul@kernel.org, Srinivas Kandagatla Subject: [RFC PATCH v3 1/4] dt-bindings/gic-v3: Add msm8996 compatible string Date: Mon, 12 Nov 2018 10:33:37 +0000 Message-Id: <20181112103340.24702-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112103340.24702-1-srinivas.kandagatla@linaro.org> References: <20181112103340.24702-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Access to GICR_WAKER is restricted on msm8996 SoC in Hypervisor. There are many devices out there with this restriction in place and there has been no update to this firmware since last few years, making those devices totally unusable for upstream development. IIDR register value conflicts with other SoCs, using compatible seems to be the only way to apply quirks required for msm8996 based SoCs. Without this quirk many qcom SoCs (atleast 3 that I know) are unable to boot mainline. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.19.1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 3ea78c4ef887..b83bb8249074 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -7,7 +7,9 @@ Interrupts (LPI). Main node required properties: -- compatible : should at least contain "arm,gic-v3". +- compatible : should at least contain "arm,gic-v3" or either + "qcom,msm8996-gic-v3", "arm,gic-v3" for msm8996 SoCs + to address SoC specific bugs/quirks - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. Must be a single cell with a value of at least 3. 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id z17-v6sm13747187wrm.65.2018.11.12.02.36.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 02:36:58 -0800 (PST) From: Srinivas Kandagatla To: marc.zyngier@arm.com Cc: sudeep.holla@arm.com, tglx@linutronix.de, jason@lakedaemon.net, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, sboyd@kernel.org, srini@kernel.org, bjorn.andersson@linaro.org, nicolas.dechesne@linaro.org, ctatlor97@gmail.com, vkoul@kernel.org, Srinivas Kandagatla Subject: [RFC PATCH v3 2/4] irqchip/gic: common: add support to device tree based quirks Date: Mon, 12 Nov 2018 10:33:38 +0000 Message-Id: <20181112103340.24702-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112103340.24702-1-srinivas.kandagatla@linaro.org> References: <20181112103340.24702-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support to device tree based quirks based on device tree compatible string. Signed-off-by: Srinivas Kandagatla --- drivers/irqchip/irq-gic-common.c | 12 ++++++++++++ drivers/irqchip/irq-gic-common.h | 3 +++ 2 files changed, 15 insertions(+) -- 2.19.1 diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 01e673c680cd..3c93c6f4d1f1 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -36,6 +36,18 @@ void gic_set_kvm_info(const struct gic_kvm_info *info) gic_kvm_info = info; } +void gic_enable_of_quirks(const struct device_node *np, + const struct gic_quirk *quirks, void *data) +{ + for (; quirks->desc; quirks++) { + if (!of_device_is_compatible(np, quirks->compatible)) + continue; + if (quirks->init(data)) + pr_info("GIC: enabling workaround for %s\n", + quirks->desc); + } +} + void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, void *data) { diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index 3919cd7c5285..97e58fb6c232 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -23,6 +23,7 @@ struct gic_quirk { const char *desc; + const char *compatible; bool (*init)(void *data); u32 iidr; u32 mask; @@ -35,6 +36,8 @@ void gic_dist_config(void __iomem *base, int gic_irqs, void gic_cpu_config(void __iomem *base, void (*sync_access)(void)); void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, void *data); +void gic_enable_of_quirks(const struct device_node *np, + const struct gic_quirk *quirks, void *data); void gic_set_kvm_info(const struct gic_kvm_info *info); From patchwork Mon Nov 12 10:33:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 150816 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2980731ljp; Mon, 12 Nov 2018 02:37:06 -0800 (PST) X-Google-Smtp-Source: AJdET5ep0+X3JuTClmM0ZfuDRrqUkvoeUXPXemBl/j36sUOHsbiihKZ1XBtJ3shC31tHbP3DChy+ X-Received: by 2002:a17:902:50ec:: with SMTP id c41-v6mr409981plj.176.1542019026700; Mon, 12 Nov 2018 02:37:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542019026; cv=none; d=google.com; s=arc-20160816; b=HD1+ihcXFveu2xXeMReoLL7HawJ1j11IPeQsPIRsE5BEomd+6QhU/wb6bnQxlkT41p 0hhPWZfa7WI3chzhiA7xHlBDtvXgHLJgUiNyf4x976wvzU+1V11JWbRbOhCndlAukLwE lWLF8O+IncbBn2Br+2Z+LC2OcxFr8RbXgz9acFcc5ZAaz074MMJqSQIUQg3qJ/udU2sS NeV4o7kjdDbcmW1Dgx4Pb61KQTtJTg4fpSKVw8BNuQssn3NyizzyXUiCpw3Mww49mO4X 07HzQB+DugWPnjHO8meHaop0/AgCkXWArm8urzD0I3Vx9z4mVOOKP2dlUO978r7wy8hc bMsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dSzyRYCj+DB3PSpFskdzVkVAIM/Xjweh2bjnaCEiMfA=; b=PPrw9vQ3SerZ2YSBFGT5IQRcrAPbz7ohrrP4uGoYUdEzeI/7cG2ug5Zsx+JchZN2FY AuDlKQg4ij2c+rxdOX9i/RlbQqmJ7aCktCyfLgpEUFOo08YMb+HAzMRRf3N8qp9OEnwG d18M1qBo06v+2APx1Gl3MGB0RRFTPW6fHWbAxJ7eKxBkApu5pOSXZm6hfUCv5lBGJf1a d/uyOAPA9TMNwH1ZyhjAfWkEbXWzeh+KBn1rWWifAQYlQX7KCqYmDatHtyHIRLWiPU4l uwlXh5u57jQO1JsmXakh/PWwuLmIVshBcKbh2A1SpNvqcrwK3TSGgD/PAvQLO4eQSTsj Q/yQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XhlEwHfg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id z17-v6sm13747187wrm.65.2018.11.12.02.36.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 02:37:00 -0800 (PST) From: Srinivas Kandagatla To: marc.zyngier@arm.com Cc: sudeep.holla@arm.com, tglx@linutronix.de, jason@lakedaemon.net, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, sboyd@kernel.org, srini@kernel.org, bjorn.andersson@linaro.org, nicolas.dechesne@linaro.org, ctatlor97@gmail.com, vkoul@kernel.org, Srinivas Kandagatla Subject: [RFC PATCH v3 3/4] irqchip: gic-v3: Add quirk for msm8996 secured registers Date: Mon, 12 Nov 2018 10:33:39 +0000 Message-Id: <20181112103340.24702-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112103340.24702-1-srinivas.kandagatla@linaro.org> References: <20181112103340.24702-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Access to GICR_WAKER is restricted on msm8996 SoC in Hypervisor. Its been more than 2+ years of wait for this to be fixed, which has no hopes to be fixed. This change was introduced for the "lead device" on msm8996 platform. It looks like all publicly available msm8996 and other qcom SoCs have this implementation. So add a quirk to not access this register on msm8996. With this quirk MSM8996 can at least boot out of mainline, which can help community to work with boards based on MSM8996 and other SoCs with have this restrictions. This Quirk is based on device tree compatible string. Without this patch Qualcomm DB820c board reboots when GICR_WAKER is accessed. Signed-off-by: Srinivas Kandagatla --- drivers/irqchip/irq-gic-v3.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.19.1 diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 8f87f40c9460..4bd3bbe1b7ce 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -41,6 +41,8 @@ #include "irq-gic-common.h" +#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) + struct redist_region { void __iomem *redist_base; phys_addr_t phys_base; @@ -55,6 +57,7 @@ struct gic_chip_data { struct irq_domain *domain; u64 redist_stride; u32 nr_redist_regions; + u64 flags; bool has_rss; unsigned int irq_nr; struct partition_desc *ppi_descs[16]; @@ -139,6 +142,9 @@ static void gic_enable_redist(bool enable) u32 count = 1000000; /* 1s! */ u32 val; + if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) + return; + rbase = gic_data_rdist_rd_base(); val = readl_relaxed(rbase + GICR_WAKER); @@ -1067,6 +1073,23 @@ static const struct irq_domain_ops partition_domain_ops = { .select = gic_irq_domain_select, }; +static bool __maybe_unused gic_enable_quirk_msm8996(void *data) +{ + struct gic_chip_data *d = data; + + d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; + + return true; +} + +static const struct gic_quirk gic_quirks[] = { + { + .desc = "GICv3: Qualcomm MSM8996 skip GICR_WAKER Read/Write", + .compatible = "qcom,msm8996-gic-v3", /* MSM8996 */ + .init = gic_enable_quirk_msm8996, + }, +}; + static int __init gic_init_bases(void __iomem *dist_base, struct redist_region *rdist_regs, u32 nr_redist_regions, @@ -1126,6 +1149,9 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_update_vlpi_properties(); + if (is_of_node(handle)) + gic_enable_of_quirks(to_of_node(handle), gic_quirks, &gic_data); + gic_smp_init(); gic_dist_init(); gic_cpu_init();